system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00100dbf_00000000-6_ex1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12vecAddKernelPfS_S_jPfS_S_j
.type _Z37__device_stub__Z12vecAddKernelPfS_S_jPfS_S_j, @function
_Z37__device_stub__Z12vecAddKernelPfS_S_jPfS_S_j:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPfS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z12vecAddKernelPfS_S_jPfS_S_j, .-_Z37__device_stub__Z12vecAddKernelPfS_S_jPfS_S_j
.globl _Z12vecAddKernelPfS_S_j
.type _Z12vecAddKernelPfS_S_j, @function
_Z12vecAddKernelPfS_S_j:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPfS_S_jPfS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12vecAddKernelPfS_S_j, .-_Z12vecAddKernelPfS_S_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "GPU Computation over, time: %f \n"
.align 8
.LC3:
.string "CPU Computation over, time: %f \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPU is %f times faster\n"
.LC5:
.string "Wrong! %f vs %f\n"
.LC6:
.string "Correct!!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $400000000, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $400000000, %rax
jne .L12
leaq 24(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %r12
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $97657, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L13:
call clock@PLT
subq %r12, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movsd %xmm2, 8(%rsp)
movapd %xmm2, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $400000000, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $400000000, %edi
call malloc@PLT
movq %rax, %r12
call clock@PLT
movq %rax, %r14
movl $0, %eax
.L14:
movss 0(%rbp,%rax), %xmm0
addss (%rbx,%rax), %xmm0
movss %xmm0, (%r12,%rax)
addq $4, %rax
cmpq $400000000, %rax
jne .L14
call clock@PLT
subq %r14, %rax
pxor %xmm3, %xmm3
cvtsi2sdq %rax, %xmm3
movq %xmm3, %r14
movapd %xmm3, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r14, %xmm0
divsd 8(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
.L18:
movss 0(%r13,%rax), %xmm0
movss (%r12,%rax), %xmm1
ucomiss %xmm1, %xmm0
jp .L20
jne .L20
addq $4, %rax
cmpq $400000000, %rax
jne .L18
jmp .L17
.L25:
movl $100000000, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPfS_S_jPfS_S_j
jmp .L13
.L20:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L17:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12vecAddKernelPfS_S_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPfS_S_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ex1.hip"
.globl _Z27__device_stub__vecAddKernelPfS_S_j # -- Begin function _Z27__device_stub__vecAddKernelPfS_S_j
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPfS_S_j,@function
_Z27__device_stub__vecAddKernelPfS_S_j: # @_Z27__device_stub__vecAddKernelPfS_S_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__vecAddKernelPfS_S_j, .Lfunc_end0-_Z27__device_stub__vecAddKernelPfS_S_j
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbx
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r14
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $100000000, %rax # imm = 0x5F5E100
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movq 24(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, %r12
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 96633(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $100000000, 36(%rsp) # imm = 0x5F5E100
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_j, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq clock
subq %r12, %rax
cvtsi2sd %rax, %xmm0
movl $.L.str, %edi
movsd %xmm0, 48(%rsp) # 8-byte Spill
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movl $400000000, %edx # imm = 0x17D78400
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r12
xorl %ebp, %ebp
callq clock
movq %rax, %r13
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rbp,4), %xmm0
movss %xmm0, (%r12,%rbp,4)
incq %rbp
cmpq $100000000, %rbp # imm = 0x5F5E100
jne .LBB1_5
# %bb.6:
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
movl $.L.str.1, %edi
movb $1, %al
callq printf
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 48(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
movss (%r15,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r12,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB1_9
jp .LBB1_9
# %bb.7: # in Loop: Header=BB1_8 Depth=1
incq %rax
cmpq $100000000, %rax # imm = 0x5F5E100
jne .LBB1_8
jmp .LBB1_10
.LBB1_9:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.3, %edi
movb $2, %al
callq printf
.LBB1_10: # %.loopexit
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPfS_S_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vecAddKernelPfS_S_j,@object # @_Z12vecAddKernelPfS_S_j
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPfS_S_j
.p2align 3, 0x0
_Z12vecAddKernelPfS_S_j:
.quad _Z27__device_stub__vecAddKernelPfS_S_j
.size _Z12vecAddKernelPfS_S_j, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU Computation over, time: %f \n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU Computation over, time: %f \n"
.size .L.str.1, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU is %f times faster\n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Wrong! %f vs %f\n"
.size .L.str.3, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12vecAddKernelPfS_S_j"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correct!!"
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPfS_S_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPfS_S_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Copyright (c) Megvii Inc. All rights reserved.
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define THREADS_BLOCK_X 32
#define THREADS_BLOCK_Y 4
#define THREADS_PER_BLOCK THREADS_BLOCK_X * THREADS_BLOCK_Y
#define DIVUP(m, n) ((m) / (n) + ((m) % (n) > 0))
__global__ void voxel_pooling_forward_kernel(int batch_size, int num_points, int num_channels, int num_voxel_x, int num_voxel_y, int num_voxel_z, const int *geom_xyz, const float *input_features,
float *output_features, int *pos_memo) {
const int bidx = blockIdx.x;
const int tidx = threadIdx.x;
const int tidy = threadIdx.y;
const int sample_dim = THREADS_PER_BLOCK;
const int idx_in_block = tidy * THREADS_BLOCK_X + tidx;
const int block_sample_idx = bidx * sample_dim;
const int thread_sample_idx = block_sample_idx + idx_in_block;
const int total_samples = batch_size * num_points;
__shared__ int geom_xyz_shared[THREADS_PER_BLOCK * 3];
if (thread_sample_idx < total_samples) {
const int sample_x = geom_xyz[thread_sample_idx * 3 + 0];
const int sample_y = geom_xyz[thread_sample_idx * 3 + 1];
const int sample_z = geom_xyz[thread_sample_idx * 3 + 2];
geom_xyz_shared[idx_in_block * 3 + 0] = sample_x;
geom_xyz_shared[idx_in_block * 3 + 1] = sample_y;
geom_xyz_shared[idx_in_block * 3 + 2] = sample_z;
if ((sample_x >= 0 && sample_x < num_voxel_x) && (sample_y >= 0 && sample_y < num_voxel_y) && (sample_z >= 0 && sample_z < num_voxel_z)) {
pos_memo[thread_sample_idx * 3 + 0] = thread_sample_idx / num_points;
pos_memo[thread_sample_idx * 3 + 1] = sample_y;
pos_memo[thread_sample_idx * 3 + 2] = sample_x;
}
}
__syncthreads();
for (int i = tidy; i < THREADS_PER_BLOCK && block_sample_idx + i < total_samples; i += THREADS_BLOCK_Y) {
const int sample_x = geom_xyz_shared[i * 3 + 0];
const int sample_y = geom_xyz_shared[i * 3 + 1];
const int sample_z = geom_xyz_shared[i * 3 + 2];
if (sample_x < 0 || sample_x >= num_voxel_x || sample_y < 0 || sample_y >= num_voxel_y || sample_z < 0 || sample_z >= num_voxel_z) {
continue;
}
const int batch_idx = (block_sample_idx + i) / num_points;
for (int j = tidx; j < num_channels; j += THREADS_BLOCK_X) {
atomicAdd(&output_features[(batch_idx * num_voxel_y * num_voxel_x + sample_y * num_voxel_x + sample_x) * num_channels + j], input_features[(block_sample_idx + i) * num_channels + j]);
}
}
}
void voxel_pooling_forward_kernel_launcher(int batch_size, int num_points, int num_channels, int num_voxel_x, int num_voxel_y, int num_voxel_z, const int *geom_xyz, const float *input_features,
float *output_features, int *pos_memo, cudaStream_t stream) {
cudaError_t err;
dim3 blocks(DIVUP(batch_size * num_points, THREADS_PER_BLOCK));
dim3 threads(THREADS_BLOCK_X, THREADS_BLOCK_Y);
voxel_pooling_forward_kernel<<<blocks, threads, 0, stream>>>(batch_size, num_points, num_channels, num_voxel_x, num_voxel_y, num_voxel_z, geom_xyz, input_features, output_features, pos_memo);
err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", cudaGetErrorString(err));
exit(-1);
}
} | code for sm_80
Function : _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x400 ; /* 0x000003c000007945 */
/* 0x000fe20003800000 */
/*0040*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0080*/ IMAD R10, R0, 0x20, R3 ; /* 0x00000020000a7824 */
/* 0x001fc800078e0203 */
/*0090*/ IMAD R7, R5.reuse, 0x80, R10 ; /* 0x0000008005077824 */
/* 0x042fe400078e020a */
/*00a0*/ IMAD R22, R5, 0x80, R0 ; /* 0x0000008005167824 */
/* 0x000fc600078e0200 */
/*00b0*/ ISETP.GE.AND P1, PT, R7, UR4, PT ; /* 0x0000000407007c0c */
/* 0x000fe4000bf26270 */
/*00c0*/ ISETP.GE.AND P0, PT, R22, UR4, PT ; /* 0x0000000416007c0c */
/* 0x000fc8000bf06270 */
/*00d0*/ ISETP.GT.OR P0, PT, R0, 0x7f, P0 ; /* 0x0000007f0000780c */
/* 0x000fce0000704670 */
/*00e0*/ @P1 BRA 0x3f0 ; /* 0x0000030000001947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD R2, R7, 0x3, RZ ; /* 0x0000000307027824 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0120*/ LDG.E R4, [R8.64] ; /* 0x0000000608047981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R6, [R8.64+0x4] ; /* 0x0000040608067981 */
/* 0x000ee8000c1e1900 */
/*0140*/ LDG.E R11, [R8.64+0x8] ; /* 0x00000806080b7981 */
/* 0x000f22000c1e1900 */
/*0150*/ IMAD R13, R10, 0xc, RZ ; /* 0x0000000c0a0d7824 */
/* 0x000fe200078e02ff */
/*0160*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x004fc80003f26270 */
/*0170*/ STS [R13], R4 ; /* 0x000000040d007388 */
/* 0x0001e20000000800 */
/*0180*/ ISETP.GE.AND P2, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x008fc60003f46270 */
/*0190*/ STS [R13+0x4], R6 ; /* 0x000004060d007388 */
/* 0x0001e20000000800 */
/*01a0*/ ISETP.GT.AND P1, PT, R4, -0x1, !P1 ; /* 0xffffffff0400780c */
/* 0x000fe40004f24270 */
/*01b0*/ ISETP.GE.AND P3, PT, R11.reuse, c[0x0][0x174], PT ; /* 0x00005d000b007a0c */
/* 0x050fe20003f66270 */
/*01c0*/ STS [R13+0x8], R11 ; /* 0x0000080b0d007388 */
/* 0x0001e20000000800 */
/*01d0*/ ISETP.GT.AND P2, PT, R6, -0x1, !P2 ; /* 0xffffffff0600780c */
/* 0x000fe40005744270 */
/*01e0*/ ISETP.GT.AND P3, PT, R11, -0x1, !P3 ; /* 0xffffffff0b00780c */
/* 0x000fc80005f64270 */
/*01f0*/ PLOP3.LUT P1, PT, P3, P1, P2, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0001f23020 */
/*0200*/ @!P1 BRA 0x3f0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0210*/ IABS R11, c[0x0][0x164] ; /* 0x00005900000b7a13 */
/* 0x001fc80000000000 */
/*0220*/ I2F.RP R10, R11 ; /* 0x0000000b000a7306 */
/* 0x000e300000209400 */
/*0230*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0240*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fcc0007ffe0ff */
/*0250*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0270*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */
/* 0x002fc800078e0a09 */
/*0280*/ IMAD R13, R12, R11, RZ ; /* 0x0000000b0c0d7224 */
/* 0x000fe200078e02ff */
/*0290*/ IABS R12, R7 ; /* 0x00000007000c7213 */
/* 0x000fe40000000000 */
/*02a0*/ LOP3.LUT R7, R7, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x0000590007077a12 */
/* 0x000fe200078e3cff */
/*02b0*/ IMAD.HI.U32 R9, R9, R13, R8 ; /* 0x0000000d09097227 */
/* 0x000fc600078e0008 */
/*02c0*/ ISETP.GE.AND P3, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f66270 */
/*02d0*/ IMAD.HI.U32 R9, R9, R12, RZ ; /* 0x0000000c09097227 */
/* 0x000fc800078e00ff */
/*02e0*/ IMAD.MOV R10, RZ, RZ, -R9 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0a09 */
/*02f0*/ IMAD R10, R11, R10, R12 ; /* 0x0000000a0b0a7224 */
/* 0x000fca00078e020c */
/*0300*/ ISETP.GT.U32.AND P2, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x000fda0003f44070 */
/*0310*/ @!P2 IMAD.IADD R10, R10, 0x1, -R11 ; /* 0x000000010a0aa824 */
/* 0x000fe200078e0a0b */
/*0320*/ @!P2 IADD3 R9, R9, 0x1, RZ ; /* 0x000000010909a810 */
/* 0x000fe40007ffe0ff */
/*0330*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fe40003f45270 */
/*0340*/ ISETP.GE.U32.AND P1, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fe40003f26070 */
/*0350*/ SHF.R.S32.HI R11, RZ, 0x1f, R2 ; /* 0x0000001fff0b7819 */
/* 0x000fd60000011402 */
/*0360*/ @P1 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109091810 */
/* 0x000fe40007ffe0ff */
/*0370*/ LEA R8, P1, R2, c[0x0][0x190], 0x2 ; /* 0x0000640002087a11 */
/* 0x000fc600078210ff */
/*0380*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*0390*/ LEA.HI.X R9, R2, c[0x0][0x194], R11, 0x2, P1 ; /* 0x0000650002097a11 */
/* 0x000fc600008f140b */
/*03a0*/ @!P3 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07b224 */
/* 0x000fe200078e0a07 */
/*03b0*/ @!P2 LOP3.LUT R7, RZ, c[0x0][0x164], RZ, 0x33, !PT ; /* 0x00005900ff07aa12 */
/* 0x000fe200078e33ff */
/*03c0*/ STG.E [R8.64+0x4], R6 ; /* 0x0000040608007986 */
/* 0x0001e8000c101906 */
/*03d0*/ STG.E [R8.64+0x8], R4 ; /* 0x0000080408007986 */
/* 0x0001e8000c101906 */
/*03e0*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0001e4000c101906 */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0400*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0410*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0420*/ LOP3.LUT R2, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff027212 */
/* 0x000fe400078e33ff */
/*0430*/ IADD3 R4, R3, 0x40, RZ ; /* 0x0000004003047810 */
/* 0x000fc40007ffe0ff */
/*0440*/ IADD3 R2, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fe40007ffe0ff */
/*0450*/ IADD3 R6, R3, 0x60, RZ ; /* 0x0000006003067810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LEA.HI R7, R2, 0x1, RZ, 0x1b ; /* 0x0000000102077811 */
/* 0x000fc800078fd8ff */
/*0470*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fe400078ec0ff */
/*0480*/ IMAD R10, R0, 0xc, RZ ; /* 0x0000000c000a7824 */
/* 0x001fe200078e02ff */
/*0490*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*04a0*/ BSSY B0, 0xbb0 ; /* 0x0000070000007945 */
/* 0x000fe60003800000 */
/*04b0*/ LDS R8, [R10] ; /* 0x000000000a087984 */
/* 0x000fe80000000800 */
/*04c0*/ LDS R9, [R10+0x4] ; /* 0x000004000a097984 */
/* 0x000e280000000800 */
/*04d0*/ LDS R12, [R10+0x8] ; /* 0x000008000a0c7984 */
/* 0x000e620000000800 */
/*04e0*/ LOP3.LUT R11, R9, R8, RZ, 0xfc, !PT ; /* 0x00000008090b7212 */
/* 0x001fc800078efcff */
/*04f0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fc80003f06270 */
/*0500*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x16c], !P0 ; /* 0x00005b0008007a0c */
/* 0x000fc80004706670 */
/*0510*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x170], P0 ; /* 0x00005c0009007a0c */
/* 0x000fc80000706670 */
/*0520*/ ISETP.LT.OR P0, PT, R12, RZ, P0 ; /* 0x000000ff0c00720c */
/* 0x002fc80000701670 */
/*0530*/ ISETP.GE.OR P0, PT, R12, c[0x0][0x174], P0 ; /* 0x00005d000c007a0c */
/* 0x000fc80000706670 */
/*0540*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x168], P0 ; /* 0x00005a0003007a0c */
/* 0x000fda0000706670 */
/*0550*/ @P0 BRA 0xba0 ; /* 0x0000064000000947 */
/* 0x000fea0003800000 */
/*0560*/ IABS R14, c[0x0][0x164] ; /* 0x00005900000e7a13 */
/* 0x000fe20000000000 */
/*0570*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*0580*/ IABS R16, R22 ; /* 0x0000001600107213 */
/* 0x000fe20000000000 */
/*0590*/ BSSY B1, 0x8c0 ; /* 0x0000032000017945 */
/* 0x000fe20003800000 */
/*05a0*/ I2F.RP R12, R14 ; /* 0x0000000e000c7306 */
/* 0x000e220000209400 */
/*05b0*/ IMAD.MOV.U32 R23, RZ, RZ, R3 ; /* 0x000000ffff177224 */
/* 0x000fce00078e0003 */
/*05c0*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x001e240000001000 */
/*05d0*/ IADD3 R13, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c0d7810 */
/* 0x001fcc0007ffe0ff */
/*05e0*/ F2I.FTZ.U32.TRUNC.NTZ R11, R13 ; /* 0x0000000d000b7305 */
/* 0x000e24000021f000 */
/*05f0*/ IMAD.MOV R15, RZ, RZ, -R11 ; /* 0x000000ffff0f7224 */
/* 0x001fc800078e0a0b */
/*0600*/ IMAD R15, R15, R14, RZ ; /* 0x0000000e0f0f7224 */
/* 0x000fc800078e02ff */
/*0610*/ IMAD.HI.U32 R10, R11, R15, R10 ; /* 0x0000000f0b0a7227 */
/* 0x000fc800078e000a */
/*0620*/ IMAD.MOV.U32 R11, RZ, RZ, R16 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0010 */
/*0630*/ IMAD.HI.U32 R10, R10, R11, RZ ; /* 0x0000000b0a0a7227 */
/* 0x000fc800078e00ff */
/*0640*/ IMAD.MOV R12, RZ, RZ, -R10 ; /* 0x000000ffff0c7224 */
/* 0x000fc800078e0a0a */
/*0650*/ IMAD R11, R14, R12, R11 ; /* 0x0000000c0e0b7224 */
/* 0x000fca00078e020b */
/*0660*/ ISETP.GT.U32.AND P1, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x000fda0003f24070 */
/*0670*/ @!P1 IMAD.IADD R11, R11, 0x1, -R14 ; /* 0x000000010b0b9824 */
/* 0x000fe200078e0a0e */
/*0680*/ @!P1 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a9810 */
/* 0x000fe40007ffe0ff */
/*0690*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fe40003f25270 */
/*06a0*/ ISETP.GE.U32.AND P0, PT, R11, R14, PT ; /* 0x0000000e0b00720c */
/* 0x000fe40003f06070 */
/*06b0*/ LOP3.LUT R11, R22, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x00005900160b7a12 */
/* 0x000fc800078e3cff */
/*06c0*/ ISETP.GE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fce0003f46270 */
/*06d0*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*06f0*/ @!P2 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0aa224 */
/* 0x000fe200078e0a0a */
/*0700*/ @!P1 LOP3.LUT R10, RZ, c[0x0][0x164], RZ, 0x33, !PT ; /* 0x00005900ff0a9a12 */
/* 0x000fca00078e33ff */
/*0710*/ IMAD R9, R10, c[0x0][0x170], R9 ; /* 0x00005c000a097a24 */
/* 0x000fc800078e0209 */
/*0720*/ IMAD R12, R9, c[0x0][0x16c], R8 ; /* 0x00005b00090c7a24 */
/* 0x000fe200078e0208 */
/*0730*/ @!P0 BRA 0x8b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0740*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0750*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe400078e00ff */
/*0760*/ IMAD R8, R22, c[0x0][0x168], R3 ; /* 0x00005a0016087a24 */
/* 0x001fc800078e0203 */
/*0770*/ IMAD.WIDE R8, R8, R15, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x000fca00078e020f */
/*0780*/ LDG.E R13, [R8.64] ; /* 0x00000006080d7981 */
/* 0x000ea2000c1e1900 */
/*0790*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f05270 */
/*07a0*/ IMAD R14, R12, c[0x0][0x168], R3 ; /* 0x00005a000c0e7a24 */
/* 0x000fc800078e0203 */
/*07b0*/ IMAD.WIDE R10, R14, R15, c[0x0][0x188] ; /* 0x000062000e0a7625 */
/* 0x000fe200078e020f */
/*07c0*/ IADD3 R23, R3, 0x20, RZ ; /* 0x0000002003177810 */
/* 0x000fc80007ffe0ff */
/*07d0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R10.64], R13 ; /* 0x0000000d0a00798e */
/* 0x0041e6000c10e786 */
/*07e0*/ @!P0 BRA 0x8b0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*07f0*/ LDG.E R13, [R8.64+0x80] ; /* 0x00008006080d7981 */
/* 0x001ea2000c1e1900 */
/*0800*/ ISETP.NE.AND P0, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x000fe40003f05270 */
/*0810*/ IADD3 R10, R14, 0x20, RZ ; /* 0x000000200e0a7810 */
/* 0x000fca0007ffe0ff */
/*0820*/ IMAD.WIDE R10, R10, R15, c[0x0][0x188] ; /* 0x000062000a0a7625 */
/* 0x000fc800078e020f */
/*0830*/ IMAD.MOV.U32 R23, RZ, RZ, R4 ; /* 0x000000ffff177224 */
/* 0x000fe200078e0004 */
/*0840*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R10.64], R13 ; /* 0x0000000d0a00798e */
/* 0x0041e2000c10e786 */
/*0850*/ @!P0 BRA 0x8b0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0860*/ LDG.E R9, [R8.64+0x100] ; /* 0x0001000608097981 */
/* 0x000ea2000c1e1900 */
/*0870*/ IMAD R10, R12, c[0x0][0x168], R4 ; /* 0x00005a000c0a7a24 */
/* 0x001fc800078e0204 */
/*0880*/ IMAD.WIDE R10, R10, R15, c[0x0][0x188] ; /* 0x000062000a0a7625 */
/* 0x000fca00078e020f */
/*0890*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R10.64], R9 ; /* 0x000000090a00798e */
/* 0x0041e2000c10e786 */
/*08a0*/ MOV R23, R6 ; /* 0x0000000600177202 */
/* 0x000fc60000000f00 */
/*08b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08c0*/ ISETP.GE.U32.AND P0, PT, R2, 0x60, PT ; /* 0x000000600200780c */
/* 0x000fda0003f06070 */
/*08d0*/ @!P0 BRA 0xba0 ; /* 0x000002c000008947 */
/* 0x000fea0003800000 */
/*08e0*/ IMAD R8, R12, c[0x0][0x168], R23.reuse ; /* 0x00005a000c087a24 */
/* 0x100fe400078e0217 */
/*08f0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fe400078e00ff */
/*0900*/ IMAD R22, R22, c[0x0][0x168], R23 ; /* 0x00005a0016167a24 */
/* 0x000fe200078e0217 */
/*0910*/ IADD3 R10, R8.reuse, 0x60, RZ ; /* 0x00000060080a7810 */
/* 0x041fe20007ffe0ff */
/*0920*/ IMAD.WIDE R20, R8.reuse, R19.reuse, c[0x0][0x188] ; /* 0x0000620008147625 */
/* 0x0c0fe200078e0213 */
/*0930*/ IADD3 R12, R8.reuse, 0x40, RZ ; /* 0x00000040080c7810 */
/* 0x040fe40007ffe0ff */
/*0940*/ IADD3 R18, R8, 0x20, RZ ; /* 0x0000002008127810 */
/* 0x000fe20007ffe0ff */
/*0950*/ IMAD.WIDE R10, R10, R19, c[0x0][0x188] ; /* 0x000062000a0a7625 */
/* 0x000fc800078e0213 */
/*0960*/ IMAD.WIDE R12, R12, R19, c[0x0][0x188] ; /* 0x000062000c0c7625 */
/* 0x000fc800078e0213 */
/*0970*/ IMAD.MOV.U32 R24, RZ, RZ, R10 ; /* 0x000000ffff187224 */
/* 0x000fe400078e000a */
/*0980*/ IMAD.WIDE R18, R18, R19, c[0x0][0x188] ; /* 0x0000620012127625 */
/* 0x000fc800078e0213 */
/*0990*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000c */
/*09a0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x000fe400078e00ff */
/*09b0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fc800078e00ff */
/*09c0*/ IMAD.WIDE R14, R22, 0x4, R8 ; /* 0x00000004160e7825 */
/* 0x001fca00078e0208 */
/*09d0*/ LDG.E R25, [R14.64] ; /* 0x000000060e197981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ IMAD.MOV.U32 R16, RZ, RZ, R20 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0014 */
/*09f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0a00*/ IMAD.MOV.U32 R17, RZ, RZ, R21 ; /* 0x000000ffff117224 */
/* 0x000fca00078e0015 */
/*0a10*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R16.64], R25 ; /* 0x000000191000798e */
/* 0x0041e8000c10e786 */
/*0a20*/ LDG.E R27, [R14.64+0x80] ; /* 0x000080060e1b7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IMAD.MOV.U32 R16, RZ, RZ, R18 ; /* 0x000000ffff107224 */
/* 0x001fe400078e0012 */
/*0a40*/ IMAD.MOV.U32 R17, RZ, RZ, R19 ; /* 0x000000ffff117224 */
/* 0x000fca00078e0013 */
/*0a50*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R16.64], R27 ; /* 0x0000001b1000798e */
/* 0x004fe8000c10e786 */
/*0a60*/ LDG.E R29, [R14.64+0x100] ; /* 0x000100060e1d7981 */
/* 0x000ea2000c1e1900 */
/*0a70*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000a */
/*0a80*/ IADD3 R23, R23, 0x80, RZ ; /* 0x0000008017177810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.GE.AND P0, PT, R23, c[0x0][0x168], PT ; /* 0x00005a0017007a0c */
/* 0x000fe20003f06270 */
/*0aa0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64], R29 ; /* 0x0000001d0c00798e */
/* 0x0041e8000c10e786 */
/*0ab0*/ LDG.E R26, [R14.64+0x180] ; /* 0x000180060e1a7981 */
/* 0x0002a2000c1e1900 */
/*0ac0*/ IADD3 R8, P1, R8, 0x200, RZ ; /* 0x0000020008087810 */
/* 0x000fe40007f3e0ff */
/*0ad0*/ IADD3 R10, P3, R10, 0x200, RZ ; /* 0x000002000a0a7810 */
/* 0x000fe40007f7e0ff */
/*0ae0*/ IADD3 R18, P4, R18, 0x200, RZ ; /* 0x0000020012127810 */
/* 0x000fc40007f9e0ff */
/*0af0*/ IADD3 R20, P5, R20, 0x200, RZ ; /* 0x0000020014147810 */
/* 0x000fe40007fbe0ff */
/*0b00*/ MOV R14, R24 ; /* 0x00000018000e7202 */
/* 0x002fe20000000f00 */
/*0b10*/ IMAD.MOV.U32 R15, RZ, RZ, R11 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e000b */
/*0b20*/ IADD3 R24, P2, R24, 0x200, RZ ; /* 0x0000020018187810 */
/* 0x000fe20007f5e0ff */
/*0b30*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe400008e0609 */
/*0b40*/ IMAD.X R13, RZ, RZ, R13, P3 ; /* 0x000000ffff0d7224 */
/* 0x001fe400018e060d */
/*0b50*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe400010e060b */
/*0b60*/ IMAD.X R19, RZ, RZ, R19, P4 ; /* 0x000000ffff137224 */
/* 0x000fc400020e0613 */
/*0b70*/ IMAD.X R21, RZ, RZ, R21, P5 ; /* 0x000000ffff157224 */
/* 0x000fe200028e0615 */
/*0b80*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64], R26 ; /* 0x0000001a0e00798e */
/* 0x0041e2000c10e786 */
/*0b90*/ @!P0 BRA 0x9c0 ; /* 0xfffffe2000008947 */
/* 0x000fea000383ffff */
/*0ba0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0bb0*/ IADD3 R8, R0.reuse, 0x4, RZ ; /* 0x0000000400087810 */
/* 0x040fe40007ffe0ff */
/*0bc0*/ ISETP.LT.AND P1, PT, R0, 0x7c, PT ; /* 0x0000007c0000780c */
/* 0x000fc60003f21270 */
/*0bd0*/ IMAD R22, R5, 0x80, R8.reuse ; /* 0x0000008005167824 */
/* 0x100fe400078e0208 */
/*0be0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0008 */
/*0bf0*/ ISETP.GE.AND P0, PT, R22, UR4, PT ; /* 0x0000000416007c0c */
/* 0x000fda000bf06270 */
/*0c00*/ @!P0 BRA P1, 0x480 ; /* 0xfffff87000008947 */
/* 0x000fea000083ffff */
/*0c10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c20*/ BRA 0xc20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Copyright (c) Megvii Inc. All rights reserved.
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define THREADS_BLOCK_X 32
#define THREADS_BLOCK_Y 4
#define THREADS_PER_BLOCK THREADS_BLOCK_X * THREADS_BLOCK_Y
#define DIVUP(m, n) ((m) / (n) + ((m) % (n) > 0))
__global__ void voxel_pooling_forward_kernel(int batch_size, int num_points, int num_channels, int num_voxel_x, int num_voxel_y, int num_voxel_z, const int *geom_xyz, const float *input_features,
float *output_features, int *pos_memo) {
const int bidx = blockIdx.x;
const int tidx = threadIdx.x;
const int tidy = threadIdx.y;
const int sample_dim = THREADS_PER_BLOCK;
const int idx_in_block = tidy * THREADS_BLOCK_X + tidx;
const int block_sample_idx = bidx * sample_dim;
const int thread_sample_idx = block_sample_idx + idx_in_block;
const int total_samples = batch_size * num_points;
__shared__ int geom_xyz_shared[THREADS_PER_BLOCK * 3];
if (thread_sample_idx < total_samples) {
const int sample_x = geom_xyz[thread_sample_idx * 3 + 0];
const int sample_y = geom_xyz[thread_sample_idx * 3 + 1];
const int sample_z = geom_xyz[thread_sample_idx * 3 + 2];
geom_xyz_shared[idx_in_block * 3 + 0] = sample_x;
geom_xyz_shared[idx_in_block * 3 + 1] = sample_y;
geom_xyz_shared[idx_in_block * 3 + 2] = sample_z;
if ((sample_x >= 0 && sample_x < num_voxel_x) && (sample_y >= 0 && sample_y < num_voxel_y) && (sample_z >= 0 && sample_z < num_voxel_z)) {
pos_memo[thread_sample_idx * 3 + 0] = thread_sample_idx / num_points;
pos_memo[thread_sample_idx * 3 + 1] = sample_y;
pos_memo[thread_sample_idx * 3 + 2] = sample_x;
}
}
__syncthreads();
for (int i = tidy; i < THREADS_PER_BLOCK && block_sample_idx + i < total_samples; i += THREADS_BLOCK_Y) {
const int sample_x = geom_xyz_shared[i * 3 + 0];
const int sample_y = geom_xyz_shared[i * 3 + 1];
const int sample_z = geom_xyz_shared[i * 3 + 2];
if (sample_x < 0 || sample_x >= num_voxel_x || sample_y < 0 || sample_y >= num_voxel_y || sample_z < 0 || sample_z >= num_voxel_z) {
continue;
}
const int batch_idx = (block_sample_idx + i) / num_points;
for (int j = tidx; j < num_channels; j += THREADS_BLOCK_X) {
atomicAdd(&output_features[(batch_idx * num_voxel_y * num_voxel_x + sample_y * num_voxel_x + sample_x) * num_channels + j], input_features[(block_sample_idx + i) * num_channels + j]);
}
}
}
void voxel_pooling_forward_kernel_launcher(int batch_size, int num_points, int num_channels, int num_voxel_x, int num_voxel_y, int num_voxel_z, const int *geom_xyz, const float *input_features,
float *output_features, int *pos_memo, cudaStream_t stream) {
cudaError_t err;
dim3 blocks(DIVUP(batch_size * num_points, THREADS_PER_BLOCK));
dim3 threads(THREADS_BLOCK_X, THREADS_BLOCK_Y);
voxel_pooling_forward_kernel<<<blocks, threads, 0, stream>>>(batch_size, num_points, num_channels, num_voxel_x, num_voxel_y, num_voxel_z, geom_xyz, input_features, output_features, pos_memo);
err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", cudaGetErrorString(err));
exit(-1);
}
} | .file "tmpxft_00143ca1_00000000-6_voxel_pooling_forward_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
.type _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi, @function
_Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi:
.LFB2082:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movl %r9d, 40(%rsp)
movq 240(%rsp), %rax
movq %rax, 32(%rsp)
movq 248(%rsp), %rax
movq %rax, 24(%rsp)
movq 256(%rsp), %rax
movq %rax, 16(%rsp)
movq 264(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi, .-_Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
.globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, @function
_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .-_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA kernel failed : %s\n"
.text
.globl _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st
.type _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st, @function
_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movl %edi, %edx
imull %esi, %edx
movl %edx, %ecx
sarl $31, %ecx
shrl $25, %ecx
leal (%rdx,%rcx), %eax
andl $127, %eax
subl %ecx, %eax
testl %eax, %eax
setg %cl
movzbl %cl, %ecx
leal 127(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $7, %eax
addl %ecx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $32, 20(%rsp)
movl $4, 24(%rsp)
movq 128(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L16
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st, .-_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Copyright (c) Megvii Inc. All rights reserved.
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define THREADS_BLOCK_X 32
#define THREADS_BLOCK_Y 4
#define THREADS_PER_BLOCK THREADS_BLOCK_X * THREADS_BLOCK_Y
#define DIVUP(m, n) ((m) / (n) + ((m) % (n) > 0))
__global__ void voxel_pooling_forward_kernel(int batch_size, int num_points, int num_channels, int num_voxel_x, int num_voxel_y, int num_voxel_z, const int *geom_xyz, const float *input_features,
float *output_features, int *pos_memo) {
const int bidx = blockIdx.x;
const int tidx = threadIdx.x;
const int tidy = threadIdx.y;
const int sample_dim = THREADS_PER_BLOCK;
const int idx_in_block = tidy * THREADS_BLOCK_X + tidx;
const int block_sample_idx = bidx * sample_dim;
const int thread_sample_idx = block_sample_idx + idx_in_block;
const int total_samples = batch_size * num_points;
__shared__ int geom_xyz_shared[THREADS_PER_BLOCK * 3];
if (thread_sample_idx < total_samples) {
const int sample_x = geom_xyz[thread_sample_idx * 3 + 0];
const int sample_y = geom_xyz[thread_sample_idx * 3 + 1];
const int sample_z = geom_xyz[thread_sample_idx * 3 + 2];
geom_xyz_shared[idx_in_block * 3 + 0] = sample_x;
geom_xyz_shared[idx_in_block * 3 + 1] = sample_y;
geom_xyz_shared[idx_in_block * 3 + 2] = sample_z;
if ((sample_x >= 0 && sample_x < num_voxel_x) && (sample_y >= 0 && sample_y < num_voxel_y) && (sample_z >= 0 && sample_z < num_voxel_z)) {
pos_memo[thread_sample_idx * 3 + 0] = thread_sample_idx / num_points;
pos_memo[thread_sample_idx * 3 + 1] = sample_y;
pos_memo[thread_sample_idx * 3 + 2] = sample_x;
}
}
__syncthreads();
for (int i = tidy; i < THREADS_PER_BLOCK && block_sample_idx + i < total_samples; i += THREADS_BLOCK_Y) {
const int sample_x = geom_xyz_shared[i * 3 + 0];
const int sample_y = geom_xyz_shared[i * 3 + 1];
const int sample_z = geom_xyz_shared[i * 3 + 2];
if (sample_x < 0 || sample_x >= num_voxel_x || sample_y < 0 || sample_y >= num_voxel_y || sample_z < 0 || sample_z >= num_voxel_z) {
continue;
}
const int batch_idx = (block_sample_idx + i) / num_points;
for (int j = tidx; j < num_channels; j += THREADS_BLOCK_X) {
atomicAdd(&output_features[(batch_idx * num_voxel_y * num_voxel_x + sample_y * num_voxel_x + sample_x) * num_channels + j], input_features[(block_sample_idx + i) * num_channels + j]);
}
}
}
void voxel_pooling_forward_kernel_launcher(int batch_size, int num_points, int num_channels, int num_voxel_x, int num_voxel_y, int num_voxel_z, const int *geom_xyz, const float *input_features,
float *output_features, int *pos_memo, cudaStream_t stream) {
cudaError_t err;
dim3 blocks(DIVUP(batch_size * num_points, THREADS_PER_BLOCK));
dim3 threads(THREADS_BLOCK_X, THREADS_BLOCK_Y);
voxel_pooling_forward_kernel<<<blocks, threads, 0, stream>>>(batch_size, num_points, num_channels, num_voxel_x, num_voxel_y, num_voxel_z, geom_xyz, input_features, output_features, pos_memo);
err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", cudaGetErrorString(err));
exit(-1);
}
} | // Copyright (c) Megvii Inc. All rights reserved.
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define THREADS_BLOCK_X 32
#define THREADS_BLOCK_Y 4
#define THREADS_PER_BLOCK THREADS_BLOCK_X * THREADS_BLOCK_Y
#define DIVUP(m, n) ((m) / (n) + ((m) % (n) > 0))
__global__ void voxel_pooling_forward_kernel(int batch_size, int num_points, int num_channels, int num_voxel_x, int num_voxel_y, int num_voxel_z, const int *geom_xyz, const float *input_features,
float *output_features, int *pos_memo) {
const int bidx = blockIdx.x;
const int tidx = threadIdx.x;
const int tidy = threadIdx.y;
const int sample_dim = THREADS_PER_BLOCK;
const int idx_in_block = tidy * THREADS_BLOCK_X + tidx;
const int block_sample_idx = bidx * sample_dim;
const int thread_sample_idx = block_sample_idx + idx_in_block;
const int total_samples = batch_size * num_points;
__shared__ int geom_xyz_shared[THREADS_PER_BLOCK * 3];
if (thread_sample_idx < total_samples) {
const int sample_x = geom_xyz[thread_sample_idx * 3 + 0];
const int sample_y = geom_xyz[thread_sample_idx * 3 + 1];
const int sample_z = geom_xyz[thread_sample_idx * 3 + 2];
geom_xyz_shared[idx_in_block * 3 + 0] = sample_x;
geom_xyz_shared[idx_in_block * 3 + 1] = sample_y;
geom_xyz_shared[idx_in_block * 3 + 2] = sample_z;
if ((sample_x >= 0 && sample_x < num_voxel_x) && (sample_y >= 0 && sample_y < num_voxel_y) && (sample_z >= 0 && sample_z < num_voxel_z)) {
pos_memo[thread_sample_idx * 3 + 0] = thread_sample_idx / num_points;
pos_memo[thread_sample_idx * 3 + 1] = sample_y;
pos_memo[thread_sample_idx * 3 + 2] = sample_x;
}
}
__syncthreads();
for (int i = tidy; i < THREADS_PER_BLOCK && block_sample_idx + i < total_samples; i += THREADS_BLOCK_Y) {
const int sample_x = geom_xyz_shared[i * 3 + 0];
const int sample_y = geom_xyz_shared[i * 3 + 1];
const int sample_z = geom_xyz_shared[i * 3 + 2];
if (sample_x < 0 || sample_x >= num_voxel_x || sample_y < 0 || sample_y >= num_voxel_y || sample_z < 0 || sample_z >= num_voxel_z) {
continue;
}
const int batch_idx = (block_sample_idx + i) / num_points;
for (int j = tidx; j < num_channels; j += THREADS_BLOCK_X) {
atomicAdd(&output_features[(batch_idx * num_voxel_y * num_voxel_x + sample_y * num_voxel_x + sample_x) * num_channels + j], input_features[(block_sample_idx + i) * num_channels + j]);
}
}
}
void voxel_pooling_forward_kernel_launcher(int batch_size, int num_points, int num_channels, int num_voxel_x, int num_voxel_y, int num_voxel_z, const int *geom_xyz, const float *input_features,
float *output_features, int *pos_memo, hipStream_t stream) {
hipError_t err;
dim3 blocks(DIVUP(batch_size * num_points, THREADS_PER_BLOCK));
dim3 threads(THREADS_BLOCK_X, THREADS_BLOCK_Y);
voxel_pooling_forward_kernel<<<blocks, threads, 0, stream>>>(batch_size, num_points, num_channels, num_voxel_x, num_voxel_y, num_voxel_z, geom_xyz, input_features, output_features, pos_memo);
err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", hipGetErrorString(err));
exit(-1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Copyright (c) Megvii Inc. All rights reserved.
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define THREADS_BLOCK_X 32
#define THREADS_BLOCK_Y 4
#define THREADS_PER_BLOCK THREADS_BLOCK_X * THREADS_BLOCK_Y
#define DIVUP(m, n) ((m) / (n) + ((m) % (n) > 0))
__global__ void voxel_pooling_forward_kernel(int batch_size, int num_points, int num_channels, int num_voxel_x, int num_voxel_y, int num_voxel_z, const int *geom_xyz, const float *input_features,
float *output_features, int *pos_memo) {
const int bidx = blockIdx.x;
const int tidx = threadIdx.x;
const int tidy = threadIdx.y;
const int sample_dim = THREADS_PER_BLOCK;
const int idx_in_block = tidy * THREADS_BLOCK_X + tidx;
const int block_sample_idx = bidx * sample_dim;
const int thread_sample_idx = block_sample_idx + idx_in_block;
const int total_samples = batch_size * num_points;
__shared__ int geom_xyz_shared[THREADS_PER_BLOCK * 3];
if (thread_sample_idx < total_samples) {
const int sample_x = geom_xyz[thread_sample_idx * 3 + 0];
const int sample_y = geom_xyz[thread_sample_idx * 3 + 1];
const int sample_z = geom_xyz[thread_sample_idx * 3 + 2];
geom_xyz_shared[idx_in_block * 3 + 0] = sample_x;
geom_xyz_shared[idx_in_block * 3 + 1] = sample_y;
geom_xyz_shared[idx_in_block * 3 + 2] = sample_z;
if ((sample_x >= 0 && sample_x < num_voxel_x) && (sample_y >= 0 && sample_y < num_voxel_y) && (sample_z >= 0 && sample_z < num_voxel_z)) {
pos_memo[thread_sample_idx * 3 + 0] = thread_sample_idx / num_points;
pos_memo[thread_sample_idx * 3 + 1] = sample_y;
pos_memo[thread_sample_idx * 3 + 2] = sample_x;
}
}
__syncthreads();
for (int i = tidy; i < THREADS_PER_BLOCK && block_sample_idx + i < total_samples; i += THREADS_BLOCK_Y) {
const int sample_x = geom_xyz_shared[i * 3 + 0];
const int sample_y = geom_xyz_shared[i * 3 + 1];
const int sample_z = geom_xyz_shared[i * 3 + 2];
if (sample_x < 0 || sample_x >= num_voxel_x || sample_y < 0 || sample_y >= num_voxel_y || sample_z < 0 || sample_z >= num_voxel_z) {
continue;
}
const int batch_idx = (block_sample_idx + i) / num_points;
for (int j = tidx; j < num_channels; j += THREADS_BLOCK_X) {
atomicAdd(&output_features[(batch_idx * num_voxel_y * num_voxel_x + sample_y * num_voxel_x + sample_x) * num_channels + j], input_features[(block_sample_idx + i) * num_channels + j]);
}
}
}
void voxel_pooling_forward_kernel_launcher(int batch_size, int num_points, int num_channels, int num_voxel_x, int num_voxel_y, int num_voxel_z, const int *geom_xyz, const float *input_features,
float *output_features, int *pos_memo, hipStream_t stream) {
hipError_t err;
dim3 blocks(DIVUP(batch_size * num_points, THREADS_PER_BLOCK));
dim3 threads(THREADS_BLOCK_X, THREADS_BLOCK_Y);
voxel_pooling_forward_kernel<<<blocks, threads, 0, stream>>>(batch_size, num_points, num_channels, num_voxel_x, num_voxel_y, num_voxel_z, geom_xyz, input_features, output_features, pos_memo);
err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", hipGetErrorString(err));
exit(-1);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.p2align 8
.type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@function
_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi:
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0xc
s_load_b32 s10, s[0:1], 0x14
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u32 v7, v0, 10, 10
s_lshl_b32 s11, s15, 7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v11, v7, 5, v6
v_add_nc_u32_e32 v9, s11, v11
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s5, s4
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v9
s_cbranch_execz .LBB0_5
s_load_b64 s[2:3], s[0:1], 0x18
v_lshl_add_u32 v0, v9, 1, v9
v_mul_u32_u24_e32 v11, 3, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v4, 2, v0
v_lshlrev_b32_e32 v11, 2, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[12:13], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[14:15], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[16:17], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s2, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
s_clause 0x2
global_load_b32 v8, v[12:13], off
global_load_b32 v10, v[14:15], off
global_load_b32 v12, v[16:17], off
s_waitcnt vmcnt(1)
ds_store_2addr_b32 v11, v8, v10 offset1:1
s_waitcnt vmcnt(0)
ds_store_b32 v11, v12 offset:8
v_cmp_lt_i32_e32 vcc_lo, -1, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_cmp_gt_i32_e32 vcc_lo, s8, v8
v_cmp_lt_i32_e64 s2, -1, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_5
v_cmp_gt_i32_e32 vcc_lo, s9, v10
v_cmp_gt_i32_e64 s2, s10, v12
v_cmp_lt_i32_e64 s3, -1, v12
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_5
s_ashr_i32 s6, s5, 31
v_ashrrev_i32_e32 v13, 31, v9
s_add_i32 s2, s5, s6
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_xor_b32 s7, s2, s6
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_cvt_f32_u32_e32 v11, s7
s_sub_i32 s2, 0, s7
v_add_nc_u32_e32 v9, v9, v13
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v11, v11
v_xor_b32_e32 v9, v9, v13
v_xor_b32_e32 v13, s6, v13
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v11, 0x4f7ffffe, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v11, v11
v_mul_lo_u32 v12, s2, v11
s_load_b64 s[2:3], s[0:1], 0x30
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v12, v11, v12
v_add_nc_u32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v11, v9, v11
v_mul_lo_u32 v12, v11, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v9, v12
v_subrev_nc_u32_e32 v14, s7, v9
v_cmp_le_u32_e32 vcc_lo, s7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v9, v9, v14 :: v_dual_add_nc_u32 v12, 1, v11
v_cndmask_b32_e32 v11, v11, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s7, v9
v_add_nc_u32_e32 v12, 1, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v11, v12, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_xor_b32_e32 v9, v9, v13
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_sub_nc_u32_e32 v9, v9, v13
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x2
global_store_b32 v[0:1], v9, off
global_store_b32 v[2:3], v10, off
global_store_b32 v[4:5], v8, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x80, v7
s_cbranch_execz .LBB0_17
s_ashr_i32 s3, s5, 31
s_load_b32 s14, s[0:1], 0x8
s_add_i32 s2, s5, s3
s_load_b128 s[4:7], s[0:1], 0x20
s_xor_b32 s13, s2, s3
s_mov_b32 s15, 0
v_cvt_f32_u32_e32 v0, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s14, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v4, v0
s_branch .LBB0_9
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s18
v_cmp_lt_u32_e64 s0, 0x7b, v7
v_add_nc_u32_e32 v0, 4, v7
s_and_not1_b32 s1, s16, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_or_b32 s16, s1, s0
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s17
v_mov_b32_e32 v7, v0
s_and_b32 s0, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s15, s0, s15
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB0_17
.LBB0_9:
v_or_b32_e32 v2, s11, v7
s_or_b32 s16, s16, exec_lo
s_mov_b32 s17, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v2
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v0, v7, 1, v7
s_mov_b32 s18, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v0
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 -1, v0
s_cbranch_execz .LBB0_7
ds_load_b32 v1, v3 offset:4
v_cmp_gt_i32_e64 s0, s8, v0
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e64 s1, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
ds_load_b32 v3, v3 offset:8
v_cmp_le_i32_e64 s0, s9, v1
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e64 s1, s10, v3
v_cmp_gt_i32_e64 s2, 0, v3
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, vcc_lo
s_xor_b32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
s_sub_i32 s0, 0, s13
v_ashrrev_i32_e32 v5, 31, v2
v_mul_lo_u32 v3, s0, v4
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v2, v5
v_mul_hi_u32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v8, v8, v5
v_xor_b32_e32 v5, s3, v5
v_add_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v8, v3
v_mul_lo_u32 v9, v3, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v8, v9
v_add_nc_u32_e32 v9, 1, v3
v_subrev_nc_u32_e32 v10, s13, v8
v_cmp_le_u32_e64 s0, s13, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v9, s0
v_cndmask_b32_e64 v8, v8, v10, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, 1, v3
v_cmp_le_u32_e64 s0, s13, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v9, s0
v_xor_b32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v5
v_mad_u64_u32 v[8:9], null, v3, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[9:10], null, v8, s8, v[0:1]
v_mul_lo_u32 v8, v2, s14
v_mul_lo_u32 v5, v9, s14
v_mov_b32_e32 v9, v6
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_14:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v0, v9, v8
v_add_nc_u32_e32 v2, v9, v5
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s0, s4, v0
v_add_co_ci_u32_e64 v11, s0, s5, v1, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s6, v2
v_add_co_ci_u32_e64 v1, s0, s7, v3, s0
global_load_b32 v10, v[10:11], off
global_load_b32 v3, v[0:1], off
.LBB0_15:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v10
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v2, v3
v_mov_b32_e32 v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s0, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_15
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v9, 32, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s14, v9
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_14
s_branch .LBB0_7
.LBB0_17:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.amdhsa_group_segment_fixed_size 1536
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .Lfunc_end0-_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1536
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Copyright (c) Megvii Inc. All rights reserved.
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define THREADS_BLOCK_X 32
#define THREADS_BLOCK_Y 4
#define THREADS_PER_BLOCK THREADS_BLOCK_X * THREADS_BLOCK_Y
#define DIVUP(m, n) ((m) / (n) + ((m) % (n) > 0))
__global__ void voxel_pooling_forward_kernel(int batch_size, int num_points, int num_channels, int num_voxel_x, int num_voxel_y, int num_voxel_z, const int *geom_xyz, const float *input_features,
float *output_features, int *pos_memo) {
const int bidx = blockIdx.x;
const int tidx = threadIdx.x;
const int tidy = threadIdx.y;
const int sample_dim = THREADS_PER_BLOCK;
const int idx_in_block = tidy * THREADS_BLOCK_X + tidx;
const int block_sample_idx = bidx * sample_dim;
const int thread_sample_idx = block_sample_idx + idx_in_block;
const int total_samples = batch_size * num_points;
__shared__ int geom_xyz_shared[THREADS_PER_BLOCK * 3];
if (thread_sample_idx < total_samples) {
const int sample_x = geom_xyz[thread_sample_idx * 3 + 0];
const int sample_y = geom_xyz[thread_sample_idx * 3 + 1];
const int sample_z = geom_xyz[thread_sample_idx * 3 + 2];
geom_xyz_shared[idx_in_block * 3 + 0] = sample_x;
geom_xyz_shared[idx_in_block * 3 + 1] = sample_y;
geom_xyz_shared[idx_in_block * 3 + 2] = sample_z;
if ((sample_x >= 0 && sample_x < num_voxel_x) && (sample_y >= 0 && sample_y < num_voxel_y) && (sample_z >= 0 && sample_z < num_voxel_z)) {
pos_memo[thread_sample_idx * 3 + 0] = thread_sample_idx / num_points;
pos_memo[thread_sample_idx * 3 + 1] = sample_y;
pos_memo[thread_sample_idx * 3 + 2] = sample_x;
}
}
__syncthreads();
for (int i = tidy; i < THREADS_PER_BLOCK && block_sample_idx + i < total_samples; i += THREADS_BLOCK_Y) {
const int sample_x = geom_xyz_shared[i * 3 + 0];
const int sample_y = geom_xyz_shared[i * 3 + 1];
const int sample_z = geom_xyz_shared[i * 3 + 2];
if (sample_x < 0 || sample_x >= num_voxel_x || sample_y < 0 || sample_y >= num_voxel_y || sample_z < 0 || sample_z >= num_voxel_z) {
continue;
}
const int batch_idx = (block_sample_idx + i) / num_points;
for (int j = tidx; j < num_channels; j += THREADS_BLOCK_X) {
atomicAdd(&output_features[(batch_idx * num_voxel_y * num_voxel_x + sample_y * num_voxel_x + sample_x) * num_channels + j], input_features[(block_sample_idx + i) * num_channels + j]);
}
}
}
void voxel_pooling_forward_kernel_launcher(int batch_size, int num_points, int num_channels, int num_voxel_x, int num_voxel_y, int num_voxel_z, const int *geom_xyz, const float *input_features,
float *output_features, int *pos_memo, hipStream_t stream) {
hipError_t err;
dim3 blocks(DIVUP(batch_size * num_points, THREADS_PER_BLOCK));
dim3 threads(THREADS_BLOCK_X, THREADS_BLOCK_Y);
voxel_pooling_forward_kernel<<<blocks, threads, 0, stream>>>(batch_size, num_points, num_channels, num_voxel_x, num_voxel_y, num_voxel_z, geom_xyz, input_features, output_features, pos_memo);
err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", hipGetErrorString(err));
exit(-1);
}
} | .text
.file "voxel_pooling_forward_cuda.hip"
.globl _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi # -- Begin function _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.p2align 4, 0x90
.type _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@function
_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi: # @_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .Lfunc_end0-_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.cfi_endproc
# -- End function
.globl _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t # -- Begin function _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t
.p2align 4, 0x90
.type _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t,@function
_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t: # @_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %esi, %eax
imull %edi, %eax
leal 127(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
movq 288(%rsp), %r9
sarl $7, %ecx
xorl %edx, %edx
testl $-2147483521, %eax # imm = 0x8000007F
setg %dl
addl %ecx, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdx, %rdi
movabsq $17179869216, %rdx # imm = 0x400000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 280(%rsp), %rax
movq 272(%rsp), %rcx
movq 264(%rsp), %rdx
movq 256(%rsp), %rsi
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
movq %rsi, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_4
# %bb.3:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t, .Lfunc_end1-_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@object # @_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.section .rodata,"a",@progbits
.globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.p2align 3, 0x0
_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi:
.quad _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA kernel failed : %s\n"
.size .L.str, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x400 ; /* 0x000003c000007945 */
/* 0x000fe20003800000 */
/*0040*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0080*/ IMAD R10, R0, 0x20, R3 ; /* 0x00000020000a7824 */
/* 0x001fc800078e0203 */
/*0090*/ IMAD R7, R5.reuse, 0x80, R10 ; /* 0x0000008005077824 */
/* 0x042fe400078e020a */
/*00a0*/ IMAD R22, R5, 0x80, R0 ; /* 0x0000008005167824 */
/* 0x000fc600078e0200 */
/*00b0*/ ISETP.GE.AND P1, PT, R7, UR4, PT ; /* 0x0000000407007c0c */
/* 0x000fe4000bf26270 */
/*00c0*/ ISETP.GE.AND P0, PT, R22, UR4, PT ; /* 0x0000000416007c0c */
/* 0x000fc8000bf06270 */
/*00d0*/ ISETP.GT.OR P0, PT, R0, 0x7f, P0 ; /* 0x0000007f0000780c */
/* 0x000fce0000704670 */
/*00e0*/ @P1 BRA 0x3f0 ; /* 0x0000030000001947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD R2, R7, 0x3, RZ ; /* 0x0000000307027824 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0120*/ LDG.E R4, [R8.64] ; /* 0x0000000608047981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R6, [R8.64+0x4] ; /* 0x0000040608067981 */
/* 0x000ee8000c1e1900 */
/*0140*/ LDG.E R11, [R8.64+0x8] ; /* 0x00000806080b7981 */
/* 0x000f22000c1e1900 */
/*0150*/ IMAD R13, R10, 0xc, RZ ; /* 0x0000000c0a0d7824 */
/* 0x000fe200078e02ff */
/*0160*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x004fc80003f26270 */
/*0170*/ STS [R13], R4 ; /* 0x000000040d007388 */
/* 0x0001e20000000800 */
/*0180*/ ISETP.GE.AND P2, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x008fc60003f46270 */
/*0190*/ STS [R13+0x4], R6 ; /* 0x000004060d007388 */
/* 0x0001e20000000800 */
/*01a0*/ ISETP.GT.AND P1, PT, R4, -0x1, !P1 ; /* 0xffffffff0400780c */
/* 0x000fe40004f24270 */
/*01b0*/ ISETP.GE.AND P3, PT, R11.reuse, c[0x0][0x174], PT ; /* 0x00005d000b007a0c */
/* 0x050fe20003f66270 */
/*01c0*/ STS [R13+0x8], R11 ; /* 0x0000080b0d007388 */
/* 0x0001e20000000800 */
/*01d0*/ ISETP.GT.AND P2, PT, R6, -0x1, !P2 ; /* 0xffffffff0600780c */
/* 0x000fe40005744270 */
/*01e0*/ ISETP.GT.AND P3, PT, R11, -0x1, !P3 ; /* 0xffffffff0b00780c */
/* 0x000fc80005f64270 */
/*01f0*/ PLOP3.LUT P1, PT, P3, P1, P2, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0001f23020 */
/*0200*/ @!P1 BRA 0x3f0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0210*/ IABS R11, c[0x0][0x164] ; /* 0x00005900000b7a13 */
/* 0x001fc80000000000 */
/*0220*/ I2F.RP R10, R11 ; /* 0x0000000b000a7306 */
/* 0x000e300000209400 */
/*0230*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0240*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fcc0007ffe0ff */
/*0250*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0270*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */
/* 0x002fc800078e0a09 */
/*0280*/ IMAD R13, R12, R11, RZ ; /* 0x0000000b0c0d7224 */
/* 0x000fe200078e02ff */
/*0290*/ IABS R12, R7 ; /* 0x00000007000c7213 */
/* 0x000fe40000000000 */
/*02a0*/ LOP3.LUT R7, R7, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x0000590007077a12 */
/* 0x000fe200078e3cff */
/*02b0*/ IMAD.HI.U32 R9, R9, R13, R8 ; /* 0x0000000d09097227 */
/* 0x000fc600078e0008 */
/*02c0*/ ISETP.GE.AND P3, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f66270 */
/*02d0*/ IMAD.HI.U32 R9, R9, R12, RZ ; /* 0x0000000c09097227 */
/* 0x000fc800078e00ff */
/*02e0*/ IMAD.MOV R10, RZ, RZ, -R9 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0a09 */
/*02f0*/ IMAD R10, R11, R10, R12 ; /* 0x0000000a0b0a7224 */
/* 0x000fca00078e020c */
/*0300*/ ISETP.GT.U32.AND P2, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x000fda0003f44070 */
/*0310*/ @!P2 IMAD.IADD R10, R10, 0x1, -R11 ; /* 0x000000010a0aa824 */
/* 0x000fe200078e0a0b */
/*0320*/ @!P2 IADD3 R9, R9, 0x1, RZ ; /* 0x000000010909a810 */
/* 0x000fe40007ffe0ff */
/*0330*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fe40003f45270 */
/*0340*/ ISETP.GE.U32.AND P1, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fe40003f26070 */
/*0350*/ SHF.R.S32.HI R11, RZ, 0x1f, R2 ; /* 0x0000001fff0b7819 */
/* 0x000fd60000011402 */
/*0360*/ @P1 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109091810 */
/* 0x000fe40007ffe0ff */
/*0370*/ LEA R8, P1, R2, c[0x0][0x190], 0x2 ; /* 0x0000640002087a11 */
/* 0x000fc600078210ff */
/*0380*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*0390*/ LEA.HI.X R9, R2, c[0x0][0x194], R11, 0x2, P1 ; /* 0x0000650002097a11 */
/* 0x000fc600008f140b */
/*03a0*/ @!P3 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07b224 */
/* 0x000fe200078e0a07 */
/*03b0*/ @!P2 LOP3.LUT R7, RZ, c[0x0][0x164], RZ, 0x33, !PT ; /* 0x00005900ff07aa12 */
/* 0x000fe200078e33ff */
/*03c0*/ STG.E [R8.64+0x4], R6 ; /* 0x0000040608007986 */
/* 0x0001e8000c101906 */
/*03d0*/ STG.E [R8.64+0x8], R4 ; /* 0x0000080408007986 */
/* 0x0001e8000c101906 */
/*03e0*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0001e4000c101906 */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0400*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0410*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0420*/ LOP3.LUT R2, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff027212 */
/* 0x000fe400078e33ff */
/*0430*/ IADD3 R4, R3, 0x40, RZ ; /* 0x0000004003047810 */
/* 0x000fc40007ffe0ff */
/*0440*/ IADD3 R2, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fe40007ffe0ff */
/*0450*/ IADD3 R6, R3, 0x60, RZ ; /* 0x0000006003067810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LEA.HI R7, R2, 0x1, RZ, 0x1b ; /* 0x0000000102077811 */
/* 0x000fc800078fd8ff */
/*0470*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fe400078ec0ff */
/*0480*/ IMAD R10, R0, 0xc, RZ ; /* 0x0000000c000a7824 */
/* 0x001fe200078e02ff */
/*0490*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*04a0*/ BSSY B0, 0xbb0 ; /* 0x0000070000007945 */
/* 0x000fe60003800000 */
/*04b0*/ LDS R8, [R10] ; /* 0x000000000a087984 */
/* 0x000fe80000000800 */
/*04c0*/ LDS R9, [R10+0x4] ; /* 0x000004000a097984 */
/* 0x000e280000000800 */
/*04d0*/ LDS R12, [R10+0x8] ; /* 0x000008000a0c7984 */
/* 0x000e620000000800 */
/*04e0*/ LOP3.LUT R11, R9, R8, RZ, 0xfc, !PT ; /* 0x00000008090b7212 */
/* 0x001fc800078efcff */
/*04f0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fc80003f06270 */
/*0500*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x16c], !P0 ; /* 0x00005b0008007a0c */
/* 0x000fc80004706670 */
/*0510*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x170], P0 ; /* 0x00005c0009007a0c */
/* 0x000fc80000706670 */
/*0520*/ ISETP.LT.OR P0, PT, R12, RZ, P0 ; /* 0x000000ff0c00720c */
/* 0x002fc80000701670 */
/*0530*/ ISETP.GE.OR P0, PT, R12, c[0x0][0x174], P0 ; /* 0x00005d000c007a0c */
/* 0x000fc80000706670 */
/*0540*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x168], P0 ; /* 0x00005a0003007a0c */
/* 0x000fda0000706670 */
/*0550*/ @P0 BRA 0xba0 ; /* 0x0000064000000947 */
/* 0x000fea0003800000 */
/*0560*/ IABS R14, c[0x0][0x164] ; /* 0x00005900000e7a13 */
/* 0x000fe20000000000 */
/*0570*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*0580*/ IABS R16, R22 ; /* 0x0000001600107213 */
/* 0x000fe20000000000 */
/*0590*/ BSSY B1, 0x8c0 ; /* 0x0000032000017945 */
/* 0x000fe20003800000 */
/*05a0*/ I2F.RP R12, R14 ; /* 0x0000000e000c7306 */
/* 0x000e220000209400 */
/*05b0*/ IMAD.MOV.U32 R23, RZ, RZ, R3 ; /* 0x000000ffff177224 */
/* 0x000fce00078e0003 */
/*05c0*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x001e240000001000 */
/*05d0*/ IADD3 R13, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c0d7810 */
/* 0x001fcc0007ffe0ff */
/*05e0*/ F2I.FTZ.U32.TRUNC.NTZ R11, R13 ; /* 0x0000000d000b7305 */
/* 0x000e24000021f000 */
/*05f0*/ IMAD.MOV R15, RZ, RZ, -R11 ; /* 0x000000ffff0f7224 */
/* 0x001fc800078e0a0b */
/*0600*/ IMAD R15, R15, R14, RZ ; /* 0x0000000e0f0f7224 */
/* 0x000fc800078e02ff */
/*0610*/ IMAD.HI.U32 R10, R11, R15, R10 ; /* 0x0000000f0b0a7227 */
/* 0x000fc800078e000a */
/*0620*/ IMAD.MOV.U32 R11, RZ, RZ, R16 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0010 */
/*0630*/ IMAD.HI.U32 R10, R10, R11, RZ ; /* 0x0000000b0a0a7227 */
/* 0x000fc800078e00ff */
/*0640*/ IMAD.MOV R12, RZ, RZ, -R10 ; /* 0x000000ffff0c7224 */
/* 0x000fc800078e0a0a */
/*0650*/ IMAD R11, R14, R12, R11 ; /* 0x0000000c0e0b7224 */
/* 0x000fca00078e020b */
/*0660*/ ISETP.GT.U32.AND P1, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x000fda0003f24070 */
/*0670*/ @!P1 IMAD.IADD R11, R11, 0x1, -R14 ; /* 0x000000010b0b9824 */
/* 0x000fe200078e0a0e */
/*0680*/ @!P1 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a9810 */
/* 0x000fe40007ffe0ff */
/*0690*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fe40003f25270 */
/*06a0*/ ISETP.GE.U32.AND P0, PT, R11, R14, PT ; /* 0x0000000e0b00720c */
/* 0x000fe40003f06070 */
/*06b0*/ LOP3.LUT R11, R22, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x00005900160b7a12 */
/* 0x000fc800078e3cff */
/*06c0*/ ISETP.GE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fce0003f46270 */
/*06d0*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*06f0*/ @!P2 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0aa224 */
/* 0x000fe200078e0a0a */
/*0700*/ @!P1 LOP3.LUT R10, RZ, c[0x0][0x164], RZ, 0x33, !PT ; /* 0x00005900ff0a9a12 */
/* 0x000fca00078e33ff */
/*0710*/ IMAD R9, R10, c[0x0][0x170], R9 ; /* 0x00005c000a097a24 */
/* 0x000fc800078e0209 */
/*0720*/ IMAD R12, R9, c[0x0][0x16c], R8 ; /* 0x00005b00090c7a24 */
/* 0x000fe200078e0208 */
/*0730*/ @!P0 BRA 0x8b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0740*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0750*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe400078e00ff */
/*0760*/ IMAD R8, R22, c[0x0][0x168], R3 ; /* 0x00005a0016087a24 */
/* 0x001fc800078e0203 */
/*0770*/ IMAD.WIDE R8, R8, R15, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x000fca00078e020f */
/*0780*/ LDG.E R13, [R8.64] ; /* 0x00000006080d7981 */
/* 0x000ea2000c1e1900 */
/*0790*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f05270 */
/*07a0*/ IMAD R14, R12, c[0x0][0x168], R3 ; /* 0x00005a000c0e7a24 */
/* 0x000fc800078e0203 */
/*07b0*/ IMAD.WIDE R10, R14, R15, c[0x0][0x188] ; /* 0x000062000e0a7625 */
/* 0x000fe200078e020f */
/*07c0*/ IADD3 R23, R3, 0x20, RZ ; /* 0x0000002003177810 */
/* 0x000fc80007ffe0ff */
/*07d0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R10.64], R13 ; /* 0x0000000d0a00798e */
/* 0x0041e6000c10e786 */
/*07e0*/ @!P0 BRA 0x8b0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*07f0*/ LDG.E R13, [R8.64+0x80] ; /* 0x00008006080d7981 */
/* 0x001ea2000c1e1900 */
/*0800*/ ISETP.NE.AND P0, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x000fe40003f05270 */
/*0810*/ IADD3 R10, R14, 0x20, RZ ; /* 0x000000200e0a7810 */
/* 0x000fca0007ffe0ff */
/*0820*/ IMAD.WIDE R10, R10, R15, c[0x0][0x188] ; /* 0x000062000a0a7625 */
/* 0x000fc800078e020f */
/*0830*/ IMAD.MOV.U32 R23, RZ, RZ, R4 ; /* 0x000000ffff177224 */
/* 0x000fe200078e0004 */
/*0840*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R10.64], R13 ; /* 0x0000000d0a00798e */
/* 0x0041e2000c10e786 */
/*0850*/ @!P0 BRA 0x8b0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0860*/ LDG.E R9, [R8.64+0x100] ; /* 0x0001000608097981 */
/* 0x000ea2000c1e1900 */
/*0870*/ IMAD R10, R12, c[0x0][0x168], R4 ; /* 0x00005a000c0a7a24 */
/* 0x001fc800078e0204 */
/*0880*/ IMAD.WIDE R10, R10, R15, c[0x0][0x188] ; /* 0x000062000a0a7625 */
/* 0x000fca00078e020f */
/*0890*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R10.64], R9 ; /* 0x000000090a00798e */
/* 0x0041e2000c10e786 */
/*08a0*/ MOV R23, R6 ; /* 0x0000000600177202 */
/* 0x000fc60000000f00 */
/*08b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08c0*/ ISETP.GE.U32.AND P0, PT, R2, 0x60, PT ; /* 0x000000600200780c */
/* 0x000fda0003f06070 */
/*08d0*/ @!P0 BRA 0xba0 ; /* 0x000002c000008947 */
/* 0x000fea0003800000 */
/*08e0*/ IMAD R8, R12, c[0x0][0x168], R23.reuse ; /* 0x00005a000c087a24 */
/* 0x100fe400078e0217 */
/*08f0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fe400078e00ff */
/*0900*/ IMAD R22, R22, c[0x0][0x168], R23 ; /* 0x00005a0016167a24 */
/* 0x000fe200078e0217 */
/*0910*/ IADD3 R10, R8.reuse, 0x60, RZ ; /* 0x00000060080a7810 */
/* 0x041fe20007ffe0ff */
/*0920*/ IMAD.WIDE R20, R8.reuse, R19.reuse, c[0x0][0x188] ; /* 0x0000620008147625 */
/* 0x0c0fe200078e0213 */
/*0930*/ IADD3 R12, R8.reuse, 0x40, RZ ; /* 0x00000040080c7810 */
/* 0x040fe40007ffe0ff */
/*0940*/ IADD3 R18, R8, 0x20, RZ ; /* 0x0000002008127810 */
/* 0x000fe20007ffe0ff */
/*0950*/ IMAD.WIDE R10, R10, R19, c[0x0][0x188] ; /* 0x000062000a0a7625 */
/* 0x000fc800078e0213 */
/*0960*/ IMAD.WIDE R12, R12, R19, c[0x0][0x188] ; /* 0x000062000c0c7625 */
/* 0x000fc800078e0213 */
/*0970*/ IMAD.MOV.U32 R24, RZ, RZ, R10 ; /* 0x000000ffff187224 */
/* 0x000fe400078e000a */
/*0980*/ IMAD.WIDE R18, R18, R19, c[0x0][0x188] ; /* 0x0000620012127625 */
/* 0x000fc800078e0213 */
/*0990*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000c */
/*09a0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x000fe400078e00ff */
/*09b0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fc800078e00ff */
/*09c0*/ IMAD.WIDE R14, R22, 0x4, R8 ; /* 0x00000004160e7825 */
/* 0x001fca00078e0208 */
/*09d0*/ LDG.E R25, [R14.64] ; /* 0x000000060e197981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ IMAD.MOV.U32 R16, RZ, RZ, R20 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0014 */
/*09f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0a00*/ IMAD.MOV.U32 R17, RZ, RZ, R21 ; /* 0x000000ffff117224 */
/* 0x000fca00078e0015 */
/*0a10*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R16.64], R25 ; /* 0x000000191000798e */
/* 0x0041e8000c10e786 */
/*0a20*/ LDG.E R27, [R14.64+0x80] ; /* 0x000080060e1b7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IMAD.MOV.U32 R16, RZ, RZ, R18 ; /* 0x000000ffff107224 */
/* 0x001fe400078e0012 */
/*0a40*/ IMAD.MOV.U32 R17, RZ, RZ, R19 ; /* 0x000000ffff117224 */
/* 0x000fca00078e0013 */
/*0a50*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R16.64], R27 ; /* 0x0000001b1000798e */
/* 0x004fe8000c10e786 */
/*0a60*/ LDG.E R29, [R14.64+0x100] ; /* 0x000100060e1d7981 */
/* 0x000ea2000c1e1900 */
/*0a70*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000a */
/*0a80*/ IADD3 R23, R23, 0x80, RZ ; /* 0x0000008017177810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.GE.AND P0, PT, R23, c[0x0][0x168], PT ; /* 0x00005a0017007a0c */
/* 0x000fe20003f06270 */
/*0aa0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64], R29 ; /* 0x0000001d0c00798e */
/* 0x0041e8000c10e786 */
/*0ab0*/ LDG.E R26, [R14.64+0x180] ; /* 0x000180060e1a7981 */
/* 0x0002a2000c1e1900 */
/*0ac0*/ IADD3 R8, P1, R8, 0x200, RZ ; /* 0x0000020008087810 */
/* 0x000fe40007f3e0ff */
/*0ad0*/ IADD3 R10, P3, R10, 0x200, RZ ; /* 0x000002000a0a7810 */
/* 0x000fe40007f7e0ff */
/*0ae0*/ IADD3 R18, P4, R18, 0x200, RZ ; /* 0x0000020012127810 */
/* 0x000fc40007f9e0ff */
/*0af0*/ IADD3 R20, P5, R20, 0x200, RZ ; /* 0x0000020014147810 */
/* 0x000fe40007fbe0ff */
/*0b00*/ MOV R14, R24 ; /* 0x00000018000e7202 */
/* 0x002fe20000000f00 */
/*0b10*/ IMAD.MOV.U32 R15, RZ, RZ, R11 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e000b */
/*0b20*/ IADD3 R24, P2, R24, 0x200, RZ ; /* 0x0000020018187810 */
/* 0x000fe20007f5e0ff */
/*0b30*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe400008e0609 */
/*0b40*/ IMAD.X R13, RZ, RZ, R13, P3 ; /* 0x000000ffff0d7224 */
/* 0x001fe400018e060d */
/*0b50*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe400010e060b */
/*0b60*/ IMAD.X R19, RZ, RZ, R19, P4 ; /* 0x000000ffff137224 */
/* 0x000fc400020e0613 */
/*0b70*/ IMAD.X R21, RZ, RZ, R21, P5 ; /* 0x000000ffff157224 */
/* 0x000fe200028e0615 */
/*0b80*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64], R26 ; /* 0x0000001a0e00798e */
/* 0x0041e2000c10e786 */
/*0b90*/ @!P0 BRA 0x9c0 ; /* 0xfffffe2000008947 */
/* 0x000fea000383ffff */
/*0ba0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0bb0*/ IADD3 R8, R0.reuse, 0x4, RZ ; /* 0x0000000400087810 */
/* 0x040fe40007ffe0ff */
/*0bc0*/ ISETP.LT.AND P1, PT, R0, 0x7c, PT ; /* 0x0000007c0000780c */
/* 0x000fc60003f21270 */
/*0bd0*/ IMAD R22, R5, 0x80, R8.reuse ; /* 0x0000008005167824 */
/* 0x100fe400078e0208 */
/*0be0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0008 */
/*0bf0*/ ISETP.GE.AND P0, PT, R22, UR4, PT ; /* 0x0000000416007c0c */
/* 0x000fda000bf06270 */
/*0c00*/ @!P0 BRA P1, 0x480 ; /* 0xfffff87000008947 */
/* 0x000fea000083ffff */
/*0c10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c20*/ BRA 0xc20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.p2align 8
.type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@function
_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi:
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0xc
s_load_b32 s10, s[0:1], 0x14
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u32 v7, v0, 10, 10
s_lshl_b32 s11, s15, 7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v11, v7, 5, v6
v_add_nc_u32_e32 v9, s11, v11
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s5, s4
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v9
s_cbranch_execz .LBB0_5
s_load_b64 s[2:3], s[0:1], 0x18
v_lshl_add_u32 v0, v9, 1, v9
v_mul_u32_u24_e32 v11, 3, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v4, 2, v0
v_lshlrev_b32_e32 v11, 2, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[12:13], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[14:15], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[16:17], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s2, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
s_clause 0x2
global_load_b32 v8, v[12:13], off
global_load_b32 v10, v[14:15], off
global_load_b32 v12, v[16:17], off
s_waitcnt vmcnt(1)
ds_store_2addr_b32 v11, v8, v10 offset1:1
s_waitcnt vmcnt(0)
ds_store_b32 v11, v12 offset:8
v_cmp_lt_i32_e32 vcc_lo, -1, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_cmp_gt_i32_e32 vcc_lo, s8, v8
v_cmp_lt_i32_e64 s2, -1, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_5
v_cmp_gt_i32_e32 vcc_lo, s9, v10
v_cmp_gt_i32_e64 s2, s10, v12
v_cmp_lt_i32_e64 s3, -1, v12
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_5
s_ashr_i32 s6, s5, 31
v_ashrrev_i32_e32 v13, 31, v9
s_add_i32 s2, s5, s6
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_xor_b32 s7, s2, s6
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_cvt_f32_u32_e32 v11, s7
s_sub_i32 s2, 0, s7
v_add_nc_u32_e32 v9, v9, v13
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v11, v11
v_xor_b32_e32 v9, v9, v13
v_xor_b32_e32 v13, s6, v13
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v11, 0x4f7ffffe, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v11, v11
v_mul_lo_u32 v12, s2, v11
s_load_b64 s[2:3], s[0:1], 0x30
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v12, v11, v12
v_add_nc_u32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v11, v9, v11
v_mul_lo_u32 v12, v11, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v9, v12
v_subrev_nc_u32_e32 v14, s7, v9
v_cmp_le_u32_e32 vcc_lo, s7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v9, v9, v14 :: v_dual_add_nc_u32 v12, 1, v11
v_cndmask_b32_e32 v11, v11, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s7, v9
v_add_nc_u32_e32 v12, 1, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v11, v12, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_xor_b32_e32 v9, v9, v13
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_sub_nc_u32_e32 v9, v9, v13
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x2
global_store_b32 v[0:1], v9, off
global_store_b32 v[2:3], v10, off
global_store_b32 v[4:5], v8, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x80, v7
s_cbranch_execz .LBB0_17
s_ashr_i32 s3, s5, 31
s_load_b32 s14, s[0:1], 0x8
s_add_i32 s2, s5, s3
s_load_b128 s[4:7], s[0:1], 0x20
s_xor_b32 s13, s2, s3
s_mov_b32 s15, 0
v_cvt_f32_u32_e32 v0, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s14, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v4, v0
s_branch .LBB0_9
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s18
v_cmp_lt_u32_e64 s0, 0x7b, v7
v_add_nc_u32_e32 v0, 4, v7
s_and_not1_b32 s1, s16, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_or_b32 s16, s1, s0
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s17
v_mov_b32_e32 v7, v0
s_and_b32 s0, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s15, s0, s15
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB0_17
.LBB0_9:
v_or_b32_e32 v2, s11, v7
s_or_b32 s16, s16, exec_lo
s_mov_b32 s17, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v2
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v0, v7, 1, v7
s_mov_b32 s18, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v0
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 -1, v0
s_cbranch_execz .LBB0_7
ds_load_b32 v1, v3 offset:4
v_cmp_gt_i32_e64 s0, s8, v0
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e64 s1, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
ds_load_b32 v3, v3 offset:8
v_cmp_le_i32_e64 s0, s9, v1
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e64 s1, s10, v3
v_cmp_gt_i32_e64 s2, 0, v3
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, vcc_lo
s_xor_b32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
s_sub_i32 s0, 0, s13
v_ashrrev_i32_e32 v5, 31, v2
v_mul_lo_u32 v3, s0, v4
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v2, v5
v_mul_hi_u32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v8, v8, v5
v_xor_b32_e32 v5, s3, v5
v_add_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v8, v3
v_mul_lo_u32 v9, v3, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v8, v9
v_add_nc_u32_e32 v9, 1, v3
v_subrev_nc_u32_e32 v10, s13, v8
v_cmp_le_u32_e64 s0, s13, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v9, s0
v_cndmask_b32_e64 v8, v8, v10, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, 1, v3
v_cmp_le_u32_e64 s0, s13, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v9, s0
v_xor_b32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v5
v_mad_u64_u32 v[8:9], null, v3, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[9:10], null, v8, s8, v[0:1]
v_mul_lo_u32 v8, v2, s14
v_mul_lo_u32 v5, v9, s14
v_mov_b32_e32 v9, v6
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_14:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v0, v9, v8
v_add_nc_u32_e32 v2, v9, v5
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s0, s4, v0
v_add_co_ci_u32_e64 v11, s0, s5, v1, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s6, v2
v_add_co_ci_u32_e64 v1, s0, s7, v3, s0
global_load_b32 v10, v[10:11], off
global_load_b32 v3, v[0:1], off
.LBB0_15:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v10
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v2, v3
v_mov_b32_e32 v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s0, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_15
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v9, 32, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s14, v9
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_14
s_branch .LBB0_7
.LBB0_17:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.amdhsa_group_segment_fixed_size 1536
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .Lfunc_end0-_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1536
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00143ca1_00000000-6_voxel_pooling_forward_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
.type _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi, @function
_Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi:
.LFB2082:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movl %r9d, 40(%rsp)
movq 240(%rsp), %rax
movq %rax, 32(%rsp)
movq 248(%rsp), %rax
movq %rax, 24(%rsp)
movq 256(%rsp), %rax
movq %rax, 16(%rsp)
movq 264(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi, .-_Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
.globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, @function
_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .-_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA kernel failed : %s\n"
.text
.globl _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st
.type _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st, @function
_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movl %edi, %edx
imull %esi, %edx
movl %edx, %ecx
sarl $31, %ecx
shrl $25, %ecx
leal (%rdx,%rcx), %eax
andl $127, %eax
subl %ecx, %eax
testl %eax, %eax
setg %cl
movzbl %cl, %ecx
leal 127(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $7, %eax
addl %ecx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $32, 20(%rsp)
movl $4, 24(%rsp)
movq 128(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L16
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st, .-_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "voxel_pooling_forward_cuda.hip"
.globl _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi # -- Begin function _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.p2align 4, 0x90
.type _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@function
_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi: # @_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .Lfunc_end0-_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.cfi_endproc
# -- End function
.globl _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t # -- Begin function _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t
.p2align 4, 0x90
.type _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t,@function
_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t: # @_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %esi, %eax
imull %edi, %eax
leal 127(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
movq 288(%rsp), %r9
sarl $7, %ecx
xorl %edx, %edx
testl $-2147483521, %eax # imm = 0x8000007F
setg %dl
addl %ecx, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdx, %rdi
movabsq $17179869216, %rdx # imm = 0x400000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 280(%rsp), %rax
movq 272(%rsp), %rcx
movq 264(%rsp), %rdx
movq 256(%rsp), %rsi
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
movq %rsi, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_4
# %bb.3:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t, .Lfunc_end1-_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@object # @_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.section .rodata,"a",@progbits
.globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.p2align 3, 0x0
_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi:
.quad _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA kernel failed : %s\n"
.size .L.str, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include<cstdio>
//#include<cuda.h>
//#include<cuda_runtime.h>
//#include<device_launch_parameters.h>
//#include<vector>
//#include "Common.cuh"
//#include "Mesh.cuh"
//using namespace std;
//
////#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 600
////#else
////__device__ double atomicAdd(double* address, double val) {
//// unsigned long long int* address_as_ull = (unsigned long long int*)address;
//// unsigned long long int old = *address_as_ull, assumed;
//// do {
//// assumed = old;
//// old = atomicCAS(address_as_ull, assumed, __double_as_longlong(val + __longlong_as_double(assumed)));
//// // Note: uses integer comparison to avoid hang in case of NaN (since NaN != NaN)
//// } while (assumed != old);
//// return __longlong_as_double(old);
////}
////
////#endif
//
//
//
//__global__ void d_square(Vector3d *d_in, Vector3d *d_out) {
// int idx = threadIdx.x;
// Vector3d val = d_in[idx];
// printf("%d\n", sizeof(d_in[idx]));
// d_out[idx] = val + val;
//}
//
//
//__global__ void reduce(double *d_data, double *d_out) {
// int tid = threadIdx.x;
// printf("%lf, %d, %lf\n", d_out[0], tid, d_data[tid]);
// atomicAdd(&d_out[0], d_data[tid]);
//}
//
//
//void main() {
// unsigned int size = 5, bytes = size * sizeof(double);
// double *test = new double[size];
// for (int i = 0; i < size; i++) {
// test[i] = i + 1;
// }
// double *res = new double[size];
//
// double *d_in, *d_out;
//
// cudaMalloc((void**)&d_in, bytes);
// cudaMalloc((void**)&d_out, bytes);
//
// cudaMemcpy(d_in, test, bytes, cudaMemcpyHostToDevice);
//
// reduce<<<1,size>>>(d_in, d_out);
//
// cudaMemcpy(res, d_out, bytes, cudaMemcpyDeviceToHost);
// printf("%lf\n", res[0]);
//
//}
//
////// TIMER
/////*chrono::high_resolution_clock Clock;
////auto t1 = Clock.now();
////auto t2 = Clock.now();
////double t = chrono::duration_cast<chrono::nanoseconds>(t2 - t1).count();
////
////printf("time = %lf \n", t * 1e-9);*/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include<cstdio>
//#include<cuda.h>
//#include<cuda_runtime.h>
//#include<device_launch_parameters.h>
//#include<vector>
//#include "Common.cuh"
//#include "Mesh.cuh"
//using namespace std;
//
////#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 600
////#else
////__device__ double atomicAdd(double* address, double val) {
//// unsigned long long int* address_as_ull = (unsigned long long int*)address;
//// unsigned long long int old = *address_as_ull, assumed;
//// do {
//// assumed = old;
//// old = atomicCAS(address_as_ull, assumed, __double_as_longlong(val + __longlong_as_double(assumed)));
//// // Note: uses integer comparison to avoid hang in case of NaN (since NaN != NaN)
//// } while (assumed != old);
//// return __longlong_as_double(old);
////}
////
////#endif
//
//
//
//__global__ void d_square(Vector3d *d_in, Vector3d *d_out) {
// int idx = threadIdx.x;
// Vector3d val = d_in[idx];
// printf("%d\n", sizeof(d_in[idx]));
// d_out[idx] = val + val;
//}
//
//
//__global__ void reduce(double *d_data, double *d_out) {
// int tid = threadIdx.x;
// printf("%lf, %d, %lf\n", d_out[0], tid, d_data[tid]);
// atomicAdd(&d_out[0], d_data[tid]);
//}
//
//
//void main() {
// unsigned int size = 5, bytes = size * sizeof(double);
// double *test = new double[size];
// for (int i = 0; i < size; i++) {
// test[i] = i + 1;
// }
// double *res = new double[size];
//
// double *d_in, *d_out;
//
// cudaMalloc((void**)&d_in, bytes);
// cudaMalloc((void**)&d_out, bytes);
//
// cudaMemcpy(d_in, test, bytes, cudaMemcpyHostToDevice);
//
// reduce<<<1,size>>>(d_in, d_out);
//
// cudaMemcpy(res, d_out, bytes, cudaMemcpyDeviceToHost);
// printf("%lf\n", res[0]);
//
//}
//
////// TIMER
/////*chrono::high_resolution_clock Clock;
////auto t1 = Clock.now();
////auto t2 = Clock.now();
////double t = chrono::duration_cast<chrono::nanoseconds>(t2 - t1).count();
////
////printf("time = %lf \n", t * 1e-9);*/ | .file "tmpxft_000f2a9b_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include<cstdio>
//#include<cuda.h>
//#include<cuda_runtime.h>
//#include<device_launch_parameters.h>
//#include<vector>
//#include "Common.cuh"
//#include "Mesh.cuh"
//using namespace std;
//
////#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 600
////#else
////__device__ double atomicAdd(double* address, double val) {
//// unsigned long long int* address_as_ull = (unsigned long long int*)address;
//// unsigned long long int old = *address_as_ull, assumed;
//// do {
//// assumed = old;
//// old = atomicCAS(address_as_ull, assumed, __double_as_longlong(val + __longlong_as_double(assumed)));
//// // Note: uses integer comparison to avoid hang in case of NaN (since NaN != NaN)
//// } while (assumed != old);
//// return __longlong_as_double(old);
////}
////
////#endif
//
//
//
//__global__ void d_square(Vector3d *d_in, Vector3d *d_out) {
// int idx = threadIdx.x;
// Vector3d val = d_in[idx];
// printf("%d\n", sizeof(d_in[idx]));
// d_out[idx] = val + val;
//}
//
//
//__global__ void reduce(double *d_data, double *d_out) {
// int tid = threadIdx.x;
// printf("%lf, %d, %lf\n", d_out[0], tid, d_data[tid]);
// atomicAdd(&d_out[0], d_data[tid]);
//}
//
//
//void main() {
// unsigned int size = 5, bytes = size * sizeof(double);
// double *test = new double[size];
// for (int i = 0; i < size; i++) {
// test[i] = i + 1;
// }
// double *res = new double[size];
//
// double *d_in, *d_out;
//
// cudaMalloc((void**)&d_in, bytes);
// cudaMalloc((void**)&d_out, bytes);
//
// cudaMemcpy(d_in, test, bytes, cudaMemcpyHostToDevice);
//
// reduce<<<1,size>>>(d_in, d_out);
//
// cudaMemcpy(res, d_out, bytes, cudaMemcpyDeviceToHost);
// printf("%lf\n", res[0]);
//
//}
//
////// TIMER
/////*chrono::high_resolution_clock Clock;
////auto t1 = Clock.now();
////auto t2 = Clock.now();
////double t = chrono::duration_cast<chrono::nanoseconds>(t2 - t1).count();
////
////printf("time = %lf \n", t * 1e-9);*/ | #include <hip/hip_runtime.h>
//#include<cstdio>
//#include<cuda.h>
//#include<cuda_runtime.h>
//#include<device_launch_parameters.h>
//#include<vector>
//#include "Common.cuh"
//#include "Mesh.cuh"
//using namespace std;
//
////#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 600
////#else
////__device__ double atomicAdd(double* address, double val) {
//// unsigned long long int* address_as_ull = (unsigned long long int*)address;
//// unsigned long long int old = *address_as_ull, assumed;
//// do {
//// assumed = old;
//// old = atomicCAS(address_as_ull, assumed, __double_as_longlong(val + __longlong_as_double(assumed)));
//// // Note: uses integer comparison to avoid hang in case of NaN (since NaN != NaN)
//// } while (assumed != old);
//// return __longlong_as_double(old);
////}
////
////#endif
//
//
//
//__global__ void d_square(Vector3d *d_in, Vector3d *d_out) {
// int idx = threadIdx.x;
// Vector3d val = d_in[idx];
// printf("%d\n", sizeof(d_in[idx]));
// d_out[idx] = val + val;
//}
//
//
//__global__ void reduce(double *d_data, double *d_out) {
// int tid = threadIdx.x;
// printf("%lf, %d, %lf\n", d_out[0], tid, d_data[tid]);
// atomicAdd(&d_out[0], d_data[tid]);
//}
//
//
//void main() {
// unsigned int size = 5, bytes = size * sizeof(double);
// double *test = new double[size];
// for (int i = 0; i < size; i++) {
// test[i] = i + 1;
// }
// double *res = new double[size];
//
// double *d_in, *d_out;
//
// cudaMalloc((void**)&d_in, bytes);
// cudaMalloc((void**)&d_out, bytes);
//
// cudaMemcpy(d_in, test, bytes, cudaMemcpyHostToDevice);
//
// reduce<<<1,size>>>(d_in, d_out);
//
// cudaMemcpy(res, d_out, bytes, cudaMemcpyDeviceToHost);
// printf("%lf\n", res[0]);
//
//}
//
////// TIMER
/////*chrono::high_resolution_clock Clock;
////auto t1 = Clock.now();
////auto t2 = Clock.now();
////double t = chrono::duration_cast<chrono::nanoseconds>(t2 - t1).count();
////
////printf("time = %lf \n", t * 1e-9);*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#include<cstdio>
//#include<cuda.h>
//#include<cuda_runtime.h>
//#include<device_launch_parameters.h>
//#include<vector>
//#include "Common.cuh"
//#include "Mesh.cuh"
//using namespace std;
//
////#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 600
////#else
////__device__ double atomicAdd(double* address, double val) {
//// unsigned long long int* address_as_ull = (unsigned long long int*)address;
//// unsigned long long int old = *address_as_ull, assumed;
//// do {
//// assumed = old;
//// old = atomicCAS(address_as_ull, assumed, __double_as_longlong(val + __longlong_as_double(assumed)));
//// // Note: uses integer comparison to avoid hang in case of NaN (since NaN != NaN)
//// } while (assumed != old);
//// return __longlong_as_double(old);
////}
////
////#endif
//
//
//
//__global__ void d_square(Vector3d *d_in, Vector3d *d_out) {
// int idx = threadIdx.x;
// Vector3d val = d_in[idx];
// printf("%d\n", sizeof(d_in[idx]));
// d_out[idx] = val + val;
//}
//
//
//__global__ void reduce(double *d_data, double *d_out) {
// int tid = threadIdx.x;
// printf("%lf, %d, %lf\n", d_out[0], tid, d_data[tid]);
// atomicAdd(&d_out[0], d_data[tid]);
//}
//
//
//void main() {
// unsigned int size = 5, bytes = size * sizeof(double);
// double *test = new double[size];
// for (int i = 0; i < size; i++) {
// test[i] = i + 1;
// }
// double *res = new double[size];
//
// double *d_in, *d_out;
//
// cudaMalloc((void**)&d_in, bytes);
// cudaMalloc((void**)&d_out, bytes);
//
// cudaMemcpy(d_in, test, bytes, cudaMemcpyHostToDevice);
//
// reduce<<<1,size>>>(d_in, d_out);
//
// cudaMemcpy(res, d_out, bytes, cudaMemcpyDeviceToHost);
// printf("%lf\n", res[0]);
//
//}
//
////// TIMER
/////*chrono::high_resolution_clock Clock;
////auto t1 = Clock.now();
////auto t2 = Clock.now();
////double t = chrono::duration_cast<chrono::nanoseconds>(t2 - t1).count();
////
////printf("time = %lf \n", t * 1e-9);*/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#include<cstdio>
//#include<cuda.h>
//#include<cuda_runtime.h>
//#include<device_launch_parameters.h>
//#include<vector>
//#include "Common.cuh"
//#include "Mesh.cuh"
//using namespace std;
//
////#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 600
////#else
////__device__ double atomicAdd(double* address, double val) {
//// unsigned long long int* address_as_ull = (unsigned long long int*)address;
//// unsigned long long int old = *address_as_ull, assumed;
//// do {
//// assumed = old;
//// old = atomicCAS(address_as_ull, assumed, __double_as_longlong(val + __longlong_as_double(assumed)));
//// // Note: uses integer comparison to avoid hang in case of NaN (since NaN != NaN)
//// } while (assumed != old);
//// return __longlong_as_double(old);
////}
////
////#endif
//
//
//
//__global__ void d_square(Vector3d *d_in, Vector3d *d_out) {
// int idx = threadIdx.x;
// Vector3d val = d_in[idx];
// printf("%d\n", sizeof(d_in[idx]));
// d_out[idx] = val + val;
//}
//
//
//__global__ void reduce(double *d_data, double *d_out) {
// int tid = threadIdx.x;
// printf("%lf, %d, %lf\n", d_out[0], tid, d_data[tid]);
// atomicAdd(&d_out[0], d_data[tid]);
//}
//
//
//void main() {
// unsigned int size = 5, bytes = size * sizeof(double);
// double *test = new double[size];
// for (int i = 0; i < size; i++) {
// test[i] = i + 1;
// }
// double *res = new double[size];
//
// double *d_in, *d_out;
//
// cudaMalloc((void**)&d_in, bytes);
// cudaMalloc((void**)&d_out, bytes);
//
// cudaMemcpy(d_in, test, bytes, cudaMemcpyHostToDevice);
//
// reduce<<<1,size>>>(d_in, d_out);
//
// cudaMemcpy(res, d_out, bytes, cudaMemcpyDeviceToHost);
// printf("%lf\n", res[0]);
//
//}
//
////// TIMER
/////*chrono::high_resolution_clock Clock;
////auto t1 = Clock.now();
////auto t2 = Clock.now();
////double t = chrono::duration_cast<chrono::nanoseconds>(t2 - t1).count();
////
////printf("time = %lf \n", t * 1e-9);*/ | .text
.file "test.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f2a9b_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void process(int N_step, int N_inst, float *input, float *output){
int g_id = blockIdx.x * blockDim.x + threadIdx.x;
if(g_id >= N_inst) return;
float ans = 0.;
for(int t=0;t<N_step;++t){
for(int i=0;i<12;++i){
ans += input[(i+t)%VEC_SIZE + VEC_SIZE * g_id];
}
}
output[g_id] = ans;
return;
} | code for sm_80
Function : _Z7processiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe400000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0x820 ; /* 0x0000077000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R12, R0, 0x3000, RZ ; /* 0x00003000000c7824 */
/* 0x000fe200078e02ff */
/*00c0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ MOV R11, 0xb ; /* 0x0000000b000b7802 */
/* 0x000fe20000000f00 */
/*00f0*/ UMOV UR5, 0x3 ; /* 0x0000000300057882 */
/* 0x000fe20000000000 */
/*0100*/ MOV R2, 0xa ; /* 0x0000000a00027802 */
/* 0x000fe20000000f00 */
/*0110*/ UMOV UR10, 0x2 ; /* 0x00000002000a7882 */
/* 0x000fe20000000000 */
/*0120*/ MOV R5, 0x9 ; /* 0x0000000900057802 */
/* 0x000fe20000000f00 */
/*0130*/ UMOV UR11, 0x1 ; /* 0x00000001000b7882 */
/* 0x000fe20000000000 */
/*0140*/ MOV R6, 0x8 ; /* 0x0000000800067802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R7, 0x7 ; /* 0x0000000700077802 */
/* 0x000fc40000000f00 */
/*0160*/ MOV R8, 0x6 ; /* 0x0000000600087802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R9, 0x5 ; /* 0x0000000500097802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R10, 0x4 ; /* 0x00000004000a7802 */
/* 0x000fc80000000f00 */
/*0190*/ UIMAD.WIDE.U32 UR6, UR11, -0x55555555, URZ ; /* 0xaaaaaaab0b0678a5 */
/* 0x000fe2000f8e003f */
/*01a0*/ IMAD.WIDE.U32 R18, R10, -0x55555555, RZ ; /* 0xaaaaaaab0a127825 */
/* 0x000fe200078e00ff */
/*01b0*/ UIMAD.WIDE.U32 UR8, UR4, -0x55555555, URZ ; /* 0xaaaaaaab040878a5 */
/* 0x000fe2000f8e003f */
/*01c0*/ IADD3 R3, R12, 0x1, RZ ; /* 0x000000010c037810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ USHF.R.U32.HI UR6, URZ, 0xd, UR7 ; /* 0x0000000d3f067899 */
/* 0x000fe20008011607 */
/*01e0*/ IMAD.WIDE.U32 R16, R9, -0x55555555, RZ ; /* 0xaaaaaaab09107825 */
/* 0x000fe200078e00ff */
/*01f0*/ USHF.R.U32.HI UR8, URZ, 0xd, UR9 ; /* 0x0000000d3f087899 */
/* 0x000fe20008011609 */
/*0200*/ SHF.R.U32.HI R13, RZ, 0xd, R19 ; /* 0x0000000dff0d7819 */
/* 0x000fc40000011613 */
/*0210*/ IMAD.WIDE.U32 R14, R8, -0x55555555, RZ ; /* 0xaaaaaaab080e7825 */
/* 0x000fe200078e00ff */
/*0220*/ MOV R16, UR6 ; /* 0x0000000600107c02 */
/* 0x000fe40008000f00 */
/*0230*/ SHF.R.U32.HI R23, RZ, 0xd, R17 ; /* 0x0000000dff177819 */
/* 0x000fe20000011611 */
/*0240*/ IMAD.WIDE.U32 R20, R7, -0x55555555, RZ ; /* 0xaaaaaaab07147825 */
/* 0x000fe200078e00ff */
/*0250*/ SHF.R.U32.HI R25, RZ, 0xd, R15 ; /* 0x0000000dff197819 */
/* 0x000fe4000001160f */
/*0260*/ MOV R17, UR8 ; /* 0x0000000800117c02 */
/* 0x000fe20008000f00 */
/*0270*/ IMAD.WIDE.U32 R14, R6, -0x55555555, RZ ; /* 0xaaaaaaab060e7825 */
/* 0x000fe200078e00ff */
/*0280*/ SHF.R.U32.HI R20, RZ, 0xd, R21 ; /* 0x0000000dff147819 */
/* 0x000fe40000011615 */
/*0290*/ MOV R28, 0x4 ; /* 0x00000004001c7802 */
/* 0x000fe20000000f00 */
/*02a0*/ IMAD.WIDE.U32 R18, R5, -0x55555555, RZ ; /* 0xaaaaaaab05127825 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD R21, R16, -0x3000, R3 ; /* 0xffffd00010157824 */
/* 0x000fe400078e0203 */
/*02c0*/ IMAD R18, R13, -0x3000, R12.reuse ; /* 0xffffd0000d127824 */
/* 0x100fe200078e020c */
/*02d0*/ SHF.R.U32.HI R13, RZ, 0xd, R15 ; /* 0x0000000dff0d7819 */
/* 0x000fe2000001160f */
/*02e0*/ IMAD R17, R17, -0x3000, R12.reuse ; /* 0xffffd00011117824 */
/* 0x100fe200078e020c */
/*02f0*/ UIMAD.WIDE.U32 UR8, UR10, -0x55555555, URZ ; /* 0xaaaaaaab0a0878a5 */
/* 0x000fe2000f8e003f */
/*0300*/ IMAD.WIDE R14, R21, R28.reuse, c[0x0][0x168] ; /* 0x00005a00150e7625 */
/* 0x080fe200078e021c */
/*0310*/ SHF.R.U32.HI R21, RZ, 0xd, R19 ; /* 0x0000000dff157819 */
/* 0x000fe40000011613 */
/*0320*/ IADD3 R19, R18, 0x4, RZ ; /* 0x0000000412137810 */
/* 0x000fe20007ffe0ff */
/*0330*/ IMAD.WIDE R16, R17, R28, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fe200078e021c */
/*0340*/ USHF.R.U32.HI UR8, URZ, 0xd, UR9 ; /* 0x0000000d3f087899 */
/* 0x000fe20008011609 */
/*0350*/ LDG.E R27, [R14.64] ; /* 0x0000000c0e1b7981 */
/* 0x0000a4000c1e1900 */
/*0360*/ IMAD R18, R23, -0x3000, R12 ; /* 0xffffd00017127824 */
/* 0x000fc400078e020c */
/*0370*/ IMAD R24, R25, -0x3000, R12.reuse ; /* 0xffffd00019187824 */
/* 0x100fe200078e020c */
/*0380*/ UIMAD.WIDE.U32 UR6, UR5, -0x55555555, URZ ; /* 0xaaaaaaab050678a5 */
/* 0x000fe2000f8e003f */
/*0390*/ IMAD R20, R20, -0x3000, R12.reuse ; /* 0xffffd00014147824 */
/* 0x100fe200078e020c */
/*03a0*/ LDG.E R29, [R16.64] ; /* 0x0000000c101d7981 */
/* 0x0002e2000c1e1900 */
/*03b0*/ IMAD.WIDE R22, R19, R28, c[0x0][0x168] ; /* 0x00005a0013167625 */
/* 0x000fe200078e021c */
/*03c0*/ IADD3 R19, R18, 0x5, RZ ; /* 0x0000000512137810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ USHF.R.U32.HI UR6, URZ, 0xd, UR7 ; /* 0x0000000d3f067899 */
/* 0x000fe20008011607 */
/*03e0*/ IADD3 R18, R20, 0x7, RZ ; /* 0x0000000714127810 */
/* 0x000fe20007ffe0ff */
/*03f0*/ IMAD R20, R13, -0x3000, R12 ; /* 0xffffd0000d147824 */
/* 0x000fe200078e020c */
/*0400*/ MOV R26, UR8 ; /* 0x00000008001a7c02 */
/* 0x000fe40008000f00 */
/*0410*/ IADD3 R17, R24, 0x6, RZ ; /* 0x0000000618117810 */
/* 0x002fc60007ffe0ff */
/*0420*/ IMAD R13, R26, -0x3000, R12 ; /* 0xffffd0001a0d7824 */
/* 0x000fe200078e020c */
/*0430*/ IADD3 R20, R20, 0x8, RZ ; /* 0x0000000814147810 */
/* 0x000fe20007ffe0ff */
/*0440*/ IMAD.WIDE R14, R19, R28.reuse, c[0x0][0x168] ; /* 0x00005a00130e7625 */
/* 0x081fe200078e021c */
/*0450*/ MOV R26, UR6 ; /* 0x00000006001a7c02 */
/* 0x000fe20008000f00 */
/*0460*/ LDG.E R25, [R22.64] ; /* 0x0000000c16197981 */
/* 0x000124000c1e1900 */
/*0470*/ IMAD.WIDE R16, R17, R28.reuse, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x080fe400078e021c */
/*0480*/ LDG.E R24, [R14.64] ; /* 0x0000000c0e187981 */
/* 0x000364000c1e1900 */
/*0490*/ IMAD.WIDE R18, R18, R28, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fc400078e021c */
/*04a0*/ LDG.E R23, [R16.64] ; /* 0x0000000c10177981 */
/* 0x001128000c1e1900 */
/*04b0*/ LDG.E R22, [R18.64] ; /* 0x0000000c12167981 */
/* 0x000122000c1e1900 */
/*04c0*/ IMAD.WIDE.U32 R14, R2, -0x55555555, RZ ; /* 0xaaaaaaab020e7825 */
/* 0x002fc800078e00ff */
/*04d0*/ IMAD.WIDE R16, R20, R28, c[0x0][0x168] ; /* 0x00005a0014107625 */
/* 0x001fc800078e021c */
/*04e0*/ IMAD R20, R26, -0x3000, R12 ; /* 0xffffd0001a147824 */
/* 0x000fe200078e020c */
/*04f0*/ IADD3 R19, R13, 0x2, RZ ; /* 0x000000020d137810 */
/* 0x000fe40007ffe0ff */
/*0500*/ SHF.R.U32.HI R26, RZ, 0xd, R15 ; /* 0x0000000dff1a7819 */
/* 0x000fe2000001160f */
/*0510*/ LDG.E R13, [R16.64] ; /* 0x0000000c100d7981 */
/* 0x000122000c1e1900 */
/*0520*/ IADD3 R20, R20, 0x3, RZ ; /* 0x0000000314147810 */
/* 0x000fe20007ffe0ff */
/*0530*/ IMAD.WIDE R14, R19, R28, c[0x0][0x168] ; /* 0x00005a00130e7625 */
/* 0x000fc800078e021c */
/*0540*/ IMAD.WIDE R18, R20, R28, c[0x0][0x168] ; /* 0x00005a0014127625 */
/* 0x000fc800078e021c */
/*0550*/ IMAD R21, R21, -0x3000, R12.reuse ; /* 0xffffd00015157824 */
/* 0x100fe400078e020c */
/*0560*/ IMAD R16, R26, -0x3000, R12 ; /* 0xffffd0001a107824 */
/* 0x001fe200078e020c */
/*0570*/ LDG.E R18, [R18.64] ; /* 0x0000000c12127981 */
/* 0x000f28000c1e1900 */
/*0580*/ LDG.E R26, [R14.64] ; /* 0x0000000c0e1a7981 */
/* 0x000122000c1e1900 */
/*0590*/ IADD3 R21, R21, 0x9, RZ ; /* 0x0000000915157810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ IADD3 R20, R16, 0xa, RZ ; /* 0x0000000a10147810 */
/* 0x000fca0007ffe0ff */
/*05b0*/ IMAD.WIDE R16, R20, R28, c[0x0][0x168] ; /* 0x00005a0014107625 */
/* 0x000fc800078e021c */
/*05c0*/ IMAD.WIDE R14, R21, R28, c[0x0][0x168] ; /* 0x00005a00150e7625 */
/* 0x001fe400078e021c */
/*05d0*/ LDG.E R16, [R16.64] ; /* 0x0000000c10107981 */
/* 0x000f64000c1e1900 */
/*05e0*/ IMAD.WIDE.U32 R20, R11, -0x55555555, RZ ; /* 0xaaaaaaab0b147825 */
/* 0x000fe400078e00ff */
/*05f0*/ LDG.E R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x000f66000c1e1900 */
/*0600*/ SHF.R.U32.HI R21, RZ, 0xd, R21 ; /* 0x0000000dff157819 */
/* 0x000fca0000011615 */
/*0610*/ IMAD R12, R21, -0x3000, R12 ; /* 0xffffd000150c7824 */
/* 0x000fca00078e020c */
/*0620*/ IADD3 R21, R12, 0xb, RZ ; /* 0x0000000b0c157810 */
/* 0x000fca0007ffe0ff */
/*0630*/ IMAD.WIDE R20, R21, R28, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x000fcc00078e021c */
/*0640*/ LDG.E R20, [R20.64] ; /* 0x0000000c14147981 */
/* 0x000f62000c1e1900 */
/*0650*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe4000fffe03f */
/*0660*/ ULDC UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000800 */
/*0670*/ UISETP.GE.AND UP0, UPT, UR4, UR6, UPT ; /* 0x000000060400728c */
/* 0x000fcc000bf06270 */
/*0680*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f008 */
/*0690*/ UIADD3 UR5, UR5, 0x1, URZ ; /* 0x0000000105057890 */
/* 0x000fe4000fffe03f */
/*06a0*/ UIADD3 UR10, UR10, 0x1, URZ ; /* 0x000000010a0a7890 */
/* 0x000fe4000fffe03f */
/*06b0*/ UIADD3 UR11, UR11, 0x1, URZ ; /* 0x000000010b0b7890 */
/* 0x000fe2000fffe03f */
/*06c0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc40007ffe0ff */
/*06f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0700*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*0710*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*0720*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0730*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe40007ffe0ff */
/*0740*/ MOV R12, R3 ; /* 0x00000003000c7202 */
/* 0x000fe20000000f00 */
/*0750*/ FADD R4, R29, R4 ; /* 0x000000041d047221 */
/* 0x008fc80000000000 */
/*0760*/ FADD R27, R4, R27 ; /* 0x0000001b041b7221 */
/* 0x004fc80000000000 */
/*0770*/ FADD R27, R27, R26 ; /* 0x0000001a1b1b7221 */
/* 0x010fc80000000000 */
/*0780*/ FADD R18, R27, R18 ; /* 0x000000121b127221 */
/* 0x000fc80000000000 */
/*0790*/ FADD R25, R18, R25 ; /* 0x0000001912197221 */
/* 0x000fc80000000000 */
/*07a0*/ FADD R24, R25, R24 ; /* 0x0000001819187221 */
/* 0x020fc80000000000 */
/*07b0*/ FADD R23, R24, R23 ; /* 0x0000001718177221 */
/* 0x000fc80000000000 */
/*07c0*/ FADD R22, R23, R22 ; /* 0x0000001617167221 */
/* 0x000fc80000000000 */
/*07d0*/ FADD R13, R22, R13 ; /* 0x0000000d160d7221 */
/* 0x000fc80000000000 */
/*07e0*/ FADD R13, R13, R14 ; /* 0x0000000e0d0d7221 */
/* 0x000fc80000000000 */
/*07f0*/ FADD R13, R13, R16 ; /* 0x000000100d0d7221 */
/* 0x000fc80000000000 */
/*0800*/ FADD R4, R13, R20 ; /* 0x000000140d047221 */
/* 0x000fe20000000000 */
/*0810*/ @!P0 BRA 0x190 ; /* 0xfffff97000008947 */
/* 0x000fea000383ffff */
/*0820*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0830*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0840*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c10190c */
/*0850*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0860*/ BRA 0x860; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void process(int N_step, int N_inst, float *input, float *output){
int g_id = blockIdx.x * blockDim.x + threadIdx.x;
if(g_id >= N_inst) return;
float ans = 0.;
for(int t=0;t<N_step;++t){
for(int i=0;i<12;++i){
ans += input[(i+t)%VEC_SIZE + VEC_SIZE * g_id];
}
}
output[g_id] = ans;
return;
} | .file "tmpxft_000dec1a_00000000-6_process.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7processiiPfS_iiPfS_
.type _Z30__device_stub__Z7processiiPfS_iiPfS_, @function
_Z30__device_stub__Z7processiiPfS_iiPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7processiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z7processiiPfS_iiPfS_, .-_Z30__device_stub__Z7processiiPfS_iiPfS_
.globl _Z7processiiPfS_
.type _Z7processiiPfS_, @function
_Z7processiiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7processiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7processiiPfS_, .-_Z7processiiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7processiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7processiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void process(int N_step, int N_inst, float *input, float *output){
int g_id = blockIdx.x * blockDim.x + threadIdx.x;
if(g_id >= N_inst) return;
float ans = 0.;
for(int t=0;t<N_step;++t){
for(int i=0;i<12;++i){
ans += input[(i+t)%VEC_SIZE + VEC_SIZE * g_id];
}
}
output[g_id] = ans;
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void process(int N_step, int N_inst, float *input, float *output){
int g_id = blockIdx.x * blockDim.x + threadIdx.x;
if(g_id >= N_inst) return;
float ans = 0.;
for(int t=0;t<N_step;++t){
for(int i=0;i<12;++i){
ans += input[(i+t)%VEC_SIZE + VEC_SIZE * g_id];
}
}
output[g_id] = ans;
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void process(int N_step, int N_inst, float *input, float *output){
int g_id = blockIdx.x * blockDim.x + threadIdx.x;
if(g_id >= N_inst) return;
float ans = 0.;
for(int t=0;t<N_step;++t){
for(int i=0;i<12;++i){
ans += input[(i+t)%VEC_SIZE + VEC_SIZE * g_id];
}
}
output[g_id] = ans;
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7processiiPfS_
.globl _Z7processiiPfS_
.p2align 8
.type _Z7processiiPfS_,@function
_Z7processiiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_8
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x8
v_mul_lo_u32 v2, v1, 0x3000
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v3, v2
s_mov_b32 s6, 12
s_mov_b32 s7, s5
.p2align 6
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_hi_u32 s8, s7, 0xaaaaaaab
s_add_i32 s6, s6, -1
s_lshr_b32 s8, s8, 13
s_add_i32 s7, s7, 1
s_mulk_i32 s8, 0x3000
s_cmp_eq_u32 s6, 0
v_subrev_nc_u32_e32 v4, s8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v0, v4 :: v_dual_add_nc_u32 v3, 1, v3
s_cbranch_scc0 .LBB0_4
v_add_nc_u32_e32 v2, 1, v2
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, s4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v0, 0
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7processiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7processiiPfS_, .Lfunc_end0-_Z7processiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7processiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7processiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void process(int N_step, int N_inst, float *input, float *output){
int g_id = blockIdx.x * blockDim.x + threadIdx.x;
if(g_id >= N_inst) return;
float ans = 0.;
for(int t=0;t<N_step;++t){
for(int i=0;i<12;++i){
ans += input[(i+t)%VEC_SIZE + VEC_SIZE * g_id];
}
}
output[g_id] = ans;
return;
} | .text
.file "process.hip"
.globl _Z22__device_stub__processiiPfS_ # -- Begin function _Z22__device_stub__processiiPfS_
.p2align 4, 0x90
.type _Z22__device_stub__processiiPfS_,@function
_Z22__device_stub__processiiPfS_: # @_Z22__device_stub__processiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7processiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__processiiPfS_, .Lfunc_end0-_Z22__device_stub__processiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7processiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7processiiPfS_,@object # @_Z7processiiPfS_
.section .rodata,"a",@progbits
.globl _Z7processiiPfS_
.p2align 3, 0x0
_Z7processiiPfS_:
.quad _Z22__device_stub__processiiPfS_
.size _Z7processiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7processiiPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__processiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7processiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7processiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe400000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0x820 ; /* 0x0000077000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R12, R0, 0x3000, RZ ; /* 0x00003000000c7824 */
/* 0x000fe200078e02ff */
/*00c0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ MOV R11, 0xb ; /* 0x0000000b000b7802 */
/* 0x000fe20000000f00 */
/*00f0*/ UMOV UR5, 0x3 ; /* 0x0000000300057882 */
/* 0x000fe20000000000 */
/*0100*/ MOV R2, 0xa ; /* 0x0000000a00027802 */
/* 0x000fe20000000f00 */
/*0110*/ UMOV UR10, 0x2 ; /* 0x00000002000a7882 */
/* 0x000fe20000000000 */
/*0120*/ MOV R5, 0x9 ; /* 0x0000000900057802 */
/* 0x000fe20000000f00 */
/*0130*/ UMOV UR11, 0x1 ; /* 0x00000001000b7882 */
/* 0x000fe20000000000 */
/*0140*/ MOV R6, 0x8 ; /* 0x0000000800067802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R7, 0x7 ; /* 0x0000000700077802 */
/* 0x000fc40000000f00 */
/*0160*/ MOV R8, 0x6 ; /* 0x0000000600087802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R9, 0x5 ; /* 0x0000000500097802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R10, 0x4 ; /* 0x00000004000a7802 */
/* 0x000fc80000000f00 */
/*0190*/ UIMAD.WIDE.U32 UR6, UR11, -0x55555555, URZ ; /* 0xaaaaaaab0b0678a5 */
/* 0x000fe2000f8e003f */
/*01a0*/ IMAD.WIDE.U32 R18, R10, -0x55555555, RZ ; /* 0xaaaaaaab0a127825 */
/* 0x000fe200078e00ff */
/*01b0*/ UIMAD.WIDE.U32 UR8, UR4, -0x55555555, URZ ; /* 0xaaaaaaab040878a5 */
/* 0x000fe2000f8e003f */
/*01c0*/ IADD3 R3, R12, 0x1, RZ ; /* 0x000000010c037810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ USHF.R.U32.HI UR6, URZ, 0xd, UR7 ; /* 0x0000000d3f067899 */
/* 0x000fe20008011607 */
/*01e0*/ IMAD.WIDE.U32 R16, R9, -0x55555555, RZ ; /* 0xaaaaaaab09107825 */
/* 0x000fe200078e00ff */
/*01f0*/ USHF.R.U32.HI UR8, URZ, 0xd, UR9 ; /* 0x0000000d3f087899 */
/* 0x000fe20008011609 */
/*0200*/ SHF.R.U32.HI R13, RZ, 0xd, R19 ; /* 0x0000000dff0d7819 */
/* 0x000fc40000011613 */
/*0210*/ IMAD.WIDE.U32 R14, R8, -0x55555555, RZ ; /* 0xaaaaaaab080e7825 */
/* 0x000fe200078e00ff */
/*0220*/ MOV R16, UR6 ; /* 0x0000000600107c02 */
/* 0x000fe40008000f00 */
/*0230*/ SHF.R.U32.HI R23, RZ, 0xd, R17 ; /* 0x0000000dff177819 */
/* 0x000fe20000011611 */
/*0240*/ IMAD.WIDE.U32 R20, R7, -0x55555555, RZ ; /* 0xaaaaaaab07147825 */
/* 0x000fe200078e00ff */
/*0250*/ SHF.R.U32.HI R25, RZ, 0xd, R15 ; /* 0x0000000dff197819 */
/* 0x000fe4000001160f */
/*0260*/ MOV R17, UR8 ; /* 0x0000000800117c02 */
/* 0x000fe20008000f00 */
/*0270*/ IMAD.WIDE.U32 R14, R6, -0x55555555, RZ ; /* 0xaaaaaaab060e7825 */
/* 0x000fe200078e00ff */
/*0280*/ SHF.R.U32.HI R20, RZ, 0xd, R21 ; /* 0x0000000dff147819 */
/* 0x000fe40000011615 */
/*0290*/ MOV R28, 0x4 ; /* 0x00000004001c7802 */
/* 0x000fe20000000f00 */
/*02a0*/ IMAD.WIDE.U32 R18, R5, -0x55555555, RZ ; /* 0xaaaaaaab05127825 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD R21, R16, -0x3000, R3 ; /* 0xffffd00010157824 */
/* 0x000fe400078e0203 */
/*02c0*/ IMAD R18, R13, -0x3000, R12.reuse ; /* 0xffffd0000d127824 */
/* 0x100fe200078e020c */
/*02d0*/ SHF.R.U32.HI R13, RZ, 0xd, R15 ; /* 0x0000000dff0d7819 */
/* 0x000fe2000001160f */
/*02e0*/ IMAD R17, R17, -0x3000, R12.reuse ; /* 0xffffd00011117824 */
/* 0x100fe200078e020c */
/*02f0*/ UIMAD.WIDE.U32 UR8, UR10, -0x55555555, URZ ; /* 0xaaaaaaab0a0878a5 */
/* 0x000fe2000f8e003f */
/*0300*/ IMAD.WIDE R14, R21, R28.reuse, c[0x0][0x168] ; /* 0x00005a00150e7625 */
/* 0x080fe200078e021c */
/*0310*/ SHF.R.U32.HI R21, RZ, 0xd, R19 ; /* 0x0000000dff157819 */
/* 0x000fe40000011613 */
/*0320*/ IADD3 R19, R18, 0x4, RZ ; /* 0x0000000412137810 */
/* 0x000fe20007ffe0ff */
/*0330*/ IMAD.WIDE R16, R17, R28, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fe200078e021c */
/*0340*/ USHF.R.U32.HI UR8, URZ, 0xd, UR9 ; /* 0x0000000d3f087899 */
/* 0x000fe20008011609 */
/*0350*/ LDG.E R27, [R14.64] ; /* 0x0000000c0e1b7981 */
/* 0x0000a4000c1e1900 */
/*0360*/ IMAD R18, R23, -0x3000, R12 ; /* 0xffffd00017127824 */
/* 0x000fc400078e020c */
/*0370*/ IMAD R24, R25, -0x3000, R12.reuse ; /* 0xffffd00019187824 */
/* 0x100fe200078e020c */
/*0380*/ UIMAD.WIDE.U32 UR6, UR5, -0x55555555, URZ ; /* 0xaaaaaaab050678a5 */
/* 0x000fe2000f8e003f */
/*0390*/ IMAD R20, R20, -0x3000, R12.reuse ; /* 0xffffd00014147824 */
/* 0x100fe200078e020c */
/*03a0*/ LDG.E R29, [R16.64] ; /* 0x0000000c101d7981 */
/* 0x0002e2000c1e1900 */
/*03b0*/ IMAD.WIDE R22, R19, R28, c[0x0][0x168] ; /* 0x00005a0013167625 */
/* 0x000fe200078e021c */
/*03c0*/ IADD3 R19, R18, 0x5, RZ ; /* 0x0000000512137810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ USHF.R.U32.HI UR6, URZ, 0xd, UR7 ; /* 0x0000000d3f067899 */
/* 0x000fe20008011607 */
/*03e0*/ IADD3 R18, R20, 0x7, RZ ; /* 0x0000000714127810 */
/* 0x000fe20007ffe0ff */
/*03f0*/ IMAD R20, R13, -0x3000, R12 ; /* 0xffffd0000d147824 */
/* 0x000fe200078e020c */
/*0400*/ MOV R26, UR8 ; /* 0x00000008001a7c02 */
/* 0x000fe40008000f00 */
/*0410*/ IADD3 R17, R24, 0x6, RZ ; /* 0x0000000618117810 */
/* 0x002fc60007ffe0ff */
/*0420*/ IMAD R13, R26, -0x3000, R12 ; /* 0xffffd0001a0d7824 */
/* 0x000fe200078e020c */
/*0430*/ IADD3 R20, R20, 0x8, RZ ; /* 0x0000000814147810 */
/* 0x000fe20007ffe0ff */
/*0440*/ IMAD.WIDE R14, R19, R28.reuse, c[0x0][0x168] ; /* 0x00005a00130e7625 */
/* 0x081fe200078e021c */
/*0450*/ MOV R26, UR6 ; /* 0x00000006001a7c02 */
/* 0x000fe20008000f00 */
/*0460*/ LDG.E R25, [R22.64] ; /* 0x0000000c16197981 */
/* 0x000124000c1e1900 */
/*0470*/ IMAD.WIDE R16, R17, R28.reuse, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x080fe400078e021c */
/*0480*/ LDG.E R24, [R14.64] ; /* 0x0000000c0e187981 */
/* 0x000364000c1e1900 */
/*0490*/ IMAD.WIDE R18, R18, R28, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fc400078e021c */
/*04a0*/ LDG.E R23, [R16.64] ; /* 0x0000000c10177981 */
/* 0x001128000c1e1900 */
/*04b0*/ LDG.E R22, [R18.64] ; /* 0x0000000c12167981 */
/* 0x000122000c1e1900 */
/*04c0*/ IMAD.WIDE.U32 R14, R2, -0x55555555, RZ ; /* 0xaaaaaaab020e7825 */
/* 0x002fc800078e00ff */
/*04d0*/ IMAD.WIDE R16, R20, R28, c[0x0][0x168] ; /* 0x00005a0014107625 */
/* 0x001fc800078e021c */
/*04e0*/ IMAD R20, R26, -0x3000, R12 ; /* 0xffffd0001a147824 */
/* 0x000fe200078e020c */
/*04f0*/ IADD3 R19, R13, 0x2, RZ ; /* 0x000000020d137810 */
/* 0x000fe40007ffe0ff */
/*0500*/ SHF.R.U32.HI R26, RZ, 0xd, R15 ; /* 0x0000000dff1a7819 */
/* 0x000fe2000001160f */
/*0510*/ LDG.E R13, [R16.64] ; /* 0x0000000c100d7981 */
/* 0x000122000c1e1900 */
/*0520*/ IADD3 R20, R20, 0x3, RZ ; /* 0x0000000314147810 */
/* 0x000fe20007ffe0ff */
/*0530*/ IMAD.WIDE R14, R19, R28, c[0x0][0x168] ; /* 0x00005a00130e7625 */
/* 0x000fc800078e021c */
/*0540*/ IMAD.WIDE R18, R20, R28, c[0x0][0x168] ; /* 0x00005a0014127625 */
/* 0x000fc800078e021c */
/*0550*/ IMAD R21, R21, -0x3000, R12.reuse ; /* 0xffffd00015157824 */
/* 0x100fe400078e020c */
/*0560*/ IMAD R16, R26, -0x3000, R12 ; /* 0xffffd0001a107824 */
/* 0x001fe200078e020c */
/*0570*/ LDG.E R18, [R18.64] ; /* 0x0000000c12127981 */
/* 0x000f28000c1e1900 */
/*0580*/ LDG.E R26, [R14.64] ; /* 0x0000000c0e1a7981 */
/* 0x000122000c1e1900 */
/*0590*/ IADD3 R21, R21, 0x9, RZ ; /* 0x0000000915157810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ IADD3 R20, R16, 0xa, RZ ; /* 0x0000000a10147810 */
/* 0x000fca0007ffe0ff */
/*05b0*/ IMAD.WIDE R16, R20, R28, c[0x0][0x168] ; /* 0x00005a0014107625 */
/* 0x000fc800078e021c */
/*05c0*/ IMAD.WIDE R14, R21, R28, c[0x0][0x168] ; /* 0x00005a00150e7625 */
/* 0x001fe400078e021c */
/*05d0*/ LDG.E R16, [R16.64] ; /* 0x0000000c10107981 */
/* 0x000f64000c1e1900 */
/*05e0*/ IMAD.WIDE.U32 R20, R11, -0x55555555, RZ ; /* 0xaaaaaaab0b147825 */
/* 0x000fe400078e00ff */
/*05f0*/ LDG.E R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x000f66000c1e1900 */
/*0600*/ SHF.R.U32.HI R21, RZ, 0xd, R21 ; /* 0x0000000dff157819 */
/* 0x000fca0000011615 */
/*0610*/ IMAD R12, R21, -0x3000, R12 ; /* 0xffffd000150c7824 */
/* 0x000fca00078e020c */
/*0620*/ IADD3 R21, R12, 0xb, RZ ; /* 0x0000000b0c157810 */
/* 0x000fca0007ffe0ff */
/*0630*/ IMAD.WIDE R20, R21, R28, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x000fcc00078e021c */
/*0640*/ LDG.E R20, [R20.64] ; /* 0x0000000c14147981 */
/* 0x000f62000c1e1900 */
/*0650*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe4000fffe03f */
/*0660*/ ULDC UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000800 */
/*0670*/ UISETP.GE.AND UP0, UPT, UR4, UR6, UPT ; /* 0x000000060400728c */
/* 0x000fcc000bf06270 */
/*0680*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f008 */
/*0690*/ UIADD3 UR5, UR5, 0x1, URZ ; /* 0x0000000105057890 */
/* 0x000fe4000fffe03f */
/*06a0*/ UIADD3 UR10, UR10, 0x1, URZ ; /* 0x000000010a0a7890 */
/* 0x000fe4000fffe03f */
/*06b0*/ UIADD3 UR11, UR11, 0x1, URZ ; /* 0x000000010b0b7890 */
/* 0x000fe2000fffe03f */
/*06c0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc40007ffe0ff */
/*06f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0700*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*0710*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*0720*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0730*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe40007ffe0ff */
/*0740*/ MOV R12, R3 ; /* 0x00000003000c7202 */
/* 0x000fe20000000f00 */
/*0750*/ FADD R4, R29, R4 ; /* 0x000000041d047221 */
/* 0x008fc80000000000 */
/*0760*/ FADD R27, R4, R27 ; /* 0x0000001b041b7221 */
/* 0x004fc80000000000 */
/*0770*/ FADD R27, R27, R26 ; /* 0x0000001a1b1b7221 */
/* 0x010fc80000000000 */
/*0780*/ FADD R18, R27, R18 ; /* 0x000000121b127221 */
/* 0x000fc80000000000 */
/*0790*/ FADD R25, R18, R25 ; /* 0x0000001912197221 */
/* 0x000fc80000000000 */
/*07a0*/ FADD R24, R25, R24 ; /* 0x0000001819187221 */
/* 0x020fc80000000000 */
/*07b0*/ FADD R23, R24, R23 ; /* 0x0000001718177221 */
/* 0x000fc80000000000 */
/*07c0*/ FADD R22, R23, R22 ; /* 0x0000001617167221 */
/* 0x000fc80000000000 */
/*07d0*/ FADD R13, R22, R13 ; /* 0x0000000d160d7221 */
/* 0x000fc80000000000 */
/*07e0*/ FADD R13, R13, R14 ; /* 0x0000000e0d0d7221 */
/* 0x000fc80000000000 */
/*07f0*/ FADD R13, R13, R16 ; /* 0x000000100d0d7221 */
/* 0x000fc80000000000 */
/*0800*/ FADD R4, R13, R20 ; /* 0x000000140d047221 */
/* 0x000fe20000000000 */
/*0810*/ @!P0 BRA 0x190 ; /* 0xfffff97000008947 */
/* 0x000fea000383ffff */
/*0820*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0830*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0840*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c10190c */
/*0850*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0860*/ BRA 0x860; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7processiiPfS_
.globl _Z7processiiPfS_
.p2align 8
.type _Z7processiiPfS_,@function
_Z7processiiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_8
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x8
v_mul_lo_u32 v2, v1, 0x3000
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v3, v2
s_mov_b32 s6, 12
s_mov_b32 s7, s5
.p2align 6
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_hi_u32 s8, s7, 0xaaaaaaab
s_add_i32 s6, s6, -1
s_lshr_b32 s8, s8, 13
s_add_i32 s7, s7, 1
s_mulk_i32 s8, 0x3000
s_cmp_eq_u32 s6, 0
v_subrev_nc_u32_e32 v4, s8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v0, v4 :: v_dual_add_nc_u32 v3, 1, v3
s_cbranch_scc0 .LBB0_4
v_add_nc_u32_e32 v2, 1, v2
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, s4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v0, 0
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7processiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7processiiPfS_, .Lfunc_end0-_Z7processiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7processiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7processiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dec1a_00000000-6_process.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7processiiPfS_iiPfS_
.type _Z30__device_stub__Z7processiiPfS_iiPfS_, @function
_Z30__device_stub__Z7processiiPfS_iiPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7processiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z7processiiPfS_iiPfS_, .-_Z30__device_stub__Z7processiiPfS_iiPfS_
.globl _Z7processiiPfS_
.type _Z7processiiPfS_, @function
_Z7processiiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7processiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7processiiPfS_, .-_Z7processiiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7processiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7processiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "process.hip"
.globl _Z22__device_stub__processiiPfS_ # -- Begin function _Z22__device_stub__processiiPfS_
.p2align 4, 0x90
.type _Z22__device_stub__processiiPfS_,@function
_Z22__device_stub__processiiPfS_: # @_Z22__device_stub__processiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7processiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__processiiPfS_, .Lfunc_end0-_Z22__device_stub__processiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7processiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7processiiPfS_,@object # @_Z7processiiPfS_
.section .rodata,"a",@progbits
.globl _Z7processiiPfS_
.p2align 3, 0x0
_Z7processiiPfS_:
.quad _Z22__device_stub__processiiPfS_
.size _Z7processiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7processiiPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__processiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7processiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <unistd.h>
#define THREADS 1024
__global__ void kernel(float* d_1,float* d_2){
int id;
id = blockDim.x*blockIdx.x + threadIdx.x;
d_1[id] += 1.0f;
d_2[id] += d_1[id];
}
int main(){
cudaError_t res;
float *d_1,*d_2,*h;
size_t pitch;
size_t size = THREADS * 10;
int i,ite = 1000;
h = (float*)malloc(sizeof(float)*size*size);
for(i = 0 ; i < size*size ; i ++)
h[i] = 0.0f;
res = cudaMallocPitch(&d_1,&pitch,sizeof(float)*size,size);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
res = cudaMallocPitch(&d_2,&pitch,sizeof(float)*size,size);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
printf("pitch : %lu\n",pitch);
printf("height : %lu\n",size);
printf("region : %lu[MB]\n",pitch*size >> 20);
res = cudaMemcpy2D(d_1,pitch,h,sizeof(float)*size,sizeof(float)*size,size,cudaMemcpyHostToDevice);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
res = cudaMemcpy2D(d_2,pitch,h,sizeof(float)*size,sizeof(float)*size,size,cudaMemcpyHostToDevice);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
dim3 threads(THREADS,1,1);
dim3 blocks(size/THREADS,1,1);
for(i = 0 ; i < ite ; i ++){
kernel<<<blocks,threads>>>(d_1,d_2);
}
res = cudaMemcpy(h,d_2,sizeof(float)*size*size,cudaMemcpyDeviceToHost);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
for(i = 0 ; i < size ; i ++){
if(h[i] != ((ite+1)*ite)/2.0f ){
printf("h[%d] == %f\n",i,h[i]);
exit(-1);
}
}
sleep(10);
return 0;
} | code for sm_80
Function : _Z6kernelPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FADD R7, R0, 1 ; /* 0x3f80000000077421 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x004fca0000000000 */
/*00d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <unistd.h>
#define THREADS 1024
__global__ void kernel(float* d_1,float* d_2){
int id;
id = blockDim.x*blockIdx.x + threadIdx.x;
d_1[id] += 1.0f;
d_2[id] += d_1[id];
}
int main(){
cudaError_t res;
float *d_1,*d_2,*h;
size_t pitch;
size_t size = THREADS * 10;
int i,ite = 1000;
h = (float*)malloc(sizeof(float)*size*size);
for(i = 0 ; i < size*size ; i ++)
h[i] = 0.0f;
res = cudaMallocPitch(&d_1,&pitch,sizeof(float)*size,size);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
res = cudaMallocPitch(&d_2,&pitch,sizeof(float)*size,size);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
printf("pitch : %lu\n",pitch);
printf("height : %lu\n",size);
printf("region : %lu[MB]\n",pitch*size >> 20);
res = cudaMemcpy2D(d_1,pitch,h,sizeof(float)*size,sizeof(float)*size,size,cudaMemcpyHostToDevice);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
res = cudaMemcpy2D(d_2,pitch,h,sizeof(float)*size,sizeof(float)*size,size,cudaMemcpyHostToDevice);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
dim3 threads(THREADS,1,1);
dim3 blocks(size/THREADS,1,1);
for(i = 0 ; i < ite ; i ++){
kernel<<<blocks,threads>>>(d_1,d_2);
}
res = cudaMemcpy(h,d_2,sizeof(float)*size*size,cudaMemcpyDeviceToHost);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
for(i = 0 ; i < size ; i ++){
if(h[i] != ((ite+1)*ite)/2.0f ){
printf("h[%d] == %f\n",i,h[i]);
exit(-1);
}
}
sleep(10);
return 0;
} | .file "tmpxft_000b2d3d_00000000-6_mp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPfS_PfS_
.type _Z27__device_stub__Z6kernelPfS_PfS_, @function
_Z27__device_stub__Z6kernelPfS_PfS_:
.LFB2095:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z27__device_stub__Z6kernelPfS_PfS_, .-_Z27__device_stub__Z6kernelPfS_PfS_
.globl _Z6kernelPfS_
.type _Z6kernelPfS_, @function
_Z6kernelPfS_:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z6kernelPfS_, .-_Z6kernelPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Oops ...\n"
.LC2:
.string "pitch : %lu\n"
.LC3:
.string "height : %lu\n"
.LC4:
.string "region : %lu[MB]\n"
.LC6:
.string "h[%d] == %f\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $419430400, %edi
call malloc@PLT
movq %rax, %rbp
leaq 419430400(%rax), %rdx
.L12:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
leaq 24(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $10240, %ecx
movl $40960, %edx
call cudaMallocPitch@PLT
testl %eax, %eax
jne .L29
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $10240, %ecx
movl $40960, %edx
call cudaMallocPitch@PLT
testl %eax, %eax
jne .L30
movq 24(%rsp), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10240, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
leaq (%rax,%rax,4), %rdx
salq $11, %rdx
shrq $20, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq $1
.cfi_def_cfa_offset 112
movl $10240, %r9d
movl $40960, %r8d
movl $40960, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy2D@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
testl %eax, %eax
jne .L31
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq $1
.cfi_def_cfa_offset 112
movl $10240, %r9d
movl $40960, %r8d
movl $40960, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy2D@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
testl %eax, %eax
jne .L32
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1000, %ebx
jmp .L18
.L29:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L30:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L31:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L32:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L17:
subl $1, %ebx
je .L33
.L18:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6kernelPfS_PfS_
jmp .L17
.L33:
movl $2, %ecx
movl $419430400, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L34
movl $0, %eax
.L19:
movss 0(%rbp,%rax,4), %xmm0
ucomiss .LC5(%rip), %xmm0
jp .L24
jne .L24
addq $1, %rax
cmpq $10240, %rax
jne .L19
movl $10, %edi
call sleep@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
cvtss2sd %xmm0, %xmm0
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6kernelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1223975552
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <unistd.h>
#define THREADS 1024
__global__ void kernel(float* d_1,float* d_2){
int id;
id = blockDim.x*blockIdx.x + threadIdx.x;
d_1[id] += 1.0f;
d_2[id] += d_1[id];
}
int main(){
cudaError_t res;
float *d_1,*d_2,*h;
size_t pitch;
size_t size = THREADS * 10;
int i,ite = 1000;
h = (float*)malloc(sizeof(float)*size*size);
for(i = 0 ; i < size*size ; i ++)
h[i] = 0.0f;
res = cudaMallocPitch(&d_1,&pitch,sizeof(float)*size,size);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
res = cudaMallocPitch(&d_2,&pitch,sizeof(float)*size,size);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
printf("pitch : %lu\n",pitch);
printf("height : %lu\n",size);
printf("region : %lu[MB]\n",pitch*size >> 20);
res = cudaMemcpy2D(d_1,pitch,h,sizeof(float)*size,sizeof(float)*size,size,cudaMemcpyHostToDevice);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
res = cudaMemcpy2D(d_2,pitch,h,sizeof(float)*size,sizeof(float)*size,size,cudaMemcpyHostToDevice);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
dim3 threads(THREADS,1,1);
dim3 blocks(size/THREADS,1,1);
for(i = 0 ; i < ite ; i ++){
kernel<<<blocks,threads>>>(d_1,d_2);
}
res = cudaMemcpy(h,d_2,sizeof(float)*size*size,cudaMemcpyDeviceToHost);
if(res != cudaSuccess){
printf("Oops ...\n");
exit(-1);
}
for(i = 0 ; i < size ; i ++){
if(h[i] != ((ite+1)*ite)/2.0f ){
printf("h[%d] == %f\n",i,h[i]);
exit(-1);
}
}
sleep(10);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
#define THREADS 1024
__global__ void kernel(float* d_1,float* d_2){
int id;
id = blockDim.x*blockIdx.x + threadIdx.x;
d_1[id] += 1.0f;
d_2[id] += d_1[id];
}
int main(){
hipError_t res;
float *d_1,*d_2,*h;
size_t pitch;
size_t size = THREADS * 10;
int i,ite = 1000;
h = (float*)malloc(sizeof(float)*size*size);
for(i = 0 ; i < size*size ; i ++)
h[i] = 0.0f;
res = hipMallocPitch(&d_1,&pitch,sizeof(float)*size,size);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
res = hipMallocPitch(&d_2,&pitch,sizeof(float)*size,size);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
printf("pitch : %lu\n",pitch);
printf("height : %lu\n",size);
printf("region : %lu[MB]\n",pitch*size >> 20);
res = hipMemcpy2D(d_1,pitch,h,sizeof(float)*size,sizeof(float)*size,size,hipMemcpyHostToDevice);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
res = hipMemcpy2D(d_2,pitch,h,sizeof(float)*size,sizeof(float)*size,size,hipMemcpyHostToDevice);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
dim3 threads(THREADS,1,1);
dim3 blocks(size/THREADS,1,1);
for(i = 0 ; i < ite ; i ++){
kernel<<<blocks,threads>>>(d_1,d_2);
}
res = hipMemcpy(h,d_2,sizeof(float)*size*size,hipMemcpyDeviceToHost);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
for(i = 0 ; i < size ; i ++){
if(h[i] != ((ite+1)*ite)/2.0f ){
printf("h[%d] == %f\n",i,h[i]);
exit(-1);
}
}
sleep(10);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
#define THREADS 1024
__global__ void kernel(float* d_1,float* d_2){
int id;
id = blockDim.x*blockIdx.x + threadIdx.x;
d_1[id] += 1.0f;
d_2[id] += d_1[id];
}
int main(){
hipError_t res;
float *d_1,*d_2,*h;
size_t pitch;
size_t size = THREADS * 10;
int i,ite = 1000;
h = (float*)malloc(sizeof(float)*size*size);
for(i = 0 ; i < size*size ; i ++)
h[i] = 0.0f;
res = hipMallocPitch(&d_1,&pitch,sizeof(float)*size,size);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
res = hipMallocPitch(&d_2,&pitch,sizeof(float)*size,size);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
printf("pitch : %lu\n",pitch);
printf("height : %lu\n",size);
printf("region : %lu[MB]\n",pitch*size >> 20);
res = hipMemcpy2D(d_1,pitch,h,sizeof(float)*size,sizeof(float)*size,size,hipMemcpyHostToDevice);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
res = hipMemcpy2D(d_2,pitch,h,sizeof(float)*size,sizeof(float)*size,size,hipMemcpyHostToDevice);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
dim3 threads(THREADS,1,1);
dim3 blocks(size/THREADS,1,1);
for(i = 0 ; i < ite ; i ++){
kernel<<<blocks,threads>>>(d_1,d_2);
}
res = hipMemcpy(h,d_2,sizeof(float)*size*size,hipMemcpyDeviceToHost);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
for(i = 0 ; i < size ; i ++){
if(h[i] != ((ite+1)*ite)/2.0f ){
printf("h[%d] == %f\n",i,h[i]);
exit(-1);
}
}
sleep(10);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_
.globl _Z6kernelPfS_
.p2align 8
.type _Z6kernelPfS_,@function
_Z6kernelPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, 1.0, v4
global_store_b32 v[2:3], v4, off
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v4, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_, .Lfunc_end0-_Z6kernelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
#define THREADS 1024
__global__ void kernel(float* d_1,float* d_2){
int id;
id = blockDim.x*blockIdx.x + threadIdx.x;
d_1[id] += 1.0f;
d_2[id] += d_1[id];
}
int main(){
hipError_t res;
float *d_1,*d_2,*h;
size_t pitch;
size_t size = THREADS * 10;
int i,ite = 1000;
h = (float*)malloc(sizeof(float)*size*size);
for(i = 0 ; i < size*size ; i ++)
h[i] = 0.0f;
res = hipMallocPitch(&d_1,&pitch,sizeof(float)*size,size);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
res = hipMallocPitch(&d_2,&pitch,sizeof(float)*size,size);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
printf("pitch : %lu\n",pitch);
printf("height : %lu\n",size);
printf("region : %lu[MB]\n",pitch*size >> 20);
res = hipMemcpy2D(d_1,pitch,h,sizeof(float)*size,sizeof(float)*size,size,hipMemcpyHostToDevice);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
res = hipMemcpy2D(d_2,pitch,h,sizeof(float)*size,sizeof(float)*size,size,hipMemcpyHostToDevice);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
dim3 threads(THREADS,1,1);
dim3 blocks(size/THREADS,1,1);
for(i = 0 ; i < ite ; i ++){
kernel<<<blocks,threads>>>(d_1,d_2);
}
res = hipMemcpy(h,d_2,sizeof(float)*size*size,hipMemcpyDeviceToHost);
if(res != hipSuccess){
printf("Oops ...\n");
exit(-1);
}
for(i = 0 ; i < size ; i ++){
if(h[i] != ((ite+1)*ite)/2.0f ){
printf("h[%d] == %f\n",i,h[i]);
exit(-1);
}
}
sleep(10);
return 0;
} | .text
.file "mp.hip"
.globl _Z21__device_stub__kernelPfS_ # -- Begin function _Z21__device_stub__kernelPfS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_,@function
_Z21__device_stub__kernelPfS_: # @_Z21__device_stub__kernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_, .Lfunc_end0-_Z21__device_stub__kernelPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x48f46280 # float 500500
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $419430400, %edi # imm = 0x19000000
callq malloc
movq %rax, %rbx
movl $419430400, %edx # imm = 0x19000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $40960, %edx # imm = 0xA000
movl $10240, %ecx # imm = 0x2800
callq hipMallocPitch
testl %eax, %eax
jne .LBB1_13
# %bb.1:
leaq 32(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $40960, %edx # imm = 0xA000
movl $10240, %ecx # imm = 0x2800
callq hipMallocPitch
testl %eax, %eax
jne .LBB1_13
# %bb.2:
movq 24(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $10240, %esi # imm = 0x2800
xorl %eax, %eax
callq printf
movq 24(%rsp), %rax
shlq $11, %rax
leaq (%rax,%rax,4), %rsi
shrq $20, %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 40(%rsp), %rdi
movq 24(%rsp), %rsi
movl $1, (%rsp)
movl $40960, %ecx # imm = 0xA000
movl $40960, %r8d # imm = 0xA000
movl $10240, %r9d # imm = 0x2800
movq %rbx, %rdx
callq hipMemcpy2D
testl %eax, %eax
jne .LBB1_13
# %bb.3:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movl $1, (%rsp)
movl $40960, %ecx # imm = 0xA000
movl $40960, %r8d # imm = 0xA000
movl $10240, %r9d # imm = 0x2800
movq %rbx, %rdx
callq hipMemcpy2D
testl %eax, %eax
jne .LBB1_13
# %bb.4: # %.preheader63
movl $1000, %ebp # imm = 0x3E8
movabsq $4294967306, %r14 # imm = 0x10000000A
leaq 1014(%r14), %r15
leaq 48(%rsp), %r12
leaq 112(%rsp), %r13
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
decl %ebp
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rax
movq 48(%rsp), %rdi
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
movl $_Z6kernelPfS_, %edi
movq %r13, %r9
callq hipLaunchKernel
jmp .LBB1_7
.LBB1_8:
movq 32(%rsp), %rsi
movl $419430400, %edx # imm = 0x19000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.9: # %.preheader.preheader
xorl %esi, %esi
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_10: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB1_14
jp .LBB1_14
# %bb.11: # in Loop: Header=BB1_10 Depth=1
incq %rsi
cmpq $10240, %rsi # imm = 0x2800
jne .LBB1_10
# %bb.12:
movl $10, %edi
callq sleep
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_14:
.cfi_def_cfa_offset 192
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.4, %edi
# kill: def $esi killed $esi killed $rsi
movb $1, %al
callq printf
movl $-1, %edi
callq exit
.LBB1_13:
movl $.Lstr.4, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfS_,@object # @_Z6kernelPfS_
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_
.p2align 3, 0x0
_Z6kernelPfS_:
.quad _Z21__device_stub__kernelPfS_
.size _Z6kernelPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "pitch : %lu\n"
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "height : %lu\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "region : %lu[MB]\n"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "h[%d] == %f\n"
.size .L.str.4, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.4,@object # @str.4
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.4:
.asciz "Oops ..."
.size .Lstr.4, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FADD R7, R0, 1 ; /* 0x3f80000000077421 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x004fca0000000000 */
/*00d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_
.globl _Z6kernelPfS_
.p2align 8
.type _Z6kernelPfS_,@function
_Z6kernelPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, 1.0, v4
global_store_b32 v[2:3], v4, off
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v4, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_, .Lfunc_end0-_Z6kernelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b2d3d_00000000-6_mp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPfS_PfS_
.type _Z27__device_stub__Z6kernelPfS_PfS_, @function
_Z27__device_stub__Z6kernelPfS_PfS_:
.LFB2095:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z27__device_stub__Z6kernelPfS_PfS_, .-_Z27__device_stub__Z6kernelPfS_PfS_
.globl _Z6kernelPfS_
.type _Z6kernelPfS_, @function
_Z6kernelPfS_:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z6kernelPfS_, .-_Z6kernelPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Oops ...\n"
.LC2:
.string "pitch : %lu\n"
.LC3:
.string "height : %lu\n"
.LC4:
.string "region : %lu[MB]\n"
.LC6:
.string "h[%d] == %f\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $419430400, %edi
call malloc@PLT
movq %rax, %rbp
leaq 419430400(%rax), %rdx
.L12:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
leaq 24(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $10240, %ecx
movl $40960, %edx
call cudaMallocPitch@PLT
testl %eax, %eax
jne .L29
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $10240, %ecx
movl $40960, %edx
call cudaMallocPitch@PLT
testl %eax, %eax
jne .L30
movq 24(%rsp), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10240, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
leaq (%rax,%rax,4), %rdx
salq $11, %rdx
shrq $20, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq $1
.cfi_def_cfa_offset 112
movl $10240, %r9d
movl $40960, %r8d
movl $40960, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy2D@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
testl %eax, %eax
jne .L31
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq $1
.cfi_def_cfa_offset 112
movl $10240, %r9d
movl $40960, %r8d
movl $40960, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy2D@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
testl %eax, %eax
jne .L32
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1000, %ebx
jmp .L18
.L29:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L30:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L31:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L32:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L17:
subl $1, %ebx
je .L33
.L18:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6kernelPfS_PfS_
jmp .L17
.L33:
movl $2, %ecx
movl $419430400, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L34
movl $0, %eax
.L19:
movss 0(%rbp,%rax,4), %xmm0
ucomiss .LC5(%rip), %xmm0
jp .L24
jne .L24
addq $1, %rax
cmpq $10240, %rax
jne .L19
movl $10, %edi
call sleep@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
cvtss2sd %xmm0, %xmm0
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6kernelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1223975552
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mp.hip"
.globl _Z21__device_stub__kernelPfS_ # -- Begin function _Z21__device_stub__kernelPfS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_,@function
_Z21__device_stub__kernelPfS_: # @_Z21__device_stub__kernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_, .Lfunc_end0-_Z21__device_stub__kernelPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x48f46280 # float 500500
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $419430400, %edi # imm = 0x19000000
callq malloc
movq %rax, %rbx
movl $419430400, %edx # imm = 0x19000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $40960, %edx # imm = 0xA000
movl $10240, %ecx # imm = 0x2800
callq hipMallocPitch
testl %eax, %eax
jne .LBB1_13
# %bb.1:
leaq 32(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $40960, %edx # imm = 0xA000
movl $10240, %ecx # imm = 0x2800
callq hipMallocPitch
testl %eax, %eax
jne .LBB1_13
# %bb.2:
movq 24(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $10240, %esi # imm = 0x2800
xorl %eax, %eax
callq printf
movq 24(%rsp), %rax
shlq $11, %rax
leaq (%rax,%rax,4), %rsi
shrq $20, %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 40(%rsp), %rdi
movq 24(%rsp), %rsi
movl $1, (%rsp)
movl $40960, %ecx # imm = 0xA000
movl $40960, %r8d # imm = 0xA000
movl $10240, %r9d # imm = 0x2800
movq %rbx, %rdx
callq hipMemcpy2D
testl %eax, %eax
jne .LBB1_13
# %bb.3:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movl $1, (%rsp)
movl $40960, %ecx # imm = 0xA000
movl $40960, %r8d # imm = 0xA000
movl $10240, %r9d # imm = 0x2800
movq %rbx, %rdx
callq hipMemcpy2D
testl %eax, %eax
jne .LBB1_13
# %bb.4: # %.preheader63
movl $1000, %ebp # imm = 0x3E8
movabsq $4294967306, %r14 # imm = 0x10000000A
leaq 1014(%r14), %r15
leaq 48(%rsp), %r12
leaq 112(%rsp), %r13
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
decl %ebp
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rax
movq 48(%rsp), %rdi
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
movl $_Z6kernelPfS_, %edi
movq %r13, %r9
callq hipLaunchKernel
jmp .LBB1_7
.LBB1_8:
movq 32(%rsp), %rsi
movl $419430400, %edx # imm = 0x19000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.9: # %.preheader.preheader
xorl %esi, %esi
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_10: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB1_14
jp .LBB1_14
# %bb.11: # in Loop: Header=BB1_10 Depth=1
incq %rsi
cmpq $10240, %rsi # imm = 0x2800
jne .LBB1_10
# %bb.12:
movl $10, %edi
callq sleep
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_14:
.cfi_def_cfa_offset 192
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.4, %edi
# kill: def $esi killed $esi killed $rsi
movb $1, %al
callq printf
movl $-1, %edi
callq exit
.LBB1_13:
movl $.Lstr.4, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfS_,@object # @_Z6kernelPfS_
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_
.p2align 3, 0x0
_Z6kernelPfS_:
.quad _Z21__device_stub__kernelPfS_
.size _Z6kernelPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "pitch : %lu\n"
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "height : %lu\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "region : %lu[MB]\n"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "h[%d] == %f\n"
.size .L.str.4, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.4,@object # @str.4
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.4:
.asciz "Oops ..."
.size .Lstr.4, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // System includes
#include <stdio.h>
// CUDA runtime
#include <cuda_runtime.h>
// CUDA device code highlight
#include <device_launch_parameters.h>
// CUDA Profiler function
#include <cuda_profiler_api.h>
#define BLOCK_DIM 16
////////////////////////////////////////////////////////////////////////////////
//! Compute reference data set matrix multiply on GPU
//! C = alpha * A * B + beta * C
//! @param A matrix A as provided to device
//! @param B matrix B as provided to device
//! @param C matrix C as provided to device
//! @param N height of matrix A and matrix C
//! @param M width of matrix B and matrix C
//! @param K width of matrix A and height of matrix C
//! @param alpha scala value for matrix multiplication
//! @param beta scala value for matrix summation with C
////////////////////////////////////////////////////////////////////////////////
__global__ void sgemm_kernel(const float *A, const float *B, float *C,
int N, int M, int K,
float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float sum = 0.f;
for (int i = 0; i < K; ++i)
sum += A[row * K + i] * B[i * K + col];
C[row * M + col] = alpha * sum + beta * C[row * M + col];
}
void random_init(float *data, int size)
{
for (int i = 0; i < size; ++i)
{
data[i] = (rand() & 0xFF) / (float)RAND_MAX;
}
}
int main()
{
float *A, *B, *C;
float *d_A, *d_B, *d_C;
int N, M, K;
float alpha = 2.f;
float beta = 1.f;
int n_iter = 1;
N = M = K = 2048;
// allocation of linear memory space
A = (float *)malloc(N * K * sizeof(float));
B = (float *)malloc(K * M * sizeof(float));
C = (float *)malloc(N * M * sizeof(float));
// allocation of gpu linear memory space
cudaMalloc((void **)&d_A, N * K * sizeof(float));
cudaMalloc((void **)&d_B, K * M * sizeof(float));
cudaMalloc((void **)&d_C, N * M * sizeof(float));
// initialize randomized values for memory space
random_init(A, N * K);
random_init(B, K * M);
random_init(C, N * M);
// copy initial value for gpu memory
cudaMemcpy(d_A, A, N * K * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, K * M * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_C, C, N * M * sizeof(float), cudaMemcpyHostToDevice);
// do operation
for (int i = 0; i < n_iter; i++) {
dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
dim3 dimGrid(M / dimBlock.x, N / dimBlock.y);
sgemm_kernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, N, M, K, alpha, beta);
cudaGetLastError();
}
cudaDeviceSynchronize();
printf("Application finished successfully.");
// terminates allocated gpu memory space
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// terminates allocated memory space
free(A);
free(B);
free(C);
return 0;
} | code for sm_80
Function : _Z12sgemm_kernelPKfS0_Pfiiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R4, c[0x0][0x4], R5 ; /* 0x0000010004037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xbd0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xad0 ; /* 0x000009b000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R6, -R5, c[0x0][0x180], RZ ; /* 0x0000600005067a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0140*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0150*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD R7, R3, c[0x0][0x180], RZ ; /* 0x0000600003077a24 */
/* 0x000fe200078e02ff */
/*0180*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fcc00078e0209 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R14, R7, 0x4, R14 ; /* 0x00000004070e7825 */
/* 0x000fca00078e020e */
/*0230*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fc600078e0208 */
/*0250*/ LDG.E R18, [R14.64+0x4] ; /* 0x000004040e127981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R22, R0.reuse, 0x4, R8 ; /* 0x0000000400167825 */
/* 0x040fe200078e0208 */
/*0270*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0000e8000c1e1900 */
/*0280*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x000322000c1e1900 */
/*0290*/ IMAD.WIDE R26, R0, 0x4, R22 ; /* 0x00000004001a7825 */
/* 0x000fc600078e0216 */
/*02a0*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008040e1d7981 */
/* 0x000f26000c1e1900 */
/*02b0*/ IMAD.WIDE R12, R0.reuse, 0x4, R26 ; /* 0x00000004000c7825 */
/* 0x040fe200078e021a */
/*02c0*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000b28000c1e1900 */
/*02d0*/ LDG.E R17, [R14.64+0xc] ; /* 0x00000c040e117981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R20, [R14.64+0x10] ; /* 0x000010040e147981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R8, [R14.64+0x14] ; /* 0x000014040e087981 */
/* 0x001f28000c1e1900 */
/*0310*/ LDG.E R26, [R14.64+0x1c] ; /* 0x00001c040e1a7981 */
/* 0x020f62000c1e1900 */
/*0320*/ IMAD.WIDE R12, R0, 0x4, R12 ; /* 0x00000004000c7825 */
/* 0x002fca00078e020c */
/*0330*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000562000c1e1900 */
/*0340*/ IMAD.WIDE R22, R0, 0x4, R12 ; /* 0x0000000400167825 */
/* 0x000fc800078e020c */
/*0350*/ FFMA R12, R11, R10, R24 ; /* 0x0000000a0b0c7223 */
/* 0x004fe40000000018 */
/*0360*/ LDG.E R10, [R14.64+0x18] ; /* 0x000018040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x0000a8000c1e1900 */
/*0390*/ LDG.E R27, [R24.64] ; /* 0x00000004181b7981 */
/* 0x0002a2000c1e1900 */
/*03a0*/ FFMA R12, R19, R18, R12 ; /* 0x00000012130c7223 */
/* 0x008fe4000000000c */
/*03b0*/ IMAD.WIDE R18, R0, 0x4, R24 ; /* 0x0000000400127825 */
/* 0x000fe200078e0218 */
/*03c0*/ LDG.E R23, [R14.64+0x20] ; /* 0x000020040e177981 */
/* 0x001ee6000c1e1900 */
/*03d0*/ FFMA R28, R28, R29, R12 ; /* 0x0000001d1c1c7223 */
/* 0x010fc4000000000c */
/*03e0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0212 */
/*03f0*/ LDG.E R25, [R14.64+0x24] ; /* 0x000024040e197981 */
/* 0x002f26000c1e1900 */
/*0400*/ FFMA R28, R16, R17, R28 ; /* 0x00000011101c7223 */
/* 0x000fe2000000001c */
/*0410*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0420*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0430*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000322000c1e1900 */
/*0440*/ FFMA R28, R21, R20, R28 ; /* 0x00000014151c7223 */
/* 0x000fc6000000001c */
/*0450*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x0002e2000c1e1900 */
/*0460*/ IMAD.WIDE R20, R0, 0x4, R16 ; /* 0x0000000400147825 */
/* 0x000fc600078e0210 */
/*0470*/ LDG.E R29, [R14.64+0x28] ; /* 0x000028040e1d7981 */
/* 0x000f28000c1e1900 */
/*0480*/ LDG.E R19, [R14.64+0x2c] ; /* 0x00002c040e137981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R24, [R14.64+0x30] ; /* 0x000030040e187981 */
/* 0x000f22000c1e1900 */
/*04a0*/ FFMA R28, R9, R8, R28 ; /* 0x00000008091c7223 */
/* 0x020fe4000000001c */
/*04b0*/ IMAD.WIDE R8, R0, 0x4, R20 ; /* 0x0000000400087825 */
/* 0x000fc400078e0214 */
/*04c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000168000c1e1900 */
/*04d0*/ LDG.E R21, [R14.64+0x38] ; /* 0x000038040e157981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R28, R11, R10, R28 ; /* 0x0000000a0b1c7223 */
/* 0x004fe4000000001c */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fe400078e0208 */
/*0500*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0000a4000c1e1900 */
/*0510*/ FFMA R13, R27, R26, R28 ; /* 0x0000001a1b0d7223 */
/* 0x002fc4000000001c */
/*0520*/ IMAD.WIDE R26, R0.reuse, 0x4, R10 ; /* 0x00000004001a7825 */
/* 0x040fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002a8000c1e1900 */
/*0540*/ LDG.E R9, [R14.64+0x34] ; /* 0x000034040e097981 */
/* 0x001ea2000c1e1900 */
/*0550*/ IMAD.WIDE R16, R0, 0x4, R26 ; /* 0x0000000400107825 */
/* 0x000fc600078e021a */
/*0560*/ LDG.E R28, [R26.64] ; /* 0x000000041a1c7981 */
/* 0x0000a8000c1e1900 */
/*0570*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x002ea8000c1e1900 */
/*0580*/ LDG.E R26, [R14.64+0x3c] ; /* 0x00003c040e1a7981 */
/* 0x001ea2000c1e1900 */
/*0590*/ FFMA R13, R18, R23, R13 ; /* 0x00000017120d7223 */
/* 0x008fc8000000000d */
/*05a0*/ FFMA R12, R12, R25, R13 ; /* 0x000000190c0c7223 */
/* 0x010fe2000000000d */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ FFMA R12, R22, R29, R12 ; /* 0x0000001d160c7223 */
/* 0x000fe2000000000c */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*05e0*/ FFMA R19, R20, R19, R12 ; /* 0x0000001314137223 */
/* 0x020fe2000000000c */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R8, R8, R24, R19 ; /* 0x0000001808087223 */
/* 0x004fc80000000013 */
/*0630*/ FFMA R8, R10, R9, R8 ; /* 0x000000090a087223 */
/* 0x000fc80000000008 */
/*0640*/ FFMA R8, R28, R21, R8 ; /* 0x000000151c087223 */
/* 0x000fc80000000008 */
/*0650*/ FFMA R24, R11, R26, R8 ; /* 0x0000001a0b187223 */
/* 0x000fe40000000008 */
/*0660*/ IMAD.WIDE R8, R0, 0x4, R16 ; /* 0x0000000400087825 */
/* 0x000fe200078e0210 */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R8 ; /* 0x0000000400107825 */
/* 0x000fe200078e0208 */
/*06b0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0.reuse, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x040fe400078e0210 */
/*06f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e4000c1e1900 */
/*0700*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fe400078e020a */
/*0710*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000964000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe400078e020c */
/*0730*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R20, R0.reuse, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x040fe200078e0212 */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R8, R0, 0x4, R20 ; /* 0x0000000400087825 */
/* 0x001fc600078e0214 */
/*07b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07c0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0208 */
/*07e0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f28000c1e1900 */
/*0800*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000328000c1e1900 */
/*0810*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x001f28000c1e1900 */
/*0820*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f28000c1e1900 */
/*0830*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08a0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*08b0*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*08c0*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*08d0*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*08e0*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x010fc80000000012 */
/*08f0*/ FFMA R8, R17, R8, R15 ; /* 0x0000000811087223 */
/* 0x000fc8000000000f */
/*0900*/ FFMA R24, R9, R19, R8 ; /* 0x0000001309187223 */
/* 0x000fe40000000008 */
/*0910*/ IMAD.WIDE R8, R0, 0x4, R12 ; /* 0x0000000400087825 */
/* 0x000fc800078e020c */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fe200078e0208 */
/*0960*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*0990*/ IMAD.WIDE R14, R0.reuse, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020a */
/*09a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*09d0*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R20, [R12.64+0x8] ; /* 0x000008040c147981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R22, [R12.64+0xc] ; /* 0x00000c040c167981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0a80*/ FFMA R18, R11, R19, R18 ; /* 0x000000130b127223 */
/* 0x008fe40000000012 */
/*0a90*/ IMAD.WIDE R8, R0, 0x4, R16 ; /* 0x0000000400087825 */
/* 0x000fc800078e0210 */
/*0aa0*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0ab0*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbd0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b00*/ IMAD R6, R3, c[0x0][0x180], R4 ; /* 0x0000600003067a24 */
/* 0x000fe400078e0204 */
/*0b10*/ IMAD R4, R4, c[0x0][0x180], R2 ; /* 0x0000600004047a24 */
/* 0x000fce00078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b30*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b40*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b50*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b60*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b70*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b80*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0b90*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0ba0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bb0*/ FFMA R24, R11, R4, R24 ; /* 0x000000040b187223 */
/* 0x004fcc0000000018 */
/*0bc0*/ @P0 BRA 0xb40 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bd0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe20000000f00 */
/*0be0*/ IMAD R2, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003027a24 */
/* 0x000fc800078e0202 */
/*0bf0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0205 */
/*0c00*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0c10*/ FMUL R5, R0, c[0x0][0x188] ; /* 0x0000620000057a20 */
/* 0x004fc80000400000 */
/*0c20*/ FFMA R5, R24, c[0x0][0x184], R5 ; /* 0x0000610018057a23 */
/* 0x000fca0000000005 */
/*0c30*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // System includes
#include <stdio.h>
// CUDA runtime
#include <cuda_runtime.h>
// CUDA device code highlight
#include <device_launch_parameters.h>
// CUDA Profiler function
#include <cuda_profiler_api.h>
#define BLOCK_DIM 16
////////////////////////////////////////////////////////////////////////////////
//! Compute reference data set matrix multiply on GPU
//! C = alpha * A * B + beta * C
//! @param A matrix A as provided to device
//! @param B matrix B as provided to device
//! @param C matrix C as provided to device
//! @param N height of matrix A and matrix C
//! @param M width of matrix B and matrix C
//! @param K width of matrix A and height of matrix C
//! @param alpha scala value for matrix multiplication
//! @param beta scala value for matrix summation with C
////////////////////////////////////////////////////////////////////////////////
__global__ void sgemm_kernel(const float *A, const float *B, float *C,
int N, int M, int K,
float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float sum = 0.f;
for (int i = 0; i < K; ++i)
sum += A[row * K + i] * B[i * K + col];
C[row * M + col] = alpha * sum + beta * C[row * M + col];
}
void random_init(float *data, int size)
{
for (int i = 0; i < size; ++i)
{
data[i] = (rand() & 0xFF) / (float)RAND_MAX;
}
}
int main()
{
float *A, *B, *C;
float *d_A, *d_B, *d_C;
int N, M, K;
float alpha = 2.f;
float beta = 1.f;
int n_iter = 1;
N = M = K = 2048;
// allocation of linear memory space
A = (float *)malloc(N * K * sizeof(float));
B = (float *)malloc(K * M * sizeof(float));
C = (float *)malloc(N * M * sizeof(float));
// allocation of gpu linear memory space
cudaMalloc((void **)&d_A, N * K * sizeof(float));
cudaMalloc((void **)&d_B, K * M * sizeof(float));
cudaMalloc((void **)&d_C, N * M * sizeof(float));
// initialize randomized values for memory space
random_init(A, N * K);
random_init(B, K * M);
random_init(C, N * M);
// copy initial value for gpu memory
cudaMemcpy(d_A, A, N * K * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, K * M * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_C, C, N * M * sizeof(float), cudaMemcpyHostToDevice);
// do operation
for (int i = 0; i < n_iter; i++) {
dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
dim3 dimGrid(M / dimBlock.x, N / dimBlock.y);
sgemm_kernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, N, M, K, alpha, beta);
cudaGetLastError();
}
cudaDeviceSynchronize();
printf("Application finished successfully.");
// terminates allocated gpu memory space
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// terminates allocated memory space
free(A);
free(B);
free(C);
return 0;
} | .file "tmpxft_000852c7_00000000-6_simple_sgemm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_initPfi
.type _Z11random_initPfi, @function
_Z11random_initPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_initPfi, .-_Z11random_initPfi
.globl _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
.type _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff, @function
_Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff:
.LFB2083:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12sgemm_kernelPKfS0_Pfiiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff, .-_Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
.globl _Z12sgemm_kernelPKfS0_Pfiiiff
.type _Z12sgemm_kernelPKfS0_Pfiiiff, @function
_Z12sgemm_kernelPKfS0_Pfiiiff:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12sgemm_kernelPKfS0_Pfiiiff, .-_Z12sgemm_kernelPKfS0_Pfiiiff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Application finished successfully."
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $4194304, %esi
movq %r12, %rdi
call _Z11random_initPfi
movl $4194304, %esi
movq %rbp, %rdi
call _Z11random_initPfi
movl $4194304, %esi
movq %rbx, %rdi
call _Z11random_initPfi
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 44(%rsp)
movl $128, 48(%rsp)
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
call cudaGetLastError@PLT
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
movl $2048, %r9d
movl $2048, %r8d
movl $2048, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z12sgemm_kernelPKfS0_Pfiiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sgemm_kernelPKfS0_Pfiiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // System includes
#include <stdio.h>
// CUDA runtime
#include <cuda_runtime.h>
// CUDA device code highlight
#include <device_launch_parameters.h>
// CUDA Profiler function
#include <cuda_profiler_api.h>
#define BLOCK_DIM 16
////////////////////////////////////////////////////////////////////////////////
//! Compute reference data set matrix multiply on GPU
//! C = alpha * A * B + beta * C
//! @param A matrix A as provided to device
//! @param B matrix B as provided to device
//! @param C matrix C as provided to device
//! @param N height of matrix A and matrix C
//! @param M width of matrix B and matrix C
//! @param K width of matrix A and height of matrix C
//! @param alpha scala value for matrix multiplication
//! @param beta scala value for matrix summation with C
////////////////////////////////////////////////////////////////////////////////
__global__ void sgemm_kernel(const float *A, const float *B, float *C,
int N, int M, int K,
float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float sum = 0.f;
for (int i = 0; i < K; ++i)
sum += A[row * K + i] * B[i * K + col];
C[row * M + col] = alpha * sum + beta * C[row * M + col];
}
void random_init(float *data, int size)
{
for (int i = 0; i < size; ++i)
{
data[i] = (rand() & 0xFF) / (float)RAND_MAX;
}
}
int main()
{
float *A, *B, *C;
float *d_A, *d_B, *d_C;
int N, M, K;
float alpha = 2.f;
float beta = 1.f;
int n_iter = 1;
N = M = K = 2048;
// allocation of linear memory space
A = (float *)malloc(N * K * sizeof(float));
B = (float *)malloc(K * M * sizeof(float));
C = (float *)malloc(N * M * sizeof(float));
// allocation of gpu linear memory space
cudaMalloc((void **)&d_A, N * K * sizeof(float));
cudaMalloc((void **)&d_B, K * M * sizeof(float));
cudaMalloc((void **)&d_C, N * M * sizeof(float));
// initialize randomized values for memory space
random_init(A, N * K);
random_init(B, K * M);
random_init(C, N * M);
// copy initial value for gpu memory
cudaMemcpy(d_A, A, N * K * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, K * M * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_C, C, N * M * sizeof(float), cudaMemcpyHostToDevice);
// do operation
for (int i = 0; i < n_iter; i++) {
dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
dim3 dimGrid(M / dimBlock.x, N / dimBlock.y);
sgemm_kernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, N, M, K, alpha, beta);
cudaGetLastError();
}
cudaDeviceSynchronize();
printf("Application finished successfully.");
// terminates allocated gpu memory space
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// terminates allocated memory space
free(A);
free(B);
free(C);
return 0;
} | // System includes
#include <stdio.h>
// CUDA runtime
#include <hip/hip_runtime.h>
// CUDA device code highlight
// CUDA Profiler function
#include <hip/hip_runtime_api.h>
#define BLOCK_DIM 16
////////////////////////////////////////////////////////////////////////////////
//! Compute reference data set matrix multiply on GPU
//! C = alpha * A * B + beta * C
//! @param A matrix A as provided to device
//! @param B matrix B as provided to device
//! @param C matrix C as provided to device
//! @param N height of matrix A and matrix C
//! @param M width of matrix B and matrix C
//! @param K width of matrix A and height of matrix C
//! @param alpha scala value for matrix multiplication
//! @param beta scala value for matrix summation with C
////////////////////////////////////////////////////////////////////////////////
__global__ void sgemm_kernel(const float *A, const float *B, float *C,
int N, int M, int K,
float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float sum = 0.f;
for (int i = 0; i < K; ++i)
sum += A[row * K + i] * B[i * K + col];
C[row * M + col] = alpha * sum + beta * C[row * M + col];
}
void random_init(float *data, int size)
{
for (int i = 0; i < size; ++i)
{
data[i] = (rand() & 0xFF) / (float)RAND_MAX;
}
}
int main()
{
float *A, *B, *C;
float *d_A, *d_B, *d_C;
int N, M, K;
float alpha = 2.f;
float beta = 1.f;
int n_iter = 1;
N = M = K = 2048;
// allocation of linear memory space
A = (float *)malloc(N * K * sizeof(float));
B = (float *)malloc(K * M * sizeof(float));
C = (float *)malloc(N * M * sizeof(float));
// allocation of gpu linear memory space
hipMalloc((void **)&d_A, N * K * sizeof(float));
hipMalloc((void **)&d_B, K * M * sizeof(float));
hipMalloc((void **)&d_C, N * M * sizeof(float));
// initialize randomized values for memory space
random_init(A, N * K);
random_init(B, K * M);
random_init(C, N * M);
// copy initial value for gpu memory
hipMemcpy(d_A, A, N * K * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, K * M * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_C, C, N * M * sizeof(float), hipMemcpyHostToDevice);
// do operation
for (int i = 0; i < n_iter; i++) {
dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
dim3 dimGrid(M / dimBlock.x, N / dimBlock.y);
sgemm_kernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, N, M, K, alpha, beta);
hipGetLastError();
}
hipDeviceSynchronize();
printf("Application finished successfully.");
// terminates allocated gpu memory space
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// terminates allocated memory space
free(A);
free(B);
free(C);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // System includes
#include <stdio.h>
// CUDA runtime
#include <hip/hip_runtime.h>
// CUDA device code highlight
// CUDA Profiler function
#include <hip/hip_runtime_api.h>
#define BLOCK_DIM 16
////////////////////////////////////////////////////////////////////////////////
//! Compute reference data set matrix multiply on GPU
//! C = alpha * A * B + beta * C
//! @param A matrix A as provided to device
//! @param B matrix B as provided to device
//! @param C matrix C as provided to device
//! @param N height of matrix A and matrix C
//! @param M width of matrix B and matrix C
//! @param K width of matrix A and height of matrix C
//! @param alpha scala value for matrix multiplication
//! @param beta scala value for matrix summation with C
////////////////////////////////////////////////////////////////////////////////
__global__ void sgemm_kernel(const float *A, const float *B, float *C,
int N, int M, int K,
float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float sum = 0.f;
for (int i = 0; i < K; ++i)
sum += A[row * K + i] * B[i * K + col];
C[row * M + col] = alpha * sum + beta * C[row * M + col];
}
void random_init(float *data, int size)
{
for (int i = 0; i < size; ++i)
{
data[i] = (rand() & 0xFF) / (float)RAND_MAX;
}
}
int main()
{
float *A, *B, *C;
float *d_A, *d_B, *d_C;
int N, M, K;
float alpha = 2.f;
float beta = 1.f;
int n_iter = 1;
N = M = K = 2048;
// allocation of linear memory space
A = (float *)malloc(N * K * sizeof(float));
B = (float *)malloc(K * M * sizeof(float));
C = (float *)malloc(N * M * sizeof(float));
// allocation of gpu linear memory space
hipMalloc((void **)&d_A, N * K * sizeof(float));
hipMalloc((void **)&d_B, K * M * sizeof(float));
hipMalloc((void **)&d_C, N * M * sizeof(float));
// initialize randomized values for memory space
random_init(A, N * K);
random_init(B, K * M);
random_init(C, N * M);
// copy initial value for gpu memory
hipMemcpy(d_A, A, N * K * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, K * M * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_C, C, N * M * sizeof(float), hipMemcpyHostToDevice);
// do operation
for (int i = 0; i < n_iter; i++) {
dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
dim3 dimGrid(M / dimBlock.x, N / dimBlock.y);
sgemm_kernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, N, M, K, alpha, beta);
hipGetLastError();
}
hipDeviceSynchronize();
printf("Application finished successfully.");
// terminates allocated gpu memory space
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// terminates allocated memory space
free(A);
free(B);
free(C);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12sgemm_kernelPKfS0_Pfiiiff
.globl _Z12sgemm_kernelPKfS0_Pfiiiff
.p2align 8
.type _Z12sgemm_kernelPKfS0_Pfiiiff,@function
_Z12sgemm_kernelPKfS0_Pfiiiff:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s0, v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sgemm_kernelPKfS0_Pfiiiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12sgemm_kernelPKfS0_Pfiiiff, .Lfunc_end0-_Z12sgemm_kernelPKfS0_Pfiiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sgemm_kernelPKfS0_Pfiiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12sgemm_kernelPKfS0_Pfiiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // System includes
#include <stdio.h>
// CUDA runtime
#include <hip/hip_runtime.h>
// CUDA device code highlight
// CUDA Profiler function
#include <hip/hip_runtime_api.h>
#define BLOCK_DIM 16
////////////////////////////////////////////////////////////////////////////////
//! Compute reference data set matrix multiply on GPU
//! C = alpha * A * B + beta * C
//! @param A matrix A as provided to device
//! @param B matrix B as provided to device
//! @param C matrix C as provided to device
//! @param N height of matrix A and matrix C
//! @param M width of matrix B and matrix C
//! @param K width of matrix A and height of matrix C
//! @param alpha scala value for matrix multiplication
//! @param beta scala value for matrix summation with C
////////////////////////////////////////////////////////////////////////////////
__global__ void sgemm_kernel(const float *A, const float *B, float *C,
int N, int M, int K,
float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float sum = 0.f;
for (int i = 0; i < K; ++i)
sum += A[row * K + i] * B[i * K + col];
C[row * M + col] = alpha * sum + beta * C[row * M + col];
}
void random_init(float *data, int size)
{
for (int i = 0; i < size; ++i)
{
data[i] = (rand() & 0xFF) / (float)RAND_MAX;
}
}
int main()
{
float *A, *B, *C;
float *d_A, *d_B, *d_C;
int N, M, K;
float alpha = 2.f;
float beta = 1.f;
int n_iter = 1;
N = M = K = 2048;
// allocation of linear memory space
A = (float *)malloc(N * K * sizeof(float));
B = (float *)malloc(K * M * sizeof(float));
C = (float *)malloc(N * M * sizeof(float));
// allocation of gpu linear memory space
hipMalloc((void **)&d_A, N * K * sizeof(float));
hipMalloc((void **)&d_B, K * M * sizeof(float));
hipMalloc((void **)&d_C, N * M * sizeof(float));
// initialize randomized values for memory space
random_init(A, N * K);
random_init(B, K * M);
random_init(C, N * M);
// copy initial value for gpu memory
hipMemcpy(d_A, A, N * K * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, K * M * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_C, C, N * M * sizeof(float), hipMemcpyHostToDevice);
// do operation
for (int i = 0; i < n_iter; i++) {
dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
dim3 dimGrid(M / dimBlock.x, N / dimBlock.y);
sgemm_kernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, N, M, K, alpha, beta);
hipGetLastError();
}
hipDeviceSynchronize();
printf("Application finished successfully.");
// terminates allocated gpu memory space
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// terminates allocated memory space
free(A);
free(B);
free(C);
return 0;
} | .text
.file "simple_sgemm.hip"
.globl _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff # -- Begin function _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.p2align 4, 0x90
.type _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff,@function
_Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff: # @_Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12sgemm_kernelPKfS0_Pfiiiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff, .Lfunc_end0-_Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11random_initPfi
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z11random_initPfi
.p2align 4, 0x90
.type _Z11random_initPfi,@function
_Z11random_initPfi: # @_Z11random_initPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_initPfi, .Lfunc_end1-_Z11random_initPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.critedge
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $200, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB2_1
# %bb.2: # %.lr.ph.i48.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i48
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB2_3
# %bb.4: # %.lr.ph.i53.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i53
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB2_5
# %bb.6: # %_Z11random_initPfi.exit57
movq 24(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $549755814016, %rdi # imm = 0x8000000080
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $2048, 52(%rsp) # imm = 0x800
movl $2048, 48(%rsp) # imm = 0x800
movl $2048, 44(%rsp) # imm = 0x800
movl $1073741824, 40(%rsp) # imm = 0x40000000
movl $1065353216, 36(%rsp) # imm = 0x3F800000
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12sgemm_kernelPKfS0_Pfiiiff, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipGetLastError
callq hipDeviceSynchronize
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sgemm_kernelPKfS0_Pfiiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12sgemm_kernelPKfS0_Pfiiiff,@object # @_Z12sgemm_kernelPKfS0_Pfiiiff
.section .rodata,"a",@progbits
.globl _Z12sgemm_kernelPKfS0_Pfiiiff
.p2align 3, 0x0
_Z12sgemm_kernelPKfS0_Pfiiiff:
.quad _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.size _Z12sgemm_kernelPKfS0_Pfiiiff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Application finished successfully."
.size .L.str, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12sgemm_kernelPKfS0_Pfiiiff"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12sgemm_kernelPKfS0_Pfiiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12sgemm_kernelPKfS0_Pfiiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R4, c[0x0][0x4], R5 ; /* 0x0000010004037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xbd0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xad0 ; /* 0x000009b000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R6, -R5, c[0x0][0x180], RZ ; /* 0x0000600005067a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0140*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0150*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD R7, R3, c[0x0][0x180], RZ ; /* 0x0000600003077a24 */
/* 0x000fe200078e02ff */
/*0180*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fcc00078e0209 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R14, R7, 0x4, R14 ; /* 0x00000004070e7825 */
/* 0x000fca00078e020e */
/*0230*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fc600078e0208 */
/*0250*/ LDG.E R18, [R14.64+0x4] ; /* 0x000004040e127981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R22, R0.reuse, 0x4, R8 ; /* 0x0000000400167825 */
/* 0x040fe200078e0208 */
/*0270*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0000e8000c1e1900 */
/*0280*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x000322000c1e1900 */
/*0290*/ IMAD.WIDE R26, R0, 0x4, R22 ; /* 0x00000004001a7825 */
/* 0x000fc600078e0216 */
/*02a0*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008040e1d7981 */
/* 0x000f26000c1e1900 */
/*02b0*/ IMAD.WIDE R12, R0.reuse, 0x4, R26 ; /* 0x00000004000c7825 */
/* 0x040fe200078e021a */
/*02c0*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000b28000c1e1900 */
/*02d0*/ LDG.E R17, [R14.64+0xc] ; /* 0x00000c040e117981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R20, [R14.64+0x10] ; /* 0x000010040e147981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R8, [R14.64+0x14] ; /* 0x000014040e087981 */
/* 0x001f28000c1e1900 */
/*0310*/ LDG.E R26, [R14.64+0x1c] ; /* 0x00001c040e1a7981 */
/* 0x020f62000c1e1900 */
/*0320*/ IMAD.WIDE R12, R0, 0x4, R12 ; /* 0x00000004000c7825 */
/* 0x002fca00078e020c */
/*0330*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000562000c1e1900 */
/*0340*/ IMAD.WIDE R22, R0, 0x4, R12 ; /* 0x0000000400167825 */
/* 0x000fc800078e020c */
/*0350*/ FFMA R12, R11, R10, R24 ; /* 0x0000000a0b0c7223 */
/* 0x004fe40000000018 */
/*0360*/ LDG.E R10, [R14.64+0x18] ; /* 0x000018040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x0000a8000c1e1900 */
/*0390*/ LDG.E R27, [R24.64] ; /* 0x00000004181b7981 */
/* 0x0002a2000c1e1900 */
/*03a0*/ FFMA R12, R19, R18, R12 ; /* 0x00000012130c7223 */
/* 0x008fe4000000000c */
/*03b0*/ IMAD.WIDE R18, R0, 0x4, R24 ; /* 0x0000000400127825 */
/* 0x000fe200078e0218 */
/*03c0*/ LDG.E R23, [R14.64+0x20] ; /* 0x000020040e177981 */
/* 0x001ee6000c1e1900 */
/*03d0*/ FFMA R28, R28, R29, R12 ; /* 0x0000001d1c1c7223 */
/* 0x010fc4000000000c */
/*03e0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0212 */
/*03f0*/ LDG.E R25, [R14.64+0x24] ; /* 0x000024040e197981 */
/* 0x002f26000c1e1900 */
/*0400*/ FFMA R28, R16, R17, R28 ; /* 0x00000011101c7223 */
/* 0x000fe2000000001c */
/*0410*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0420*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0430*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000322000c1e1900 */
/*0440*/ FFMA R28, R21, R20, R28 ; /* 0x00000014151c7223 */
/* 0x000fc6000000001c */
/*0450*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x0002e2000c1e1900 */
/*0460*/ IMAD.WIDE R20, R0, 0x4, R16 ; /* 0x0000000400147825 */
/* 0x000fc600078e0210 */
/*0470*/ LDG.E R29, [R14.64+0x28] ; /* 0x000028040e1d7981 */
/* 0x000f28000c1e1900 */
/*0480*/ LDG.E R19, [R14.64+0x2c] ; /* 0x00002c040e137981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R24, [R14.64+0x30] ; /* 0x000030040e187981 */
/* 0x000f22000c1e1900 */
/*04a0*/ FFMA R28, R9, R8, R28 ; /* 0x00000008091c7223 */
/* 0x020fe4000000001c */
/*04b0*/ IMAD.WIDE R8, R0, 0x4, R20 ; /* 0x0000000400087825 */
/* 0x000fc400078e0214 */
/*04c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000168000c1e1900 */
/*04d0*/ LDG.E R21, [R14.64+0x38] ; /* 0x000038040e157981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R28, R11, R10, R28 ; /* 0x0000000a0b1c7223 */
/* 0x004fe4000000001c */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fe400078e0208 */
/*0500*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0000a4000c1e1900 */
/*0510*/ FFMA R13, R27, R26, R28 ; /* 0x0000001a1b0d7223 */
/* 0x002fc4000000001c */
/*0520*/ IMAD.WIDE R26, R0.reuse, 0x4, R10 ; /* 0x00000004001a7825 */
/* 0x040fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002a8000c1e1900 */
/*0540*/ LDG.E R9, [R14.64+0x34] ; /* 0x000034040e097981 */
/* 0x001ea2000c1e1900 */
/*0550*/ IMAD.WIDE R16, R0, 0x4, R26 ; /* 0x0000000400107825 */
/* 0x000fc600078e021a */
/*0560*/ LDG.E R28, [R26.64] ; /* 0x000000041a1c7981 */
/* 0x0000a8000c1e1900 */
/*0570*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x002ea8000c1e1900 */
/*0580*/ LDG.E R26, [R14.64+0x3c] ; /* 0x00003c040e1a7981 */
/* 0x001ea2000c1e1900 */
/*0590*/ FFMA R13, R18, R23, R13 ; /* 0x00000017120d7223 */
/* 0x008fc8000000000d */
/*05a0*/ FFMA R12, R12, R25, R13 ; /* 0x000000190c0c7223 */
/* 0x010fe2000000000d */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ FFMA R12, R22, R29, R12 ; /* 0x0000001d160c7223 */
/* 0x000fe2000000000c */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*05e0*/ FFMA R19, R20, R19, R12 ; /* 0x0000001314137223 */
/* 0x020fe2000000000c */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R8, R8, R24, R19 ; /* 0x0000001808087223 */
/* 0x004fc80000000013 */
/*0630*/ FFMA R8, R10, R9, R8 ; /* 0x000000090a087223 */
/* 0x000fc80000000008 */
/*0640*/ FFMA R8, R28, R21, R8 ; /* 0x000000151c087223 */
/* 0x000fc80000000008 */
/*0650*/ FFMA R24, R11, R26, R8 ; /* 0x0000001a0b187223 */
/* 0x000fe40000000008 */
/*0660*/ IMAD.WIDE R8, R0, 0x4, R16 ; /* 0x0000000400087825 */
/* 0x000fe200078e0210 */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R8 ; /* 0x0000000400107825 */
/* 0x000fe200078e0208 */
/*06b0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0.reuse, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x040fe400078e0210 */
/*06f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e4000c1e1900 */
/*0700*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fe400078e020a */
/*0710*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000964000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe400078e020c */
/*0730*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R20, R0.reuse, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x040fe200078e0212 */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R8, R0, 0x4, R20 ; /* 0x0000000400087825 */
/* 0x001fc600078e0214 */
/*07b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07c0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0208 */
/*07e0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f28000c1e1900 */
/*0800*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000328000c1e1900 */
/*0810*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x001f28000c1e1900 */
/*0820*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f28000c1e1900 */
/*0830*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08a0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*08b0*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*08c0*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*08d0*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*08e0*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x010fc80000000012 */
/*08f0*/ FFMA R8, R17, R8, R15 ; /* 0x0000000811087223 */
/* 0x000fc8000000000f */
/*0900*/ FFMA R24, R9, R19, R8 ; /* 0x0000001309187223 */
/* 0x000fe40000000008 */
/*0910*/ IMAD.WIDE R8, R0, 0x4, R12 ; /* 0x0000000400087825 */
/* 0x000fc800078e020c */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fe200078e0208 */
/*0960*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*0990*/ IMAD.WIDE R14, R0.reuse, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020a */
/*09a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*09d0*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R20, [R12.64+0x8] ; /* 0x000008040c147981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R22, [R12.64+0xc] ; /* 0x00000c040c167981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0a80*/ FFMA R18, R11, R19, R18 ; /* 0x000000130b127223 */
/* 0x008fe40000000012 */
/*0a90*/ IMAD.WIDE R8, R0, 0x4, R16 ; /* 0x0000000400087825 */
/* 0x000fc800078e0210 */
/*0aa0*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0ab0*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbd0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b00*/ IMAD R6, R3, c[0x0][0x180], R4 ; /* 0x0000600003067a24 */
/* 0x000fe400078e0204 */
/*0b10*/ IMAD R4, R4, c[0x0][0x180], R2 ; /* 0x0000600004047a24 */
/* 0x000fce00078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b30*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b40*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b50*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b60*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b70*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b80*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0b90*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0ba0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bb0*/ FFMA R24, R11, R4, R24 ; /* 0x000000040b187223 */
/* 0x004fcc0000000018 */
/*0bc0*/ @P0 BRA 0xb40 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bd0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe20000000f00 */
/*0be0*/ IMAD R2, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003027a24 */
/* 0x000fc800078e0202 */
/*0bf0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0205 */
/*0c00*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0c10*/ FMUL R5, R0, c[0x0][0x188] ; /* 0x0000620000057a20 */
/* 0x004fc80000400000 */
/*0c20*/ FFMA R5, R24, c[0x0][0x184], R5 ; /* 0x0000610018057a23 */
/* 0x000fca0000000005 */
/*0c30*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12sgemm_kernelPKfS0_Pfiiiff
.globl _Z12sgemm_kernelPKfS0_Pfiiiff
.p2align 8
.type _Z12sgemm_kernelPKfS0_Pfiiiff,@function
_Z12sgemm_kernelPKfS0_Pfiiiff:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s0, v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sgemm_kernelPKfS0_Pfiiiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12sgemm_kernelPKfS0_Pfiiiff, .Lfunc_end0-_Z12sgemm_kernelPKfS0_Pfiiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sgemm_kernelPKfS0_Pfiiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12sgemm_kernelPKfS0_Pfiiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000852c7_00000000-6_simple_sgemm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_initPfi
.type _Z11random_initPfi, @function
_Z11random_initPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_initPfi, .-_Z11random_initPfi
.globl _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
.type _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff, @function
_Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff:
.LFB2083:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12sgemm_kernelPKfS0_Pfiiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff, .-_Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
.globl _Z12sgemm_kernelPKfS0_Pfiiiff
.type _Z12sgemm_kernelPKfS0_Pfiiiff, @function
_Z12sgemm_kernelPKfS0_Pfiiiff:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12sgemm_kernelPKfS0_Pfiiiff, .-_Z12sgemm_kernelPKfS0_Pfiiiff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Application finished successfully."
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $4194304, %esi
movq %r12, %rdi
call _Z11random_initPfi
movl $4194304, %esi
movq %rbp, %rdi
call _Z11random_initPfi
movl $4194304, %esi
movq %rbx, %rdi
call _Z11random_initPfi
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 44(%rsp)
movl $128, 48(%rsp)
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
call cudaGetLastError@PLT
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
movl $2048, %r9d
movl $2048, %r8d
movl $2048, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z12sgemm_kernelPKfS0_Pfiiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sgemm_kernelPKfS0_Pfiiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple_sgemm.hip"
.globl _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff # -- Begin function _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.p2align 4, 0x90
.type _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff,@function
_Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff: # @_Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12sgemm_kernelPKfS0_Pfiiiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff, .Lfunc_end0-_Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11random_initPfi
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z11random_initPfi
.p2align 4, 0x90
.type _Z11random_initPfi,@function
_Z11random_initPfi: # @_Z11random_initPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_initPfi, .Lfunc_end1-_Z11random_initPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.critedge
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $200, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB2_1
# %bb.2: # %.lr.ph.i48.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i48
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB2_3
# %bb.4: # %.lr.ph.i53.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i53
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB2_5
# %bb.6: # %_Z11random_initPfi.exit57
movq 24(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $549755814016, %rdi # imm = 0x8000000080
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $2048, 52(%rsp) # imm = 0x800
movl $2048, 48(%rsp) # imm = 0x800
movl $2048, 44(%rsp) # imm = 0x800
movl $1073741824, 40(%rsp) # imm = 0x40000000
movl $1065353216, 36(%rsp) # imm = 0x3F800000
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12sgemm_kernelPKfS0_Pfiiiff, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipGetLastError
callq hipDeviceSynchronize
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sgemm_kernelPKfS0_Pfiiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12sgemm_kernelPKfS0_Pfiiiff,@object # @_Z12sgemm_kernelPKfS0_Pfiiiff
.section .rodata,"a",@progbits
.globl _Z12sgemm_kernelPKfS0_Pfiiiff
.p2align 3, 0x0
_Z12sgemm_kernelPKfS0_Pfiiiff:
.quad _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.size _Z12sgemm_kernelPKfS0_Pfiiiff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Application finished successfully."
.size .L.str, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12sgemm_kernelPKfS0_Pfiiiff"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12sgemm_kernelPKfS0_Pfiiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cmath>
#include <iostream>
#include <memory>
#include <limits>
#include <cassert>
__global__ void
function(float a, int n_per, double step, float temp, double * sum_array){
double sum_part = 0.0;
double x = a + (temp * (threadIdx.x));
for(int i = 0; i < n_per; i++){
if(x != 0.0){
double val = sin(x)/x;
sum_part += val;
}
x += step;
}
sum_array[threadIdx.x] = sum_part;
__syncthreads();
}
int main(int argc, char **argv){
cudaError_t rv;
rv = cudaDeviceReset();
assert(rv == cudaSuccess);
if(argc != 5) {std::cerr<< "Incorrect number of arguments" << std::endl; return EINVAL;};
float a = std::stod(argv[1]);
float b = std::stod(argv[2]);
int n = atoi(argv[3]);
int n_threads = std::stoull(argv[4]);
if(n_threads < 1) {std::cerr << "Incorrect number of arguments" << std::endl; return EINVAL;};
//Here the number of steps per thread is calculated and the size of each subsection is also calculated and set to temp
float temp = std::abs((b-a)) / n_threads;
double step = (b-a)/n;
int n_per = n / n_threads;
//create sum on global mem
double sum = 0.0;
double *sum_array;
rv = cudaMalloc(&sum_array, n_threads * sizeof(double));
assert(rv == cudaSuccess);
double *sum_temp = (double *)malloc(n_threads * sizeof(double));
for(int i = 0; i < n_threads; i++){
sum_temp[i] = 0.0;
}
cudaMemcpy(sum_array, sum_temp, n_threads * sizeof(double), cudaMemcpyHostToDevice);
//and have it set to 0
//cuda kernel call
function<<<1, n_threads>>>(a, n_per, step, temp, sum_array);
cudaMemcpy(sum_temp, sum_array, n_threads*sizeof(double), cudaMemcpyDeviceToHost);
for(int i = 0; i < n_threads; i++){
sum += sum_temp[i];
}
//Here the different values of the trapezoidal rule are calculated to give the result as "answer"
double val2 = 0.0;
if(a != 0) val2 = (sin(a)/a);
double val3 = 0.0;
if(b != 0) val3 = (sin(b)/b);
val3 = val3 / 2;
val2 = val2 / 2;
typedef std::numeric_limits< double > dbl;
std::cout.precision(dbl::max_digits10);
double answer = step * (val2 + sum + val3);
std::cout << answer << std::endl;
rv = cudaFree(sum_array);
assert(rv == cudaSuccess);
free(sum_temp);
return 0;
} | .file "tmpxft_00179506_00000000-6_monte.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4316:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4316:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8functionfidfPdfidfPd
.type _Z31__device_stub__Z8functionfidfPdfidfPd, @function
_Z31__device_stub__Z8functionfidfPdfidfPd:
.LFB4338:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movl %edi, 24(%rsp)
movsd %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8functionfidfPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4338:
.size _Z31__device_stub__Z8functionfidfPdfidfPd, .-_Z31__device_stub__Z8functionfidfPdfidfPd
.globl _Z8functionfidfPd
.type _Z8functionfidfPd, @function
_Z8functionfidfPd:
.LFB4339:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8functionfidfPdfidfPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4339:
.size _Z8functionfidfPd, .-_Z8functionfidfPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8functionfidfPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4341:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8functionfidfPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4341:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.weak _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.type _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function
_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_:
.LFB4469:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4469
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %rbp
movq %rcx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r13d
movl $0, (%rax)
movq %rsp, %rsi
movq %rbp, %rdi
.LEHB0:
call *%r15
movq (%rsp), %rax
cmpq %rbp, %rax
je .L26
cmpl $34, (%rbx)
je .L27
testq %r12, %r12
je .L18
subq %rbp, %rax
movq %rax, (%r12)
.L18:
cmpl $0, (%rbx)
jne .L13
movl %r13d, (%rbx)
.L13:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L29
movq %r14, %rdi
call _ZSt24__throw_invalid_argumentPKc@PLT
.L24:
endbr64
movq %rax, %rdi
cmpl $0, (%rbx)
jne .L21
movl %r13d, (%rbx)
.L21:
movq 8(%rsp), %rax
subq %fs:40, %rax
je .L22
call __stack_chk_fail@PLT
.L29:
call __stack_chk_fail@PLT
.L27:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L30
movq %r14, %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE0:
.L30:
call __stack_chk_fail@PLT
.L22:
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4469:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.LLSDA4469:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4469-.LLSDACSB4469
.LLSDACSB4469:
.uleb128 .LEHB0-.LFB4469
.uleb128 .LEHE0-.LEHB0
.uleb128 .L24-.LFB4469
.uleb128 0
.uleb128 .LEHB1-.LFB4469
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE4469:
.section .text._ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.size _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4650:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L40
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L41
cmpq $1, %rax
jne .L36
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L37:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L43
leaq .LC1(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L43:
call __stack_chk_fail@PLT
.L41:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L35:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L37
.L36:
testq %rax, %rax
je .L37
jmp .L35
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4650:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC3:
.string "Incorrect number of arguments"
.LC4:
.string "stod"
.LC5:
.string "stoull"
.text
.globl main
.type main, @function
main:
.LFB4313:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4313
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
.LEHB2:
call cudaDeviceReset@PLT
cmpl $5, %ebp
jne .L80
leaq 64(%rsp), %rdx
movq 8(%rbx), %rsi
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE2:
movl $0, %ecx
movq 80(%rsp), %rdx
leaq .LC4(%rip), %rsi
movq strtod@GOTPCREL(%rip), %rdi
.LEHB3:
call _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE3:
jmp .L81
.L80:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB4:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $22, %eax
jmp .L44
.L81:
pxor %xmm7, %xmm7
cvtsd2ss %xmm0, %xmm7
movss %xmm7, 8(%rsp)
leaq 80(%rsp), %rbp
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 64(%rsp), %rdx
movq 16(%rbx), %rsi
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movl $0, %ecx
movq 80(%rsp), %rdx
leaq .LC4(%rip), %rsi
movq strtod@GOTPCREL(%rip), %rdi
.LEHB5:
call _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE5:
pxor %xmm7, %xmm7
cvtsd2ss %xmm0, %xmm7
movss %xmm7, 12(%rsp)
movq %rbp, %r12
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 24(%rsp)
leaq 52(%rsp), %rdx
movq 32(%rbx), %rsi
movq %r12, %rdi
.LEHB6:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
movq 80(%rsp), %r14
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r13d
movl $0, (%rax)
leaq 64(%rsp), %rsi
movl $10, %edx
movq %r14, %rdi
call __isoc23_strtoull@PLT
movq %rax, %r12
cmpq 64(%rsp), %r14
je .L82
movl (%rbx), %eax
cmpl $34, %eax
je .L83
testl %eax, %eax
jne .L51
movl %r13d, (%rbx)
.L51:
movl %r12d, %r15d
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
testl %r12d, %r12d
jle .L84
movss 12(%rsp), %xmm4
subss 8(%rsp), %xmm4
movss %xmm4, 28(%rsp)
pxor %xmm1, %xmm1
cvtsi2ssl %ebp, %xmm1
divss %xmm1, %xmm4
pxor %xmm7, %xmm7
cvtss2sd %xmm4, %xmm7
movsd %xmm7, 16(%rsp)
movslq %r12d, %r14
salq $3, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, %rbx
leal -1(%r12), %eax
leaq 8(%r13,%rax,8), %rbp
movq %r13, %rax
.L57:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rbp, %rax
jne .L57
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L58:
movl $2, %ecx
movq %r14, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0x000000000, %r12d
.L59:
movq %r12, %xmm3
addsd (%rbx), %xmm3
movq %xmm3, %r12
addq $8, %rbx
cmpq %rbp, %rbx
jne .L59
pxor %xmm0, %xmm0
movss 8(%rsp), %xmm5
ucomiss %xmm0, %xmm5
jp .L74
movl $0x000000000, %ebx
jne .L74
.L60:
pxor %xmm0, %xmm0
movss 12(%rsp), %xmm6
ucomiss %xmm0, %xmm6
jp .L75
pxor %xmm1, %xmm1
jne .L75
.L62:
movq $17, 16+_ZSt4cout(%rip)
movsd .LC8(%rip), %xmm2
movq %rbx, %xmm0
mulsd %xmm2, %xmm0
movq %r12, %xmm7
addsd %xmm7, %xmm0
mulsd %xmm2, %xmm1
addsd %xmm1, %xmm0
mulsd 16(%rsp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
.LEHE6:
movq %r13, %rdi
call free@PLT
movl $0, %eax
.L44:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L86
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L87
leaq .LC5(%rip), %rdi
.LEHB7:
call _ZSt24__throw_invalid_argumentPKc@PLT
.L73:
endbr64
movq %rax, %rbp
cmpl $0, (%rbx)
jne .L55
movl %r13d, (%rbx)
.L55:
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L56
call __stack_chk_fail@PLT
.L87:
call __stack_chk_fail@PLT
.L83:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L88
leaq .LC5(%rip), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE7:
.L88:
call __stack_chk_fail@PLT
.L56:
movq %rbp, %rdi
.LEHB8:
call _Unwind_Resume@PLT
.L84:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $22, %eax
jmp .L44
.L85:
movss 28(%rsp), %xmm2
andps .LC6(%rip), %xmm2
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
movl 24(%rsp), %eax
cltd
idivl %r15d
movl %eax, %edi
movq 40(%rsp), %rsi
divss %xmm0, %xmm2
movsd 16(%rsp), %xmm1
movss 8(%rsp), %xmm0
call _Z31__device_stub__Z8functionfidfPdfidfPd
jmp .L58
.L74:
movss 8(%rsp), %xmm0
call sinf@PLT
divss 8(%rsp), %xmm0
pxor %xmm5, %xmm5
cvtss2sd %xmm0, %xmm5
movq %xmm5, %rbx
jmp .L60
.L75:
movss 12(%rsp), %xmm0
call sinf@PLT
movaps %xmm0, %xmm1
divss 12(%rsp), %xmm1
cvtss2sd %xmm1, %xmm1
jmp .L62
.L71:
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L65
call __stack_chk_fail@PLT
.L65:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L72:
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L67
call __stack_chk_fail@PLT
.L67:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE8:
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4313:
.section .gcc_except_table,"a",@progbits
.LLSDA4313:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4313-.LLSDACSB4313
.LLSDACSB4313:
.uleb128 .LEHB2-.LFB4313
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4313
.uleb128 .LEHE3-.LEHB3
.uleb128 .L71-.LFB4313
.uleb128 0
.uleb128 .LEHB4-.LFB4313
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4313
.uleb128 .LEHE5-.LEHB5
.uleb128 .L72-.LFB4313
.uleb128 0
.uleb128 .LEHB6-.LFB4313
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB4313
.uleb128 .LEHE7-.LEHB7
.uleb128 .L73-.LFB4313
.uleb128 0
.uleb128 .LEHB8-.LFB4313
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.LLSDACSE4313:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1071644672
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cmath>
#include <iostream>
#include <memory>
#include <limits>
#include <cassert>
__global__ void
function(float a, int n_per, double step, float temp, double * sum_array){
double sum_part = 0.0;
double x = a + (temp * (threadIdx.x));
for(int i = 0; i < n_per; i++){
if(x != 0.0){
double val = sin(x)/x;
sum_part += val;
}
x += step;
}
sum_array[threadIdx.x] = sum_part;
__syncthreads();
}
int main(int argc, char **argv){
cudaError_t rv;
rv = cudaDeviceReset();
assert(rv == cudaSuccess);
if(argc != 5) {std::cerr<< "Incorrect number of arguments" << std::endl; return EINVAL;};
float a = std::stod(argv[1]);
float b = std::stod(argv[2]);
int n = atoi(argv[3]);
int n_threads = std::stoull(argv[4]);
if(n_threads < 1) {std::cerr << "Incorrect number of arguments" << std::endl; return EINVAL;};
//Here the number of steps per thread is calculated and the size of each subsection is also calculated and set to temp
float temp = std::abs((b-a)) / n_threads;
double step = (b-a)/n;
int n_per = n / n_threads;
//create sum on global mem
double sum = 0.0;
double *sum_array;
rv = cudaMalloc(&sum_array, n_threads * sizeof(double));
assert(rv == cudaSuccess);
double *sum_temp = (double *)malloc(n_threads * sizeof(double));
for(int i = 0; i < n_threads; i++){
sum_temp[i] = 0.0;
}
cudaMemcpy(sum_array, sum_temp, n_threads * sizeof(double), cudaMemcpyHostToDevice);
//and have it set to 0
//cuda kernel call
function<<<1, n_threads>>>(a, n_per, step, temp, sum_array);
cudaMemcpy(sum_temp, sum_array, n_threads*sizeof(double), cudaMemcpyDeviceToHost);
for(int i = 0; i < n_threads; i++){
sum += sum_temp[i];
}
//Here the different values of the trapezoidal rule are calculated to give the result as "answer"
double val2 = 0.0;
if(a != 0) val2 = (sin(a)/a);
double val3 = 0.0;
if(b != 0) val3 = (sin(b)/b);
val3 = val3 / 2;
val2 = val2 / 2;
typedef std::numeric_limits< double > dbl;
std::cout.precision(dbl::max_digits10);
double answer = step * (val2 + sum + val3);
std::cout << answer << std::endl;
rv = cudaFree(sum_array);
assert(rv == cudaSuccess);
free(sum_temp);
return 0;
} | #include <hip/hip_runtime.h>
#include <cmath>
#include <iostream>
#include <memory>
#include <limits>
#include <cassert>
__global__ void
function(float a, int n_per, double step, float temp, double * sum_array){
double sum_part = 0.0;
double x = a + (temp * (threadIdx.x));
for(int i = 0; i < n_per; i++){
if(x != 0.0){
double val = sin(x)/x;
sum_part += val;
}
x += step;
}
sum_array[threadIdx.x] = sum_part;
__syncthreads();
}
int main(int argc, char **argv){
hipError_t rv;
rv = hipDeviceReset();
assert(rv == hipSuccess);
if(argc != 5) {std::cerr<< "Incorrect number of arguments" << std::endl; return EINVAL;};
float a = std::stod(argv[1]);
float b = std::stod(argv[2]);
int n = atoi(argv[3]);
int n_threads = std::stoull(argv[4]);
if(n_threads < 1) {std::cerr << "Incorrect number of arguments" << std::endl; return EINVAL;};
//Here the number of steps per thread is calculated and the size of each subsection is also calculated and set to temp
float temp = std::abs((b-a)) / n_threads;
double step = (b-a)/n;
int n_per = n / n_threads;
//create sum on global mem
double sum = 0.0;
double *sum_array;
rv = hipMalloc(&sum_array, n_threads * sizeof(double));
assert(rv == hipSuccess);
double *sum_temp = (double *)malloc(n_threads * sizeof(double));
for(int i = 0; i < n_threads; i++){
sum_temp[i] = 0.0;
}
hipMemcpy(sum_array, sum_temp, n_threads * sizeof(double), hipMemcpyHostToDevice);
//and have it set to 0
//cuda kernel call
function<<<1, n_threads>>>(a, n_per, step, temp, sum_array);
hipMemcpy(sum_temp, sum_array, n_threads*sizeof(double), hipMemcpyDeviceToHost);
for(int i = 0; i < n_threads; i++){
sum += sum_temp[i];
}
//Here the different values of the trapezoidal rule are calculated to give the result as "answer"
double val2 = 0.0;
if(a != 0) val2 = (sin(a)/a);
double val3 = 0.0;
if(b != 0) val3 = (sin(b)/b);
val3 = val3 / 2;
val2 = val2 / 2;
typedef std::numeric_limits< double > dbl;
std::cout.precision(dbl::max_digits10);
double answer = step * (val2 + sum + val3);
std::cout << answer << std::endl;
rv = hipFree(sum_array);
assert(rv == hipSuccess);
free(sum_temp);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <iostream>
#include <memory>
#include <limits>
#include <cassert>
__global__ void
function(float a, int n_per, double step, float temp, double * sum_array){
double sum_part = 0.0;
double x = a + (temp * (threadIdx.x));
for(int i = 0; i < n_per; i++){
if(x != 0.0){
double val = sin(x)/x;
sum_part += val;
}
x += step;
}
sum_array[threadIdx.x] = sum_part;
__syncthreads();
}
int main(int argc, char **argv){
hipError_t rv;
rv = hipDeviceReset();
assert(rv == hipSuccess);
if(argc != 5) {std::cerr<< "Incorrect number of arguments" << std::endl; return EINVAL;};
float a = std::stod(argv[1]);
float b = std::stod(argv[2]);
int n = atoi(argv[3]);
int n_threads = std::stoull(argv[4]);
if(n_threads < 1) {std::cerr << "Incorrect number of arguments" << std::endl; return EINVAL;};
//Here the number of steps per thread is calculated and the size of each subsection is also calculated and set to temp
float temp = std::abs((b-a)) / n_threads;
double step = (b-a)/n;
int n_per = n / n_threads;
//create sum on global mem
double sum = 0.0;
double *sum_array;
rv = hipMalloc(&sum_array, n_threads * sizeof(double));
assert(rv == hipSuccess);
double *sum_temp = (double *)malloc(n_threads * sizeof(double));
for(int i = 0; i < n_threads; i++){
sum_temp[i] = 0.0;
}
hipMemcpy(sum_array, sum_temp, n_threads * sizeof(double), hipMemcpyHostToDevice);
//and have it set to 0
//cuda kernel call
function<<<1, n_threads>>>(a, n_per, step, temp, sum_array);
hipMemcpy(sum_temp, sum_array, n_threads*sizeof(double), hipMemcpyDeviceToHost);
for(int i = 0; i < n_threads; i++){
sum += sum_temp[i];
}
//Here the different values of the trapezoidal rule are calculated to give the result as "answer"
double val2 = 0.0;
if(a != 0) val2 = (sin(a)/a);
double val3 = 0.0;
if(b != 0) val3 = (sin(b)/b);
val3 = val3 / 2;
val2 = val2 / 2;
typedef std::numeric_limits< double > dbl;
std::cout.precision(dbl::max_digits10);
double answer = step * (val2 + sum + val3);
std::cout << answer << std::endl;
rv = hipFree(sum_array);
assert(rv == hipSuccess);
free(sum_temp);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8functionfidfPd
.globl _Z8functionfidfPd
.p2align 8
.type _Z8functionfidfPd,@function
_Z8functionfidfPd:
s_load_b32 s33, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s33, 1
s_cbranch_scc1 .LBB0_9
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x0
v_cvt_f32_u32_e32 v1, v0
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s6, 0x54442d18
s_mov_b32 s9, 0x3c91a626
s_mov_b32 s10, 0x33145c07
s_mov_b32 s13, 0x3fe45f30
s_mov_b32 s12, 0x6dc9c883
s_mov_b32 s7, 0xbff921fb
s_mov_b32 s15, 0xbc91a626
s_mov_b32 s14, 0x33145c00
s_mov_b32 s17, 0xb97b839a
s_mov_b32 s16, 0x252049c0
s_mov_b32 s19, 0x3e21eeb6
s_mov_b32 s18, 0x9037ab78
s_mov_b32 s21, 0xbda907db
s_mov_b32 s20, 0x46cc5e42
s_mov_b32 s23, 0xbe927e4f
s_mov_b32 s22, 0xa17f65f6
s_mov_b32 s25, 0x3efa01a0
s_waitcnt lgkmcnt(0)
v_fma_f32 v1, v1, s2, s3
s_mov_b32 s3, 0x3ff921fb
s_mov_b32 s24, 0x19f4ec90
s_mov_b32 s27, 0xbf56c16c
s_mov_b32 s26, 0x16c16967
v_cvt_f64_f32_e32 v[3:4], v1
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_mov_b32 s29, 0x3fa55555
s_mov_b32 s28, 0x55555555
s_mov_b32 s31, 0xbe5ae600
s_mov_b32 s30, 0xb42fdfa7
s_mov_b32 s35, 0x3de5e0b2
s_mov_b32 s34, 0xf9a43bb8
s_mov_b32 s37, 0x3ec71de3
s_mov_b32 s36, 0x796cde01
s_mov_b32 s39, 0xbf2a01a0
s_mov_b32 s38, 0x19e83e5c
s_mov_b32 s41, 0x3f811111
s_mov_b32 s40, 0x11110bb3
s_mov_b32 s43, 0xbfc55555
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_mul_f64 v[10:11], v[5:6], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f64 v[20:21], v[7:8], 0.5
s_mov_b32 s42, s28
v_cmp_class_f64_e64 s2, v[3:4], 0x1f8
v_fma_f64 v[12:13], v[10:11], s[34:35], s[30:31]
v_fma_f64 v[14:15], v[10:11], s[20:21], s[18:19]
v_mul_f64 v[16:17], v[10:11], 0.5
v_mul_f64 v[22:23], v[5:6], -v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[36:37]
v_fma_f64 v[14:15], v[10:11], v[14:15], s[22:23]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], -v[16:17], 1.0
v_fma_f64 v[12:13], v[10:11], v[12:13], s[38:39]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[24:25]
v_add_f64 v[24:25], -v[18:19], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[40:41]
v_fma_f64 v[14:15], v[10:11], v[14:15], s[26:27]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[24:25], -v[16:17]
v_fma_f64 v[12:13], v[22:23], v[12:13], v[20:21]
v_mul_f64 v[20:21], v[10:11], v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[28:29]
v_fma_f64 v[16:17], v[5:6], -v[7:8], v[16:17]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[7:8], v[10:11], v[12:13], -v[7:8]
v_fma_f64 v[10:11], v[20:21], v[14:15], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[7:8], v[22:23], s[42:43], v[7:8]
v_add_f64 v[10:11], v[18:19], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], -v[7:8]
v_and_b32_e32 v7, 1, v9
v_cmp_eq_u32_e32 vcc_lo, 0, v7
v_lshlrev_b32_e32 v7, 30, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v7, v7, v4
v_dual_cndmask_b32 v6, v11, v6 :: v_dual_and_b32 v7, 0x80000000, v7
v_cndmask_b32_e32 v5, v10, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, v6, v7
v_cndmask_b32_e64 v5, 0, v5, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, 0x7ff80000, v6, s2
v_div_scale_f64 v[7:8], null, v[3:4], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_div_scale_f64 v[11:12], vcc_lo, v[5:6], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[11:12], v[9:10]
v_fma_f64 v[7:8], -v[7:8], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[13:14]
v_div_fixup_f64 v[5:6], v[7:8], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s44
v_add_f64 v[3:4], v[3:4], s[4:5]
s_add_i32 s33, s33, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s33, 0
s_cbranch_scc1 .LBB0_10
.LBB0_4:
s_mov_b32 s44, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_neq_f64_e32 0, v[3:4]
s_cbranch_execz .LBB0_3
s_mov_b32 s8, exec_lo
v_cmpx_ngt_f64_e64 0x41d00000, |v[3:4]|
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_7
v_ldexp_f64 v[5:6], |v[3:4]|, 0xffffff80
v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[3:4]|
v_trig_preop_f64 v[7:8], |v[3:4]|, 0
v_and_b32_e32 v9, 0x7fffffff, v4
v_trig_preop_f64 v[19:20], |v[3:4]|, 2
v_mov_b32_e32 v27, 0
s_mov_b32 s11, s9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v6, v9, v6 :: v_dual_cndmask_b32 v5, v3, v5
v_trig_preop_f64 v[9:10], |v[3:4]|, 1
v_mul_f64 v[11:12], v[7:8], v[5:6]
v_mul_f64 v[25:26], v[19:20], v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[13:14], v[9:10], v[5:6]
v_fma_f64 v[7:8], v[7:8], v[5:6], -v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[9:10], v[9:10], v[5:6], -v[13:14]
v_fma_f64 v[5:6], v[19:20], v[5:6], -v[25:26]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[15:16], v[13:14], v[7:8]
v_add_f64 v[17:18], v[15:16], -v[13:14]
v_add_f64 v[23:24], v[11:12], v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[21:22], v[15:16], -v[17:18]
v_add_f64 v[7:8], v[7:8], -v[17:18]
v_ldexp_f64 v[17:18], v[23:24], -2
v_add_f64 v[11:12], v[23:24], -v[11:12]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[13:14], v[13:14], -v[21:22]
v_add_f64 v[21:22], v[25:26], v[9:10]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[17:18]|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[11:12], v[15:16], -v[11:12]
v_add_f64 v[7:8], v[7:8], v[13:14]
v_fract_f64_e32 v[13:14], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[15:16], v[21:22], v[7:8]
v_dual_cndmask_b32 v14, 0, v14 :: v_dual_cndmask_b32 v13, 0, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f64 v[13:14], v[13:14], 2
v_add_f64 v[17:18], v[11:12], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[23:24], v[17:18], v[13:14]
v_add_f64 v[11:12], v[17:18], -v[11:12]
v_cmp_gt_f64_e32 vcc_lo, 0, v[23:24]
v_add_f64 v[23:24], v[21:22], -v[25:26]
v_cndmask_b32_e64 v28, 0, 0x40100000, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[32:33], v[21:22], -v[23:24]
v_add_f64 v[9:10], v[9:10], -v[23:24]
v_add_f64 v[13:14], v[13:14], v[27:28]
v_add_f64 v[28:29], v[15:16], -v[21:22]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[23:24], v[25:26], -v[32:33]
v_add_f64 v[30:31], v[17:18], v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[34:35], v[15:16], -v[28:29]
v_add_f64 v[7:8], v[7:8], -v[28:29]
v_add_f64 v[9:10], v[9:10], v[23:24]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f64_e32 v30, v[30:31]
v_add_f64 v[21:22], v[21:22], -v[34:35]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[28:29], v30
v_add_f64 v[7:8], v[7:8], v[21:22]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[13:14], v[13:14], -v[28:29]
v_add_f64 v[7:8], v[9:10], v[7:8]
v_add_f64 v[9:10], v[15:16], -v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[19:20], v[17:18], v[13:14]
v_add_f64 v[5:6], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[19:20], -v[13:14]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[19:20]
v_add_f64 v[5:6], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[17:18], -v[7:8]
v_cndmask_b32_e64 v28, 0, 0x3ff00000, vcc_lo
v_add_co_ci_u32_e64 v9, s2, 0, v30, vcc_lo
s_mov_b32 s2, s6
v_add_f64 v[5:6], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[19:20], -v[27:28]
v_add_f64 v[10:11], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[12:13], v[10:11], s[2:3]
v_add_f64 v[7:8], v[10:11], -v[7:8]
v_fma_f64 v[14:15], v[10:11], s[2:3], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], -v[7:8]
v_fma_f64 v[7:8], v[10:11], s[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[5:6], s[2:3], v[7:8]
v_add_f64 v[5:6], v[12:13], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[5:6], -v[12:13]
v_add_f64 v[7:8], v[7:8], -v[10:11]
.LBB0_7:
s_and_not1_saveexec_b32 s2, s8
s_cbranch_execz .LBB0_2
v_mul_f64 v[5:6], |v[3:4]|, s[12:13]
s_mov_b32 s8, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[9:10], v[5:6]
v_fma_f64 v[5:6], v[9:10], s[6:7], |v[3:4]|
v_mul_f64 v[7:8], v[9:10], s[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[13:14], v[9:10], s[14:15], v[5:6]
v_add_f64 v[11:12], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[5:6], v[5:6], -v[11:12]
v_add_f64 v[11:12], v[11:12], -v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[7:8]
v_fma_f64 v[7:8], v[9:10], s[8:9], v[7:8]
v_add_f64 v[5:6], v[11:12], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], -v[7:8]
v_fma_f64 v[7:8], v[9:10], s[16:17], v[5:6]
v_cvt_i32_f64_e32 v9, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[13:14], v[7:8]
v_add_f64 v[11:12], v[5:6], -v[13:14]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], -v[11:12]
s_branch .LBB0_2
.LBB0_9:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_10:
s_load_b64 s[0:1], s[0:1], 0x18
v_lshlrev_b32_e32 v0, 3, v0
s_waitcnt lgkmcnt(0)
global_store_b64 v0, v[1:2], s[0:1]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8functionfidfPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 36
.amdhsa_next_free_sgpr 45
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8functionfidfPd, .Lfunc_end0-_Z8functionfidfPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8functionfidfPd
.private_segment_fixed_size: 0
.sgpr_count: 47
.sgpr_spill_count: 0
.symbol: _Z8functionfidfPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 36
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <iostream>
#include <memory>
#include <limits>
#include <cassert>
__global__ void
function(float a, int n_per, double step, float temp, double * sum_array){
double sum_part = 0.0;
double x = a + (temp * (threadIdx.x));
for(int i = 0; i < n_per; i++){
if(x != 0.0){
double val = sin(x)/x;
sum_part += val;
}
x += step;
}
sum_array[threadIdx.x] = sum_part;
__syncthreads();
}
int main(int argc, char **argv){
hipError_t rv;
rv = hipDeviceReset();
assert(rv == hipSuccess);
if(argc != 5) {std::cerr<< "Incorrect number of arguments" << std::endl; return EINVAL;};
float a = std::stod(argv[1]);
float b = std::stod(argv[2]);
int n = atoi(argv[3]);
int n_threads = std::stoull(argv[4]);
if(n_threads < 1) {std::cerr << "Incorrect number of arguments" << std::endl; return EINVAL;};
//Here the number of steps per thread is calculated and the size of each subsection is also calculated and set to temp
float temp = std::abs((b-a)) / n_threads;
double step = (b-a)/n;
int n_per = n / n_threads;
//create sum on global mem
double sum = 0.0;
double *sum_array;
rv = hipMalloc(&sum_array, n_threads * sizeof(double));
assert(rv == hipSuccess);
double *sum_temp = (double *)malloc(n_threads * sizeof(double));
for(int i = 0; i < n_threads; i++){
sum_temp[i] = 0.0;
}
hipMemcpy(sum_array, sum_temp, n_threads * sizeof(double), hipMemcpyHostToDevice);
//and have it set to 0
//cuda kernel call
function<<<1, n_threads>>>(a, n_per, step, temp, sum_array);
hipMemcpy(sum_temp, sum_array, n_threads*sizeof(double), hipMemcpyDeviceToHost);
for(int i = 0; i < n_threads; i++){
sum += sum_temp[i];
}
//Here the different values of the trapezoidal rule are calculated to give the result as "answer"
double val2 = 0.0;
if(a != 0) val2 = (sin(a)/a);
double val3 = 0.0;
if(b != 0) val3 = (sin(b)/b);
val3 = val3 / 2;
val2 = val2 / 2;
typedef std::numeric_limits< double > dbl;
std::cout.precision(dbl::max_digits10);
double answer = step * (val2 + sum + val3);
std::cout << answer << std::endl;
rv = hipFree(sum_array);
assert(rv == hipSuccess);
free(sum_temp);
return 0;
} | .text
.file "monte.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__functionfidfPd # -- Begin function _Z23__device_stub__functionfidfPd
.p2align 4, 0x90
.type _Z23__device_stub__functionfidfPd,@function
_Z23__device_stub__functionfidfPd: # @_Z23__device_stub__functionfidfPd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 12(%rsp)
movl %edi, 8(%rsp)
movsd %xmm1, 72(%rsp)
movss %xmm2, 4(%rsp)
movq %rsi, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8functionfidfPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__functionfidfPd, .Lfunc_end0-_Z23__device_stub__functionfidfPd
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebx
.cfi_escape 0x2e, 0x00
callq hipDeviceReset
cmpl $5, %ebx
jne .LBB1_10
# %bb.1:
movq 8(%r14), %rbx
leaq 32(%rsp), %r13
movq %r13, 16(%rsp)
testq %rbx, %rbx
je .LBB1_86
# %bb.2:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq strlen
movq %rax, %r15
cmpq $16, %rax
jb .LBB1_7
# %bb.3:
testq %r15, %r15
js .LBB1_100
# %bb.4:
movq %r15, %rdi
incq %rdi
js .LBB1_80
# %bb.5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
.Ltmp0:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp1:
# %bb.6: # %.noexc79
movq %rax, 16(%rsp)
movq %r15, 32(%rsp)
.LBB1_7:
testq %r15, %r15
je .LBB1_17
# %bb.8:
movq 16(%rsp), %rdi
cmpq $1, %r15
jne .LBB1_16
# %bb.9:
movzbl (%rbx), %eax
movb %al, (%rdi)
jmp .LBB1_17
.LBB1_10:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_88
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_13
# %bb.12:
movzbl 67(%rbx), %eax
jmp .LBB1_14
.LBB1_13:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
.LBB1_15:
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movl $22, %eax
jmp .LBB1_78
.LBB1_16:
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB1_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
movq %r15, 24(%rsp)
movq 16(%rsp), %rax
movb $0, (%rax,%r15)
movq 16(%rsp), %r15
.cfi_escape 0x2e, 0x00
callq __errno_location
movq %rax, %rbx
movl (%rax), %ebp
movl $0, (%rax)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rsi
movq %r15, %rdi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
cmpq %r15, 56(%rsp)
je .LBB1_89
# %bb.18:
movl (%rbx), %eax
testl %eax, %eax
je .LBB1_22
# %bb.19:
cmpl $34, %eax
jne .LBB1_23
# %bb.20: # %.critedge.i.i
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp3:
# %bb.21:
.LBB1_22:
movl %ebp, (%rbx)
.LBB1_23: # %_ZNSt7__cxx114stodERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPm.exit
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_25
# %bb.24: # %.critedge.i.i80
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq 16(%r14), %r15
movq %r13, 16(%rsp)
testq %r15, %r15
je .LBB1_91
# %bb.26:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq strlen
movq %rax, %r12
cmpq $16, %rax
jb .LBB1_31
# %bb.27:
testq %r12, %r12
js .LBB1_102
# %bb.28:
movq %r12, %rdi
incq %rdi
js .LBB1_82
# %bb.29: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i81
.Ltmp4:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp5:
# %bb.30: # %.noexc87
movq %rax, 16(%rsp)
movq %r12, 32(%rsp)
.LBB1_31:
testq %r12, %r12
je .LBB1_35
# %bb.32:
movq 16(%rsp), %rdi
cmpq $1, %r12
jne .LBB1_34
# %bb.33:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB1_35
.LBB1_34:
.cfi_escape 0x2e, 0x00
movq %r15, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB1_35: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit88
movq %r12, 24(%rsp)
movq 16(%rsp), %rax
movb $0, (%rax,%r12)
movq 16(%rsp), %r15
movl (%rbx), %ebp
movl $0, (%rbx)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rsi
movq %r15, %rdi
callq strtod
cmpq %r15, 56(%rsp)
je .LBB1_93
# %bb.36:
movl (%rbx), %eax
testl %eax, %eax
movsd %xmm0, 8(%rsp) # 8-byte Spill
je .LBB1_40
# %bb.37:
cmpl $34, %eax
jne .LBB1_41
# %bb.38: # %.critedge.i.i89
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp7:
# %bb.39:
.LBB1_40:
movl %ebp, (%rbx)
.LBB1_41: # %_ZNSt7__cxx114stodERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPm.exit93
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_43
# %bb.42: # %.critedge.i.i94
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_43: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit96
movq 24(%r14), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq 32(%r14), %r14
movq %r13, 16(%rsp)
testq %r14, %r14
je .LBB1_95
# %bb.44:
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq strlen
movq %rax, %r12
cmpq $16, %rax
jb .LBB1_49
# %bb.45:
testq %r12, %r12
js .LBB1_104
# %bb.46:
movq %r12, %rdi
incq %rdi
js .LBB1_84
# %bb.47: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i97
.Ltmp8:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp9:
# %bb.48: # %.noexc103
movq %rax, 16(%rsp)
movq %r12, 32(%rsp)
.LBB1_49:
testq %r12, %r12
je .LBB1_53
# %bb.50:
movq 16(%rsp), %rdi
cmpq $1, %r12
jne .LBB1_52
# %bb.51:
movzbl (%r14), %eax
movb %al, (%rdi)
jmp .LBB1_53
.LBB1_52:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB1_53: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit104
movq %r12, 24(%rsp)
movq 16(%rsp), %rax
movb $0, (%rax,%r12)
movq 16(%rsp), %r12
movl (%rbx), %ebp
movl $0, (%rbx)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rsi
movq %r12, %rdi
movl $10, %edx
callq __isoc23_strtoull
cmpq %r12, 56(%rsp)
je .LBB1_97
# %bb.54:
movq %rax, %r14
movl (%rbx), %eax
testl %eax, %eax
je .LBB1_58
# %bb.55:
cmpl $34, %eax
jne .LBB1_59
# %bb.56: # %.critedge.i.i105
.Ltmp10:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp11:
# %bb.57:
.LBB1_58:
movl %ebp, (%rbx)
.LBB1_59: # %_ZNSt7__cxx116stoullERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_61
# %bb.60: # %.critedge.i.i108
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_61: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit110
testl %r14d, %r14d
jle .LBB1_73
# %bb.62:
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 88(%rsp) # 4-byte Spill
movaps %xmm0, %xmm2
movss %xmm1, 8(%rsp) # 4-byte Spill
subss %xmm1, %xmm2
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
movaps %xmm2, 112(%rsp) # 16-byte Spill
movaps %xmm2, %xmm1
divss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movsd %xmm0, 72(%rsp) # 8-byte Spill
movl %r14d, %r13d
leaq (,%r13,8), %r12
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq malloc
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
movq 80(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $1, %ebp
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %r13
orq $1, %rdi
.cfi_escape 0x2e, 0x00
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_64
# %bb.63:
movl %r15d, %eax
cltd
idivl %r14d
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
movaps 112(%rsp), %xmm1 # 16-byte Reload
andps .LCPI1_0(%rip), %xmm1
divss %xmm0, %xmm1
movq 80(%rsp), %rcx
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 108(%rsp)
movl %eax, 104(%rsp)
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 176(%rsp)
movss %xmm1, 100(%rsp)
movq %rcx, 168(%rsp)
leaq 108(%rsp), %rax
movq %rax, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 24(%rsp)
leaq 176(%rsp), %rax
movq %rax, 32(%rsp)
leaq 100(%rsp), %rax
movq %rax, 40(%rsp)
leaq 168(%rsp), %rax
movq %rax, 48(%rsp)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z8functionfidfPd, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_64: # %.lr.ph.preheader
movq 80(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $2, %r14d
cmovgel %r14d, %ebp
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_65: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addsd (%rbx,%rax,8), %xmm0
incq %rax
cmpq %rax, %rbp
jne .LBB1_65
# %bb.66: # %._crit_edge
movsd %xmm0, 112(%rsp) # 8-byte Spill
xorps %xmm1, %xmm1
xorps %xmm3, %xmm3
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss %xmm3, %xmm0
xorps %xmm2, %xmm2
jne .LBB1_67
jnp .LBB1_68
.LBB1_67:
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
callq sin
xorps %xmm3, %xmm3
xorps %xmm1, %xmm1
movaps %xmm0, %xmm2
divsd 8(%rsp), %xmm2 # 8-byte Folded Reload
mulsd .LCPI1_1(%rip), %xmm2
.LBB1_68:
movss 88(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss %xmm3, %xmm0
jne .LBB1_69
jnp .LBB1_70
.LBB1_69:
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 88(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movsd %xmm2, 8(%rsp) # 8-byte Spill
callq sin
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movaps %xmm0, %xmm1
divsd 88(%rsp), %xmm1 # 8-byte Folded Reload
mulsd .LCPI1_1(%rip), %xmm1
.LBB1_70:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $17, _ZSt4cout+8(%rax)
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm2, %xmm0
addsd %xmm1, %xmm0
mulsd 72(%rsp), %xmm0 # 8-byte Folded Reload
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_99
# %bb.71: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i126
cmpb $0, 56(%r14)
je .LBB1_76
# %bb.72:
movzbl 67(%r14), %ecx
jmp .LBB1_77
.LBB1_73:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_106
# %bb.74: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i121
cmpb $0, 56(%rbx)
je .LBB1_79
# %bb.75:
movzbl 67(%rbx), %eax
.cfi_escape 0x2e, 0x00
jmp .LBB1_15
.LBB1_76:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_77: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit129
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq 80(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq free
xorl %eax, %eax
.LBB1_78:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_79:
.cfi_def_cfa_offset 240
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.cfi_escape 0x2e, 0x00
jmp .LBB1_15
.LBB1_80: # %.noexc11.i
.Ltmp35:
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.Ltmp36:
# %bb.81: # %.noexc78
.LBB1_82: # %.noexc11.i82
.Ltmp25:
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.Ltmp26:
# %bb.83: # %.noexc86
.LBB1_84: # %.noexc11.i98
.Ltmp15:
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.Ltmp16:
# %bb.85: # %.noexc102
.LBB1_86:
.Ltmp39:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt19__throw_logic_errorPKc
.Ltmp40:
# %bb.87: # %.noexc
.LBB1_88:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_89:
.Ltmp32:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp33:
# %bb.90:
.LBB1_91:
.Ltmp29:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt19__throw_logic_errorPKc
.Ltmp30:
# %bb.92: # %.noexc84
.LBB1_93:
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp23:
# %bb.94:
.LBB1_95:
.Ltmp19:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt19__throw_logic_errorPKc
.Ltmp20:
# %bb.96: # %.noexc100
.LBB1_97:
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp13:
# %bb.98:
.LBB1_99:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_100: # %.noexc.i
.Ltmp37:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp38:
# %bb.101: # %.noexc77
.LBB1_102: # %.noexc.i83
.Ltmp27:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp28:
# %bb.103: # %.noexc85
.LBB1_104: # %.noexc.i99
.Ltmp17:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp18:
# %bb.105: # %.noexc101
.LBB1_106:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_107:
.Ltmp14:
movq %rax, %r14
cmpl $0, (%rbx)
jne .LBB1_109
# %bb.108:
movl %ebp, (%rbx)
.LBB1_109: # %_ZZN9__gnu_cxx6__stoaIyycJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_120
# %bb.110: # %.critedge.i.i117
.cfi_escape 0x2e, 0x00
jmp .LBB1_119
.LBB1_111:
.Ltmp24:
movq %rax, %r14
cmpl $0, (%rbx)
jne .LBB1_113
# %bb.112:
movl %ebp, (%rbx)
.LBB1_113: # %_ZZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i90
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_120
# %bb.114: # %.critedge.i.i114
.cfi_escape 0x2e, 0x00
jmp .LBB1_119
.LBB1_115:
.Ltmp34:
movq %rax, %r14
cmpl $0, (%rbx)
jne .LBB1_117
# %bb.116:
movl %ebp, (%rbx)
.LBB1_117: # %_ZZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_120
# %bb.118: # %.critedge.i.i111
.cfi_escape 0x2e, 0x00
.LBB1_119: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit113
callq _ZdlPv
.LBB1_120: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit113
movq %r14, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.LBB1_121:
.Ltmp21:
movq %rax, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.LBB1_122:
.Ltmp31:
movq %rax, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.LBB1_123:
.Ltmp41:
movq %rax, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp2-.Ltmp1 # Call between .Ltmp1 and .Ltmp2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp3-.Ltmp2 # Call between .Ltmp2 and .Ltmp3
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp5-.Ltmp4 # Call between .Ltmp4 and .Ltmp5
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp35-.Ltmp11 # Call between .Ltmp11 and .Ltmp35
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp36-.Ltmp35 # Call between .Ltmp35 and .Ltmp36
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp26-.Ltmp25 # Call between .Ltmp25 and .Ltmp26
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp32-.Ltmp40 # Call between .Ltmp40 and .Ltmp32
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp33-.Ltmp32 # Call between .Ltmp32 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp30-.Ltmp29 # Call between .Ltmp29 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 20 <<
.uleb128 .Ltmp20-.Ltmp19 # Call between .Ltmp19 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 21 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 22 <<
.uleb128 .Ltmp37-.Ltmp13 # Call between .Ltmp13 and .Ltmp37
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 23 <<
.uleb128 .Ltmp38-.Ltmp37 # Call between .Ltmp37 and .Ltmp38
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 24 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 25 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 26 <<
.uleb128 .Lfunc_end1-.Ltmp18 # Call between .Ltmp18 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8functionfidfPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8functionfidfPd,@object # @_Z8functionfidfPd
.section .rodata,"a",@progbits
.globl _Z8functionfidfPd
.p2align 3, 0x0
_Z8functionfidfPd:
.quad _Z23__device_stub__functionfidfPd
.size _Z8functionfidfPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Incorrect number of arguments"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "stod"
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "basic_string: construction from null is not valid"
.size .L.str.2, 50
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "basic_string::_M_create"
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "stoull"
.size .L.str.4, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8functionfidfPd"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__functionfidfPd
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z8functionfidfPd
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00179506_00000000-6_monte.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4316:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4316:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8functionfidfPdfidfPd
.type _Z31__device_stub__Z8functionfidfPdfidfPd, @function
_Z31__device_stub__Z8functionfidfPdfidfPd:
.LFB4338:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movl %edi, 24(%rsp)
movsd %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8functionfidfPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4338:
.size _Z31__device_stub__Z8functionfidfPdfidfPd, .-_Z31__device_stub__Z8functionfidfPdfidfPd
.globl _Z8functionfidfPd
.type _Z8functionfidfPd, @function
_Z8functionfidfPd:
.LFB4339:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8functionfidfPdfidfPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4339:
.size _Z8functionfidfPd, .-_Z8functionfidfPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8functionfidfPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4341:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8functionfidfPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4341:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.weak _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.type _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function
_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_:
.LFB4469:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4469
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %rbp
movq %rcx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r13d
movl $0, (%rax)
movq %rsp, %rsi
movq %rbp, %rdi
.LEHB0:
call *%r15
movq (%rsp), %rax
cmpq %rbp, %rax
je .L26
cmpl $34, (%rbx)
je .L27
testq %r12, %r12
je .L18
subq %rbp, %rax
movq %rax, (%r12)
.L18:
cmpl $0, (%rbx)
jne .L13
movl %r13d, (%rbx)
.L13:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L29
movq %r14, %rdi
call _ZSt24__throw_invalid_argumentPKc@PLT
.L24:
endbr64
movq %rax, %rdi
cmpl $0, (%rbx)
jne .L21
movl %r13d, (%rbx)
.L21:
movq 8(%rsp), %rax
subq %fs:40, %rax
je .L22
call __stack_chk_fail@PLT
.L29:
call __stack_chk_fail@PLT
.L27:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L30
movq %r14, %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE0:
.L30:
call __stack_chk_fail@PLT
.L22:
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4469:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.LLSDA4469:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4469-.LLSDACSB4469
.LLSDACSB4469:
.uleb128 .LEHB0-.LFB4469
.uleb128 .LEHE0-.LEHB0
.uleb128 .L24-.LFB4469
.uleb128 0
.uleb128 .LEHB1-.LFB4469
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE4469:
.section .text._ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.size _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4650:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L40
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L41
cmpq $1, %rax
jne .L36
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L37:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L43
leaq .LC1(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L43:
call __stack_chk_fail@PLT
.L41:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L35:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L37
.L36:
testq %rax, %rax
je .L37
jmp .L35
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4650:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC3:
.string "Incorrect number of arguments"
.LC4:
.string "stod"
.LC5:
.string "stoull"
.text
.globl main
.type main, @function
main:
.LFB4313:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4313
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
.LEHB2:
call cudaDeviceReset@PLT
cmpl $5, %ebp
jne .L80
leaq 64(%rsp), %rdx
movq 8(%rbx), %rsi
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE2:
movl $0, %ecx
movq 80(%rsp), %rdx
leaq .LC4(%rip), %rsi
movq strtod@GOTPCREL(%rip), %rdi
.LEHB3:
call _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE3:
jmp .L81
.L80:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB4:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $22, %eax
jmp .L44
.L81:
pxor %xmm7, %xmm7
cvtsd2ss %xmm0, %xmm7
movss %xmm7, 8(%rsp)
leaq 80(%rsp), %rbp
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 64(%rsp), %rdx
movq 16(%rbx), %rsi
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movl $0, %ecx
movq 80(%rsp), %rdx
leaq .LC4(%rip), %rsi
movq strtod@GOTPCREL(%rip), %rdi
.LEHB5:
call _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE5:
pxor %xmm7, %xmm7
cvtsd2ss %xmm0, %xmm7
movss %xmm7, 12(%rsp)
movq %rbp, %r12
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 24(%rsp)
leaq 52(%rsp), %rdx
movq 32(%rbx), %rsi
movq %r12, %rdi
.LEHB6:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
movq 80(%rsp), %r14
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r13d
movl $0, (%rax)
leaq 64(%rsp), %rsi
movl $10, %edx
movq %r14, %rdi
call __isoc23_strtoull@PLT
movq %rax, %r12
cmpq 64(%rsp), %r14
je .L82
movl (%rbx), %eax
cmpl $34, %eax
je .L83
testl %eax, %eax
jne .L51
movl %r13d, (%rbx)
.L51:
movl %r12d, %r15d
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
testl %r12d, %r12d
jle .L84
movss 12(%rsp), %xmm4
subss 8(%rsp), %xmm4
movss %xmm4, 28(%rsp)
pxor %xmm1, %xmm1
cvtsi2ssl %ebp, %xmm1
divss %xmm1, %xmm4
pxor %xmm7, %xmm7
cvtss2sd %xmm4, %xmm7
movsd %xmm7, 16(%rsp)
movslq %r12d, %r14
salq $3, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, %rbx
leal -1(%r12), %eax
leaq 8(%r13,%rax,8), %rbp
movq %r13, %rax
.L57:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rbp, %rax
jne .L57
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L58:
movl $2, %ecx
movq %r14, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0x000000000, %r12d
.L59:
movq %r12, %xmm3
addsd (%rbx), %xmm3
movq %xmm3, %r12
addq $8, %rbx
cmpq %rbp, %rbx
jne .L59
pxor %xmm0, %xmm0
movss 8(%rsp), %xmm5
ucomiss %xmm0, %xmm5
jp .L74
movl $0x000000000, %ebx
jne .L74
.L60:
pxor %xmm0, %xmm0
movss 12(%rsp), %xmm6
ucomiss %xmm0, %xmm6
jp .L75
pxor %xmm1, %xmm1
jne .L75
.L62:
movq $17, 16+_ZSt4cout(%rip)
movsd .LC8(%rip), %xmm2
movq %rbx, %xmm0
mulsd %xmm2, %xmm0
movq %r12, %xmm7
addsd %xmm7, %xmm0
mulsd %xmm2, %xmm1
addsd %xmm1, %xmm0
mulsd 16(%rsp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
.LEHE6:
movq %r13, %rdi
call free@PLT
movl $0, %eax
.L44:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L86
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L87
leaq .LC5(%rip), %rdi
.LEHB7:
call _ZSt24__throw_invalid_argumentPKc@PLT
.L73:
endbr64
movq %rax, %rbp
cmpl $0, (%rbx)
jne .L55
movl %r13d, (%rbx)
.L55:
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L56
call __stack_chk_fail@PLT
.L87:
call __stack_chk_fail@PLT
.L83:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L88
leaq .LC5(%rip), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE7:
.L88:
call __stack_chk_fail@PLT
.L56:
movq %rbp, %rdi
.LEHB8:
call _Unwind_Resume@PLT
.L84:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $22, %eax
jmp .L44
.L85:
movss 28(%rsp), %xmm2
andps .LC6(%rip), %xmm2
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
movl 24(%rsp), %eax
cltd
idivl %r15d
movl %eax, %edi
movq 40(%rsp), %rsi
divss %xmm0, %xmm2
movsd 16(%rsp), %xmm1
movss 8(%rsp), %xmm0
call _Z31__device_stub__Z8functionfidfPdfidfPd
jmp .L58
.L74:
movss 8(%rsp), %xmm0
call sinf@PLT
divss 8(%rsp), %xmm0
pxor %xmm5, %xmm5
cvtss2sd %xmm0, %xmm5
movq %xmm5, %rbx
jmp .L60
.L75:
movss 12(%rsp), %xmm0
call sinf@PLT
movaps %xmm0, %xmm1
divss 12(%rsp), %xmm1
cvtss2sd %xmm1, %xmm1
jmp .L62
.L71:
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L65
call __stack_chk_fail@PLT
.L65:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L72:
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L67
call __stack_chk_fail@PLT
.L67:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE8:
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4313:
.section .gcc_except_table,"a",@progbits
.LLSDA4313:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4313-.LLSDACSB4313
.LLSDACSB4313:
.uleb128 .LEHB2-.LFB4313
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4313
.uleb128 .LEHE3-.LEHB3
.uleb128 .L71-.LFB4313
.uleb128 0
.uleb128 .LEHB4-.LFB4313
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4313
.uleb128 .LEHE5-.LEHB5
.uleb128 .L72-.LFB4313
.uleb128 0
.uleb128 .LEHB6-.LFB4313
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB4313
.uleb128 .LEHE7-.LEHB7
.uleb128 .L73-.LFB4313
.uleb128 0
.uleb128 .LEHB8-.LFB4313
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.LLSDACSE4313:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1071644672
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "monte.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__functionfidfPd # -- Begin function _Z23__device_stub__functionfidfPd
.p2align 4, 0x90
.type _Z23__device_stub__functionfidfPd,@function
_Z23__device_stub__functionfidfPd: # @_Z23__device_stub__functionfidfPd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 12(%rsp)
movl %edi, 8(%rsp)
movsd %xmm1, 72(%rsp)
movss %xmm2, 4(%rsp)
movq %rsi, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8functionfidfPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__functionfidfPd, .Lfunc_end0-_Z23__device_stub__functionfidfPd
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebx
.cfi_escape 0x2e, 0x00
callq hipDeviceReset
cmpl $5, %ebx
jne .LBB1_10
# %bb.1:
movq 8(%r14), %rbx
leaq 32(%rsp), %r13
movq %r13, 16(%rsp)
testq %rbx, %rbx
je .LBB1_86
# %bb.2:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq strlen
movq %rax, %r15
cmpq $16, %rax
jb .LBB1_7
# %bb.3:
testq %r15, %r15
js .LBB1_100
# %bb.4:
movq %r15, %rdi
incq %rdi
js .LBB1_80
# %bb.5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
.Ltmp0:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp1:
# %bb.6: # %.noexc79
movq %rax, 16(%rsp)
movq %r15, 32(%rsp)
.LBB1_7:
testq %r15, %r15
je .LBB1_17
# %bb.8:
movq 16(%rsp), %rdi
cmpq $1, %r15
jne .LBB1_16
# %bb.9:
movzbl (%rbx), %eax
movb %al, (%rdi)
jmp .LBB1_17
.LBB1_10:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_88
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_13
# %bb.12:
movzbl 67(%rbx), %eax
jmp .LBB1_14
.LBB1_13:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
.LBB1_15:
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movl $22, %eax
jmp .LBB1_78
.LBB1_16:
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB1_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
movq %r15, 24(%rsp)
movq 16(%rsp), %rax
movb $0, (%rax,%r15)
movq 16(%rsp), %r15
.cfi_escape 0x2e, 0x00
callq __errno_location
movq %rax, %rbx
movl (%rax), %ebp
movl $0, (%rax)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rsi
movq %r15, %rdi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
cmpq %r15, 56(%rsp)
je .LBB1_89
# %bb.18:
movl (%rbx), %eax
testl %eax, %eax
je .LBB1_22
# %bb.19:
cmpl $34, %eax
jne .LBB1_23
# %bb.20: # %.critedge.i.i
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp3:
# %bb.21:
.LBB1_22:
movl %ebp, (%rbx)
.LBB1_23: # %_ZNSt7__cxx114stodERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPm.exit
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_25
# %bb.24: # %.critedge.i.i80
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq 16(%r14), %r15
movq %r13, 16(%rsp)
testq %r15, %r15
je .LBB1_91
# %bb.26:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq strlen
movq %rax, %r12
cmpq $16, %rax
jb .LBB1_31
# %bb.27:
testq %r12, %r12
js .LBB1_102
# %bb.28:
movq %r12, %rdi
incq %rdi
js .LBB1_82
# %bb.29: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i81
.Ltmp4:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp5:
# %bb.30: # %.noexc87
movq %rax, 16(%rsp)
movq %r12, 32(%rsp)
.LBB1_31:
testq %r12, %r12
je .LBB1_35
# %bb.32:
movq 16(%rsp), %rdi
cmpq $1, %r12
jne .LBB1_34
# %bb.33:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB1_35
.LBB1_34:
.cfi_escape 0x2e, 0x00
movq %r15, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB1_35: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit88
movq %r12, 24(%rsp)
movq 16(%rsp), %rax
movb $0, (%rax,%r12)
movq 16(%rsp), %r15
movl (%rbx), %ebp
movl $0, (%rbx)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rsi
movq %r15, %rdi
callq strtod
cmpq %r15, 56(%rsp)
je .LBB1_93
# %bb.36:
movl (%rbx), %eax
testl %eax, %eax
movsd %xmm0, 8(%rsp) # 8-byte Spill
je .LBB1_40
# %bb.37:
cmpl $34, %eax
jne .LBB1_41
# %bb.38: # %.critedge.i.i89
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp7:
# %bb.39:
.LBB1_40:
movl %ebp, (%rbx)
.LBB1_41: # %_ZNSt7__cxx114stodERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPm.exit93
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_43
# %bb.42: # %.critedge.i.i94
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_43: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit96
movq 24(%r14), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq 32(%r14), %r14
movq %r13, 16(%rsp)
testq %r14, %r14
je .LBB1_95
# %bb.44:
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq strlen
movq %rax, %r12
cmpq $16, %rax
jb .LBB1_49
# %bb.45:
testq %r12, %r12
js .LBB1_104
# %bb.46:
movq %r12, %rdi
incq %rdi
js .LBB1_84
# %bb.47: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i97
.Ltmp8:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp9:
# %bb.48: # %.noexc103
movq %rax, 16(%rsp)
movq %r12, 32(%rsp)
.LBB1_49:
testq %r12, %r12
je .LBB1_53
# %bb.50:
movq 16(%rsp), %rdi
cmpq $1, %r12
jne .LBB1_52
# %bb.51:
movzbl (%r14), %eax
movb %al, (%rdi)
jmp .LBB1_53
.LBB1_52:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB1_53: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit104
movq %r12, 24(%rsp)
movq 16(%rsp), %rax
movb $0, (%rax,%r12)
movq 16(%rsp), %r12
movl (%rbx), %ebp
movl $0, (%rbx)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rsi
movq %r12, %rdi
movl $10, %edx
callq __isoc23_strtoull
cmpq %r12, 56(%rsp)
je .LBB1_97
# %bb.54:
movq %rax, %r14
movl (%rbx), %eax
testl %eax, %eax
je .LBB1_58
# %bb.55:
cmpl $34, %eax
jne .LBB1_59
# %bb.56: # %.critedge.i.i105
.Ltmp10:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp11:
# %bb.57:
.LBB1_58:
movl %ebp, (%rbx)
.LBB1_59: # %_ZNSt7__cxx116stoullERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_61
# %bb.60: # %.critedge.i.i108
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_61: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit110
testl %r14d, %r14d
jle .LBB1_73
# %bb.62:
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 88(%rsp) # 4-byte Spill
movaps %xmm0, %xmm2
movss %xmm1, 8(%rsp) # 4-byte Spill
subss %xmm1, %xmm2
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
movaps %xmm2, 112(%rsp) # 16-byte Spill
movaps %xmm2, %xmm1
divss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movsd %xmm0, 72(%rsp) # 8-byte Spill
movl %r14d, %r13d
leaq (,%r13,8), %r12
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq malloc
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
movq 80(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $1, %ebp
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %r13
orq $1, %rdi
.cfi_escape 0x2e, 0x00
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_64
# %bb.63:
movl %r15d, %eax
cltd
idivl %r14d
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
movaps 112(%rsp), %xmm1 # 16-byte Reload
andps .LCPI1_0(%rip), %xmm1
divss %xmm0, %xmm1
movq 80(%rsp), %rcx
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 108(%rsp)
movl %eax, 104(%rsp)
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 176(%rsp)
movss %xmm1, 100(%rsp)
movq %rcx, 168(%rsp)
leaq 108(%rsp), %rax
movq %rax, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 24(%rsp)
leaq 176(%rsp), %rax
movq %rax, 32(%rsp)
leaq 100(%rsp), %rax
movq %rax, 40(%rsp)
leaq 168(%rsp), %rax
movq %rax, 48(%rsp)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z8functionfidfPd, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_64: # %.lr.ph.preheader
movq 80(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $2, %r14d
cmovgel %r14d, %ebp
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_65: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addsd (%rbx,%rax,8), %xmm0
incq %rax
cmpq %rax, %rbp
jne .LBB1_65
# %bb.66: # %._crit_edge
movsd %xmm0, 112(%rsp) # 8-byte Spill
xorps %xmm1, %xmm1
xorps %xmm3, %xmm3
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss %xmm3, %xmm0
xorps %xmm2, %xmm2
jne .LBB1_67
jnp .LBB1_68
.LBB1_67:
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
callq sin
xorps %xmm3, %xmm3
xorps %xmm1, %xmm1
movaps %xmm0, %xmm2
divsd 8(%rsp), %xmm2 # 8-byte Folded Reload
mulsd .LCPI1_1(%rip), %xmm2
.LBB1_68:
movss 88(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss %xmm3, %xmm0
jne .LBB1_69
jnp .LBB1_70
.LBB1_69:
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 88(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movsd %xmm2, 8(%rsp) # 8-byte Spill
callq sin
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movaps %xmm0, %xmm1
divsd 88(%rsp), %xmm1 # 8-byte Folded Reload
mulsd .LCPI1_1(%rip), %xmm1
.LBB1_70:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $17, _ZSt4cout+8(%rax)
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm2, %xmm0
addsd %xmm1, %xmm0
mulsd 72(%rsp), %xmm0 # 8-byte Folded Reload
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_99
# %bb.71: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i126
cmpb $0, 56(%r14)
je .LBB1_76
# %bb.72:
movzbl 67(%r14), %ecx
jmp .LBB1_77
.LBB1_73:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_106
# %bb.74: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i121
cmpb $0, 56(%rbx)
je .LBB1_79
# %bb.75:
movzbl 67(%rbx), %eax
.cfi_escape 0x2e, 0x00
jmp .LBB1_15
.LBB1_76:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_77: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit129
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq 80(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq free
xorl %eax, %eax
.LBB1_78:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_79:
.cfi_def_cfa_offset 240
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.cfi_escape 0x2e, 0x00
jmp .LBB1_15
.LBB1_80: # %.noexc11.i
.Ltmp35:
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.Ltmp36:
# %bb.81: # %.noexc78
.LBB1_82: # %.noexc11.i82
.Ltmp25:
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.Ltmp26:
# %bb.83: # %.noexc86
.LBB1_84: # %.noexc11.i98
.Ltmp15:
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.Ltmp16:
# %bb.85: # %.noexc102
.LBB1_86:
.Ltmp39:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt19__throw_logic_errorPKc
.Ltmp40:
# %bb.87: # %.noexc
.LBB1_88:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_89:
.Ltmp32:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp33:
# %bb.90:
.LBB1_91:
.Ltmp29:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt19__throw_logic_errorPKc
.Ltmp30:
# %bb.92: # %.noexc84
.LBB1_93:
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp23:
# %bb.94:
.LBB1_95:
.Ltmp19:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt19__throw_logic_errorPKc
.Ltmp20:
# %bb.96: # %.noexc100
.LBB1_97:
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp13:
# %bb.98:
.LBB1_99:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_100: # %.noexc.i
.Ltmp37:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp38:
# %bb.101: # %.noexc77
.LBB1_102: # %.noexc.i83
.Ltmp27:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp28:
# %bb.103: # %.noexc85
.LBB1_104: # %.noexc.i99
.Ltmp17:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp18:
# %bb.105: # %.noexc101
.LBB1_106:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_107:
.Ltmp14:
movq %rax, %r14
cmpl $0, (%rbx)
jne .LBB1_109
# %bb.108:
movl %ebp, (%rbx)
.LBB1_109: # %_ZZN9__gnu_cxx6__stoaIyycJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_120
# %bb.110: # %.critedge.i.i117
.cfi_escape 0x2e, 0x00
jmp .LBB1_119
.LBB1_111:
.Ltmp24:
movq %rax, %r14
cmpl $0, (%rbx)
jne .LBB1_113
# %bb.112:
movl %ebp, (%rbx)
.LBB1_113: # %_ZZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i90
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_120
# %bb.114: # %.critedge.i.i114
.cfi_escape 0x2e, 0x00
jmp .LBB1_119
.LBB1_115:
.Ltmp34:
movq %rax, %r14
cmpl $0, (%rbx)
jne .LBB1_117
# %bb.116:
movl %ebp, (%rbx)
.LBB1_117: # %_ZZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_120
# %bb.118: # %.critedge.i.i111
.cfi_escape 0x2e, 0x00
.LBB1_119: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit113
callq _ZdlPv
.LBB1_120: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit113
movq %r14, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.LBB1_121:
.Ltmp21:
movq %rax, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.LBB1_122:
.Ltmp31:
movq %rax, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.LBB1_123:
.Ltmp41:
movq %rax, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp2-.Ltmp1 # Call between .Ltmp1 and .Ltmp2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp3-.Ltmp2 # Call between .Ltmp2 and .Ltmp3
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp5-.Ltmp4 # Call between .Ltmp4 and .Ltmp5
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp35-.Ltmp11 # Call between .Ltmp11 and .Ltmp35
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp36-.Ltmp35 # Call between .Ltmp35 and .Ltmp36
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp26-.Ltmp25 # Call between .Ltmp25 and .Ltmp26
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp32-.Ltmp40 # Call between .Ltmp40 and .Ltmp32
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp33-.Ltmp32 # Call between .Ltmp32 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp30-.Ltmp29 # Call between .Ltmp29 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 20 <<
.uleb128 .Ltmp20-.Ltmp19 # Call between .Ltmp19 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 21 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 22 <<
.uleb128 .Ltmp37-.Ltmp13 # Call between .Ltmp13 and .Ltmp37
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 23 <<
.uleb128 .Ltmp38-.Ltmp37 # Call between .Ltmp37 and .Ltmp38
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 24 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 25 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 26 <<
.uleb128 .Lfunc_end1-.Ltmp18 # Call between .Ltmp18 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8functionfidfPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8functionfidfPd,@object # @_Z8functionfidfPd
.section .rodata,"a",@progbits
.globl _Z8functionfidfPd
.p2align 3, 0x0
_Z8functionfidfPd:
.quad _Z23__device_stub__functionfidfPd
.size _Z8functionfidfPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Incorrect number of arguments"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "stod"
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "basic_string: construction from null is not valid"
.size .L.str.2, 50
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "basic_string::_M_create"
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "stoull"
.size .L.str.4, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8functionfidfPd"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__functionfidfPd
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z8functionfidfPd
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
comp += +1.1894E25f + var_2 * var_3;
comp = (var_4 / (var_5 + expf(logf(expf((var_6 - (+1.3359E-35f - (var_7 * +1.2098E-43f + (-0.0f - var_8)))))))));
for (int i=0; i < var_1; ++i) {
float tmp_1 = -1.7854E-42f;
comp += tmp_1 * var_9 - -1.2149E-36f - var_10 - (+1.7379E34f + var_11);
comp += -1.1339E-44f - +1.2085E34f;
comp = (var_12 * (var_13 * sinf(-1.2139E-23f)));
}
if (comp >= +1.2367E-37f + -0.0f / (+1.7729E15f / (-1.2644E36f + var_14))) {
comp = fabsf(-0.0f);
}
if (comp <= (+1.4110E34f + -0.0f)) {
comp += var_15 - var_16;
float tmp_2 = +1.5469E-15f;
comp = tmp_2 - (var_17 + cosf((-0.0f + var_18 / ldexpf(+1.8918E36f / sqrtf(-1.3862E-35f + (-1.5382E29f * -1.3392E35f)), 2))));
comp = (var_19 - (+1.5999E-35f / +1.2273E-8f * (var_20 * +0.0f)));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z7computefifffffffffffffffffff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ HFMA2.MMA R3, -RZ, RZ, 0, 5.12599945068359375e-06 ; /* 0x00000056ff037435 */
/* 0x000fe200000001ff */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3e055027 ; /* 0x3e055027ff087424 */
/* 0x000fe200078e00ff */
/*0050*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fcc0007ffe0ff */
/*0060*/ FFMA R0, R0, -R3, c[0x0][0x180] ; /* 0x0000600000007623 */
/* 0x000fc80000000803 */
/*0070*/ FADD R2, R0, 1.3358999681303448325e-35 ; /* 0x058e0ea800027421 */
/* 0x000fe40000000000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff007424 */
/* 0x000fe400078e00ff */
/*0090*/ FADD R3, -R2, c[0x0][0x178] ; /* 0x00005e0002037621 */
/* 0x000fe40000000100 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x437c0000 ; /* 0x437c0000ff027424 */
/* 0x000fe400078e00ff */
/*00b0*/ FFMA.SAT R5, R3, R0, 0.5 ; /* 0x3f00000003057423 */
/* 0x000fc80000002000 */
/*00c0*/ FFMA.RM R5, R5, R2, 12582913 ; /* 0x4b40000105057423 */
/* 0x000fc80000004002 */
/*00d0*/ FADD R4, R5.reuse, -12583039 ; /* 0xcb40007f05047421 */
/* 0x040fe20000000000 */
/*00e0*/ SHF.L.U32 R5, R5, 0x17, RZ ; /* 0x0000001705057819 */
/* 0x000fc600000006ff */
/*00f0*/ FFMA R4, R3, 1.4426950216293334961, -R4 ; /* 0x3fb8aa3b03047823 */
/* 0x000fc80000000804 */
/*0100*/ FFMA R4, R3, 1.925963033500011079e-08, R4 ; /* 0x32a5706003047823 */
/* 0x000fcc0000000004 */
/*0110*/ MUFU.EX2 R4, R4 ; /* 0x0000000400047308 */
/* 0x000e240000000800 */
/*0120*/ FMUL R5, R5, R4 ; /* 0x0000000405057220 */
/* 0x001fca0000400000 */
/*0130*/ FSETP.GEU.AND P0, PT, R5, 1.175494350822287508e-38, PT ; /* 0x008000000500780b */
/* 0x000fda0003f0e000 */
/*0140*/ @!P0 FMUL R5, R5, 8388608 ; /* 0x4b00000005058820 */
/* 0x000fca0000400000 */
/*0150*/ IADD3 R3, R5.reuse, -0x3f2aaaab, RZ ; /* 0xc0d5555505037810 */
/* 0x040fe40007ffe0ff */
/*0160*/ ISETP.GE.U32.AND P1, PT, R5, 0x7f800000, PT ; /* 0x7f8000000500780c */
/* 0x000fe40003f26070 */
/*0170*/ LOP3.LUT R6, R3, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000003067812 */
/* 0x000fca00078ec0ff */
/*0180*/ IMAD.IADD R3, R5, 0x1, -R6 ; /* 0x0000000105037824 */
/* 0x000fe400078e0a06 */
/*0190*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x000e240000201400 */
/*01a0*/ FADD R7, R3, -1 ; /* 0xbf80000003077421 */
/* 0x000fe20000000000 */
/*01b0*/ FSEL R3, RZ, -23, P0 ; /* 0xc1b80000ff037808 */
/* 0x000fe40000000000 */
/*01c0*/ @P1 MOV R4, 0x7f800000 ; /* 0x7f80000000041802 */
/* 0x000fe20000000f00 */
/*01d0*/ FFMA R8, R7, -R8, 0.14084610342979431152 ; /* 0x3e1039f607087423 */
/* 0x000fe20000000808 */
/*01e0*/ FSETP.NEU.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720b */
/* 0x000fc60003f0d000 */
/*01f0*/ FFMA R8, R7, R8, -0.12148627638816833496 ; /* 0xbdf8cdcc07087423 */
/* 0x000fc80000000008 */
/*0200*/ FFMA R8, R7.reuse, R8, 0.13980610668659210205 ; /* 0x3e0f295507087423 */
/* 0x040fe40000000008 */
/*0210*/ FFMA R3, R6, 1.1920928955078125e-07, R3 ; /* 0x3400000006037823 */
/* 0x001fe40000000003 */
/*0220*/ FFMA R8, R7.reuse, R8, -0.16684235632419586182 ; /* 0xbe2ad8b907087423 */
/* 0x040fe40000000008 */
/*0230*/ IMAD.U32 R6, RZ, RZ, UR4 ; /* 0x00000004ff067e24 */
/* 0x000fe4000f8e00ff */
/*0240*/ FFMA R8, R7, R8, 0.20012299716472625732 ; /* 0x3e4ced0b07087423 */
/* 0x000fc80000000008 */
/*0250*/ FFMA R8, R7, R8, -0.24999669194221496582 ; /* 0xbe7fff2207087423 */
/* 0x000fc80000000008 */
/*0260*/ FFMA R8, R7, R8, 0.33333182334899902344 ; /* 0x3eaaaa7807087423 */
/* 0x000fc80000000008 */
/*0270*/ FFMA R8, R7, R8, -0.5 ; /* 0xbf00000007087423 */
/* 0x000fc80000000008 */
/*0280*/ FMUL R8, R7, R8 ; /* 0x0000000807087220 */
/* 0x000fc80000400000 */
/*0290*/ FFMA R8, R7, R8, R7 ; /* 0x0000000807087223 */
/* 0x000fc80000000007 */
/*02a0*/ FFMA R3, R3, 0.69314718246459960938, R8 ; /* 0x3f31721803037823 */
/* 0x000fe40000000008 */
/*02b0*/ @P1 FFMA R3, R5, R4, +INF ; /* 0x7f80000005031423 */
/* 0x000fca0000000004 */
/*02c0*/ FSEL R3, R3, -INF , P0 ; /* 0xff80000003037808 */
/* 0x000fca0000000000 */
/*02d0*/ FFMA.SAT R5, R3, R0, 0.5 ; /* 0x3f00000003057423 */
/* 0x000fc80000002000 */
/*02e0*/ FFMA.RM R5, R5, R2, 12582913 ; /* 0x4b40000105057423 */
/* 0x000fc80000004002 */
/*02f0*/ FADD R0, R5.reuse, -12583039 ; /* 0xcb40007f05007421 */
/* 0x040fe40000000000 */
/*0300*/ IMAD.SHL.U32 R5, R5, 0x800000, RZ ; /* 0x0080000005057824 */
/* 0x000fe400078e00ff */
/*0310*/ FFMA R0, R3, 1.4426950216293334961, -R0 ; /* 0x3fb8aa3b03007823 */
/* 0x000fc80000000800 */
/*0320*/ FFMA R0, R3, 1.925963033500011079e-08, R0 ; /* 0x32a5706003007823 */
/* 0x000fcc0000000000 */
/*0330*/ MUFU.EX2 R0, R0 ; /* 0x0000000000007308 */
/* 0x000e240000000800 */
/*0340*/ FFMA R9, R5, R0, c[0x0][0x174] ; /* 0x00005d0005097623 */
/* 0x001fcc0000000000 */
/*0350*/ MUFU.RCP R2, R9 ; /* 0x0000000900027308 */
/* 0x000e300000001000 */
/*0360*/ FCHK P0, R6, R9 ; /* 0x0000000906007302 */
/* 0x000e620000000000 */
/*0370*/ FFMA R3, -R9, R2, 1 ; /* 0x3f80000009037423 */
/* 0x001fc80000000102 */
/*0380*/ FFMA R3, R2, R3, R2 ; /* 0x0000000302037223 */
/* 0x000fc80000000002 */
/*0390*/ FFMA R2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003027a23 */
/* 0x000fc800000000ff */
/*03a0*/ FFMA R4, -R9, R2, c[0x0][0x170] ; /* 0x00005c0009047623 */
/* 0x000fc80000000102 */
/*03b0*/ FFMA R0, R3, R4, R2 ; /* 0x0000000403007223 */
/* 0x000fe20000000002 */
/*03c0*/ @!P0 BRA 0x410 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*03d0*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe40000000f00 */
/*03e0*/ MOV R2, 0x400 ; /* 0x0000040000027802 */
/* 0x000fe40000000f00 */
/*03f0*/ CALL.REL.NOINC 0x7a0 ; /* 0x000003a000007944 */
/* 0x000fea0003c00000 */
/*0400*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0004 */
/*0410*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff037624 */
/* 0x000fe200078e00ff */
/*0420*/ UMOV UR4, 0x58c98e2e ; /* 0x58c98e2e00047882 */
/* 0x000fe20000000000 */
/*0430*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fe40003f01270 */
/*0440*/ FADD R3, R3, -1.26440002717659416425e+36 ; /* 0xfb7383bc03037421 */
/* 0x000fe20000000000 */
/*0450*/ MOV R8, UR4 ; /* 0x0000000400087c02 */
/* 0x000fc60008000f00 */
/*0460*/ MUFU.RCP R2, R3 ; /* 0x0000000300027308 */
/* 0x000e300000001000 */
/*0470*/ FCHK P1, -R8, R3 ; /* 0x0000000308007302 */
/* 0x000e620000020100 */
/*0480*/ FFMA R5, -R3, R2, 1 ; /* 0x3f80000003057423 */
/* 0x001fc80000000102 */
/*0490*/ FFMA R5, R2, R5, R2 ; /* 0x0000000502057223 */
/* 0x000fe40000000002 */
/*04a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff027624 */
/* 0x000fe400078e00ff */
/*04b0*/ FFMA R4, R5, -1.77289995432755200000e+15, RZ ; /* 0xd8c98e2e05047823 */
/* 0x000fe400000000ff */
/*04c0*/ FMUL R2, R2, -1.2139000287010887093e-23 ; /* 0x996acd6b02027820 */
/* 0x000fe40000400000 */
/*04d0*/ FFMA R6, -R3, R4, -1.77289995432755200000e+15 ; /* 0xd8c98e2e03067423 */
/* 0x000fe40000000104 */
/*04e0*/ @P0 FMUL R0, R2, c[0x0][0x190] ; /* 0x0000640002000a20 */
/* 0x000fc40000400000 */
/*04f0*/ FFMA R4, R5, R6, R4 ; /* 0x0000000605047223 */
/* 0x000fe20000000004 */
/*0500*/ @!P1 BRA 0x550 ; /* 0x0000004000009947 */
/* 0x002fea0003800000 */
/*0510*/ HFMA2.MMA R8, -RZ, RZ, -153.125, -0.000377178192138671875 ; /* 0xd8c98e2eff087435 */
/* 0x000fe200000001ff */
/*0520*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0003 */
/*0530*/ MOV R2, 0x550 ; /* 0x0000055000027802 */
/* 0x000fc80000000f00 */
/*0540*/ CALL.REL.NOINC 0x7a0 ; /* 0x0000025000007944 */
/* 0x000fea0003c00000 */
/*0550*/ MUFU.RCP R3, R4 ; /* 0x0000000400037308 */
/* 0x000e220000001000 */
/*0560*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f3e0ff */
/*0570*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*0580*/ FCHK P0, RZ, R4 ; /* 0x00000004ff007302 */
/* 0x000e620000000000 */
/*0590*/ FFMA R2, R3, -R4, 1 ; /* 0x3f80000003027423 */
/* 0x001fc80000000804 */
/*05a0*/ FFMA R2, R3, R2, R3 ; /* 0x0000000203027223 */
/* 0x000fc80000000003 */
/*05b0*/ FFMA R3, RZ, R2, RZ ; /* 0x00000002ff037223 */
/* 0x000fc800000000ff */
/*05c0*/ FFMA R5, R3, -R4, RZ ; /* 0x8000000403057223 */
/* 0x000fc800000000ff */
/*05d0*/ FFMA R2, R2, R5, R3 ; /* 0x0000000502027223 */
/* 0x000fe20000000003 */
/*05e0*/ @!P0 BRA 0x640 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*05f0*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0600*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0610*/ MOV R2, 0x630 ; /* 0x0000063000027802 */
/* 0x000fe40000000f00 */
/*0620*/ CALL.REL.NOINC 0x7a0 ; /* 0x0000017000007944 */
/* 0x000fea0003c00000 */
/*0630*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0640*/ FADD R3, R2, 1.236700040939312576e-37 ; /* 0x022854b502037421 */
/* 0x000fe20000000000 */
/*0650*/ MOV R4, c[0x4][0x8] ; /* 0x0100020000047a02 */
/* 0x000fe20000000f00 */
/*0660*/ FMUL R2, RZ, c[0x0][0x1b0] ; /* 0x00006c00ff027a20 */
/* 0x000fe40000400000 */
/*0670*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0680*/ FSETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720b */
/* 0x000fe20003f06000 */
/*0690*/ IMAD.MOV.U32 R3, RZ, RZ, 0x12ce9006 ; /* 0x12ce9006ff037424 */
/* 0x000fc600078e00ff */
/*06a0*/ FSEL R0, R0, RZ, !P0 ; /* 0x000000ff00007208 */
/* 0x000fc80004000000 */
/*06b0*/ FSETP.GTU.AND P0, PT, R0, 1.41099997157534679558e+34, PT ; /* 0x782deb4f0000780b */
/* 0x000fda0003f0c000 */
/*06c0*/ @!P0 FFMA R0, R2, -R3, c[0x0][0x1ac] ; /* 0x00006b0002008623 */
/* 0x000fe20000000803 */
/*06d0*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fc60000000f00 */
/*06e0*/ F2F.F64.F32 R8, R0 ; /* 0x0000000000087310 */
/* 0x000e260000201800 */
/*06f0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*0700*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0011e40000100a00 */
/*0710*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe20000000000 */
/*0720*/ MOV R11, 0x790 ; /* 0x00000790000b7802 */
/* 0x000fe40000000f00 */
/*0730*/ MOV R20, 0x710 ; /* 0x0000071000147802 */
/* 0x000fe40000000f00 */
/*0740*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0750*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*0760*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0770*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0780*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0790*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07a0*/ SHF.R.U32.HI R4, RZ, 0x17, R9.reuse ; /* 0x00000017ff047819 */
/* 0x100fe40000011609 */
/*07b0*/ SHF.R.U32.HI R3, RZ, 0x17, R8 ; /* 0x00000017ff037819 */
/* 0x000fe40000011608 */
/*07c0*/ LOP3.LUT R13, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040d7812 */
/* 0x000fe200078ec0ff */
/*07d0*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0009 */
/*07e0*/ LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030b7812 */
/* 0x000fe400078ec0ff */
/*07f0*/ IADD3 R12, R13, -0x1, RZ ; /* 0xffffffff0d0c7810 */
/* 0x000fe40007ffe0ff */
/*0800*/ IADD3 R10, R11, -0x1, RZ ; /* 0xffffffff0b0a7810 */
/* 0x000fc40007ffe0ff */
/*0810*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fe40003f04070 */
/*0820*/ MOV R3, R8 ; /* 0x0000000800037202 */
/* 0x000fe40000000f00 */
/*0830*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0840*/ @!P0 MOV R5, RZ ; /* 0x000000ff00058202 */
/* 0x000fe20000000f00 */
/*0850*/ @!P0 BRA 0x9d0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0860*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*0870*/ FSETP.GTU.FTZ.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fc80003f3c200 */
/*0880*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0890*/ @P0 BRA 0xdb0 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*08a0*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, R3, 0xc8, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fda000780c803 */
/*08b0*/ @!P0 BRA 0xd90 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*08c0*/ FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ; /* 0x7f8000000800780b */
/* 0x040fe40003f5d200 */
/*08d0*/ FSETP.NEU.FTZ.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f3d200 */
/*08e0*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*08f0*/ @!P1 BRA !P2, 0xd90 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*0900*/ LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fc8000784c0ff */
/*0910*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0920*/ @P1 BRA 0xd70 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*0930*/ LOP3.LUT P1, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fc8000782c0ff */
/*0940*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0950*/ @P0 BRA 0xd40 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0960*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0970*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0980*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff050224 */
/* 0x000fe200078e00ff */
/*0990*/ @!P0 MOV R5, 0xffffffc0 ; /* 0xffffffc000058802 */
/* 0x000fe20000000f00 */
/*09a0*/ @!P0 FFMA R3, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008038823 */
/* 0x000fe400000000ff */
/*09b0*/ @!P1 FFMA R4, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009049823 */
/* 0x000fe200000000ff */
/*09c0*/ @!P1 IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005059810 */
/* 0x000fe40007ffe0ff */
/*09d0*/ LEA R9, R13, 0xc0800000, 0x17 ; /* 0xc08000000d097811 */
/* 0x000fca00078eb8ff */
/*09e0*/ IMAD.IADD R9, R4, 0x1, -R9 ; /* 0x0000000104097824 */
/* 0x000fe200078e0a09 */
/*09f0*/ IADD3 R4, R11, -0x7f, RZ ; /* 0xffffff810b047810 */
/* 0x000fc60007ffe0ff */
/*0a00*/ MUFU.RCP R8, R9 ; /* 0x0000000900087308 */
/* 0x000e220000001000 */
/*0a10*/ FADD.FTZ R10, -R9, -RZ ; /* 0x800000ff090a7221 */
/* 0x000fe40000010100 */
/*0a20*/ IMAD R3, R4, -0x800000, R3 ; /* 0xff80000004037824 */
/* 0x000fe400078e0203 */
/*0a30*/ FFMA R11, R8, R10, 1 ; /* 0x3f800000080b7423 */
/* 0x001fc8000000000a */
/*0a40*/ FFMA R12, R8, R11, R8 ; /* 0x0000000b080c7223 */
/* 0x000fc80000000008 */
/*0a50*/ FFMA R8, R3, R12, RZ ; /* 0x0000000c03087223 */
/* 0x000fc800000000ff */
/*0a60*/ FFMA R11, R10, R8, R3 ; /* 0x000000080a0b7223 */
/* 0x000fc80000000003 */
/*0a70*/ FFMA R11, R12, R11, R8 ; /* 0x0000000b0c0b7223 */
/* 0x000fe20000000008 */
/*0a80*/ IADD3 R8, R4, 0x7f, -R13 ; /* 0x0000007f04087810 */
/* 0x000fc60007ffe80d */
/*0a90*/ FFMA R10, R10, R11, R3 ; /* 0x0000000b0a0a7223 */
/* 0x000fe20000000003 */
/*0aa0*/ IADD3 R8, R8, R5, RZ ; /* 0x0000000508087210 */
/* 0x000fc60007ffe0ff */
/*0ab0*/ FFMA R3, R12, R10, R11 ; /* 0x0000000a0c037223 */
/* 0x000fca000000000b */
/*0ac0*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0ad0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0ae0*/ IMAD.IADD R13, R4, 0x1, R8 ; /* 0x00000001040d7824 */
/* 0x000fca00078e0208 */
/*0af0*/ IADD3 R4, R13, -0x1, RZ ; /* 0xffffffff0d047810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0b10*/ @!P0 BRA 0xd20 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0b20*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*0b30*/ @P0 BRA 0xcf0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0b40*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*0b50*/ @P0 BRA 0xdc0 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0b60*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0b70*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0b80*/ @!P0 BRA 0xdc0 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0b90*/ FFMA.RZ R4, R12.reuse, R10.reuse, R11.reuse ; /* 0x0000000a0c047223 */
/* 0x1c0fe2000000c00b */
/*0ba0*/ IADD3 R9, R13.reuse, 0x20, RZ ; /* 0x000000200d097810 */
/* 0x040fe20007ffe0ff */
/*0bb0*/ FFMA.RM R5, R12, R10.reuse, R11.reuse ; /* 0x0000000a0c057223 */
/* 0x180fe2000000400b */
/*0bc0*/ ISETP.NE.AND P2, PT, R13.reuse, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x040fe40003f45270 */
/*0bd0*/ LOP3.LUT R8, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04087812 */
/* 0x000fe200078ec0ff */
/*0be0*/ FFMA.RP R4, R12, R10, R11 ; /* 0x0000000a0c047223 */
/* 0x000fe2000000800b */
/*0bf0*/ ISETP.NE.AND P1, PT, R13.reuse, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x040fe40003f25270 */
/*0c00*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*0c10*/ IADD3 R10, -R13, RZ, RZ ; /* 0x000000ff0d0a7210 */
/* 0x000fc40007ffe1ff */
/*0c20*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0c30*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fe40003f1d000 */
/*0c40*/ SEL R5, R10, RZ, P2 ; /* 0x000000ff0a057207 */
/* 0x000fe40001000000 */
/*0c50*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0c60*/ SHF.R.U32.HI R5, RZ, R5, R8 ; /* 0x00000005ff057219 */
/* 0x000fe40000011608 */
/*0c70*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0c80*/ SHF.R.U32.HI R9, RZ, 0x1, R5 ; /* 0x00000001ff097819 */
/* 0x000fe40000011605 */
/*0c90*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0ca0*/ LOP3.LUT R4, R4, 0x1, R9, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef809 */
/*0cb0*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0cc0*/ IMAD.IADD R4, R9, 0x1, R4 ; /* 0x0000000109047824 */
/* 0x000fca00078e0204 */
/*0cd0*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0ce0*/ BRA 0xdc0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0cf0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0d00*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0d10*/ BRA 0xdc0 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0d20*/ LEA R3, R8, R3, 0x17 ; /* 0x0000000308037211 */
/* 0x000fe200078eb8ff */
/*0d30*/ BRA 0xdc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0d40*/ LOP3.LUT R3, R4, 0x80000000, R3, 0x48, !PT ; /* 0x8000000004037812 */
/* 0x000fc800078e4803 */
/*0d50*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0d60*/ BRA 0xdc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d70*/ LOP3.LUT R3, R4, 0x80000000, R3, 0x48, !PT ; /* 0x8000000004037812 */
/* 0x000fe200078e4803 */
/*0d80*/ BRA 0xdc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0d90*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0da0*/ BRA 0xdc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0db0*/ FADD.FTZ R3, R8, R9 ; /* 0x0000000908037221 */
/* 0x000fc80000010000 */
/*0dc0*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0003 */
/*0dd0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fcc00000001ff */
/*0de0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff21002007950 */
/* 0x000fea0003c3ffff */
/*0df0*/ BRA 0xdf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
comp += +1.1894E25f + var_2 * var_3;
comp = (var_4 / (var_5 + expf(logf(expf((var_6 - (+1.3359E-35f - (var_7 * +1.2098E-43f + (-0.0f - var_8)))))))));
for (int i=0; i < var_1; ++i) {
float tmp_1 = -1.7854E-42f;
comp += tmp_1 * var_9 - -1.2149E-36f - var_10 - (+1.7379E34f + var_11);
comp += -1.1339E-44f - +1.2085E34f;
comp = (var_12 * (var_13 * sinf(-1.2139E-23f)));
}
if (comp >= +1.2367E-37f + -0.0f / (+1.7729E15f / (-1.2644E36f + var_14))) {
comp = fabsf(-0.0f);
}
if (comp <= (+1.4110E34f + -0.0f)) {
comp += var_15 - var_16;
float tmp_2 = +1.5469E-15f;
comp = tmp_2 - (var_17 + cosf((-0.0f + var_18 / ldexpf(+1.8918E36f / sqrtf(-1.3862E-35f + (-1.5382E29f * -1.3392E35f)), 2))));
comp = (var_19 - (+1.5999E-35f / +1.2273E-8f * (var_20 * +0.0f)));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00193779_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
.type _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff, @function
_Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 304(%rsp), %rax
movq %rax, 184(%rsp)
leaq 312(%rsp), %rax
movq %rax, 192(%rsp)
leaq 320(%rsp), %rax
movq %rax, 200(%rsp)
leaq 328(%rsp), %rax
movq %rax, 208(%rsp)
leaq 336(%rsp), %rax
movq %rax, 216(%rsp)
leaq 344(%rsp), %rax
movq %rax, 224(%rsp)
leaq 352(%rsp), %rax
movq %rax, 232(%rsp)
leaq 360(%rsp), %rax
movq %rax, 240(%rsp)
leaq 368(%rsp), %rax
movq %rax, 248(%rsp)
leaq 376(%rsp), %rax
movq %rax, 256(%rsp)
leaq 384(%rsp), %rax
movq %rax, 264(%rsp)
leaq 392(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 312
pushq 56(%rsp)
.cfi_def_cfa_offset 320
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefifffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff, .-_Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
.globl _Z7computefifffffffffffffffffff
.type _Z7computefifffffffffffffffffff, @function
_Z7computefifffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss 200(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 120(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 112(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefifffffffffffffffffff, .-_Z7computefifffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 168(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 152(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -96(%rsp), %rsp
.cfi_def_cfa_offset 320
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 104(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 192(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 200(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 208(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 216(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 224(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 232(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movl %ebp, %edi
call _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
addq $96, %rsp
.cfi_def_cfa_offset 224
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefifffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefifffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
comp += +1.1894E25f + var_2 * var_3;
comp = (var_4 / (var_5 + expf(logf(expf((var_6 - (+1.3359E-35f - (var_7 * +1.2098E-43f + (-0.0f - var_8)))))))));
for (int i=0; i < var_1; ++i) {
float tmp_1 = -1.7854E-42f;
comp += tmp_1 * var_9 - -1.2149E-36f - var_10 - (+1.7379E34f + var_11);
comp += -1.1339E-44f - +1.2085E34f;
comp = (var_12 * (var_13 * sinf(-1.2139E-23f)));
}
if (comp >= +1.2367E-37f + -0.0f / (+1.7729E15f / (-1.2644E36f + var_14))) {
comp = fabsf(-0.0f);
}
if (comp <= (+1.4110E34f + -0.0f)) {
comp += var_15 - var_16;
float tmp_2 = +1.5469E-15f;
comp = tmp_2 - (var_17 + cosf((-0.0f + var_18 / ldexpf(+1.8918E36f / sqrtf(-1.3862E-35f + (-1.5382E29f * -1.3392E35f)), 2))));
comp = (var_19 - (+1.5999E-35f / +1.2273E-8f * (var_20 * +0.0f)));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
comp += +1.1894E25f + var_2 * var_3;
comp = (var_4 / (var_5 + expf(logf(expf((var_6 - (+1.3359E-35f - (var_7 * +1.2098E-43f + (-0.0f - var_8)))))))));
for (int i=0; i < var_1; ++i) {
float tmp_1 = -1.7854E-42f;
comp += tmp_1 * var_9 - -1.2149E-36f - var_10 - (+1.7379E34f + var_11);
comp += -1.1339E-44f - +1.2085E34f;
comp = (var_12 * (var_13 * sinf(-1.2139E-23f)));
}
if (comp >= +1.2367E-37f + -0.0f / (+1.7729E15f / (-1.2644E36f + var_14))) {
comp = fabsf(-0.0f);
}
if (comp <= (+1.4110E34f + -0.0f)) {
comp += var_15 - var_16;
float tmp_2 = +1.5469E-15f;
comp = tmp_2 - (var_17 + cosf((-0.0f + var_18 / ldexpf(+1.8918E36f / sqrtf(-1.3862E-35f + (-1.5382E29f * -1.3392E35f)), 2))));
comp = (var_19 - (+1.5999E-35f / +1.2273E-8f * (var_20 * +0.0f)));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
comp += +1.1894E25f + var_2 * var_3;
comp = (var_4 / (var_5 + expf(logf(expf((var_6 - (+1.3359E-35f - (var_7 * +1.2098E-43f + (-0.0f - var_8)))))))));
for (int i=0; i < var_1; ++i) {
float tmp_1 = -1.7854E-42f;
comp += tmp_1 * var_9 - -1.2149E-36f - var_10 - (+1.7379E34f + var_11);
comp += -1.1339E-44f - +1.2085E34f;
comp = (var_12 * (var_13 * sinf(-1.2139E-23f)));
}
if (comp >= +1.2367E-37f + -0.0f / (+1.7729E15f / (-1.2644E36f + var_14))) {
comp = fabsf(-0.0f);
}
if (comp <= (+1.4110E34f + -0.0f)) {
comp += var_15 - var_16;
float tmp_2 = +1.5469E-15f;
comp = tmp_2 - (var_17 + cosf((-0.0f + var_18 / ldexpf(+1.8918E36f / sqrtf(-1.3862E-35f + (-1.5382E29f * -1.3392E35f)), 2))));
comp = (var_19 - (+1.5999E-35f / +1.2273E-8f * (var_20 * +0.0f)));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefifffffffffffffffffff # -- Begin function _Z22__device_stub__computefifffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefifffffffffffffffffff,@function
_Z22__device_stub__computefifffffffffffffffffff: # @_Z22__device_stub__computefifffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 272(%rsp), %rax
movq %rax, 168(%rsp)
leaq 280(%rsp), %rax
movq %rax, 176(%rsp)
leaq 288(%rsp), %rax
movq %rax, 184(%rsp)
leaq 296(%rsp), %rax
movq %rax, 192(%rsp)
leaq 304(%rsp), %rax
movq %rax, 200(%rsp)
leaq 312(%rsp), %rax
movq %rax, 208(%rsp)
leaq 320(%rsp), %rax
movq %rax, 216(%rsp)
leaq 328(%rsp), %rax
movq %rax, 224(%rsp)
leaq 336(%rsp), %rax
movq %rax, 232(%rsp)
leaq 344(%rsp), %rax
movq %rax, 240(%rsp)
leaq 352(%rsp), %rax
movq %rax, 248(%rsp)
leaq 360(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefifffffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $280, %rsp # imm = 0x118
.cfi_adjust_cfa_offset -280
retq
.Lfunc_end0:
.size _Z22__device_stub__computefifffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefifffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 128(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 136(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 144(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 152(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 160(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 168(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 104(%rsp) # 4-byte Spill
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 128(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 88(%rsp)
movss %xmm9, 80(%rsp)
movss %xmm10, 72(%rsp)
movss %xmm11, 64(%rsp)
movss %xmm12, 56(%rsp)
movss %xmm13, 48(%rsp)
movss %xmm14, 40(%rsp)
movss %xmm15, 32(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, (%rsp)
movl %ebx, %edi
movss 128(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 120(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 112(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 104(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefifffffffffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefifffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefifffffffffffffffffff,@object # @_Z7computefifffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefifffffffffffffffffff
.p2align 3, 0x0
_Z7computefifffffffffffffffffff:
.quad _Z22__device_stub__computefifffffffffffffffffff
.size _Z7computefifffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefifffffffffffffffffff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefifffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefifffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00193779_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
.type _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff, @function
_Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 304(%rsp), %rax
movq %rax, 184(%rsp)
leaq 312(%rsp), %rax
movq %rax, 192(%rsp)
leaq 320(%rsp), %rax
movq %rax, 200(%rsp)
leaq 328(%rsp), %rax
movq %rax, 208(%rsp)
leaq 336(%rsp), %rax
movq %rax, 216(%rsp)
leaq 344(%rsp), %rax
movq %rax, 224(%rsp)
leaq 352(%rsp), %rax
movq %rax, 232(%rsp)
leaq 360(%rsp), %rax
movq %rax, 240(%rsp)
leaq 368(%rsp), %rax
movq %rax, 248(%rsp)
leaq 376(%rsp), %rax
movq %rax, 256(%rsp)
leaq 384(%rsp), %rax
movq %rax, 264(%rsp)
leaq 392(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 312
pushq 56(%rsp)
.cfi_def_cfa_offset 320
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefifffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff, .-_Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
.globl _Z7computefifffffffffffffffffff
.type _Z7computefifffffffffffffffffff, @function
_Z7computefifffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss 200(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 120(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 112(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefifffffffffffffffffff, .-_Z7computefifffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 168(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 152(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -96(%rsp), %rsp
.cfi_def_cfa_offset 320
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 104(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 192(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 200(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 208(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 216(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 224(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 232(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movl %ebp, %edi
call _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
addq $96, %rsp
.cfi_def_cfa_offset 224
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefifffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefifffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefifffffffffffffffffff # -- Begin function _Z22__device_stub__computefifffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefifffffffffffffffffff,@function
_Z22__device_stub__computefifffffffffffffffffff: # @_Z22__device_stub__computefifffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 272(%rsp), %rax
movq %rax, 168(%rsp)
leaq 280(%rsp), %rax
movq %rax, 176(%rsp)
leaq 288(%rsp), %rax
movq %rax, 184(%rsp)
leaq 296(%rsp), %rax
movq %rax, 192(%rsp)
leaq 304(%rsp), %rax
movq %rax, 200(%rsp)
leaq 312(%rsp), %rax
movq %rax, 208(%rsp)
leaq 320(%rsp), %rax
movq %rax, 216(%rsp)
leaq 328(%rsp), %rax
movq %rax, 224(%rsp)
leaq 336(%rsp), %rax
movq %rax, 232(%rsp)
leaq 344(%rsp), %rax
movq %rax, 240(%rsp)
leaq 352(%rsp), %rax
movq %rax, 248(%rsp)
leaq 360(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefifffffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $280, %rsp # imm = 0x118
.cfi_adjust_cfa_offset -280
retq
.Lfunc_end0:
.size _Z22__device_stub__computefifffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefifffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 128(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 136(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 144(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 152(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 160(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 168(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 104(%rsp) # 4-byte Spill
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 128(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 88(%rsp)
movss %xmm9, 80(%rsp)
movss %xmm10, 72(%rsp)
movss %xmm11, 64(%rsp)
movss %xmm12, 56(%rsp)
movss %xmm13, 48(%rsp)
movss %xmm14, 40(%rsp)
movss %xmm15, 32(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, (%rsp)
movl %ebx, %edi
movss 128(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 120(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 112(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 104(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefifffffffffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefifffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefifffffffffffffffffff,@object # @_Z7computefifffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefifffffffffffffffffff
.p2align 3, 0x0
_Z7computefifffffffffffffffffff:
.quad _Z22__device_stub__computefifffffffffffffffffff
.size _Z7computefifffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefifffffffffffffffffff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefifffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefifffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void count_spikes(const double *Params, const int *id, int *nsp){
int tid, tind, bid, ind, Nspikes, Nfilters, Nthreads, Nblocks;
Nspikes = (int) Params[0];
Nfilters = (int) Params[2];
tid = threadIdx.x;
bid = blockIdx.x;
Nthreads = blockDim.x;
Nblocks = gridDim.x;
tind = tid + Nthreads *bid;
while (tind<Nfilters){
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==tind)
nsp[tind] += 1;
tind += Nthreads * Nblocks;
}
} | code for sm_80
Function : _Z12count_spikesPKdPKiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64 R4, [R2.64+0x10] ; /* 0x0000100402047981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0060*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R6 ; /* 0x0000000007077a24 */
/* 0x001fe200078e0206 */
/*0080*/ F2I.F64.TRUNC R0, R4 ; /* 0x0000000400007311 */
/* 0x004e28000030d100 */
/*0090*/ ISETP.GE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x001fda0003f06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1b00 */
/*00c0*/ F2I.F64.TRUNC R5, R2 ; /* 0x0000000200057311 */
/* 0x004e24000030d100 */
/*00d0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x001fda0003f06270 */
/*00e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00f0*/ LOP3.LUT R6, R5.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305067812 */
/* 0x040fe400078ec0ff */
/*0100*/ IADD3 R2, R5, -0x1, RZ ; /* 0xffffffff05027810 */
/* 0x000fc60007ffe0ff */
/*0110*/ IMAD.IADD R8, R5, 0x1, -R6 ; /* 0x0000000105087824 */
/* 0x000fe200078e0a06 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fd00003f26070 */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.WIDE R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fe200078e0202 */
/*0160*/ @!P1 BRA 0xc60 ; /* 0x00000af000009947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0180*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0008 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fc400078e00ff */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fcc00078e00ff */
/*01c0*/ @!P0 BRA 0xac0 ; /* 0x000008f000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P2, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f44270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P2 BRA 0x770 ; /* 0x000005700000a947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f45270 */
/*0230*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x000ea4000c1e1900 */
/*0240*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x004fca0007ffe0ff */
/*0250*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e8000c101904 */
/*0260*/ LDG.E R12, [R4.64+0x4] ; /* 0x00000404040c7981 */
/* 0x000ea4000c1e1900 */
/*0270*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f45270 */
/*0280*/ @!P2 LDG.E R13, [R2.64] ; /* 0x00000004020da981 */
/* 0x000ea4000c1e1900 */
/*0290*/ @!P2 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0da810 */
/* 0x004fca0007ffe0ff */
/*02a0*/ @!P2 STG.E [R2.64], R13 ; /* 0x0000000d0200a986 */
/* 0x0003e8000c101904 */
/*02b0*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f45270 */
/*02d0*/ @!P2 LDG.E R15, [R2.64] ; /* 0x00000004020fa981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ @!P2 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0fa810 */
/* 0x004fca0007ffe0ff */
/*02f0*/ @!P2 STG.E [R2.64], R15 ; /* 0x0000000f0200a986 */
/* 0x0005e8000c101904 */
/*0300*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000ee4000c1e1900 */
/*0310*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0320*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x001ee4000c1e1900 */
/*0330*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x008fca0007ffe0ff */
/*0340*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e8000c101904 */
/*0350*/ LDG.E R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x000ee4000c1e1900 */
/*0360*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0370*/ @!P2 LDG.E R13, [R2.64] ; /* 0x00000004020da981 */
/* 0x002ee4000c1e1900 */
/*0380*/ @!P2 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0da810 */
/* 0x008fca0007ffe0ff */
/*0390*/ @!P2 STG.E [R2.64], R13 ; /* 0x0000000d0200a986 */
/* 0x0003e8000c101904 */
/*03a0*/ LDG.E R12, [R4.64+0x14] ; /* 0x00001404040c7981 */
/* 0x000ee4000c1e1900 */
/*03b0*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*03c0*/ @!P2 LDG.E R15, [R2.64] ; /* 0x00000004020fa981 */
/* 0x004ea4000c1e1900 */
/*03d0*/ @!P2 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0fa810 */
/* 0x004fca0007ffe0ff */
/*03e0*/ @!P2 STG.E [R2.64], R15 ; /* 0x0000000f0200a986 */
/* 0x0005e8000c101904 */
/*03f0*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000ee4000c1e1900 */
/*0400*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0410*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x001ee4000c1e1900 */
/*0420*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x008fca0007ffe0ff */
/*0430*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e8000c101904 */
/*0440*/ LDG.E R12, [R4.64+0x1c] ; /* 0x00001c04040c7981 */
/* 0x000ee4000c1e1900 */
/*0450*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0460*/ @!P2 LDG.E R13, [R2.64] ; /* 0x00000004020da981 */
/* 0x002ee4000c1e1900 */
/*0470*/ @!P2 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0da810 */
/* 0x008fca0007ffe0ff */
/*0480*/ @!P2 STG.E [R2.64], R13 ; /* 0x0000000d0200a986 */
/* 0x0003e8000c101904 */
/*0490*/ LDG.E R12, [R4.64+0x20] ; /* 0x00002004040c7981 */
/* 0x000ee4000c1e1900 */
/*04a0*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*04b0*/ @!P2 LDG.E R15, [R2.64] ; /* 0x00000004020fa981 */
/* 0x004ea4000c1e1900 */
/*04c0*/ @!P2 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0fa810 */
/* 0x004fca0007ffe0ff */
/*04d0*/ @!P2 STG.E [R2.64], R15 ; /* 0x0000000f0200a986 */
/* 0x0005e8000c101904 */
/*04e0*/ LDG.E R12, [R4.64+0x24] ; /* 0x00002404040c7981 */
/* 0x000ee4000c1e1900 */
/*04f0*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0500*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x001ee4000c1e1900 */
/*0510*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x008fca0007ffe0ff */
/*0520*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e8000c101904 */
/*0530*/ LDG.E R12, [R4.64+0x28] ; /* 0x00002804040c7981 */
/* 0x000ee4000c1e1900 */
/*0540*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0550*/ @!P2 LDG.E R13, [R2.64] ; /* 0x00000004020da981 */
/* 0x002ee4000c1e1900 */
/*0560*/ @!P2 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0da810 */
/* 0x008fca0007ffe0ff */
/*0570*/ @!P2 STG.E [R2.64], R13 ; /* 0x0000000d0200a986 */
/* 0x0003e8000c101904 */
/*0580*/ LDG.E R12, [R4.64+0x2c] ; /* 0x00002c04040c7981 */
/* 0x000ee4000c1e1900 */
/*0590*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*05a0*/ @!P2 LDG.E R15, [R2.64] ; /* 0x00000004020fa981 */
/* 0x004ea4000c1e1900 */
/*05b0*/ @!P2 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0fa810 */
/* 0x004fca0007ffe0ff */
/*05c0*/ @!P2 STG.E [R2.64], R15 ; /* 0x0000000f0200a986 */
/* 0x0005e8000c101904 */
/*05d0*/ LDG.E R12, [R4.64+0x30] ; /* 0x00003004040c7981 */
/* 0x000ee4000c1e1900 */
/*05e0*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*05f0*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x001ee4000c1e1900 */
/*0600*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x008fca0007ffe0ff */
/*0610*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e8000c101904 */
/*0620*/ LDG.E R12, [R4.64+0x34] ; /* 0x00003404040c7981 */
/* 0x000ee4000c1e1900 */
/*0630*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0640*/ @!P2 LDG.E R13, [R2.64] ; /* 0x00000004020da981 */
/* 0x002ee4000c1e1900 */
/*0650*/ @!P2 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0da810 */
/* 0x008fca0007ffe0ff */
/*0660*/ @!P2 STG.E [R2.64], R13 ; /* 0x0000000d0200a986 */
/* 0x0003e8000c101904 */
/*0670*/ LDG.E R12, [R4.64+0x38] ; /* 0x00003804040c7981 */
/* 0x000ee4000c1e1900 */
/*0680*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0690*/ @!P2 LDG.E R15, [R2.64] ; /* 0x00000004020fa981 */
/* 0x004ea4000c1e1900 */
/*06a0*/ @!P2 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0fa810 */
/* 0x004fca0007ffe0ff */
/*06b0*/ @!P2 STG.E [R2.64], R15 ; /* 0x0000000f0200a986 */
/* 0x0003e8000c101904 */
/*06c0*/ LDG.E R12, [R4.64+0x3c] ; /* 0x00003c04040c7981 */
/* 0x000ea4000c1e1900 */
/*06d0*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f45270 */
/*06e0*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x001ea2000c1e1900 */
/*06f0*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe40007ffe0ff */
/*0700*/ IADD3 R4, P3, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x000fe40007f7e0ff */
/*0710*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fc60007ffe0ff */
/*0720*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe200018e0605 */
/*0730*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x004fca0007ffe0ff */
/*0740*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0003e2000c101904 */
/*0750*/ ISETP.GT.AND P2, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fda0003f44270 */
/*0760*/ @P2 BRA 0x210 ; /* 0xfffffaa000002947 */
/* 0x002fea000383ffff */
/*0770*/ ISETP.GT.AND P2, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f44270 */
/*0780*/ @!P2 BRA 0xaa0 ; /* 0x000003100000a947 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea4000c1e1900 */
/*07a0*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f05270 */
/*07b0*/ @!P0 LDG.E R11, [R2.64] ; /* 0x00000004020b8981 */
/* 0x000ea4000c1e1900 */
/*07c0*/ @!P0 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b8810 */
/* 0x004fca0007ffe0ff */
/*07d0*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0001e8000c101904 */
/*07e0*/ LDG.E R12, [R4.64+0x4] ; /* 0x00000404040c7981 */
/* 0x000ea4000c1e1900 */
/*07f0*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f05270 */
/*0800*/ @!P0 LDG.E R13, [R2.64] ; /* 0x00000004020d8981 */
/* 0x000ea4000c1e1900 */
/*0810*/ @!P0 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d8810 */
/* 0x004fca0007ffe0ff */
/*0820*/ @!P0 STG.E [R2.64], R13 ; /* 0x0000000d02008986 */
/* 0x0003e8000c101904 */
/*0830*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ea4000c1e1900 */
/*0840*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f05270 */
/*0850*/ @!P0 LDG.E R15, [R2.64] ; /* 0x00000004020f8981 */
/* 0x000ea4000c1e1900 */
/*0860*/ @!P0 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f8810 */
/* 0x004fca0007ffe0ff */
/*0870*/ @!P0 STG.E [R2.64], R15 ; /* 0x0000000f02008986 */
/* 0x0005e8000c101904 */
/*0880*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000ee4000c1e1900 */
/*0890*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f05270 */
/*08a0*/ @!P0 LDG.E R11, [R2.64] ; /* 0x00000004020b8981 */
/* 0x001ee4000c1e1900 */
/*08b0*/ @!P0 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b8810 */
/* 0x008fca0007ffe0ff */
/*08c0*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0001e8000c101904 */
/*08d0*/ LDG.E R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x000ee4000c1e1900 */
/*08e0*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f05270 */
/*08f0*/ @!P0 LDG.E R14, [R2.64] ; /* 0x00000004020e8981 */
/* 0x000ea2000c1e1900 */
/*0900*/ IADD3 R12, P2, R4, 0x10, RZ ; /* 0x00000010040c7810 */
/* 0x000fca0007f5e0ff */
/*0910*/ IMAD.X R13, RZ, RZ, R5, P2 ; /* 0x000000ffff0d7224 */
/* 0x002fe200010e0605 */
/*0920*/ @!P0 IADD3 R15, R14, 0x1, RZ ; /* 0x000000010e0f8810 */
/* 0x004fca0007ffe0ff */
/*0930*/ @!P0 STG.E [R2.64], R15 ; /* 0x0000000f02008986 */
/* 0x0003e8000c101904 */
/*0940*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ea4000c1e1900 */
/*0950*/ ISETP.NE.AND P0, PT, R14, R7, PT ; /* 0x000000070e00720c */
/* 0x004fda0003f05270 */
/*0960*/ @!P0 LDG.E R14, [R2.64] ; /* 0x00000004020e8981 */
/* 0x000e24000c1e1900 */
/*0970*/ @!P0 IADD3 R11, R14, 0x1, RZ ; /* 0x000000010e0b8810 */
/* 0x001fca0007ffe0ff */
/*0980*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x000fe8000c101904 */
/*0990*/ LDG.E R4, [R12.64+0x8] ; /* 0x000008040c047981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ ISETP.NE.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fda0003f05270 */
/*09b0*/ @!P0 LDG.E R5, [R2.64] ; /* 0x0000000402058981 */
/* 0x000ea4000c1e1900 */
/*09c0*/ @!P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105058810 */
/* 0x004fca0007ffe0ff */
/*09d0*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e8000c101904 */
/*09e0*/ LDG.E R4, [R12.64+0xc] ; /* 0x00000c040c047981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ ISETP.NE.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fda0003f05270 */
/*0a00*/ @!P0 LDG.E R15, [R2.64] ; /* 0x00000004020f8981 */
/* 0x002ea2000c1e1900 */
/*0a10*/ IADD3 R4, P2, R12, 0x10, RZ ; /* 0x000000100c047810 */
/* 0x000fe40007f5e0ff */
/*0a20*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*0a30*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ IMAD.X R5, RZ, RZ, R13, P2 ; /* 0x000000ffff057224 */
/* 0x001fe200010e060d */
/*0a50*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*0a60*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ @!P0 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f8810 */
/* 0x004fca0007ffe0ff */
/*0a80*/ @!P0 STG.E [R2.64], R15 ; /* 0x0000000f02008986 */
/* 0x0001e2000c101904 */
/*0a90*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0aa0*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0ab0*/ @!P0 BRA 0xc60 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea4000c1e1900 */
/*0ad0*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f05270 */
/*0ae0*/ @!P0 LDG.E R11, [R2.64] ; /* 0x00000004020b8981 */
/* 0x000ea4000c1e1900 */
/*0af0*/ @!P0 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b8810 */
/* 0x004fca0007ffe0ff */
/*0b00*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0003e8000c101904 */
/*0b10*/ LDG.E R12, [R4.64+0x4] ; /* 0x00000404040c7981 */
/* 0x000ea4000c1e1900 */
/*0b20*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f05270 */
/*0b30*/ @!P0 LDG.E R13, [R2.64] ; /* 0x00000004020d8981 */
/* 0x000ea4000c1e1900 */
/*0b40*/ @!P0 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d8810 */
/* 0x004fca0007ffe0ff */
/*0b50*/ @!P0 STG.E [R2.64], R13 ; /* 0x0000000d02008986 */
/* 0x0005e8000c101904 */
/*0b60*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ee4000c1e1900 */
/*0b70*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f05270 */
/*0b80*/ @!P0 LDG.E R15, [R2.64] ; /* 0x00000004020f8981 */
/* 0x001ee4000c1e1900 */
/*0b90*/ @!P0 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f8810 */
/* 0x008fca0007ffe0ff */
/*0ba0*/ @!P0 STG.E [R2.64], R15 ; /* 0x0000000f02008986 */
/* 0x0005e8000c101904 */
/*0bb0*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000ee4000c1e1900 */
/*0bc0*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f05270 */
/*0bd0*/ @!P0 LDG.E R11, [R2.64] ; /* 0x00000004020b8981 */
/* 0x002ee2000c1e1900 */
/*0be0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ IADD3 R4, P2, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007f5e0ff */
/*0c00*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc60007ffe0ff */
/*0c10*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0c20*/ @!P0 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b8810 */
/* 0x008fca0007ffe0ff */
/*0c30*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0005e2000c101904 */
/*0c40*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0c50*/ @P0 BRA 0xac0 ; /* 0xfffffe6000000947 */
/* 0x004fea000383ffff */
/*0c60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0c70*/ @!P0 BRA 0xe60 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*0c80*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0c90*/ IMAD.WIDE R4, R9, R4, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fca00078e0204 */
/*0ca0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea2000c1e1900 */
/*0cb0*/ BSSY B0, 0xd30 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0cc0*/ ISETP.NE.AND P2, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f45270 */
/*0cd0*/ ISETP.NE.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x004fda0003f05270 */
/*0ce0*/ @P0 BRA 0xd20 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0cf0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea4000c1e1900 */
/*0d00*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x004fca0007ffe0ff */
/*0d10*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e4000c101904 */
/*0d20*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d30*/ BSSY B0, 0xe60 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0d40*/ @!P2 BRA 0xe50 ; /* 0x000001000000a947 */
/* 0x000fea0003800000 */
/*0d50*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea2000c1e1900 */
/*0d60*/ BSSY B1, 0xde0 ; /* 0x0000007000017945 */
/* 0x000fe20003800000 */
/*0d70*/ ISETP.NE.AND P2, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fe40003f45270 */
/*0d80*/ ISETP.NE.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x004fda0003f05270 */
/*0d90*/ @P0 BRA 0xdd0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0da0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x002ea4000c1e1900 */
/*0db0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x004fca0007ffe0ff */
/*0dc0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e4000c101904 */
/*0dd0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0de0*/ @!P2 BRA 0xe50 ; /* 0x000000600000a947 */
/* 0x000fea0003800000 */
/*0df0*/ LDG.E R4, [R4.64+0x8] ; /* 0x0000080404047981 */
/* 0x000ea4000c1e1900 */
/*0e00*/ ISETP.NE.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fda0003f05270 */
/*0e10*/ @P0 BRA 0xe50 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0e20*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*0e30*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x004fca0007ffe0ff */
/*0e40*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0005e4000c101904 */
/*0e50*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0e60*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x007fc800078e00ff */
/*0e70*/ IMAD R7, R2, c[0x0][0xc], R7 ; /* 0x0000030002077a24 */
/* 0x000fca00078e0207 */
/*0e80*/ ISETP.GE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06270 */
/*0e90*/ @P0 CALL.REL.NOINC 0xeb0 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0ea0*/ BRA 0x130 ; /* 0xfffff28000007947 */
/* 0x000fea000383ffff */
/*0eb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ec0*/ BRA 0xec0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void count_spikes(const double *Params, const int *id, int *nsp){
int tid, tind, bid, ind, Nspikes, Nfilters, Nthreads, Nblocks;
Nspikes = (int) Params[0];
Nfilters = (int) Params[2];
tid = threadIdx.x;
bid = blockIdx.x;
Nthreads = blockDim.x;
Nblocks = gridDim.x;
tind = tid + Nthreads *bid;
while (tind<Nfilters){
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==tind)
nsp[tind] += 1;
tind += Nthreads * Nblocks;
}
} | .file "tmpxft_0019b919_00000000-6_count_spikes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12count_spikesPKdPKiPiPKdPKiPi
.type _Z38__device_stub__Z12count_spikesPKdPKiPiPKdPKiPi, @function
_Z38__device_stub__Z12count_spikesPKdPKiPiPKdPKiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12count_spikesPKdPKiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12count_spikesPKdPKiPiPKdPKiPi, .-_Z38__device_stub__Z12count_spikesPKdPKiPiPKdPKiPi
.globl _Z12count_spikesPKdPKiPi
.type _Z12count_spikesPKdPKiPi, @function
_Z12count_spikesPKdPKiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12count_spikesPKdPKiPiPKdPKiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12count_spikesPKdPKiPi, .-_Z12count_spikesPKdPKiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12count_spikesPKdPKiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12count_spikesPKdPKiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void count_spikes(const double *Params, const int *id, int *nsp){
int tid, tind, bid, ind, Nspikes, Nfilters, Nthreads, Nblocks;
Nspikes = (int) Params[0];
Nfilters = (int) Params[2];
tid = threadIdx.x;
bid = blockIdx.x;
Nthreads = blockDim.x;
Nblocks = gridDim.x;
tind = tid + Nthreads *bid;
while (tind<Nfilters){
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==tind)
nsp[tind] += 1;
tind += Nthreads * Nblocks;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void count_spikes(const double *Params, const int *id, int *nsp){
int tid, tind, bid, ind, Nspikes, Nfilters, Nthreads, Nblocks;
Nspikes = (int) Params[0];
Nfilters = (int) Params[2];
tid = threadIdx.x;
bid = blockIdx.x;
Nthreads = blockDim.x;
Nblocks = gridDim.x;
tind = tid + Nthreads *bid;
while (tind<Nfilters){
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==tind)
nsp[tind] += 1;
tind += Nthreads * Nblocks;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void count_spikes(const double *Params, const int *id, int *nsp){
int tid, tind, bid, ind, Nspikes, Nfilters, Nthreads, Nblocks;
Nspikes = (int) Params[0];
Nfilters = (int) Params[2];
tid = threadIdx.x;
bid = blockIdx.x;
Nthreads = blockDim.x;
Nblocks = gridDim.x;
tind = tid + Nthreads *bid;
while (tind<Nfilters){
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==tind)
nsp[tind] += 1;
tind += Nthreads * Nblocks;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12count_spikesPKdPKiPi
.globl _Z12count_spikesPKdPKiPi
.p2align 8
.type _Z12count_spikesPKdPKiPi,@function
_Z12count_spikesPKdPKiPi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[2:3], 0x10
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v4, s[4:5]
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_and_b32 s8, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v1, v4
s_cbranch_execz .LBB0_8
s_load_b64 s[2:3], s[2:3], 0x0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v0, s[2:3]
s_load_b32 s2, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s2, s8
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e64 s0, 0, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v1, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v1, v4
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_8
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, v0
s_mov_b64 s[2:3], s[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v6, -1, v6
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v6
s_cbranch_vccz .LBB0_2
.LBB0_6:
global_load_b32 v7, v5, s[2:3]
s_mov_b32 s9, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v7, v1
s_cbranch_execz .LBB0_5
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, 1, v7
global_store_b32 v[2:3], v7, off
s_branch .LBB0_5
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12count_spikesPKdPKiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12count_spikesPKdPKiPi, .Lfunc_end0-_Z12count_spikesPKdPKiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12count_spikesPKdPKiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12count_spikesPKdPKiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void count_spikes(const double *Params, const int *id, int *nsp){
int tid, tind, bid, ind, Nspikes, Nfilters, Nthreads, Nblocks;
Nspikes = (int) Params[0];
Nfilters = (int) Params[2];
tid = threadIdx.x;
bid = blockIdx.x;
Nthreads = blockDim.x;
Nblocks = gridDim.x;
tind = tid + Nthreads *bid;
while (tind<Nfilters){
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==tind)
nsp[tind] += 1;
tind += Nthreads * Nblocks;
}
} | .text
.file "count_spikes.hip"
.globl _Z27__device_stub__count_spikesPKdPKiPi # -- Begin function _Z27__device_stub__count_spikesPKdPKiPi
.p2align 4, 0x90
.type _Z27__device_stub__count_spikesPKdPKiPi,@function
_Z27__device_stub__count_spikesPKdPKiPi: # @_Z27__device_stub__count_spikesPKdPKiPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12count_spikesPKdPKiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__count_spikesPKdPKiPi, .Lfunc_end0-_Z27__device_stub__count_spikesPKdPKiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12count_spikesPKdPKiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12count_spikesPKdPKiPi,@object # @_Z12count_spikesPKdPKiPi
.section .rodata,"a",@progbits
.globl _Z12count_spikesPKdPKiPi
.p2align 3, 0x0
_Z12count_spikesPKdPKiPi:
.quad _Z27__device_stub__count_spikesPKdPKiPi
.size _Z12count_spikesPKdPKiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12count_spikesPKdPKiPi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__count_spikesPKdPKiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12count_spikesPKdPKiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12count_spikesPKdPKiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64 R4, [R2.64+0x10] ; /* 0x0000100402047981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0060*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R6 ; /* 0x0000000007077a24 */
/* 0x001fe200078e0206 */
/*0080*/ F2I.F64.TRUNC R0, R4 ; /* 0x0000000400007311 */
/* 0x004e28000030d100 */
/*0090*/ ISETP.GE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x001fda0003f06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1b00 */
/*00c0*/ F2I.F64.TRUNC R5, R2 ; /* 0x0000000200057311 */
/* 0x004e24000030d100 */
/*00d0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x001fda0003f06270 */
/*00e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00f0*/ LOP3.LUT R6, R5.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305067812 */
/* 0x040fe400078ec0ff */
/*0100*/ IADD3 R2, R5, -0x1, RZ ; /* 0xffffffff05027810 */
/* 0x000fc60007ffe0ff */
/*0110*/ IMAD.IADD R8, R5, 0x1, -R6 ; /* 0x0000000105087824 */
/* 0x000fe200078e0a06 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fd00003f26070 */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.WIDE R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fe200078e0202 */
/*0160*/ @!P1 BRA 0xc60 ; /* 0x00000af000009947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0180*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0008 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fc400078e00ff */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fcc00078e00ff */
/*01c0*/ @!P0 BRA 0xac0 ; /* 0x000008f000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P2, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f44270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P2 BRA 0x770 ; /* 0x000005700000a947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f45270 */
/*0230*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x000ea4000c1e1900 */
/*0240*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x004fca0007ffe0ff */
/*0250*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e8000c101904 */
/*0260*/ LDG.E R12, [R4.64+0x4] ; /* 0x00000404040c7981 */
/* 0x000ea4000c1e1900 */
/*0270*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f45270 */
/*0280*/ @!P2 LDG.E R13, [R2.64] ; /* 0x00000004020da981 */
/* 0x000ea4000c1e1900 */
/*0290*/ @!P2 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0da810 */
/* 0x004fca0007ffe0ff */
/*02a0*/ @!P2 STG.E [R2.64], R13 ; /* 0x0000000d0200a986 */
/* 0x0003e8000c101904 */
/*02b0*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f45270 */
/*02d0*/ @!P2 LDG.E R15, [R2.64] ; /* 0x00000004020fa981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ @!P2 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0fa810 */
/* 0x004fca0007ffe0ff */
/*02f0*/ @!P2 STG.E [R2.64], R15 ; /* 0x0000000f0200a986 */
/* 0x0005e8000c101904 */
/*0300*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000ee4000c1e1900 */
/*0310*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0320*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x001ee4000c1e1900 */
/*0330*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x008fca0007ffe0ff */
/*0340*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e8000c101904 */
/*0350*/ LDG.E R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x000ee4000c1e1900 */
/*0360*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0370*/ @!P2 LDG.E R13, [R2.64] ; /* 0x00000004020da981 */
/* 0x002ee4000c1e1900 */
/*0380*/ @!P2 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0da810 */
/* 0x008fca0007ffe0ff */
/*0390*/ @!P2 STG.E [R2.64], R13 ; /* 0x0000000d0200a986 */
/* 0x0003e8000c101904 */
/*03a0*/ LDG.E R12, [R4.64+0x14] ; /* 0x00001404040c7981 */
/* 0x000ee4000c1e1900 */
/*03b0*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*03c0*/ @!P2 LDG.E R15, [R2.64] ; /* 0x00000004020fa981 */
/* 0x004ea4000c1e1900 */
/*03d0*/ @!P2 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0fa810 */
/* 0x004fca0007ffe0ff */
/*03e0*/ @!P2 STG.E [R2.64], R15 ; /* 0x0000000f0200a986 */
/* 0x0005e8000c101904 */
/*03f0*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000ee4000c1e1900 */
/*0400*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0410*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x001ee4000c1e1900 */
/*0420*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x008fca0007ffe0ff */
/*0430*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e8000c101904 */
/*0440*/ LDG.E R12, [R4.64+0x1c] ; /* 0x00001c04040c7981 */
/* 0x000ee4000c1e1900 */
/*0450*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0460*/ @!P2 LDG.E R13, [R2.64] ; /* 0x00000004020da981 */
/* 0x002ee4000c1e1900 */
/*0470*/ @!P2 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0da810 */
/* 0x008fca0007ffe0ff */
/*0480*/ @!P2 STG.E [R2.64], R13 ; /* 0x0000000d0200a986 */
/* 0x0003e8000c101904 */
/*0490*/ LDG.E R12, [R4.64+0x20] ; /* 0x00002004040c7981 */
/* 0x000ee4000c1e1900 */
/*04a0*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*04b0*/ @!P2 LDG.E R15, [R2.64] ; /* 0x00000004020fa981 */
/* 0x004ea4000c1e1900 */
/*04c0*/ @!P2 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0fa810 */
/* 0x004fca0007ffe0ff */
/*04d0*/ @!P2 STG.E [R2.64], R15 ; /* 0x0000000f0200a986 */
/* 0x0005e8000c101904 */
/*04e0*/ LDG.E R12, [R4.64+0x24] ; /* 0x00002404040c7981 */
/* 0x000ee4000c1e1900 */
/*04f0*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0500*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x001ee4000c1e1900 */
/*0510*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x008fca0007ffe0ff */
/*0520*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e8000c101904 */
/*0530*/ LDG.E R12, [R4.64+0x28] ; /* 0x00002804040c7981 */
/* 0x000ee4000c1e1900 */
/*0540*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0550*/ @!P2 LDG.E R13, [R2.64] ; /* 0x00000004020da981 */
/* 0x002ee4000c1e1900 */
/*0560*/ @!P2 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0da810 */
/* 0x008fca0007ffe0ff */
/*0570*/ @!P2 STG.E [R2.64], R13 ; /* 0x0000000d0200a986 */
/* 0x0003e8000c101904 */
/*0580*/ LDG.E R12, [R4.64+0x2c] ; /* 0x00002c04040c7981 */
/* 0x000ee4000c1e1900 */
/*0590*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*05a0*/ @!P2 LDG.E R15, [R2.64] ; /* 0x00000004020fa981 */
/* 0x004ea4000c1e1900 */
/*05b0*/ @!P2 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0fa810 */
/* 0x004fca0007ffe0ff */
/*05c0*/ @!P2 STG.E [R2.64], R15 ; /* 0x0000000f0200a986 */
/* 0x0005e8000c101904 */
/*05d0*/ LDG.E R12, [R4.64+0x30] ; /* 0x00003004040c7981 */
/* 0x000ee4000c1e1900 */
/*05e0*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*05f0*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x001ee4000c1e1900 */
/*0600*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x008fca0007ffe0ff */
/*0610*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e8000c101904 */
/*0620*/ LDG.E R12, [R4.64+0x34] ; /* 0x00003404040c7981 */
/* 0x000ee4000c1e1900 */
/*0630*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0640*/ @!P2 LDG.E R13, [R2.64] ; /* 0x00000004020da981 */
/* 0x002ee4000c1e1900 */
/*0650*/ @!P2 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0da810 */
/* 0x008fca0007ffe0ff */
/*0660*/ @!P2 STG.E [R2.64], R13 ; /* 0x0000000d0200a986 */
/* 0x0003e8000c101904 */
/*0670*/ LDG.E R12, [R4.64+0x38] ; /* 0x00003804040c7981 */
/* 0x000ee4000c1e1900 */
/*0680*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f45270 */
/*0690*/ @!P2 LDG.E R15, [R2.64] ; /* 0x00000004020fa981 */
/* 0x004ea4000c1e1900 */
/*06a0*/ @!P2 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0fa810 */
/* 0x004fca0007ffe0ff */
/*06b0*/ @!P2 STG.E [R2.64], R15 ; /* 0x0000000f0200a986 */
/* 0x0003e8000c101904 */
/*06c0*/ LDG.E R12, [R4.64+0x3c] ; /* 0x00003c04040c7981 */
/* 0x000ea4000c1e1900 */
/*06d0*/ ISETP.NE.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f45270 */
/*06e0*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x001ea2000c1e1900 */
/*06f0*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe40007ffe0ff */
/*0700*/ IADD3 R4, P3, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x000fe40007f7e0ff */
/*0710*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fc60007ffe0ff */
/*0720*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe200018e0605 */
/*0730*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x004fca0007ffe0ff */
/*0740*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0003e2000c101904 */
/*0750*/ ISETP.GT.AND P2, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fda0003f44270 */
/*0760*/ @P2 BRA 0x210 ; /* 0xfffffaa000002947 */
/* 0x002fea000383ffff */
/*0770*/ ISETP.GT.AND P2, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f44270 */
/*0780*/ @!P2 BRA 0xaa0 ; /* 0x000003100000a947 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea4000c1e1900 */
/*07a0*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f05270 */
/*07b0*/ @!P0 LDG.E R11, [R2.64] ; /* 0x00000004020b8981 */
/* 0x000ea4000c1e1900 */
/*07c0*/ @!P0 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b8810 */
/* 0x004fca0007ffe0ff */
/*07d0*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0001e8000c101904 */
/*07e0*/ LDG.E R12, [R4.64+0x4] ; /* 0x00000404040c7981 */
/* 0x000ea4000c1e1900 */
/*07f0*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f05270 */
/*0800*/ @!P0 LDG.E R13, [R2.64] ; /* 0x00000004020d8981 */
/* 0x000ea4000c1e1900 */
/*0810*/ @!P0 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d8810 */
/* 0x004fca0007ffe0ff */
/*0820*/ @!P0 STG.E [R2.64], R13 ; /* 0x0000000d02008986 */
/* 0x0003e8000c101904 */
/*0830*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ea4000c1e1900 */
/*0840*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f05270 */
/*0850*/ @!P0 LDG.E R15, [R2.64] ; /* 0x00000004020f8981 */
/* 0x000ea4000c1e1900 */
/*0860*/ @!P0 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f8810 */
/* 0x004fca0007ffe0ff */
/*0870*/ @!P0 STG.E [R2.64], R15 ; /* 0x0000000f02008986 */
/* 0x0005e8000c101904 */
/*0880*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000ee4000c1e1900 */
/*0890*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f05270 */
/*08a0*/ @!P0 LDG.E R11, [R2.64] ; /* 0x00000004020b8981 */
/* 0x001ee4000c1e1900 */
/*08b0*/ @!P0 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b8810 */
/* 0x008fca0007ffe0ff */
/*08c0*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0001e8000c101904 */
/*08d0*/ LDG.E R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x000ee4000c1e1900 */
/*08e0*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f05270 */
/*08f0*/ @!P0 LDG.E R14, [R2.64] ; /* 0x00000004020e8981 */
/* 0x000ea2000c1e1900 */
/*0900*/ IADD3 R12, P2, R4, 0x10, RZ ; /* 0x00000010040c7810 */
/* 0x000fca0007f5e0ff */
/*0910*/ IMAD.X R13, RZ, RZ, R5, P2 ; /* 0x000000ffff0d7224 */
/* 0x002fe200010e0605 */
/*0920*/ @!P0 IADD3 R15, R14, 0x1, RZ ; /* 0x000000010e0f8810 */
/* 0x004fca0007ffe0ff */
/*0930*/ @!P0 STG.E [R2.64], R15 ; /* 0x0000000f02008986 */
/* 0x0003e8000c101904 */
/*0940*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ea4000c1e1900 */
/*0950*/ ISETP.NE.AND P0, PT, R14, R7, PT ; /* 0x000000070e00720c */
/* 0x004fda0003f05270 */
/*0960*/ @!P0 LDG.E R14, [R2.64] ; /* 0x00000004020e8981 */
/* 0x000e24000c1e1900 */
/*0970*/ @!P0 IADD3 R11, R14, 0x1, RZ ; /* 0x000000010e0b8810 */
/* 0x001fca0007ffe0ff */
/*0980*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x000fe8000c101904 */
/*0990*/ LDG.E R4, [R12.64+0x8] ; /* 0x000008040c047981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ ISETP.NE.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fda0003f05270 */
/*09b0*/ @!P0 LDG.E R5, [R2.64] ; /* 0x0000000402058981 */
/* 0x000ea4000c1e1900 */
/*09c0*/ @!P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105058810 */
/* 0x004fca0007ffe0ff */
/*09d0*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e8000c101904 */
/*09e0*/ LDG.E R4, [R12.64+0xc] ; /* 0x00000c040c047981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ ISETP.NE.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fda0003f05270 */
/*0a00*/ @!P0 LDG.E R15, [R2.64] ; /* 0x00000004020f8981 */
/* 0x002ea2000c1e1900 */
/*0a10*/ IADD3 R4, P2, R12, 0x10, RZ ; /* 0x000000100c047810 */
/* 0x000fe40007f5e0ff */
/*0a20*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*0a30*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ IMAD.X R5, RZ, RZ, R13, P2 ; /* 0x000000ffff057224 */
/* 0x001fe200010e060d */
/*0a50*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*0a60*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ @!P0 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f8810 */
/* 0x004fca0007ffe0ff */
/*0a80*/ @!P0 STG.E [R2.64], R15 ; /* 0x0000000f02008986 */
/* 0x0001e2000c101904 */
/*0a90*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0aa0*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0ab0*/ @!P0 BRA 0xc60 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea4000c1e1900 */
/*0ad0*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f05270 */
/*0ae0*/ @!P0 LDG.E R11, [R2.64] ; /* 0x00000004020b8981 */
/* 0x000ea4000c1e1900 */
/*0af0*/ @!P0 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b8810 */
/* 0x004fca0007ffe0ff */
/*0b00*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0003e8000c101904 */
/*0b10*/ LDG.E R12, [R4.64+0x4] ; /* 0x00000404040c7981 */
/* 0x000ea4000c1e1900 */
/*0b20*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x004fda0003f05270 */
/*0b30*/ @!P0 LDG.E R13, [R2.64] ; /* 0x00000004020d8981 */
/* 0x000ea4000c1e1900 */
/*0b40*/ @!P0 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d8810 */
/* 0x004fca0007ffe0ff */
/*0b50*/ @!P0 STG.E [R2.64], R13 ; /* 0x0000000d02008986 */
/* 0x0005e8000c101904 */
/*0b60*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ee4000c1e1900 */
/*0b70*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f05270 */
/*0b80*/ @!P0 LDG.E R15, [R2.64] ; /* 0x00000004020f8981 */
/* 0x001ee4000c1e1900 */
/*0b90*/ @!P0 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f8810 */
/* 0x008fca0007ffe0ff */
/*0ba0*/ @!P0 STG.E [R2.64], R15 ; /* 0x0000000f02008986 */
/* 0x0005e8000c101904 */
/*0bb0*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000ee4000c1e1900 */
/*0bc0*/ ISETP.NE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x008fda0003f05270 */
/*0bd0*/ @!P0 LDG.E R11, [R2.64] ; /* 0x00000004020b8981 */
/* 0x002ee2000c1e1900 */
/*0be0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ IADD3 R4, P2, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007f5e0ff */
/*0c00*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc60007ffe0ff */
/*0c10*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0c20*/ @!P0 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b8810 */
/* 0x008fca0007ffe0ff */
/*0c30*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0005e2000c101904 */
/*0c40*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0c50*/ @P0 BRA 0xac0 ; /* 0xfffffe6000000947 */
/* 0x004fea000383ffff */
/*0c60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0c70*/ @!P0 BRA 0xe60 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*0c80*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0c90*/ IMAD.WIDE R4, R9, R4, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fca00078e0204 */
/*0ca0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea2000c1e1900 */
/*0cb0*/ BSSY B0, 0xd30 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0cc0*/ ISETP.NE.AND P2, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f45270 */
/*0cd0*/ ISETP.NE.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x004fda0003f05270 */
/*0ce0*/ @P0 BRA 0xd20 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0cf0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea4000c1e1900 */
/*0d00*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x004fca0007ffe0ff */
/*0d10*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e4000c101904 */
/*0d20*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d30*/ BSSY B0, 0xe60 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0d40*/ @!P2 BRA 0xe50 ; /* 0x000001000000a947 */
/* 0x000fea0003800000 */
/*0d50*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea2000c1e1900 */
/*0d60*/ BSSY B1, 0xde0 ; /* 0x0000007000017945 */
/* 0x000fe20003800000 */
/*0d70*/ ISETP.NE.AND P2, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fe40003f45270 */
/*0d80*/ ISETP.NE.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x004fda0003f05270 */
/*0d90*/ @P0 BRA 0xdd0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0da0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x002ea4000c1e1900 */
/*0db0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x004fca0007ffe0ff */
/*0dc0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e4000c101904 */
/*0dd0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0de0*/ @!P2 BRA 0xe50 ; /* 0x000000600000a947 */
/* 0x000fea0003800000 */
/*0df0*/ LDG.E R4, [R4.64+0x8] ; /* 0x0000080404047981 */
/* 0x000ea4000c1e1900 */
/*0e00*/ ISETP.NE.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fda0003f05270 */
/*0e10*/ @P0 BRA 0xe50 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0e20*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*0e30*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x004fca0007ffe0ff */
/*0e40*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0005e4000c101904 */
/*0e50*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0e60*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x007fc800078e00ff */
/*0e70*/ IMAD R7, R2, c[0x0][0xc], R7 ; /* 0x0000030002077a24 */
/* 0x000fca00078e0207 */
/*0e80*/ ISETP.GE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06270 */
/*0e90*/ @P0 CALL.REL.NOINC 0xeb0 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0ea0*/ BRA 0x130 ; /* 0xfffff28000007947 */
/* 0x000fea000383ffff */
/*0eb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ec0*/ BRA 0xec0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12count_spikesPKdPKiPi
.globl _Z12count_spikesPKdPKiPi
.p2align 8
.type _Z12count_spikesPKdPKiPi,@function
_Z12count_spikesPKdPKiPi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[2:3], 0x10
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v4, s[4:5]
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_and_b32 s8, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v1, v4
s_cbranch_execz .LBB0_8
s_load_b64 s[2:3], s[2:3], 0x0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v0, s[2:3]
s_load_b32 s2, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s2, s8
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e64 s0, 0, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v1, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v1, v4
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_8
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, v0
s_mov_b64 s[2:3], s[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v6, -1, v6
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v6
s_cbranch_vccz .LBB0_2
.LBB0_6:
global_load_b32 v7, v5, s[2:3]
s_mov_b32 s9, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v7, v1
s_cbranch_execz .LBB0_5
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, 1, v7
global_store_b32 v[2:3], v7, off
s_branch .LBB0_5
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12count_spikesPKdPKiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12count_spikesPKdPKiPi, .Lfunc_end0-_Z12count_spikesPKdPKiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12count_spikesPKdPKiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12count_spikesPKdPKiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019b919_00000000-6_count_spikes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12count_spikesPKdPKiPiPKdPKiPi
.type _Z38__device_stub__Z12count_spikesPKdPKiPiPKdPKiPi, @function
_Z38__device_stub__Z12count_spikesPKdPKiPiPKdPKiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12count_spikesPKdPKiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12count_spikesPKdPKiPiPKdPKiPi, .-_Z38__device_stub__Z12count_spikesPKdPKiPiPKdPKiPi
.globl _Z12count_spikesPKdPKiPi
.type _Z12count_spikesPKdPKiPi, @function
_Z12count_spikesPKdPKiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12count_spikesPKdPKiPiPKdPKiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12count_spikesPKdPKiPi, .-_Z12count_spikesPKdPKiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12count_spikesPKdPKiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12count_spikesPKdPKiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "count_spikes.hip"
.globl _Z27__device_stub__count_spikesPKdPKiPi # -- Begin function _Z27__device_stub__count_spikesPKdPKiPi
.p2align 4, 0x90
.type _Z27__device_stub__count_spikesPKdPKiPi,@function
_Z27__device_stub__count_spikesPKdPKiPi: # @_Z27__device_stub__count_spikesPKdPKiPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12count_spikesPKdPKiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__count_spikesPKdPKiPi, .Lfunc_end0-_Z27__device_stub__count_spikesPKdPKiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12count_spikesPKdPKiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12count_spikesPKdPKiPi,@object # @_Z12count_spikesPKdPKiPi
.section .rodata,"a",@progbits
.globl _Z12count_spikesPKdPKiPi
.p2align 3, 0x0
_Z12count_spikesPKdPKiPi:
.quad _Z27__device_stub__count_spikesPKdPKiPi
.size _Z12count_spikesPKdPKiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12count_spikesPKdPKiPi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__count_spikesPKdPKiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12count_spikesPKdPKiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cstdlib>
#include <cuda_runtime_api.h>
int main(int argc, char *argv[])
{
cudaDeviceProp prop;
cudaError_t status;
int device_count;
int min_v = 0;
status = cudaGetDeviceCount(&device_count);
if (status != cudaSuccess) {
fprintf(stderr,"cudaGetDeviceCount() failed: %s\n", cudaGetErrorString(status));
return -1;
}
for(int device_index=0; device_index < device_count; ++device_index){
status = cudaGetDeviceProperties(&prop, device_index);
if (status != cudaSuccess) {
fprintf(stderr,"cudaGetDeviceProperties() for device %i failed: %s\n", device_index, cudaGetErrorString(status));
return -1;
}
int v = prop.major * 10 + prop.minor;
if(min_v < v) min_v = v;
}
return min_v;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cstdlib>
#include <cuda_runtime_api.h>
int main(int argc, char *argv[])
{
cudaDeviceProp prop;
cudaError_t status;
int device_count;
int min_v = 0;
status = cudaGetDeviceCount(&device_count);
if (status != cudaSuccess) {
fprintf(stderr,"cudaGetDeviceCount() failed: %s\n", cudaGetErrorString(status));
return -1;
}
for(int device_index=0; device_index < device_count; ++device_index){
status = cudaGetDeviceProperties(&prop, device_index);
if (status != cudaSuccess) {
fprintf(stderr,"cudaGetDeviceProperties() for device %i failed: %s\n", device_index, cudaGetErrorString(status));
return -1;
}
int v = prop.major * 10 + prop.minor;
if(min_v < v) min_v = v;
}
return min_v;
} | .file "tmpxft_001672f8_00000000-6_get_cuda_sm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaGetDeviceCount() failed: %s\n"
.align 8
.LC1:
.string "cudaGetDeviceProperties() for device %i failed: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L4
movl $0, %ebx
movl $0, %ebp
leaq 16(%rsp), %r12
cmpl $0, 12(%rsp)
jle .L3
.L5:
movl %ebx, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L13
movl 376(%rsp), %eax
leal (%rax,%rax,4), %edx
movl 380(%rsp), %eax
leal (%rax,%rdx,2), %eax
cmpl %eax, %ebp
cmovl %eax, %ebp
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
jmp .L3
.L4:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %ebp
jmp .L3
.L13:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %ebp
.L3:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L14
movl %ebp, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cstdlib>
#include <cuda_runtime_api.h>
int main(int argc, char *argv[])
{
cudaDeviceProp prop;
cudaError_t status;
int device_count;
int min_v = 0;
status = cudaGetDeviceCount(&device_count);
if (status != cudaSuccess) {
fprintf(stderr,"cudaGetDeviceCount() failed: %s\n", cudaGetErrorString(status));
return -1;
}
for(int device_index=0; device_index < device_count; ++device_index){
status = cudaGetDeviceProperties(&prop, device_index);
if (status != cudaSuccess) {
fprintf(stderr,"cudaGetDeviceProperties() for device %i failed: %s\n", device_index, cudaGetErrorString(status));
return -1;
}
int v = prop.major * 10 + prop.minor;
if(min_v < v) min_v = v;
}
return min_v;
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <hip/hip_runtime_api.h>
int main(int argc, char *argv[])
{
hipDeviceProp_t prop;
hipError_t status;
int device_count;
int min_v = 0;
status = hipGetDeviceCount(&device_count);
if (status != hipSuccess) {
fprintf(stderr,"cudaGetDeviceCount() failed: %s\n", hipGetErrorString(status));
return -1;
}
for(int device_index=0; device_index < device_count; ++device_index){
status = hipGetDeviceProperties(&prop, device_index);
if (status != hipSuccess) {
fprintf(stderr,"cudaGetDeviceProperties() for device %i failed: %s\n", device_index, hipGetErrorString(status));
return -1;
}
int v = prop.major * 10 + prop.minor;
if(min_v < v) min_v = v;
}
return min_v;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <hip/hip_runtime_api.h>
int main(int argc, char *argv[])
{
hipDeviceProp_t prop;
hipError_t status;
int device_count;
int min_v = 0;
status = hipGetDeviceCount(&device_count);
if (status != hipSuccess) {
fprintf(stderr,"cudaGetDeviceCount() failed: %s\n", hipGetErrorString(status));
return -1;
}
for(int device_index=0; device_index < device_count; ++device_index){
status = hipGetDeviceProperties(&prop, device_index);
if (status != hipSuccess) {
fprintf(stderr,"cudaGetDeviceProperties() for device %i failed: %s\n", device_index, hipGetErrorString(status));
return -1;
}
int v = prop.major * 10 + prop.minor;
if(min_v < v) min_v = v;
}
return min_v;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <hip/hip_runtime_api.h>
int main(int argc, char *argv[])
{
hipDeviceProp_t prop;
hipError_t status;
int device_count;
int min_v = 0;
status = hipGetDeviceCount(&device_count);
if (status != hipSuccess) {
fprintf(stderr,"cudaGetDeviceCount() failed: %s\n", hipGetErrorString(status));
return -1;
}
for(int device_index=0; device_index < device_count; ++device_index){
status = hipGetDeviceProperties(&prop, device_index);
if (status != hipSuccess) {
fprintf(stderr,"cudaGetDeviceProperties() for device %i failed: %s\n", device_index, hipGetErrorString(status));
return -1;
}
int v = prop.major * 10 + prop.minor;
if(min_v < v) min_v = v;
}
return min_v;
} | .text
.file "get_cuda_sm.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_3
# %bb.1: # %.preheader
cmpl $0, 12(%rsp)
jle .LBB0_2
# %bb.4: # %.lr.ph
xorl %ebx, %ebx
leaq 16(%rsp), %r14
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_6
# %bb.7: # in Loop: Header=BB0_5 Depth=1
movl 376(%rsp), %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
addl 380(%rsp), %eax
cmpl %eax, %ebp
cmovlel %eax, %ebp
incl %ebx
cmpl 12(%rsp), %ebx
jl .LBB0_5
jmp .LBB0_8
.LBB0_2:
xorl %ebp, %ebp
.LBB0_8: # %.loopexit
movl %ebp, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 1520
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %ebp
jmp .LBB0_8
.LBB0_6:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %r14, %rdi
movl %ebx, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $-1, %ebp
jmp .LBB0_8
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaGetDeviceCount() failed: %s\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cudaGetDeviceProperties() for device %i failed: %s\n"
.size .L.str.1, 52
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001672f8_00000000-6_get_cuda_sm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaGetDeviceCount() failed: %s\n"
.align 8
.LC1:
.string "cudaGetDeviceProperties() for device %i failed: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L4
movl $0, %ebx
movl $0, %ebp
leaq 16(%rsp), %r12
cmpl $0, 12(%rsp)
jle .L3
.L5:
movl %ebx, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L13
movl 376(%rsp), %eax
leal (%rax,%rax,4), %edx
movl 380(%rsp), %eax
leal (%rax,%rdx,2), %eax
cmpl %eax, %ebp
cmovl %eax, %ebp
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
jmp .L3
.L4:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %ebp
jmp .L3
.L13:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %ebp
.L3:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L14
movl %ebp, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "get_cuda_sm.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_3
# %bb.1: # %.preheader
cmpl $0, 12(%rsp)
jle .LBB0_2
# %bb.4: # %.lr.ph
xorl %ebx, %ebx
leaq 16(%rsp), %r14
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_6
# %bb.7: # in Loop: Header=BB0_5 Depth=1
movl 376(%rsp), %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
addl 380(%rsp), %eax
cmpl %eax, %ebp
cmovlel %eax, %ebp
incl %ebx
cmpl 12(%rsp), %ebx
jl .LBB0_5
jmp .LBB0_8
.LBB0_2:
xorl %ebp, %ebp
.LBB0_8: # %.loopexit
movl %ebp, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 1520
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %ebp
jmp .LBB0_8
.LBB0_6:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %r14, %rdi
movl %ebx, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $-1, %ebp
jmp .LBB0_8
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaGetDeviceCount() failed: %s\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cudaGetDeviceProperties() for device %i failed: %s\n"
.size .L.str.1, 52
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void scan_local(float *in, float *out) {
out[0] = in[0];
for (int i = 0; i < 32; i ++) {
out[i] = out[i-1] + in[i];
}
}
int main(void) {
float v[32];
float r[32];
float *dv;
float *dr;
for (int i = 0; i < 32; i ++) {
v[i] = 1.0;
r[i] = 7.0;
}
cudaMalloc((void**)&dv,32*sizeof(float));
cudaMalloc((void**)&dr,32*sizeof(float));
cudaMemcpy(dv,v,32*sizeof(float),cudaMemcpyHostToDevice);
scan_local<<<1,1,0>>>(dv,dr);
cudaMemcpy(r,dr,32*sizeof(float),cudaMemcpyDeviceToHost);
for (int i = 0; i < 32; i ++) {
printf("%f ",r[i]);
}
return 0;
} | code for sm_80
Function : _Z10scan_localPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*0060*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*0070*/ LDG.E R0, [R2.64+-0x4] ; /* 0xfffffc0402007981 */
/* 0x000ee8000c1e1900 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041e8000c101904 */
/*0090*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ee4000c1e1900 */
/*00a0*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x008fca0000000000 */
/*00b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*00c0*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x0005e8000c101904 */
/*00f0*/ LDG.E R0, [R4.64+0x8] ; /* 0x0000080404007981 */
/* 0x000ee4000c1e1900 */
/*0100*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*0110*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x0007e8000c101904 */
/*0120*/ LDG.E R0, [R4.64+0xc] ; /* 0x00000c0404007981 */
/* 0x000e24000c1e1900 */
/*0130*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*0140*/ STG.E [R2.64+0xc], R7 ; /* 0x00000c0702007986 */
/* 0x0001e8000c101904 */
/*0150*/ LDG.E R0, [R4.64+0x10] ; /* 0x0000100404007981 */
/* 0x000e64000c1e1900 */
/*0160*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*0170*/ STG.E [R2.64+0x10], R9 ; /* 0x0000100902007986 */
/* 0x0003e8000c101904 */
/*0180*/ LDG.E R0, [R4.64+0x14] ; /* 0x0000140404007981 */
/* 0x000ea4000c1e1900 */
/*0190*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*01a0*/ STG.E [R2.64+0x14], R11 ; /* 0x0000140b02007986 */
/* 0x0005e8000c101904 */
/*01b0*/ LDG.E R0, [R4.64+0x18] ; /* 0x0000180404007981 */
/* 0x000ee4000c1e1900 */
/*01c0*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*01d0*/ STG.E [R2.64+0x18], R13 ; /* 0x0000180d02007986 */
/* 0x0007e8000c101904 */
/*01e0*/ LDG.E R0, [R4.64+0x1c] ; /* 0x00001c0404007981 */
/* 0x000e24000c1e1900 */
/*01f0*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*0200*/ STG.E [R2.64+0x1c], R7 ; /* 0x00001c0702007986 */
/* 0x0001e8000c101904 */
/*0210*/ LDG.E R0, [R4.64+0x20] ; /* 0x0000200404007981 */
/* 0x000e64000c1e1900 */
/*0220*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*0230*/ STG.E [R2.64+0x20], R9 ; /* 0x0000200902007986 */
/* 0x0003e8000c101904 */
/*0240*/ LDG.E R0, [R4.64+0x24] ; /* 0x0000240404007981 */
/* 0x000ea4000c1e1900 */
/*0250*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*0260*/ STG.E [R2.64+0x24], R11 ; /* 0x0000240b02007986 */
/* 0x0005e8000c101904 */
/*0270*/ LDG.E R0, [R4.64+0x28] ; /* 0x0000280404007981 */
/* 0x000ee4000c1e1900 */
/*0280*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*0290*/ STG.E [R2.64+0x28], R13 ; /* 0x0000280d02007986 */
/* 0x0007e8000c101904 */
/*02a0*/ LDG.E R0, [R4.64+0x2c] ; /* 0x00002c0404007981 */
/* 0x000e24000c1e1900 */
/*02b0*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*02c0*/ STG.E [R2.64+0x2c], R7 ; /* 0x00002c0702007986 */
/* 0x0001e8000c101904 */
/*02d0*/ LDG.E R0, [R4.64+0x30] ; /* 0x0000300404007981 */
/* 0x000e64000c1e1900 */
/*02e0*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*02f0*/ STG.E [R2.64+0x30], R9 ; /* 0x0000300902007986 */
/* 0x0003e8000c101904 */
/*0300*/ LDG.E R0, [R4.64+0x34] ; /* 0x0000340404007981 */
/* 0x000ea4000c1e1900 */
/*0310*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*0320*/ STG.E [R2.64+0x34], R11 ; /* 0x0000340b02007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R0, [R4.64+0x38] ; /* 0x0000380404007981 */
/* 0x000ee4000c1e1900 */
/*0340*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*0350*/ STG.E [R2.64+0x38], R13 ; /* 0x0000380d02007986 */
/* 0x0007e8000c101904 */
/*0360*/ LDG.E R0, [R4.64+0x3c] ; /* 0x00003c0404007981 */
/* 0x000e24000c1e1900 */
/*0370*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*0380*/ STG.E [R2.64+0x3c], R7 ; /* 0x00003c0702007986 */
/* 0x0001e8000c101904 */
/*0390*/ LDG.E R0, [R4.64+0x40] ; /* 0x0000400404007981 */
/* 0x000e64000c1e1900 */
/*03a0*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*03b0*/ STG.E [R2.64+0x40], R9 ; /* 0x0000400902007986 */
/* 0x0003e8000c101904 */
/*03c0*/ LDG.E R0, [R4.64+0x44] ; /* 0x0000440404007981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*03e0*/ STG.E [R2.64+0x44], R11 ; /* 0x0000440b02007986 */
/* 0x0005e8000c101904 */
/*03f0*/ LDG.E R0, [R4.64+0x48] ; /* 0x0000480404007981 */
/* 0x000ee4000c1e1900 */
/*0400*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*0410*/ STG.E [R2.64+0x48], R13 ; /* 0x0000480d02007986 */
/* 0x0007e8000c101904 */
/*0420*/ LDG.E R0, [R4.64+0x4c] ; /* 0x00004c0404007981 */
/* 0x000e24000c1e1900 */
/*0430*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*0440*/ STG.E [R2.64+0x4c], R7 ; /* 0x00004c0702007986 */
/* 0x0001e8000c101904 */
/*0450*/ LDG.E R0, [R4.64+0x50] ; /* 0x0000500404007981 */
/* 0x000e64000c1e1900 */
/*0460*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*0470*/ STG.E [R2.64+0x50], R9 ; /* 0x0000500902007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R0, [R4.64+0x54] ; /* 0x0000540404007981 */
/* 0x000ea4000c1e1900 */
/*0490*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*04a0*/ STG.E [R2.64+0x54], R11 ; /* 0x0000540b02007986 */
/* 0x0005e8000c101904 */
/*04b0*/ LDG.E R0, [R4.64+0x58] ; /* 0x0000580404007981 */
/* 0x000ee4000c1e1900 */
/*04c0*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*04d0*/ STG.E [R2.64+0x58], R13 ; /* 0x0000580d02007986 */
/* 0x0007e8000c101904 */
/*04e0*/ LDG.E R0, [R4.64+0x5c] ; /* 0x00005c0404007981 */
/* 0x000e24000c1e1900 */
/*04f0*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*0500*/ STG.E [R2.64+0x5c], R7 ; /* 0x00005c0702007986 */
/* 0x0001e8000c101904 */
/*0510*/ LDG.E R0, [R4.64+0x60] ; /* 0x0000600404007981 */
/* 0x000e64000c1e1900 */
/*0520*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*0530*/ STG.E [R2.64+0x60], R9 ; /* 0x0000600902007986 */
/* 0x0003e8000c101904 */
/*0540*/ LDG.E R0, [R4.64+0x64] ; /* 0x0000640404007981 */
/* 0x000ea4000c1e1900 */
/*0550*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*0560*/ STG.E [R2.64+0x64], R11 ; /* 0x0000640b02007986 */
/* 0x0005e8000c101904 */
/*0570*/ LDG.E R0, [R4.64+0x68] ; /* 0x0000680404007981 */
/* 0x000ee4000c1e1900 */
/*0580*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*0590*/ STG.E [R2.64+0x68], R13 ; /* 0x0000680d02007986 */
/* 0x0007e8000c101904 */
/*05a0*/ LDG.E R0, [R4.64+0x6c] ; /* 0x00006c0404007981 */
/* 0x000e24000c1e1900 */
/*05b0*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*05c0*/ STG.E [R2.64+0x6c], R7 ; /* 0x00006c0702007986 */
/* 0x0001e8000c101904 */
/*05d0*/ LDG.E R0, [R4.64+0x70] ; /* 0x0000700404007981 */
/* 0x000e64000c1e1900 */
/*05e0*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*05f0*/ STG.E [R2.64+0x70], R9 ; /* 0x0000700902007986 */
/* 0x000fe8000c101904 */
/*0600*/ LDG.E R0, [R4.64+0x74] ; /* 0x0000740404007981 */
/* 0x000ea4000c1e1900 */
/*0610*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*0620*/ STG.E [R2.64+0x74], R11 ; /* 0x0000740b02007986 */
/* 0x000fe8000c101904 */
/*0630*/ LDG.E R0, [R4.64+0x78] ; /* 0x0000780404007981 */
/* 0x000ee4000c1e1900 */
/*0640*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*0650*/ STG.E [R2.64+0x78], R13 ; /* 0x0000780d02007986 */
/* 0x000fe8000c101904 */
/*0660*/ LDG.E R0, [R4.64+0x7c] ; /* 0x00007c0404007981 */
/* 0x000e24000c1e1900 */
/*0670*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*0680*/ STG.E [R2.64+0x7c], R7 ; /* 0x00007c0702007986 */
/* 0x000fe2000c101904 */
/*0690*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void scan_local(float *in, float *out) {
out[0] = in[0];
for (int i = 0; i < 32; i ++) {
out[i] = out[i-1] + in[i];
}
}
int main(void) {
float v[32];
float r[32];
float *dv;
float *dr;
for (int i = 0; i < 32; i ++) {
v[i] = 1.0;
r[i] = 7.0;
}
cudaMalloc((void**)&dv,32*sizeof(float));
cudaMalloc((void**)&dr,32*sizeof(float));
cudaMemcpy(dv,v,32*sizeof(float),cudaMemcpyHostToDevice);
scan_local<<<1,1,0>>>(dv,dr);
cudaMemcpy(r,dr,32*sizeof(float),cudaMemcpyDeviceToHost);
for (int i = 0; i < 32; i ++) {
printf("%f ",r[i]);
}
return 0;
} | .file "tmpxft_000abe54_00000000-6_naive_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10scan_localPfS_PfS_
.type _Z32__device_stub__Z10scan_localPfS_PfS_, @function
_Z32__device_stub__Z10scan_localPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10scan_localPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z10scan_localPfS_PfS_, .-_Z32__device_stub__Z10scan_localPfS_PfS_
.globl _Z10scan_localPfS_
.type _Z10scan_localPfS_, @function
_Z10scan_localPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10scan_localPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10scan_localPfS_, .-_Z10scan_localPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $320, %rsp
.cfi_def_cfa_offset 352
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movss %xmm1, 48(%rsp,%rax)
movss %xmm0, 176(%rsp,%rax)
addq $4, %rax
cmpq $128, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 176(%rsp), %rbx
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 304(%rsp), %r12
leaq .LC2(%rip), %rbp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $320, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z10scan_localPfS_PfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10scan_localPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10scan_localPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1088421888
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
__global__ void scan_local(float *in, float *out) {
out[0] = in[0];
for (int i = 0; i < 32; i ++) {
out[i] = out[i-1] + in[i];
}
}
int main(void) {
float v[32];
float r[32];
float *dv;
float *dr;
for (int i = 0; i < 32; i ++) {
v[i] = 1.0;
r[i] = 7.0;
}
cudaMalloc((void**)&dv,32*sizeof(float));
cudaMalloc((void**)&dr,32*sizeof(float));
cudaMemcpy(dv,v,32*sizeof(float),cudaMemcpyHostToDevice);
scan_local<<<1,1,0>>>(dv,dr);
cudaMemcpy(r,dr,32*sizeof(float),cudaMemcpyDeviceToHost);
for (int i = 0; i < 32; i ++) {
printf("%f ",r[i]);
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void scan_local(float *in, float *out) {
out[0] = in[0];
for (int i = 0; i < 32; i ++) {
out[i] = out[i-1] + in[i];
}
}
int main(void) {
float v[32];
float r[32];
float *dv;
float *dr;
for (int i = 0; i < 32; i ++) {
v[i] = 1.0;
r[i] = 7.0;
}
hipMalloc((void**)&dv,32*sizeof(float));
hipMalloc((void**)&dr,32*sizeof(float));
hipMemcpy(dv,v,32*sizeof(float),hipMemcpyHostToDevice);
scan_local<<<1,1,0>>>(dv,dr);
hipMemcpy(r,dr,32*sizeof(float),hipMemcpyDeviceToHost);
for (int i = 0; i < 32; i ++) {
printf("%f ",r[i]);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void scan_local(float *in, float *out) {
out[0] = in[0];
for (int i = 0; i < 32; i ++) {
out[i] = out[i-1] + in[i];
}
}
int main(void) {
float v[32];
float r[32];
float *dv;
float *dr;
for (int i = 0; i < 32; i ++) {
v[i] = 1.0;
r[i] = 7.0;
}
hipMalloc((void**)&dv,32*sizeof(float));
hipMalloc((void**)&dr,32*sizeof(float));
hipMemcpy(dv,v,32*sizeof(float),hipMemcpyHostToDevice);
scan_local<<<1,1,0>>>(dv,dr);
hipMemcpy(r,dr,32*sizeof(float),hipMemcpyDeviceToHost);
for (int i = 0; i < 32; i ++) {
printf("%f ",r[i]);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10scan_localPfS_
.globl _Z10scan_localPfS_
.p2align 8
.type _Z10scan_localPfS_,@function
_Z10scan_localPfS_:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s2, -4
s_addc_u32 s5, s3, -1
s_load_b32 s6, s[0:1], 0x0
s_load_b32 s4, s[4:5], 0x0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v1, s4
s_mov_b64 s[4:5], 0
global_store_b32 v0, v2, s[2:3]
.LBB0_1:
s_add_u32 s6, s2, s4
s_addc_u32 s7, s3, s5
s_add_u32 s8, s0, s4
s_addc_u32 s9, s1, s5
s_add_u32 s4, s4, 4
global_load_b32 v2, v0, s[8:9]
s_addc_u32 s5, s5, 0
s_cmpk_eq_i32 s4, 0x80
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[6:7]
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10scan_localPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10scan_localPfS_, .Lfunc_end0-_Z10scan_localPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10scan_localPfS_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z10scan_localPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void scan_local(float *in, float *out) {
out[0] = in[0];
for (int i = 0; i < 32; i ++) {
out[i] = out[i-1] + in[i];
}
}
int main(void) {
float v[32];
float r[32];
float *dv;
float *dr;
for (int i = 0; i < 32; i ++) {
v[i] = 1.0;
r[i] = 7.0;
}
hipMalloc((void**)&dv,32*sizeof(float));
hipMalloc((void**)&dr,32*sizeof(float));
hipMemcpy(dv,v,32*sizeof(float),hipMemcpyHostToDevice);
scan_local<<<1,1,0>>>(dv,dr);
hipMemcpy(r,dr,32*sizeof(float),hipMemcpyDeviceToHost);
for (int i = 0; i < 32; i ++) {
printf("%f ",r[i]);
}
return 0;
} | .text
.file "naive_scan.hip"
.globl _Z25__device_stub__scan_localPfS_ # -- Begin function _Z25__device_stub__scan_localPfS_
.p2align 4, 0x90
.type _Z25__device_stub__scan_localPfS_,@function
_Z25__device_stub__scan_localPfS_: # @_Z25__device_stub__scan_localPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10scan_localPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__scan_localPfS_, .Lfunc_end0-_Z25__device_stub__scan_localPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $352, %rsp # imm = 0x160
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, 224(%rsp,%rax,4) # imm = 0x3F800000
movl $1088421888, 96(%rsp,%rax,4) # imm = 0x40E00000
incq %rax
cmpq $32, %rax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10scan_localPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss 96(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $352, %rsp # imm = 0x160
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10scan_localPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10scan_localPfS_,@object # @_Z10scan_localPfS_
.section .rodata,"a",@progbits
.globl _Z10scan_localPfS_
.p2align 3, 0x0
_Z10scan_localPfS_:
.quad _Z25__device_stub__scan_localPfS_
.size _Z10scan_localPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10scan_localPfS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__scan_localPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10scan_localPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10scan_localPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*0060*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*0070*/ LDG.E R0, [R2.64+-0x4] ; /* 0xfffffc0402007981 */
/* 0x000ee8000c1e1900 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041e8000c101904 */
/*0090*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ee4000c1e1900 */
/*00a0*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x008fca0000000000 */
/*00b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*00c0*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x0005e8000c101904 */
/*00f0*/ LDG.E R0, [R4.64+0x8] ; /* 0x0000080404007981 */
/* 0x000ee4000c1e1900 */
/*0100*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*0110*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x0007e8000c101904 */
/*0120*/ LDG.E R0, [R4.64+0xc] ; /* 0x00000c0404007981 */
/* 0x000e24000c1e1900 */
/*0130*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*0140*/ STG.E [R2.64+0xc], R7 ; /* 0x00000c0702007986 */
/* 0x0001e8000c101904 */
/*0150*/ LDG.E R0, [R4.64+0x10] ; /* 0x0000100404007981 */
/* 0x000e64000c1e1900 */
/*0160*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*0170*/ STG.E [R2.64+0x10], R9 ; /* 0x0000100902007986 */
/* 0x0003e8000c101904 */
/*0180*/ LDG.E R0, [R4.64+0x14] ; /* 0x0000140404007981 */
/* 0x000ea4000c1e1900 */
/*0190*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*01a0*/ STG.E [R2.64+0x14], R11 ; /* 0x0000140b02007986 */
/* 0x0005e8000c101904 */
/*01b0*/ LDG.E R0, [R4.64+0x18] ; /* 0x0000180404007981 */
/* 0x000ee4000c1e1900 */
/*01c0*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*01d0*/ STG.E [R2.64+0x18], R13 ; /* 0x0000180d02007986 */
/* 0x0007e8000c101904 */
/*01e0*/ LDG.E R0, [R4.64+0x1c] ; /* 0x00001c0404007981 */
/* 0x000e24000c1e1900 */
/*01f0*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*0200*/ STG.E [R2.64+0x1c], R7 ; /* 0x00001c0702007986 */
/* 0x0001e8000c101904 */
/*0210*/ LDG.E R0, [R4.64+0x20] ; /* 0x0000200404007981 */
/* 0x000e64000c1e1900 */
/*0220*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*0230*/ STG.E [R2.64+0x20], R9 ; /* 0x0000200902007986 */
/* 0x0003e8000c101904 */
/*0240*/ LDG.E R0, [R4.64+0x24] ; /* 0x0000240404007981 */
/* 0x000ea4000c1e1900 */
/*0250*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*0260*/ STG.E [R2.64+0x24], R11 ; /* 0x0000240b02007986 */
/* 0x0005e8000c101904 */
/*0270*/ LDG.E R0, [R4.64+0x28] ; /* 0x0000280404007981 */
/* 0x000ee4000c1e1900 */
/*0280*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*0290*/ STG.E [R2.64+0x28], R13 ; /* 0x0000280d02007986 */
/* 0x0007e8000c101904 */
/*02a0*/ LDG.E R0, [R4.64+0x2c] ; /* 0x00002c0404007981 */
/* 0x000e24000c1e1900 */
/*02b0*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*02c0*/ STG.E [R2.64+0x2c], R7 ; /* 0x00002c0702007986 */
/* 0x0001e8000c101904 */
/*02d0*/ LDG.E R0, [R4.64+0x30] ; /* 0x0000300404007981 */
/* 0x000e64000c1e1900 */
/*02e0*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*02f0*/ STG.E [R2.64+0x30], R9 ; /* 0x0000300902007986 */
/* 0x0003e8000c101904 */
/*0300*/ LDG.E R0, [R4.64+0x34] ; /* 0x0000340404007981 */
/* 0x000ea4000c1e1900 */
/*0310*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*0320*/ STG.E [R2.64+0x34], R11 ; /* 0x0000340b02007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R0, [R4.64+0x38] ; /* 0x0000380404007981 */
/* 0x000ee4000c1e1900 */
/*0340*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*0350*/ STG.E [R2.64+0x38], R13 ; /* 0x0000380d02007986 */
/* 0x0007e8000c101904 */
/*0360*/ LDG.E R0, [R4.64+0x3c] ; /* 0x00003c0404007981 */
/* 0x000e24000c1e1900 */
/*0370*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*0380*/ STG.E [R2.64+0x3c], R7 ; /* 0x00003c0702007986 */
/* 0x0001e8000c101904 */
/*0390*/ LDG.E R0, [R4.64+0x40] ; /* 0x0000400404007981 */
/* 0x000e64000c1e1900 */
/*03a0*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*03b0*/ STG.E [R2.64+0x40], R9 ; /* 0x0000400902007986 */
/* 0x0003e8000c101904 */
/*03c0*/ LDG.E R0, [R4.64+0x44] ; /* 0x0000440404007981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*03e0*/ STG.E [R2.64+0x44], R11 ; /* 0x0000440b02007986 */
/* 0x0005e8000c101904 */
/*03f0*/ LDG.E R0, [R4.64+0x48] ; /* 0x0000480404007981 */
/* 0x000ee4000c1e1900 */
/*0400*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*0410*/ STG.E [R2.64+0x48], R13 ; /* 0x0000480d02007986 */
/* 0x0007e8000c101904 */
/*0420*/ LDG.E R0, [R4.64+0x4c] ; /* 0x00004c0404007981 */
/* 0x000e24000c1e1900 */
/*0430*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*0440*/ STG.E [R2.64+0x4c], R7 ; /* 0x00004c0702007986 */
/* 0x0001e8000c101904 */
/*0450*/ LDG.E R0, [R4.64+0x50] ; /* 0x0000500404007981 */
/* 0x000e64000c1e1900 */
/*0460*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*0470*/ STG.E [R2.64+0x50], R9 ; /* 0x0000500902007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R0, [R4.64+0x54] ; /* 0x0000540404007981 */
/* 0x000ea4000c1e1900 */
/*0490*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*04a0*/ STG.E [R2.64+0x54], R11 ; /* 0x0000540b02007986 */
/* 0x0005e8000c101904 */
/*04b0*/ LDG.E R0, [R4.64+0x58] ; /* 0x0000580404007981 */
/* 0x000ee4000c1e1900 */
/*04c0*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*04d0*/ STG.E [R2.64+0x58], R13 ; /* 0x0000580d02007986 */
/* 0x0007e8000c101904 */
/*04e0*/ LDG.E R0, [R4.64+0x5c] ; /* 0x00005c0404007981 */
/* 0x000e24000c1e1900 */
/*04f0*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*0500*/ STG.E [R2.64+0x5c], R7 ; /* 0x00005c0702007986 */
/* 0x0001e8000c101904 */
/*0510*/ LDG.E R0, [R4.64+0x60] ; /* 0x0000600404007981 */
/* 0x000e64000c1e1900 */
/*0520*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*0530*/ STG.E [R2.64+0x60], R9 ; /* 0x0000600902007986 */
/* 0x0003e8000c101904 */
/*0540*/ LDG.E R0, [R4.64+0x64] ; /* 0x0000640404007981 */
/* 0x000ea4000c1e1900 */
/*0550*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*0560*/ STG.E [R2.64+0x64], R11 ; /* 0x0000640b02007986 */
/* 0x0005e8000c101904 */
/*0570*/ LDG.E R0, [R4.64+0x68] ; /* 0x0000680404007981 */
/* 0x000ee4000c1e1900 */
/*0580*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*0590*/ STG.E [R2.64+0x68], R13 ; /* 0x0000680d02007986 */
/* 0x0007e8000c101904 */
/*05a0*/ LDG.E R0, [R4.64+0x6c] ; /* 0x00006c0404007981 */
/* 0x000e24000c1e1900 */
/*05b0*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*05c0*/ STG.E [R2.64+0x6c], R7 ; /* 0x00006c0702007986 */
/* 0x0001e8000c101904 */
/*05d0*/ LDG.E R0, [R4.64+0x70] ; /* 0x0000700404007981 */
/* 0x000e64000c1e1900 */
/*05e0*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x002fca0000000000 */
/*05f0*/ STG.E [R2.64+0x70], R9 ; /* 0x0000700902007986 */
/* 0x000fe8000c101904 */
/*0600*/ LDG.E R0, [R4.64+0x74] ; /* 0x0000740404007981 */
/* 0x000ea4000c1e1900 */
/*0610*/ FADD R11, R9, R0 ; /* 0x00000000090b7221 */
/* 0x004fca0000000000 */
/*0620*/ STG.E [R2.64+0x74], R11 ; /* 0x0000740b02007986 */
/* 0x000fe8000c101904 */
/*0630*/ LDG.E R0, [R4.64+0x78] ; /* 0x0000780404007981 */
/* 0x000ee4000c1e1900 */
/*0640*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x008fca0000000000 */
/*0650*/ STG.E [R2.64+0x78], R13 ; /* 0x0000780d02007986 */
/* 0x000fe8000c101904 */
/*0660*/ LDG.E R0, [R4.64+0x7c] ; /* 0x00007c0404007981 */
/* 0x000e24000c1e1900 */
/*0670*/ FADD R7, R13, R0 ; /* 0x000000000d077221 */
/* 0x001fca0000000000 */
/*0680*/ STG.E [R2.64+0x7c], R7 ; /* 0x00007c0702007986 */
/* 0x000fe2000c101904 */
/*0690*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10scan_localPfS_
.globl _Z10scan_localPfS_
.p2align 8
.type _Z10scan_localPfS_,@function
_Z10scan_localPfS_:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s2, -4
s_addc_u32 s5, s3, -1
s_load_b32 s6, s[0:1], 0x0
s_load_b32 s4, s[4:5], 0x0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v1, s4
s_mov_b64 s[4:5], 0
global_store_b32 v0, v2, s[2:3]
.LBB0_1:
s_add_u32 s6, s2, s4
s_addc_u32 s7, s3, s5
s_add_u32 s8, s0, s4
s_addc_u32 s9, s1, s5
s_add_u32 s4, s4, 4
global_load_b32 v2, v0, s[8:9]
s_addc_u32 s5, s5, 0
s_cmpk_eq_i32 s4, 0x80
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[6:7]
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10scan_localPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10scan_localPfS_, .Lfunc_end0-_Z10scan_localPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10scan_localPfS_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z10scan_localPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000abe54_00000000-6_naive_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10scan_localPfS_PfS_
.type _Z32__device_stub__Z10scan_localPfS_PfS_, @function
_Z32__device_stub__Z10scan_localPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10scan_localPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z10scan_localPfS_PfS_, .-_Z32__device_stub__Z10scan_localPfS_PfS_
.globl _Z10scan_localPfS_
.type _Z10scan_localPfS_, @function
_Z10scan_localPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10scan_localPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10scan_localPfS_, .-_Z10scan_localPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $320, %rsp
.cfi_def_cfa_offset 352
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movss %xmm1, 48(%rsp,%rax)
movss %xmm0, 176(%rsp,%rax)
addq $4, %rax
cmpq $128, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 176(%rsp), %rbx
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 304(%rsp), %r12
leaq .LC2(%rip), %rbp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $320, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z10scan_localPfS_PfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10scan_localPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10scan_localPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1088421888
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "naive_scan.hip"
.globl _Z25__device_stub__scan_localPfS_ # -- Begin function _Z25__device_stub__scan_localPfS_
.p2align 4, 0x90
.type _Z25__device_stub__scan_localPfS_,@function
_Z25__device_stub__scan_localPfS_: # @_Z25__device_stub__scan_localPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10scan_localPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__scan_localPfS_, .Lfunc_end0-_Z25__device_stub__scan_localPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $352, %rsp # imm = 0x160
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, 224(%rsp,%rax,4) # imm = 0x3F800000
movl $1088421888, 96(%rsp,%rax,4) # imm = 0x40E00000
incq %rax
cmpq $32, %rax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10scan_localPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss 96(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $352, %rsp # imm = 0x160
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10scan_localPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10scan_localPfS_,@object # @_Z10scan_localPfS_
.section .rodata,"a",@progbits
.globl _Z10scan_localPfS_
.p2align 3, 0x0
_Z10scan_localPfS_:
.quad _Z25__device_stub__scan_localPfS_
.size _Z10scan_localPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10scan_localPfS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__scan_localPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10scan_localPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //xfail:REPAIR_ERROR
//--blockDim=512 --gridDim=64 --loop-unwind=2 --no-inline
#include <cuda.h>
extern "C" {
__global__ void helloCUDA(float *A)
{
__shared__ float B[256];
for(int i = 0; i < 10; i ++) {
B[i] = A[i];
}
}
} | code for sm_80
Function : helloCUDA
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //xfail:REPAIR_ERROR
//--blockDim=512 --gridDim=64 --loop-unwind=2 --no-inline
#include <cuda.h>
extern "C" {
__global__ void helloCUDA(float *A)
{
__shared__ float B[256];
for(int i = 0; i < 10; i ++) {
B[i] = A[i];
}
}
} | .file "tmpxft_0018e2c8_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z9helloCUDAPfPf
.type _Z28__device_stub__Z9helloCUDAPfPf, @function
_Z28__device_stub__Z9helloCUDAPfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq helloCUDA(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z9helloCUDAPfPf, .-_Z28__device_stub__Z9helloCUDAPfPf
.globl helloCUDA
.type helloCUDA, @function
helloCUDA:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9helloCUDAPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size helloCUDA, .-helloCUDA
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "helloCUDA"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq helloCUDA(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //xfail:REPAIR_ERROR
//--blockDim=512 --gridDim=64 --loop-unwind=2 --no-inline
#include <cuda.h>
extern "C" {
__global__ void helloCUDA(float *A)
{
__shared__ float B[256];
for(int i = 0; i < 10; i ++) {
B[i] = A[i];
}
}
} | //xfail:REPAIR_ERROR
//--blockDim=512 --gridDim=64 --loop-unwind=2 --no-inline
#include <hip/hip_runtime.h>
extern "C" {
__global__ void helloCUDA(float *A)
{
__shared__ float B[256];
for(int i = 0; i < 10; i ++) {
B[i] = A[i];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //xfail:REPAIR_ERROR
//--blockDim=512 --gridDim=64 --loop-unwind=2 --no-inline
#include <hip/hip_runtime.h>
extern "C" {
__global__ void helloCUDA(float *A)
{
__shared__ float B[256];
for(int i = 0; i < 10; i ++) {
B[i] = A[i];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected helloCUDA
.globl helloCUDA
.p2align 8
.type helloCUDA,@function
helloCUDA:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel helloCUDA
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size helloCUDA, .Lfunc_end0-helloCUDA
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: helloCUDA
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: helloCUDA.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //xfail:REPAIR_ERROR
//--blockDim=512 --gridDim=64 --loop-unwind=2 --no-inline
#include <hip/hip_runtime.h>
extern "C" {
__global__ void helloCUDA(float *A)
{
__shared__ float B[256];
for(int i = 0; i < 10; i ++) {
B[i] = A[i];
}
}
} | .text
.file "kernel.hip"
.globl __device_stub__helloCUDA # -- Begin function __device_stub__helloCUDA
.p2align 4, 0x90
.type __device_stub__helloCUDA,@function
__device_stub__helloCUDA: # @__device_stub__helloCUDA
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $helloCUDA, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__helloCUDA, .Lfunc_end0-__device_stub__helloCUDA
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $helloCUDA, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type helloCUDA,@object # @helloCUDA
.section .rodata,"a",@progbits
.globl helloCUDA
.p2align 3, 0x0
helloCUDA:
.quad __device_stub__helloCUDA
.size helloCUDA, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "helloCUDA"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__helloCUDA
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym helloCUDA
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : helloCUDA
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected helloCUDA
.globl helloCUDA
.p2align 8
.type helloCUDA,@function
helloCUDA:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel helloCUDA
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size helloCUDA, .Lfunc_end0-helloCUDA
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: helloCUDA
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: helloCUDA.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018e2c8_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z9helloCUDAPfPf
.type _Z28__device_stub__Z9helloCUDAPfPf, @function
_Z28__device_stub__Z9helloCUDAPfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq helloCUDA(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z9helloCUDAPfPf, .-_Z28__device_stub__Z9helloCUDAPfPf
.globl helloCUDA
.type helloCUDA, @function
helloCUDA:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9helloCUDAPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size helloCUDA, .-helloCUDA
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "helloCUDA"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq helloCUDA(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl __device_stub__helloCUDA # -- Begin function __device_stub__helloCUDA
.p2align 4, 0x90
.type __device_stub__helloCUDA,@function
__device_stub__helloCUDA: # @__device_stub__helloCUDA
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $helloCUDA, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__helloCUDA, .Lfunc_end0-__device_stub__helloCUDA
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $helloCUDA, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type helloCUDA,@object # @helloCUDA
.section .rodata,"a",@progbits
.globl helloCUDA
.p2align 3, 0x0
helloCUDA:
.quad __device_stub__helloCUDA
.size helloCUDA, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "helloCUDA"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__helloCUDA
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym helloCUDA
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //pass
//--blockDim=64 --gridDim=1 --no-inline
#include "cuda.h"
__device__ void bar(int* p) {
p[threadIdx.x] = 0;
}
__global__ void foo(int* p) {
bar(p);
} | code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //pass
//--blockDim=64 --gridDim=1 --no-inline
#include "cuda.h"
__device__ void bar(int* p) {
p[threadIdx.x] = 0;
}
__global__ void foo(int* p) {
bar(p);
} | .file "tmpxft_00184c06_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3barPi
.type _Z3barPi, @function
_Z3barPi:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z3barPi, .-_Z3barPi
.globl _Z22__device_stub__Z3fooPiPi
.type _Z22__device_stub__Z3fooPiPi, @function
_Z22__device_stub__Z3fooPiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z22__device_stub__Z3fooPiPi, .-_Z22__device_stub__Z3fooPiPi
.globl _Z3fooPi
.type _Z3fooPi, @function
_Z3fooPi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z3fooPi, .-_Z3fooPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //pass
//--blockDim=64 --gridDim=1 --no-inline
#include "cuda.h"
__device__ void bar(int* p) {
p[threadIdx.x] = 0;
}
__global__ void foo(int* p) {
bar(p);
} | //pass
//--blockDim=64 --gridDim=1 --no-inline
#include "hip/hip_runtime.h"
__device__ void bar(int* p) {
p[threadIdx.x] = 0;
}
__global__ void foo(int* p) {
bar(p);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //pass
//--blockDim=64 --gridDim=1 --no-inline
#include "hip/hip_runtime.h"
__device__ void bar(int* p) {
p[threadIdx.x] = 0;
}
__global__ void foo(int* p) {
bar(p);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPi, .Lfunc_end0-_Z3fooPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3fooPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //pass
//--blockDim=64 --gridDim=1 --no-inline
#include "hip/hip_runtime.h"
__device__ void bar(int* p) {
p[threadIdx.x] = 0;
}
__global__ void foo(int* p) {
bar(p);
} | .text
.file "kernel.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPi, .Lfunc_end0-_Z18__device_stub__fooPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPi,@object # @_Z3fooPi
.section .rodata,"a",@progbits
.globl _Z3fooPi
.p2align 3, 0x0
_Z3fooPi:
.quad _Z18__device_stub__fooPi
.size _Z3fooPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPi, .Lfunc_end0-_Z3fooPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3fooPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00184c06_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3barPi
.type _Z3barPi, @function
_Z3barPi:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z3barPi, .-_Z3barPi
.globl _Z22__device_stub__Z3fooPiPi
.type _Z22__device_stub__Z3fooPiPi, @function
_Z22__device_stub__Z3fooPiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z22__device_stub__Z3fooPiPi, .-_Z22__device_stub__Z3fooPiPi
.globl _Z3fooPi
.type _Z3fooPi, @function
_Z3fooPi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z3fooPi, .-_Z3fooPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPi, .Lfunc_end0-_Z18__device_stub__fooPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPi,@object # @_Z3fooPi
.section .rodata,"a",@progbits
.globl _Z3fooPi
.p2align 3, 0x0
_Z3fooPi:
.quad _Z18__device_stub__fooPi
.size _Z3fooPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <cuda.h>
/* Utility function, use to do error checking.
Use this function like this:
checkCudaCall(cudaMalloc((void **) &deviceRGB, imgS * sizeof(color_t)));
And to check the result of a kernel invocation:
checkCudaCall(cudaGetLastError());
*/
static void checkCudaCall(cudaError_t result) {
if (result != cudaSuccess) {
printf("cuda Error \n");
exit(1);
}
}
__global__ void vectorAddKernel(int* deviceA, int* deviceResult) {
unsigned i = blockIdx.x * blockDim.x + threadIdx.x;
// insert operation here
deviceResult[i] = deviceA[i];
}
extern "C"
void histogram(int *v, long n){
int* deviceIn, *deviceOut;
int threadBlockSize=256;
int result[256];
checkCudaCall(cudaMalloc((void **) &deviceIn, n * sizeof(int)));
if (deviceIn == NULL) {
printf("Error in cudaMalloc! \n");
return;
}
checkCudaCall(cudaMalloc((void **) &deviceOut, n * sizeof(int)));
if (deviceOut == NULL) {
checkCudaCall(cudaFree(deviceIn));
printf("Error in cudaMalloc! \n");
return;
}
checkCudaCall(cudaMemcpy(deviceIn, v, n * sizeof(int), cudaMemcpyDeviceToHost));
vectorAddKernel<<<n/threadBlockSize, threadBlockSize>>>(deviceIn, deviceOut);
cudaDeviceSynchronize();
checkCudaCall(cudaMemcpy(result, deviceOut, n * sizeof(int), cudaMemcpyDeviceToHost));
checkCudaCall(cudaFree(deviceIn));
checkCudaCall(cudaFree(deviceOut));
} | code for sm_80
Function : _Z15vectorAddKernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0005 */
/*0090*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <cuda.h>
/* Utility function, use to do error checking.
Use this function like this:
checkCudaCall(cudaMalloc((void **) &deviceRGB, imgS * sizeof(color_t)));
And to check the result of a kernel invocation:
checkCudaCall(cudaGetLastError());
*/
static void checkCudaCall(cudaError_t result) {
if (result != cudaSuccess) {
printf("cuda Error \n");
exit(1);
}
}
__global__ void vectorAddKernel(int* deviceA, int* deviceResult) {
unsigned i = blockIdx.x * blockDim.x + threadIdx.x;
// insert operation here
deviceResult[i] = deviceA[i];
}
extern "C"
void histogram(int *v, long n){
int* deviceIn, *deviceOut;
int threadBlockSize=256;
int result[256];
checkCudaCall(cudaMalloc((void **) &deviceIn, n * sizeof(int)));
if (deviceIn == NULL) {
printf("Error in cudaMalloc! \n");
return;
}
checkCudaCall(cudaMalloc((void **) &deviceOut, n * sizeof(int)));
if (deviceOut == NULL) {
checkCudaCall(cudaFree(deviceIn));
printf("Error in cudaMalloc! \n");
return;
}
checkCudaCall(cudaMemcpy(deviceIn, v, n * sizeof(int), cudaMemcpyDeviceToHost));
vectorAddKernel<<<n/threadBlockSize, threadBlockSize>>>(deviceIn, deviceOut);
cudaDeviceSynchronize();
checkCudaCall(cudaMemcpy(result, deviceOut, n * sizeof(int), cudaMemcpyDeviceToHost));
checkCudaCall(cudaFree(deviceIn));
checkCudaCall(cudaFree(deviceOut));
} | .file "tmpxft_0017af30_00000000-6_histo_kernel.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cuda Error \n"
#NO_APP
.text
.type _ZL13checkCudaCall9cudaError, @function
_ZL13checkCudaCall9cudaError:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL13checkCudaCall9cudaError, .-_ZL13checkCudaCall9cudaError
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z15vectorAddKernelPiS_PiS_
.type _Z37__device_stub__Z15vectorAddKernelPiS_PiS_, @function
_Z37__device_stub__Z15vectorAddKernelPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15vectorAddKernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z15vectorAddKernelPiS_PiS_, .-_Z37__device_stub__Z15vectorAddKernelPiS_PiS_
.globl _Z15vectorAddKernelPiS_
.type _Z15vectorAddKernelPiS_, @function
_Z15vectorAddKernelPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15vectorAddKernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15vectorAddKernelPiS_, .-_Z15vectorAddKernelPiS_
.section .rodata.str1.1
.LC1:
.string "Error in cudaMalloc! \n"
.text
.globl histogram
.type histogram, @function
histogram:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1088, %rsp
.cfi_def_cfa_offset 1120
movq %rdi, %r12
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 0(,%rsi,4), %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
cmpq $0, 8(%rsp)
je .L25
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
cmpq $0, 16(%rsp)
je .L26
movl $2, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
movl $256, 36(%rsp)
movl $1, 40(%rsp)
leaq 255(%rbx), %rax
testq %rbx, %rbx
cmovns %rbx, %rax
sarq $8, %rax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
.L17:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $1088, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L26:
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L27:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z15vectorAddKernelPiS_PiS_
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size histogram, .-histogram
.section .rodata.str1.1
.LC2:
.string "_Z15vectorAddKernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15vectorAddKernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <cuda.h>
/* Utility function, use to do error checking.
Use this function like this:
checkCudaCall(cudaMalloc((void **) &deviceRGB, imgS * sizeof(color_t)));
And to check the result of a kernel invocation:
checkCudaCall(cudaGetLastError());
*/
static void checkCudaCall(cudaError_t result) {
if (result != cudaSuccess) {
printf("cuda Error \n");
exit(1);
}
}
__global__ void vectorAddKernel(int* deviceA, int* deviceResult) {
unsigned i = blockIdx.x * blockDim.x + threadIdx.x;
// insert operation here
deviceResult[i] = deviceA[i];
}
extern "C"
void histogram(int *v, long n){
int* deviceIn, *deviceOut;
int threadBlockSize=256;
int result[256];
checkCudaCall(cudaMalloc((void **) &deviceIn, n * sizeof(int)));
if (deviceIn == NULL) {
printf("Error in cudaMalloc! \n");
return;
}
checkCudaCall(cudaMalloc((void **) &deviceOut, n * sizeof(int)));
if (deviceOut == NULL) {
checkCudaCall(cudaFree(deviceIn));
printf("Error in cudaMalloc! \n");
return;
}
checkCudaCall(cudaMemcpy(deviceIn, v, n * sizeof(int), cudaMemcpyDeviceToHost));
vectorAddKernel<<<n/threadBlockSize, threadBlockSize>>>(deviceIn, deviceOut);
cudaDeviceSynchronize();
checkCudaCall(cudaMemcpy(result, deviceOut, n * sizeof(int), cudaMemcpyDeviceToHost));
checkCudaCall(cudaFree(deviceIn));
checkCudaCall(cudaFree(deviceOut));
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <hip/hip_runtime.h>
/* Utility function, use to do error checking.
Use this function like this:
checkCudaCall(cudaMalloc((void **) &deviceRGB, imgS * sizeof(color_t)));
And to check the result of a kernel invocation:
checkCudaCall(cudaGetLastError());
*/
static void checkCudaCall(hipError_t result) {
if (result != hipSuccess) {
printf("cuda Error \n");
exit(1);
}
}
__global__ void vectorAddKernel(int* deviceA, int* deviceResult) {
unsigned i = blockIdx.x * blockDim.x + threadIdx.x;
// insert operation here
deviceResult[i] = deviceA[i];
}
extern "C"
void histogram(int *v, long n){
int* deviceIn, *deviceOut;
int threadBlockSize=256;
int result[256];
checkCudaCall(hipMalloc((void **) &deviceIn, n * sizeof(int)));
if (deviceIn == NULL) {
printf("Error in cudaMalloc! \n");
return;
}
checkCudaCall(hipMalloc((void **) &deviceOut, n * sizeof(int)));
if (deviceOut == NULL) {
checkCudaCall(hipFree(deviceIn));
printf("Error in cudaMalloc! \n");
return;
}
checkCudaCall(hipMemcpy(deviceIn, v, n * sizeof(int), hipMemcpyDeviceToHost));
vectorAddKernel<<<n/threadBlockSize, threadBlockSize>>>(deviceIn, deviceOut);
hipDeviceSynchronize();
checkCudaCall(hipMemcpy(result, deviceOut, n * sizeof(int), hipMemcpyDeviceToHost));
checkCudaCall(hipFree(deviceIn));
checkCudaCall(hipFree(deviceOut));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <hip/hip_runtime.h>
/* Utility function, use to do error checking.
Use this function like this:
checkCudaCall(cudaMalloc((void **) &deviceRGB, imgS * sizeof(color_t)));
And to check the result of a kernel invocation:
checkCudaCall(cudaGetLastError());
*/
static void checkCudaCall(hipError_t result) {
if (result != hipSuccess) {
printf("cuda Error \n");
exit(1);
}
}
__global__ void vectorAddKernel(int* deviceA, int* deviceResult) {
unsigned i = blockIdx.x * blockDim.x + threadIdx.x;
// insert operation here
deviceResult[i] = deviceA[i];
}
extern "C"
void histogram(int *v, long n){
int* deviceIn, *deviceOut;
int threadBlockSize=256;
int result[256];
checkCudaCall(hipMalloc((void **) &deviceIn, n * sizeof(int)));
if (deviceIn == NULL) {
printf("Error in cudaMalloc! \n");
return;
}
checkCudaCall(hipMalloc((void **) &deviceOut, n * sizeof(int)));
if (deviceOut == NULL) {
checkCudaCall(hipFree(deviceIn));
printf("Error in cudaMalloc! \n");
return;
}
checkCudaCall(hipMemcpy(deviceIn, v, n * sizeof(int), hipMemcpyDeviceToHost));
vectorAddKernel<<<n/threadBlockSize, threadBlockSize>>>(deviceIn, deviceOut);
hipDeviceSynchronize();
checkCudaCall(hipMemcpy(result, deviceOut, n * sizeof(int), hipMemcpyDeviceToHost));
checkCudaCall(hipFree(deviceIn));
checkCudaCall(hipFree(deviceOut));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15vectorAddKernelPiS_
.globl _Z15vectorAddKernelPiS_
.p2align 8
.type _Z15vectorAddKernelPiS_,@function
_Z15vectorAddKernelPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15vectorAddKernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15vectorAddKernelPiS_, .Lfunc_end0-_Z15vectorAddKernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15vectorAddKernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15vectorAddKernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <hip/hip_runtime.h>
/* Utility function, use to do error checking.
Use this function like this:
checkCudaCall(cudaMalloc((void **) &deviceRGB, imgS * sizeof(color_t)));
And to check the result of a kernel invocation:
checkCudaCall(cudaGetLastError());
*/
static void checkCudaCall(hipError_t result) {
if (result != hipSuccess) {
printf("cuda Error \n");
exit(1);
}
}
__global__ void vectorAddKernel(int* deviceA, int* deviceResult) {
unsigned i = blockIdx.x * blockDim.x + threadIdx.x;
// insert operation here
deviceResult[i] = deviceA[i];
}
extern "C"
void histogram(int *v, long n){
int* deviceIn, *deviceOut;
int threadBlockSize=256;
int result[256];
checkCudaCall(hipMalloc((void **) &deviceIn, n * sizeof(int)));
if (deviceIn == NULL) {
printf("Error in cudaMalloc! \n");
return;
}
checkCudaCall(hipMalloc((void **) &deviceOut, n * sizeof(int)));
if (deviceOut == NULL) {
checkCudaCall(hipFree(deviceIn));
printf("Error in cudaMalloc! \n");
return;
}
checkCudaCall(hipMemcpy(deviceIn, v, n * sizeof(int), hipMemcpyDeviceToHost));
vectorAddKernel<<<n/threadBlockSize, threadBlockSize>>>(deviceIn, deviceOut);
hipDeviceSynchronize();
checkCudaCall(hipMemcpy(result, deviceOut, n * sizeof(int), hipMemcpyDeviceToHost));
checkCudaCall(hipFree(deviceIn));
checkCudaCall(hipFree(deviceOut));
} | .text
.file "histo_kernel.hip"
.globl _Z30__device_stub__vectorAddKernelPiS_ # -- Begin function _Z30__device_stub__vectorAddKernelPiS_
.p2align 4, 0x90
.type _Z30__device_stub__vectorAddKernelPiS_,@function
_Z30__device_stub__vectorAddKernelPiS_: # @_Z30__device_stub__vectorAddKernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15vectorAddKernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__vectorAddKernelPiS_, .Lfunc_end0-_Z30__device_stub__vectorAddKernelPiS_
.cfi_endproc
# -- End function
.globl histogram # -- Begin function histogram
.p2align 4, 0x90
.type histogram,@function
histogram: # @histogram
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1104, %rsp # imm = 0x450
.cfi_def_cfa_offset 1136
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq %rdi, %r15
leaq (,%rsi,4), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.1: # %_ZL13checkCudaCall10hipError_t.exit
cmpq $0, 8(%rsp)
je .LBB1_5
# %bb.2:
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.3: # %_ZL13checkCudaCall10hipError_t.exit12
cmpq $0, (%rsp)
movq 8(%rsp), %rdi
je .LBB1_4
# %bb.6:
movq %r15, %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.7: # %_ZL13checkCudaCall10hipError_t.exit18
leaq 255(%r14), %rax
testq %r14, %r14
cmovnsq %r14, %rax
shrq $8, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15vectorAddKernelPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
callq hipDeviceSynchronize
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.10: # %_ZL13checkCudaCall10hipError_t.exit21
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_13
# %bb.11: # %_ZL13checkCudaCall10hipError_t.exit24
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_12
jmp .LBB1_13
.LBB1_4:
callq hipFree
testl %eax, %eax
jne .LBB1_13
.LBB1_5: # %_ZL13checkCudaCall10hipError_t.exit27.sink.split
movl $.Lstr.1, %edi
callq puts@PLT
.LBB1_12: # %_ZL13checkCudaCall10hipError_t.exit27
addq $1104, %rsp # imm = 0x450
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 1136
movl $.Lstr.2, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size histogram, .Lfunc_end1-histogram
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15vectorAddKernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15vectorAddKernelPiS_,@object # @_Z15vectorAddKernelPiS_
.section .rodata,"a",@progbits
.globl _Z15vectorAddKernelPiS_
.p2align 3, 0x0
_Z15vectorAddKernelPiS_:
.quad _Z30__device_stub__vectorAddKernelPiS_
.size _Z15vectorAddKernelPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15vectorAddKernelPiS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "Error in cudaMalloc! "
.size .Lstr.1, 22
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "cuda Error "
.size .Lstr.2, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__vectorAddKernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15vectorAddKernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15vectorAddKernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0005 */
/*0090*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15vectorAddKernelPiS_
.globl _Z15vectorAddKernelPiS_
.p2align 8
.type _Z15vectorAddKernelPiS_,@function
_Z15vectorAddKernelPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15vectorAddKernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15vectorAddKernelPiS_, .Lfunc_end0-_Z15vectorAddKernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15vectorAddKernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15vectorAddKernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017af30_00000000-6_histo_kernel.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cuda Error \n"
#NO_APP
.text
.type _ZL13checkCudaCall9cudaError, @function
_ZL13checkCudaCall9cudaError:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL13checkCudaCall9cudaError, .-_ZL13checkCudaCall9cudaError
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z15vectorAddKernelPiS_PiS_
.type _Z37__device_stub__Z15vectorAddKernelPiS_PiS_, @function
_Z37__device_stub__Z15vectorAddKernelPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15vectorAddKernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z15vectorAddKernelPiS_PiS_, .-_Z37__device_stub__Z15vectorAddKernelPiS_PiS_
.globl _Z15vectorAddKernelPiS_
.type _Z15vectorAddKernelPiS_, @function
_Z15vectorAddKernelPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15vectorAddKernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15vectorAddKernelPiS_, .-_Z15vectorAddKernelPiS_
.section .rodata.str1.1
.LC1:
.string "Error in cudaMalloc! \n"
.text
.globl histogram
.type histogram, @function
histogram:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1088, %rsp
.cfi_def_cfa_offset 1120
movq %rdi, %r12
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 0(,%rsi,4), %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
cmpq $0, 8(%rsp)
je .L25
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
cmpq $0, 16(%rsp)
je .L26
movl $2, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
movl $256, 36(%rsp)
movl $1, 40(%rsp)
leaq 255(%rbx), %rax
testq %rbx, %rbx
cmovns %rbx, %rax
sarq $8, %rax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
.L17:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $1088, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L26:
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _ZL13checkCudaCall9cudaError
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L27:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z15vectorAddKernelPiS_PiS_
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size histogram, .-histogram
.section .rodata.str1.1
.LC2:
.string "_Z15vectorAddKernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15vectorAddKernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "histo_kernel.hip"
.globl _Z30__device_stub__vectorAddKernelPiS_ # -- Begin function _Z30__device_stub__vectorAddKernelPiS_
.p2align 4, 0x90
.type _Z30__device_stub__vectorAddKernelPiS_,@function
_Z30__device_stub__vectorAddKernelPiS_: # @_Z30__device_stub__vectorAddKernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15vectorAddKernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__vectorAddKernelPiS_, .Lfunc_end0-_Z30__device_stub__vectorAddKernelPiS_
.cfi_endproc
# -- End function
.globl histogram # -- Begin function histogram
.p2align 4, 0x90
.type histogram,@function
histogram: # @histogram
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1104, %rsp # imm = 0x450
.cfi_def_cfa_offset 1136
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq %rdi, %r15
leaq (,%rsi,4), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.1: # %_ZL13checkCudaCall10hipError_t.exit
cmpq $0, 8(%rsp)
je .LBB1_5
# %bb.2:
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.3: # %_ZL13checkCudaCall10hipError_t.exit12
cmpq $0, (%rsp)
movq 8(%rsp), %rdi
je .LBB1_4
# %bb.6:
movq %r15, %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.7: # %_ZL13checkCudaCall10hipError_t.exit18
leaq 255(%r14), %rax
testq %r14, %r14
cmovnsq %r14, %rax
shrq $8, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15vectorAddKernelPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
callq hipDeviceSynchronize
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.10: # %_ZL13checkCudaCall10hipError_t.exit21
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_13
# %bb.11: # %_ZL13checkCudaCall10hipError_t.exit24
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_12
jmp .LBB1_13
.LBB1_4:
callq hipFree
testl %eax, %eax
jne .LBB1_13
.LBB1_5: # %_ZL13checkCudaCall10hipError_t.exit27.sink.split
movl $.Lstr.1, %edi
callq puts@PLT
.LBB1_12: # %_ZL13checkCudaCall10hipError_t.exit27
addq $1104, %rsp # imm = 0x450
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 1136
movl $.Lstr.2, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size histogram, .Lfunc_end1-histogram
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15vectorAddKernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15vectorAddKernelPiS_,@object # @_Z15vectorAddKernelPiS_
.section .rodata,"a",@progbits
.globl _Z15vectorAddKernelPiS_
.p2align 3, 0x0
_Z15vectorAddKernelPiS_:
.quad _Z30__device_stub__vectorAddKernelPiS_
.size _Z15vectorAddKernelPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15vectorAddKernelPiS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "Error in cudaMalloc! "
.size .Lstr.1, 22
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "cuda Error "
.size .Lstr.2, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__vectorAddKernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15vectorAddKernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Program for Matrix Addition in CUDA
// For Hadoop-CUDA Lab
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
__global__ void gpu_matrixadd(int *a,int *b, int *c, int N) {
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int index = row * N + col;
if(col < N && row < N)
c[index] = a[index]+b[index];
}
void cpu_matrixadd(int *a,int *b, int *c, int N) {
int index;
for(int col=0;col < N; col++)
for(int row=0;row < N; row++) {
index = row * N + col;
c[index] = a[index]+b[index];
}
}
int main(int argc, char *argv[]) {
char key;
int i, j; // loop counters
int Grid_Dim_x=1, Grid_Dim_y=1; //Grid structure values
int Block_Dim_x=1, Block_Dim_y=1; //Block structure values
int noThreads_x, noThreads_y; // number of threads available in device, each dimension
int noThreads_block; // number of threads in a block
int N = 10; // size of array in each dimension
int *a,*b,*c,*d;
int *dev_a, *dev_b, *dev_c;
int size; // number of bytes in arrays
cudaEvent_t start, stop; // using cuda events to measure time
float elapsed_time_ms; // which is applicable for asynchronous code also
/* --------------------ENTER INPUT PARAMETERS AND DATA -----------------------*/
do { // loop to repeat complete program
printf ("Device characteristics -- some limitations (compute capability 1.0)\n");
printf (" Maximum number of threads per block = 512\n");
printf (" Maximum sizes of x- and y- dimension of thread block = 512\n");
printf (" Maximum size of each dimension of grid of thread blocks = 65535\n");
printf("Enter size of array in one dimension (square array), currently %d\n",N);
scanf("%d",&N);
do {
printf("\nEnter nuumber of blocks per grid in x dimension), currently %d : ",Grid_Dim_x);
scanf("%d",&Grid_Dim_x);
printf("\nEnter nuumber of blocks per grid in y dimension), currently %d : ",Grid_Dim_y);
scanf("%d",&Grid_Dim_y);
printf("\nEnter nuumber of threads per block in x dimension), currently %d : ",Block_Dim_x);
scanf("%d",&Block_Dim_x);
printf("\nEnter nuumber of threads per block in y dimension), currently %d : ",Block_Dim_y);
scanf("%d",&Block_Dim_y);
noThreads_x = Grid_Dim_x * Block_Dim_x; // number of threads in x dimension
noThreads_y = Grid_Dim_y * Block_Dim_y; // number of threads in y dimension
noThreads_block = Block_Dim_x * Block_Dim_y; // number of threads in a block
if (noThreads_x < N) printf("Error -- number of threads in x dimension less than number of elements in arrays, try again\n");
else if (noThreads_y < N) printf("Error -- number of threads in y dimension less than number of elements in arrays, try again\n");
else if (noThreads_block > 512) printf("Error -- too many threads in block, try again\n");
else printf("Number of threads not used = %d\n", noThreads_x * noThreads_y - N * N);
} while (noThreads_x < N || noThreads_y < N || noThreads_block > 512);
dim3 Grid(Grid_Dim_x, Grid_Dim_x); //Grid structure
dim3 Block(Block_Dim_x,Block_Dim_y); //Block structure, threads/block limited by specific device
size = N * N * sizeof(int); // number of bytes in total in arrays
a = (int*) malloc(size); //this time use dynamically allocated memory for arrays on host
b = (int*) malloc(size);
c = (int*) malloc(size); // results from GPU
d = (int*) malloc(size); // results from CPU
for(i=0;i < N;i++) // load arrays with some numbers
for(j=0;j < N;j++) {
a[i * N + j] = i;
b[i * N + j] = i;
}
/* ------------- COMPUTATION DONE ON GPU ----------------------------*/
cudaMalloc((void**)&dev_a, size); // allocate memory on device
cudaMalloc((void**)&dev_b, size);
cudaMalloc((void**)&dev_c, size);
cudaMemcpy(dev_a, a , size ,cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b , size ,cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c , size ,cudaMemcpyHostToDevice);
cudaEventCreate(&start); // instrument code to measure start time
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// cudaEventSynchronize(start); // Needed?
gpu_matrixadd<<<Grid,Block>>>(dev_a,dev_b,dev_c,N);
cudaMemcpy(c,dev_c, size ,cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0); // instrument code to measue end time
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time_ms, start, stop );
// for(i=0;i < N;i++)
// for(j=0;j < N;j++)
// printf("%d+%d=%d\n",a[i * N + j],b[i * N + j],c[i * N + j]);
printf("Time to calculate results on GPU: %f ms.\n", elapsed_time_ms); // print out execution time
/* ------------- COMPUTATION DONE ON HOST CPU ----------------------------*/
cudaEventRecord(start, 0); // use same timing
// cudaEventSynchronize(start); // Needed?
cpu_matrixadd(a,b,d,N); // do calculation on host
cudaEventRecord(stop, 0); // instrument code to measue end time
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time_ms, start, stop );
printf("Time to calculate results on CPU: %f ms.\n", elapsed_time_ms); // print out execution time
/* ------------------- check device creates correct results -----------------*/
for(i=0;i < N*N;i++) {
if (c[i] != d[i]) printf("*********** ERROR in results, CPU and GPU create different answers ********\n");
break;
}
printf("\nEnter c to repeat, return to terminate\n");
scanf("%c",&key);
scanf("%c",&key);
} while (key == 'c'); // loop of complete program
/* -------------- clean up ---------------------------------------*/
free(a);
free(b);
free(c);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | code for sm_80
Function : _Z13gpu_matrixaddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0120*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Program for Matrix Addition in CUDA
// For Hadoop-CUDA Lab
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
__global__ void gpu_matrixadd(int *a,int *b, int *c, int N) {
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int index = row * N + col;
if(col < N && row < N)
c[index] = a[index]+b[index];
}
void cpu_matrixadd(int *a,int *b, int *c, int N) {
int index;
for(int col=0;col < N; col++)
for(int row=0;row < N; row++) {
index = row * N + col;
c[index] = a[index]+b[index];
}
}
int main(int argc, char *argv[]) {
char key;
int i, j; // loop counters
int Grid_Dim_x=1, Grid_Dim_y=1; //Grid structure values
int Block_Dim_x=1, Block_Dim_y=1; //Block structure values
int noThreads_x, noThreads_y; // number of threads available in device, each dimension
int noThreads_block; // number of threads in a block
int N = 10; // size of array in each dimension
int *a,*b,*c,*d;
int *dev_a, *dev_b, *dev_c;
int size; // number of bytes in arrays
cudaEvent_t start, stop; // using cuda events to measure time
float elapsed_time_ms; // which is applicable for asynchronous code also
/* --------------------ENTER INPUT PARAMETERS AND DATA -----------------------*/
do { // loop to repeat complete program
printf ("Device characteristics -- some limitations (compute capability 1.0)\n");
printf (" Maximum number of threads per block = 512\n");
printf (" Maximum sizes of x- and y- dimension of thread block = 512\n");
printf (" Maximum size of each dimension of grid of thread blocks = 65535\n");
printf("Enter size of array in one dimension (square array), currently %d\n",N);
scanf("%d",&N);
do {
printf("\nEnter nuumber of blocks per grid in x dimension), currently %d : ",Grid_Dim_x);
scanf("%d",&Grid_Dim_x);
printf("\nEnter nuumber of blocks per grid in y dimension), currently %d : ",Grid_Dim_y);
scanf("%d",&Grid_Dim_y);
printf("\nEnter nuumber of threads per block in x dimension), currently %d : ",Block_Dim_x);
scanf("%d",&Block_Dim_x);
printf("\nEnter nuumber of threads per block in y dimension), currently %d : ",Block_Dim_y);
scanf("%d",&Block_Dim_y);
noThreads_x = Grid_Dim_x * Block_Dim_x; // number of threads in x dimension
noThreads_y = Grid_Dim_y * Block_Dim_y; // number of threads in y dimension
noThreads_block = Block_Dim_x * Block_Dim_y; // number of threads in a block
if (noThreads_x < N) printf("Error -- number of threads in x dimension less than number of elements in arrays, try again\n");
else if (noThreads_y < N) printf("Error -- number of threads in y dimension less than number of elements in arrays, try again\n");
else if (noThreads_block > 512) printf("Error -- too many threads in block, try again\n");
else printf("Number of threads not used = %d\n", noThreads_x * noThreads_y - N * N);
} while (noThreads_x < N || noThreads_y < N || noThreads_block > 512);
dim3 Grid(Grid_Dim_x, Grid_Dim_x); //Grid structure
dim3 Block(Block_Dim_x,Block_Dim_y); //Block structure, threads/block limited by specific device
size = N * N * sizeof(int); // number of bytes in total in arrays
a = (int*) malloc(size); //this time use dynamically allocated memory for arrays on host
b = (int*) malloc(size);
c = (int*) malloc(size); // results from GPU
d = (int*) malloc(size); // results from CPU
for(i=0;i < N;i++) // load arrays with some numbers
for(j=0;j < N;j++) {
a[i * N + j] = i;
b[i * N + j] = i;
}
/* ------------- COMPUTATION DONE ON GPU ----------------------------*/
cudaMalloc((void**)&dev_a, size); // allocate memory on device
cudaMalloc((void**)&dev_b, size);
cudaMalloc((void**)&dev_c, size);
cudaMemcpy(dev_a, a , size ,cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b , size ,cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c , size ,cudaMemcpyHostToDevice);
cudaEventCreate(&start); // instrument code to measure start time
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// cudaEventSynchronize(start); // Needed?
gpu_matrixadd<<<Grid,Block>>>(dev_a,dev_b,dev_c,N);
cudaMemcpy(c,dev_c, size ,cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0); // instrument code to measue end time
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time_ms, start, stop );
// for(i=0;i < N;i++)
// for(j=0;j < N;j++)
// printf("%d+%d=%d\n",a[i * N + j],b[i * N + j],c[i * N + j]);
printf("Time to calculate results on GPU: %f ms.\n", elapsed_time_ms); // print out execution time
/* ------------- COMPUTATION DONE ON HOST CPU ----------------------------*/
cudaEventRecord(start, 0); // use same timing
// cudaEventSynchronize(start); // Needed?
cpu_matrixadd(a,b,d,N); // do calculation on host
cudaEventRecord(stop, 0); // instrument code to measue end time
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time_ms, start, stop );
printf("Time to calculate results on CPU: %f ms.\n", elapsed_time_ms); // print out execution time
/* ------------------- check device creates correct results -----------------*/
for(i=0;i < N*N;i++) {
if (c[i] != d[i]) printf("*********** ERROR in results, CPU and GPU create different answers ********\n");
break;
}
printf("\nEnter c to repeat, return to terminate\n");
scanf("%c",&key);
scanf("%c",&key);
} while (key == 'c'); // loop of complete program
/* -------------- clean up ---------------------------------------*/
free(a);
free(b);
free(c);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | .file "tmpxft_0003befe_00000000-6_2_Matrix_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13cpu_matrixaddPiS_S_i
.type _Z13cpu_matrixaddPiS_S_i, @function
_Z13cpu_matrixaddPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L9
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r9
movslq %ecx, %rbx
leaq 0(,%rbx,4), %r10
movl $0, %r11d
.L5:
leaq 0(,%r11,4), %rax
movl $0, %r8d
.L6:
movl (%rsi,%rax), %edi
addl (%r9,%rax), %edi
movl %edi, (%rdx,%rax)
addl $1, %r8d
addq %r10, %rax
cmpl %r8d, %ecx
jne .L6
addq $1, %r11
cmpq %rbx, %r11
jne .L5
popq %rbx
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore 3
ret
.cfi_endproc
.LFE2057:
.size _Z13cpu_matrixaddPiS_S_i, .-_Z13cpu_matrixaddPiS_S_i
.globl _Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i
.type _Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i, @function
_Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13gpu_matrixaddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i, .-_Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i
.globl _Z13gpu_matrixaddPiS_S_i
.type _Z13gpu_matrixaddPiS_S_i, @function
_Z13gpu_matrixaddPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13gpu_matrixaddPiS_S_i, .-_Z13gpu_matrixaddPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Device characteristics -- some limitations (compute capability 1.0)\n"
.align 8
.LC1:
.string "\t\tMaximum number of threads per block = 512\n"
.align 8
.LC2:
.string "\t\tMaximum sizes of x- and y- dimension of thread block = 512\n"
.align 8
.LC3:
.string "\t\tMaximum size of each dimension of grid of thread blocks = 65535\n"
.align 8
.LC4:
.string "Enter size of array in one dimension (square array), currently %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%d"
.section .rodata.str1.8
.align 8
.LC6:
.string "\nEnter nuumber of blocks per grid in x dimension), currently %d : "
.align 8
.LC7:
.string "\nEnter nuumber of blocks per grid in y dimension), currently %d : "
.align 8
.LC8:
.string "\nEnter nuumber of threads per block in x dimension), currently %d : "
.align 8
.LC9:
.string "\nEnter nuumber of threads per block in y dimension), currently %d : "
.align 8
.LC10:
.string "Error -- number of threads in x dimension less than number of elements in arrays, try again\n"
.align 8
.LC11:
.string "Error -- number of threads in y dimension less than number of elements in arrays, try again\n"
.align 8
.LC12:
.string "Error -- too many threads in block, try again\n"
.align 8
.LC13:
.string "Number of threads not used = %d\n"
.align 8
.LC14:
.string "Time to calculate results on GPU: %f ms.\n"
.align 8
.LC15:
.string "Time to calculate results on CPU: %f ms.\n"
.align 8
.LC16:
.string "*********** ERROR in results, CPU and GPU create different answers ********\n"
.align 8
.LC17:
.string "\nEnter c to repeat, return to terminate\n"
.section .rodata.str1.1
.LC18:
.string "%c"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 48(%rsp)
leaq .LC5(%rip), %r12
jmp .L34
.L40:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
movl 48(%rsp), %r14d
cmpl %r13d, %ebx
cmovg %r13d, %ebx
cmpl %ebx, %r14d
jg .L28
cmpl $512, %ebp
jle .L39
.L28:
movl 32(%rsp), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 36(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 36(%rsp), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 40(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 44(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 44(%rsp), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 40(%rsp), %ebp
movl %ebp, %ebx
imull 32(%rsp), %ebx
movl 44(%rsp), %eax
movl %eax, %r13d
imull 36(%rsp), %r13d
imull %eax, %ebp
movl 48(%rsp), %eax
cmpl %ebx, %eax
jg .L40
cmpl %r13d, %eax
jg .L41
cmpl $512, %ebp
jle .L24
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L41:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L24:
movl %ebx, %edx
imull %r13d, %edx
imull %eax, %eax
subl %eax, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L39:
movl 32(%rsp), %eax
movl %eax, 96(%rsp)
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl 40(%rsp), %eax
movl %eax, 108(%rsp)
movl 44(%rsp), %eax
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
movl %r14d, %r13d
imull %r14d, %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
movq %r13, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %r14d, %r14d
jle .L29
movslq %r14d, %rsi
leaq 0(,%rsi,4), %rdi
negq %rsi
salq $2, %rsi
movq %rdi, %rcx
movl $0, %edx
.L30:
leaq (%rcx,%rsi), %rax
.L31:
movl %edx, 0(%rbp,%rax)
movl %edx, (%rbx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L31
addl $1, %edx
addq %rdi, %rcx
cmpl %edx, %r14d
jne .L30
.L29:
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl 116(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movq 96(%rsp), %rdi
movl 104(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L32:
movl $2, %ecx
movq %r13, %rdx
movq 72(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %r13
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq %r13, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl 48(%rsp), %ecx
movq 8(%rsp), %r14
movq %r14, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z13cpu_matrixaddPiS_S_i
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq %r13, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 48(%rsp), %eax
imull %eax, %eax
testl %eax, %eax
jle .L33
movl (%r14), %eax
cmpl %eax, (%r15)
jne .L43
.L33:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 31(%rsp), %r14
movq %r14, %rsi
leaq .LC18(%rip), %r13
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %r14, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpb $99, 31(%rsp)
jne .L44
.L34:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 48(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC6(%rip), %r15
jmp .L28
.L42:
movl 48(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i
jmp .L32
.L43:
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L33
.L44:
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L45
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z13gpu_matrixaddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z13gpu_matrixaddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Program for Matrix Addition in CUDA
// For Hadoop-CUDA Lab
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
__global__ void gpu_matrixadd(int *a,int *b, int *c, int N) {
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int index = row * N + col;
if(col < N && row < N)
c[index] = a[index]+b[index];
}
void cpu_matrixadd(int *a,int *b, int *c, int N) {
int index;
for(int col=0;col < N; col++)
for(int row=0;row < N; row++) {
index = row * N + col;
c[index] = a[index]+b[index];
}
}
int main(int argc, char *argv[]) {
char key;
int i, j; // loop counters
int Grid_Dim_x=1, Grid_Dim_y=1; //Grid structure values
int Block_Dim_x=1, Block_Dim_y=1; //Block structure values
int noThreads_x, noThreads_y; // number of threads available in device, each dimension
int noThreads_block; // number of threads in a block
int N = 10; // size of array in each dimension
int *a,*b,*c,*d;
int *dev_a, *dev_b, *dev_c;
int size; // number of bytes in arrays
cudaEvent_t start, stop; // using cuda events to measure time
float elapsed_time_ms; // which is applicable for asynchronous code also
/* --------------------ENTER INPUT PARAMETERS AND DATA -----------------------*/
do { // loop to repeat complete program
printf ("Device characteristics -- some limitations (compute capability 1.0)\n");
printf (" Maximum number of threads per block = 512\n");
printf (" Maximum sizes of x- and y- dimension of thread block = 512\n");
printf (" Maximum size of each dimension of grid of thread blocks = 65535\n");
printf("Enter size of array in one dimension (square array), currently %d\n",N);
scanf("%d",&N);
do {
printf("\nEnter nuumber of blocks per grid in x dimension), currently %d : ",Grid_Dim_x);
scanf("%d",&Grid_Dim_x);
printf("\nEnter nuumber of blocks per grid in y dimension), currently %d : ",Grid_Dim_y);
scanf("%d",&Grid_Dim_y);
printf("\nEnter nuumber of threads per block in x dimension), currently %d : ",Block_Dim_x);
scanf("%d",&Block_Dim_x);
printf("\nEnter nuumber of threads per block in y dimension), currently %d : ",Block_Dim_y);
scanf("%d",&Block_Dim_y);
noThreads_x = Grid_Dim_x * Block_Dim_x; // number of threads in x dimension
noThreads_y = Grid_Dim_y * Block_Dim_y; // number of threads in y dimension
noThreads_block = Block_Dim_x * Block_Dim_y; // number of threads in a block
if (noThreads_x < N) printf("Error -- number of threads in x dimension less than number of elements in arrays, try again\n");
else if (noThreads_y < N) printf("Error -- number of threads in y dimension less than number of elements in arrays, try again\n");
else if (noThreads_block > 512) printf("Error -- too many threads in block, try again\n");
else printf("Number of threads not used = %d\n", noThreads_x * noThreads_y - N * N);
} while (noThreads_x < N || noThreads_y < N || noThreads_block > 512);
dim3 Grid(Grid_Dim_x, Grid_Dim_x); //Grid structure
dim3 Block(Block_Dim_x,Block_Dim_y); //Block structure, threads/block limited by specific device
size = N * N * sizeof(int); // number of bytes in total in arrays
a = (int*) malloc(size); //this time use dynamically allocated memory for arrays on host
b = (int*) malloc(size);
c = (int*) malloc(size); // results from GPU
d = (int*) malloc(size); // results from CPU
for(i=0;i < N;i++) // load arrays with some numbers
for(j=0;j < N;j++) {
a[i * N + j] = i;
b[i * N + j] = i;
}
/* ------------- COMPUTATION DONE ON GPU ----------------------------*/
cudaMalloc((void**)&dev_a, size); // allocate memory on device
cudaMalloc((void**)&dev_b, size);
cudaMalloc((void**)&dev_c, size);
cudaMemcpy(dev_a, a , size ,cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b , size ,cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c , size ,cudaMemcpyHostToDevice);
cudaEventCreate(&start); // instrument code to measure start time
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// cudaEventSynchronize(start); // Needed?
gpu_matrixadd<<<Grid,Block>>>(dev_a,dev_b,dev_c,N);
cudaMemcpy(c,dev_c, size ,cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0); // instrument code to measue end time
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time_ms, start, stop );
// for(i=0;i < N;i++)
// for(j=0;j < N;j++)
// printf("%d+%d=%d\n",a[i * N + j],b[i * N + j],c[i * N + j]);
printf("Time to calculate results on GPU: %f ms.\n", elapsed_time_ms); // print out execution time
/* ------------- COMPUTATION DONE ON HOST CPU ----------------------------*/
cudaEventRecord(start, 0); // use same timing
// cudaEventSynchronize(start); // Needed?
cpu_matrixadd(a,b,d,N); // do calculation on host
cudaEventRecord(stop, 0); // instrument code to measue end time
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time_ms, start, stop );
printf("Time to calculate results on CPU: %f ms.\n", elapsed_time_ms); // print out execution time
/* ------------------- check device creates correct results -----------------*/
for(i=0;i < N*N;i++) {
if (c[i] != d[i]) printf("*********** ERROR in results, CPU and GPU create different answers ********\n");
break;
}
printf("\nEnter c to repeat, return to terminate\n");
scanf("%c",&key);
scanf("%c",&key);
} while (key == 'c'); // loop of complete program
/* -------------- clean up ---------------------------------------*/
free(a);
free(b);
free(c);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | // Program for Matrix Addition in CUDA
// For Hadoop-CUDA Lab
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
__global__ void gpu_matrixadd(int *a,int *b, int *c, int N) {
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int index = row * N + col;
if(col < N && row < N)
c[index] = a[index]+b[index];
}
void cpu_matrixadd(int *a,int *b, int *c, int N) {
int index;
for(int col=0;col < N; col++)
for(int row=0;row < N; row++) {
index = row * N + col;
c[index] = a[index]+b[index];
}
}
int main(int argc, char *argv[]) {
char key;
int i, j; // loop counters
int Grid_Dim_x=1, Grid_Dim_y=1; //Grid structure values
int Block_Dim_x=1, Block_Dim_y=1; //Block structure values
int noThreads_x, noThreads_y; // number of threads available in device, each dimension
int noThreads_block; // number of threads in a block
int N = 10; // size of array in each dimension
int *a,*b,*c,*d;
int *dev_a, *dev_b, *dev_c;
int size; // number of bytes in arrays
hipEvent_t start, stop; // using cuda events to measure time
float elapsed_time_ms; // which is applicable for asynchronous code also
/* --------------------ENTER INPUT PARAMETERS AND DATA -----------------------*/
do { // loop to repeat complete program
printf ("Device characteristics -- some limitations (compute capability 1.0)\n");
printf (" Maximum number of threads per block = 512\n");
printf (" Maximum sizes of x- and y- dimension of thread block = 512\n");
printf (" Maximum size of each dimension of grid of thread blocks = 65535\n");
printf("Enter size of array in one dimension (square array), currently %d\n",N);
scanf("%d",&N);
do {
printf("\nEnter nuumber of blocks per grid in x dimension), currently %d : ",Grid_Dim_x);
scanf("%d",&Grid_Dim_x);
printf("\nEnter nuumber of blocks per grid in y dimension), currently %d : ",Grid_Dim_y);
scanf("%d",&Grid_Dim_y);
printf("\nEnter nuumber of threads per block in x dimension), currently %d : ",Block_Dim_x);
scanf("%d",&Block_Dim_x);
printf("\nEnter nuumber of threads per block in y dimension), currently %d : ",Block_Dim_y);
scanf("%d",&Block_Dim_y);
noThreads_x = Grid_Dim_x * Block_Dim_x; // number of threads in x dimension
noThreads_y = Grid_Dim_y * Block_Dim_y; // number of threads in y dimension
noThreads_block = Block_Dim_x * Block_Dim_y; // number of threads in a block
if (noThreads_x < N) printf("Error -- number of threads in x dimension less than number of elements in arrays, try again\n");
else if (noThreads_y < N) printf("Error -- number of threads in y dimension less than number of elements in arrays, try again\n");
else if (noThreads_block > 512) printf("Error -- too many threads in block, try again\n");
else printf("Number of threads not used = %d\n", noThreads_x * noThreads_y - N * N);
} while (noThreads_x < N || noThreads_y < N || noThreads_block > 512);
dim3 Grid(Grid_Dim_x, Grid_Dim_x); //Grid structure
dim3 Block(Block_Dim_x,Block_Dim_y); //Block structure, threads/block limited by specific device
size = N * N * sizeof(int); // number of bytes in total in arrays
a = (int*) malloc(size); //this time use dynamically allocated memory for arrays on host
b = (int*) malloc(size);
c = (int*) malloc(size); // results from GPU
d = (int*) malloc(size); // results from CPU
for(i=0;i < N;i++) // load arrays with some numbers
for(j=0;j < N;j++) {
a[i * N + j] = i;
b[i * N + j] = i;
}
/* ------------- COMPUTATION DONE ON GPU ----------------------------*/
hipMalloc((void**)&dev_a, size); // allocate memory on device
hipMalloc((void**)&dev_b, size);
hipMalloc((void**)&dev_c, size);
hipMemcpy(dev_a, a , size ,hipMemcpyHostToDevice);
hipMemcpy(dev_b, b , size ,hipMemcpyHostToDevice);
hipMemcpy(dev_c, c , size ,hipMemcpyHostToDevice);
hipEventCreate(&start); // instrument code to measure start time
hipEventCreate(&stop);
hipEventRecord(start, 0);
// cudaEventSynchronize(start); // Needed?
gpu_matrixadd<<<Grid,Block>>>(dev_a,dev_b,dev_c,N);
hipMemcpy(c,dev_c, size ,hipMemcpyDeviceToHost);
hipEventRecord(stop, 0); // instrument code to measue end time
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time_ms, start, stop );
// for(i=0;i < N;i++)
// for(j=0;j < N;j++)
// printf("%d+%d=%d\n",a[i * N + j],b[i * N + j],c[i * N + j]);
printf("Time to calculate results on GPU: %f ms.\n", elapsed_time_ms); // print out execution time
/* ------------- COMPUTATION DONE ON HOST CPU ----------------------------*/
hipEventRecord(start, 0); // use same timing
// cudaEventSynchronize(start); // Needed?
cpu_matrixadd(a,b,d,N); // do calculation on host
hipEventRecord(stop, 0); // instrument code to measue end time
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time_ms, start, stop );
printf("Time to calculate results on CPU: %f ms.\n", elapsed_time_ms); // print out execution time
/* ------------------- check device creates correct results -----------------*/
for(i=0;i < N*N;i++) {
if (c[i] != d[i]) printf("*********** ERROR in results, CPU and GPU create different answers ********\n");
break;
}
printf("\nEnter c to repeat, return to terminate\n");
scanf("%c",&key);
scanf("%c",&key);
} while (key == 'c'); // loop of complete program
/* -------------- clean up ---------------------------------------*/
free(a);
free(b);
free(c);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Program for Matrix Addition in CUDA
// For Hadoop-CUDA Lab
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
__global__ void gpu_matrixadd(int *a,int *b, int *c, int N) {
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int index = row * N + col;
if(col < N && row < N)
c[index] = a[index]+b[index];
}
void cpu_matrixadd(int *a,int *b, int *c, int N) {
int index;
for(int col=0;col < N; col++)
for(int row=0;row < N; row++) {
index = row * N + col;
c[index] = a[index]+b[index];
}
}
int main(int argc, char *argv[]) {
char key;
int i, j; // loop counters
int Grid_Dim_x=1, Grid_Dim_y=1; //Grid structure values
int Block_Dim_x=1, Block_Dim_y=1; //Block structure values
int noThreads_x, noThreads_y; // number of threads available in device, each dimension
int noThreads_block; // number of threads in a block
int N = 10; // size of array in each dimension
int *a,*b,*c,*d;
int *dev_a, *dev_b, *dev_c;
int size; // number of bytes in arrays
hipEvent_t start, stop; // using cuda events to measure time
float elapsed_time_ms; // which is applicable for asynchronous code also
/* --------------------ENTER INPUT PARAMETERS AND DATA -----------------------*/
do { // loop to repeat complete program
printf ("Device characteristics -- some limitations (compute capability 1.0)\n");
printf (" Maximum number of threads per block = 512\n");
printf (" Maximum sizes of x- and y- dimension of thread block = 512\n");
printf (" Maximum size of each dimension of grid of thread blocks = 65535\n");
printf("Enter size of array in one dimension (square array), currently %d\n",N);
scanf("%d",&N);
do {
printf("\nEnter nuumber of blocks per grid in x dimension), currently %d : ",Grid_Dim_x);
scanf("%d",&Grid_Dim_x);
printf("\nEnter nuumber of blocks per grid in y dimension), currently %d : ",Grid_Dim_y);
scanf("%d",&Grid_Dim_y);
printf("\nEnter nuumber of threads per block in x dimension), currently %d : ",Block_Dim_x);
scanf("%d",&Block_Dim_x);
printf("\nEnter nuumber of threads per block in y dimension), currently %d : ",Block_Dim_y);
scanf("%d",&Block_Dim_y);
noThreads_x = Grid_Dim_x * Block_Dim_x; // number of threads in x dimension
noThreads_y = Grid_Dim_y * Block_Dim_y; // number of threads in y dimension
noThreads_block = Block_Dim_x * Block_Dim_y; // number of threads in a block
if (noThreads_x < N) printf("Error -- number of threads in x dimension less than number of elements in arrays, try again\n");
else if (noThreads_y < N) printf("Error -- number of threads in y dimension less than number of elements in arrays, try again\n");
else if (noThreads_block > 512) printf("Error -- too many threads in block, try again\n");
else printf("Number of threads not used = %d\n", noThreads_x * noThreads_y - N * N);
} while (noThreads_x < N || noThreads_y < N || noThreads_block > 512);
dim3 Grid(Grid_Dim_x, Grid_Dim_x); //Grid structure
dim3 Block(Block_Dim_x,Block_Dim_y); //Block structure, threads/block limited by specific device
size = N * N * sizeof(int); // number of bytes in total in arrays
a = (int*) malloc(size); //this time use dynamically allocated memory for arrays on host
b = (int*) malloc(size);
c = (int*) malloc(size); // results from GPU
d = (int*) malloc(size); // results from CPU
for(i=0;i < N;i++) // load arrays with some numbers
for(j=0;j < N;j++) {
a[i * N + j] = i;
b[i * N + j] = i;
}
/* ------------- COMPUTATION DONE ON GPU ----------------------------*/
hipMalloc((void**)&dev_a, size); // allocate memory on device
hipMalloc((void**)&dev_b, size);
hipMalloc((void**)&dev_c, size);
hipMemcpy(dev_a, a , size ,hipMemcpyHostToDevice);
hipMemcpy(dev_b, b , size ,hipMemcpyHostToDevice);
hipMemcpy(dev_c, c , size ,hipMemcpyHostToDevice);
hipEventCreate(&start); // instrument code to measure start time
hipEventCreate(&stop);
hipEventRecord(start, 0);
// cudaEventSynchronize(start); // Needed?
gpu_matrixadd<<<Grid,Block>>>(dev_a,dev_b,dev_c,N);
hipMemcpy(c,dev_c, size ,hipMemcpyDeviceToHost);
hipEventRecord(stop, 0); // instrument code to measue end time
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time_ms, start, stop );
// for(i=0;i < N;i++)
// for(j=0;j < N;j++)
// printf("%d+%d=%d\n",a[i * N + j],b[i * N + j],c[i * N + j]);
printf("Time to calculate results on GPU: %f ms.\n", elapsed_time_ms); // print out execution time
/* ------------- COMPUTATION DONE ON HOST CPU ----------------------------*/
hipEventRecord(start, 0); // use same timing
// cudaEventSynchronize(start); // Needed?
cpu_matrixadd(a,b,d,N); // do calculation on host
hipEventRecord(stop, 0); // instrument code to measue end time
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time_ms, start, stop );
printf("Time to calculate results on CPU: %f ms.\n", elapsed_time_ms); // print out execution time
/* ------------------- check device creates correct results -----------------*/
for(i=0;i < N*N;i++) {
if (c[i] != d[i]) printf("*********** ERROR in results, CPU and GPU create different answers ********\n");
break;
}
printf("\nEnter c to repeat, return to terminate\n");
scanf("%c",&key);
scanf("%c",&key);
} while (key == 'c'); // loop of complete program
/* -------------- clean up ---------------------------------------*/
free(a);
free(b);
free(c);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13gpu_matrixaddPiS_S_i
.globl _Z13gpu_matrixaddPiS_S_i
.p2align 8
.type _Z13gpu_matrixaddPiS_S_i,@function
_Z13gpu_matrixaddPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13gpu_matrixaddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13gpu_matrixaddPiS_S_i, .Lfunc_end0-_Z13gpu_matrixaddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13gpu_matrixaddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13gpu_matrixaddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Program for Matrix Addition in CUDA
// For Hadoop-CUDA Lab
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
__global__ void gpu_matrixadd(int *a,int *b, int *c, int N) {
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int index = row * N + col;
if(col < N && row < N)
c[index] = a[index]+b[index];
}
void cpu_matrixadd(int *a,int *b, int *c, int N) {
int index;
for(int col=0;col < N; col++)
for(int row=0;row < N; row++) {
index = row * N + col;
c[index] = a[index]+b[index];
}
}
int main(int argc, char *argv[]) {
char key;
int i, j; // loop counters
int Grid_Dim_x=1, Grid_Dim_y=1; //Grid structure values
int Block_Dim_x=1, Block_Dim_y=1; //Block structure values
int noThreads_x, noThreads_y; // number of threads available in device, each dimension
int noThreads_block; // number of threads in a block
int N = 10; // size of array in each dimension
int *a,*b,*c,*d;
int *dev_a, *dev_b, *dev_c;
int size; // number of bytes in arrays
hipEvent_t start, stop; // using cuda events to measure time
float elapsed_time_ms; // which is applicable for asynchronous code also
/* --------------------ENTER INPUT PARAMETERS AND DATA -----------------------*/
do { // loop to repeat complete program
printf ("Device characteristics -- some limitations (compute capability 1.0)\n");
printf (" Maximum number of threads per block = 512\n");
printf (" Maximum sizes of x- and y- dimension of thread block = 512\n");
printf (" Maximum size of each dimension of grid of thread blocks = 65535\n");
printf("Enter size of array in one dimension (square array), currently %d\n",N);
scanf("%d",&N);
do {
printf("\nEnter nuumber of blocks per grid in x dimension), currently %d : ",Grid_Dim_x);
scanf("%d",&Grid_Dim_x);
printf("\nEnter nuumber of blocks per grid in y dimension), currently %d : ",Grid_Dim_y);
scanf("%d",&Grid_Dim_y);
printf("\nEnter nuumber of threads per block in x dimension), currently %d : ",Block_Dim_x);
scanf("%d",&Block_Dim_x);
printf("\nEnter nuumber of threads per block in y dimension), currently %d : ",Block_Dim_y);
scanf("%d",&Block_Dim_y);
noThreads_x = Grid_Dim_x * Block_Dim_x; // number of threads in x dimension
noThreads_y = Grid_Dim_y * Block_Dim_y; // number of threads in y dimension
noThreads_block = Block_Dim_x * Block_Dim_y; // number of threads in a block
if (noThreads_x < N) printf("Error -- number of threads in x dimension less than number of elements in arrays, try again\n");
else if (noThreads_y < N) printf("Error -- number of threads in y dimension less than number of elements in arrays, try again\n");
else if (noThreads_block > 512) printf("Error -- too many threads in block, try again\n");
else printf("Number of threads not used = %d\n", noThreads_x * noThreads_y - N * N);
} while (noThreads_x < N || noThreads_y < N || noThreads_block > 512);
dim3 Grid(Grid_Dim_x, Grid_Dim_x); //Grid structure
dim3 Block(Block_Dim_x,Block_Dim_y); //Block structure, threads/block limited by specific device
size = N * N * sizeof(int); // number of bytes in total in arrays
a = (int*) malloc(size); //this time use dynamically allocated memory for arrays on host
b = (int*) malloc(size);
c = (int*) malloc(size); // results from GPU
d = (int*) malloc(size); // results from CPU
for(i=0;i < N;i++) // load arrays with some numbers
for(j=0;j < N;j++) {
a[i * N + j] = i;
b[i * N + j] = i;
}
/* ------------- COMPUTATION DONE ON GPU ----------------------------*/
hipMalloc((void**)&dev_a, size); // allocate memory on device
hipMalloc((void**)&dev_b, size);
hipMalloc((void**)&dev_c, size);
hipMemcpy(dev_a, a , size ,hipMemcpyHostToDevice);
hipMemcpy(dev_b, b , size ,hipMemcpyHostToDevice);
hipMemcpy(dev_c, c , size ,hipMemcpyHostToDevice);
hipEventCreate(&start); // instrument code to measure start time
hipEventCreate(&stop);
hipEventRecord(start, 0);
// cudaEventSynchronize(start); // Needed?
gpu_matrixadd<<<Grid,Block>>>(dev_a,dev_b,dev_c,N);
hipMemcpy(c,dev_c, size ,hipMemcpyDeviceToHost);
hipEventRecord(stop, 0); // instrument code to measue end time
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time_ms, start, stop );
// for(i=0;i < N;i++)
// for(j=0;j < N;j++)
// printf("%d+%d=%d\n",a[i * N + j],b[i * N + j],c[i * N + j]);
printf("Time to calculate results on GPU: %f ms.\n", elapsed_time_ms); // print out execution time
/* ------------- COMPUTATION DONE ON HOST CPU ----------------------------*/
hipEventRecord(start, 0); // use same timing
// cudaEventSynchronize(start); // Needed?
cpu_matrixadd(a,b,d,N); // do calculation on host
hipEventRecord(stop, 0); // instrument code to measue end time
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time_ms, start, stop );
printf("Time to calculate results on CPU: %f ms.\n", elapsed_time_ms); // print out execution time
/* ------------------- check device creates correct results -----------------*/
for(i=0;i < N*N;i++) {
if (c[i] != d[i]) printf("*********** ERROR in results, CPU and GPU create different answers ********\n");
break;
}
printf("\nEnter c to repeat, return to terminate\n");
scanf("%c",&key);
scanf("%c",&key);
} while (key == 'c'); // loop of complete program
/* -------------- clean up ---------------------------------------*/
free(a);
free(b);
free(c);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.file "2_Matrix_addition.hip"
.globl _Z28__device_stub__gpu_matrixaddPiS_S_i # -- Begin function _Z28__device_stub__gpu_matrixaddPiS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__gpu_matrixaddPiS_S_i,@function
_Z28__device_stub__gpu_matrixaddPiS_S_i: # @_Z28__device_stub__gpu_matrixaddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13gpu_matrixaddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__gpu_matrixaddPiS_S_i, .Lfunc_end0-_Z28__device_stub__gpu_matrixaddPiS_S_i
.cfi_endproc
# -- End function
.globl _Z13cpu_matrixaddPiS_S_i # -- Begin function _Z13cpu_matrixaddPiS_S_i
.p2align 4, 0x90
.type _Z13cpu_matrixaddPiS_S_i,@function
_Z13cpu_matrixaddPiS_S_i: # @_Z13cpu_matrixaddPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movq %rax, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%r10), %r11d
addl (%rdi,%r10), %r11d
movl %r11d, (%rdx,%r10)
addq %rcx, %r10
decq %r9
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r8
addq $4, %rdx
addq $4, %rsi
addq $4, %rdi
cmpq %rax, %r8
jne .LBB1_2
.LBB1_5: # %._crit_edge18
retq
.Lfunc_end1:
.size _Z13cpu_matrixaddPiS_S_i, .Lfunc_end1-_Z13cpu_matrixaddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1, 8(%rsp)
movl $1, 20(%rsp)
movl $1, 16(%rsp)
movl $1, 12(%rsp)
movl $10, (%rsp)
leaq 8(%rsp), %r15
leaq 20(%rsp), %r13
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_27: # in Loop: Header=BB2_1 Depth=1
movl $.Lstr.8, %edi
callq puts@PLT
movl $.L.str.18, %edi
leaq 7(%rsp), %r14
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.18, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
cmpb $99, 7(%rsp)
jne .LBB2_28
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_14 Depth 2
# Child Loop BB2_15 Depth 3
# Child Loop BB2_21 Depth 2
# Child Loop BB2_22 Depth 3
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl (%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movq %rsp, %rsi
xorl %eax, %eax
callq __isoc23_scanf
.p2align 4, 0x90
.LBB2_2: # %.critedge
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl 8(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl 20(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl 16(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
leaq 16(%rsp), %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
leaq 12(%rsp), %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl 16(%rsp), %eax
movl 8(%rsp), %ebp
imull %eax, %ebp
movl 12(%rsp), %ebx
movl 20(%rsp), %r14d
imull %ebx, %r14d
imull %eax, %ebx
movl (%rsp), %eax
cmpl %eax, %ebp
jge .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=2
movl $.Lstr.6, %edi
callq puts@PLT
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=2
cmpl %eax, %r14d
jge .LBB2_6
# %bb.5: # in Loop: Header=BB2_2 Depth=2
movl $.Lstr.5, %edi
callq puts@PLT
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_2 Depth=2
cmpl $513, %ebx # imm = 0x201
jl .LBB2_8
# %bb.7: # in Loop: Header=BB2_2 Depth=2
movl $.Lstr.4, %edi
callq puts@PLT
jmp .LBB2_9
.LBB2_8: # in Loop: Header=BB2_2 Depth=2
movl %r14d, %esi
imull %ebp, %esi
imull %eax, %eax
subl %eax, %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_2 Depth=2
movl (%rsp), %r12d
cmpl %r12d, %ebp
jl .LBB2_2
# %bb.10: # in Loop: Header=BB2_2 Depth=2
cmpl %r12d, %r14d
jl .LBB2_2
# %bb.11: # in Loop: Header=BB2_2 Depth=2
cmpl $512, %ebx # imm = 0x200
jg .LBB2_2
# %bb.12: # in Loop: Header=BB2_1 Depth=1
movl 8(%rsp), %r13d
movl 16(%rsp), %eax
movq %rax, 88(%rsp) # 8-byte Spill
movl 12(%rsp), %r15d
movl %r12d, %eax
imull %r12d, %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %rbp
movq %r14, %rdi
callq malloc
movq %rax, 96(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB2_17
# %bb.13: # %.preheader.preheader
# in Loop: Header=BB2_1 Depth=1
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_14: # %.preheader
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_15 Depth 3
movl %eax, %esi
leaq (,%rsi,4), %rdx
addq %rbp, %rdx
leaq (%rbx,%rsi,4), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_15: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_14 Depth=2
# => This Inner Loop Header: Depth=3
movl %ecx, (%rsi,%rdi,4)
movl %ecx, (%rdx,%rdi,4)
incq %rdi
cmpq %rdi, %r12
jne .LBB2_15
# %bb.16: # %._crit_edge
# in Loop: Header=BB2_14 Depth=2
incq %rcx
addl %r12d, %eax
cmpq %r12, %rcx
jne .LBB2_14
.LBB2_17: # %._crit_edge75
# in Loop: Header=BB2_1 Depth=1
movq %r13, %r12
shlq $32, %r12
orq %r13, %r12
shlq $32, %r15
addq 88(%rsp), %r15 # 8-byte Folded Reload
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 64(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 96(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_19
# %bb.18: # in Loop: Header=BB2_1 Depth=1
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movl (%rsp), %esi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 76(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 76(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movl $_Z13gpu_matrixaddPiS_S_i, %edi
leaq 176(%rsp), %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_19: # in Loop: Header=BB2_1 Depth=1
movq 48(%rsp), %rsi
movq %r13, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 44(%rsp), %r14
movq %r14, %rdi
callq hipEventElapsedTime
movss 44(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%rsp), %eax
testl %eax, %eax
leaq 8(%rsp), %r15
movq %r13, %r12
leaq 20(%rsp), %r13
jle .LBB2_24
# %bb.20: # %.preheader.lr.ph.i
# in Loop: Header=BB2_1 Depth=1
leaq (,%rax,4), %rcx
movq %rbx, %rdx
movq %rbp, %rsi
movq 80(%rsp), %rdi # 8-byte Reload
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_21: # %.preheader.i
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_22 Depth 3
xorl %r9d, %r9d
movq %rax, %r10
.p2align 4, 0x90
.LBB2_22: # %.lr.ph.i
# Parent Loop BB2_1 Depth=1
# Parent Loop BB2_21 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rsi,%r9), %r11d
addl (%rdx,%r9), %r11d
movl %r11d, (%rdi,%r9)
addq %rcx, %r9
decq %r10
jne .LBB2_22
# %bb.23: # %._crit_edge.i
# in Loop: Header=BB2_21 Depth=2
incq %r8
addq $4, %rdi
addq $4, %rsi
addq $4, %rdx
cmpq %rax, %r8
jne .LBB2_21
.LBB2_24: # %_Z13cpu_matrixaddPiS_S_i.exit
# in Loop: Header=BB2_1 Depth=1
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
movq %r14, %rdi
callq hipEventElapsedTime
movss 44(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
cmpl $0, (%rsp)
je .LBB2_27
# %bb.25: # in Loop: Header=BB2_1 Depth=1
movl (%r12), %eax
movq 80(%rsp), %rcx # 8-byte Reload
cmpl (%rcx), %eax
je .LBB2_27
# %bb.26: # in Loop: Header=BB2_1 Depth=1
movl $.Lstr.7, %edi
callq puts@PLT
jmp .LBB2_27
.LBB2_28:
movq %rbx, %rdi
callq free
movq %rbp, %rdi
callq free
movq %r12, %rdi
callq free
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpu_matrixaddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13gpu_matrixaddPiS_S_i,@object # @_Z13gpu_matrixaddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z13gpu_matrixaddPiS_S_i
.p2align 3, 0x0
_Z13gpu_matrixaddPiS_S_i:
.quad _Z28__device_stub__gpu_matrixaddPiS_S_i
.size _Z13gpu_matrixaddPiS_S_i, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Enter size of array in one dimension (square array), currently %d\n"
.size .L.str.4, 67
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\nEnter nuumber of blocks per grid in x dimension), currently %d : "
.size .L.str.6, 68
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\nEnter nuumber of blocks per grid in y dimension), currently %d : "
.size .L.str.7, 68
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\nEnter nuumber of threads per block in x dimension), currently %d : "
.size .L.str.8, 70
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\nEnter nuumber of threads per block in y dimension), currently %d : "
.size .L.str.9, 70
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Number of threads not used = %d\n"
.size .L.str.13, 33
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Time to calculate results on GPU: %f ms.\n"
.size .L.str.14, 42
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Time to calculate results on CPU: %f ms.\n"
.size .L.str.15, 42
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "%c"
.size .L.str.18, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13gpu_matrixaddPiS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Device characteristics -- some limitations (compute capability 1.0)"
.size .Lstr, 68
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\t\tMaximum number of threads per block = 512"
.size .Lstr.1, 44
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\t\tMaximum sizes of x- and y- dimension of thread block = 512"
.size .Lstr.2, 61
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\t\tMaximum size of each dimension of grid of thread blocks = 65535"
.size .Lstr.3, 66
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error -- too many threads in block, try again"
.size .Lstr.4, 46
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Error -- number of threads in y dimension less than number of elements in arrays, try again"
.size .Lstr.5, 92
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Error -- number of threads in x dimension less than number of elements in arrays, try again"
.size .Lstr.6, 92
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "*********** ERROR in results, CPU and GPU create different answers ********"
.size .Lstr.7, 76
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "\nEnter c to repeat, return to terminate"
.size .Lstr.8, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__gpu_matrixaddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13gpu_matrixaddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13gpu_matrixaddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0120*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13gpu_matrixaddPiS_S_i
.globl _Z13gpu_matrixaddPiS_S_i
.p2align 8
.type _Z13gpu_matrixaddPiS_S_i,@function
_Z13gpu_matrixaddPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13gpu_matrixaddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13gpu_matrixaddPiS_S_i, .Lfunc_end0-_Z13gpu_matrixaddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13gpu_matrixaddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13gpu_matrixaddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003befe_00000000-6_2_Matrix_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13cpu_matrixaddPiS_S_i
.type _Z13cpu_matrixaddPiS_S_i, @function
_Z13cpu_matrixaddPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L9
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r9
movslq %ecx, %rbx
leaq 0(,%rbx,4), %r10
movl $0, %r11d
.L5:
leaq 0(,%r11,4), %rax
movl $0, %r8d
.L6:
movl (%rsi,%rax), %edi
addl (%r9,%rax), %edi
movl %edi, (%rdx,%rax)
addl $1, %r8d
addq %r10, %rax
cmpl %r8d, %ecx
jne .L6
addq $1, %r11
cmpq %rbx, %r11
jne .L5
popq %rbx
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore 3
ret
.cfi_endproc
.LFE2057:
.size _Z13cpu_matrixaddPiS_S_i, .-_Z13cpu_matrixaddPiS_S_i
.globl _Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i
.type _Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i, @function
_Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13gpu_matrixaddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i, .-_Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i
.globl _Z13gpu_matrixaddPiS_S_i
.type _Z13gpu_matrixaddPiS_S_i, @function
_Z13gpu_matrixaddPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13gpu_matrixaddPiS_S_i, .-_Z13gpu_matrixaddPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Device characteristics -- some limitations (compute capability 1.0)\n"
.align 8
.LC1:
.string "\t\tMaximum number of threads per block = 512\n"
.align 8
.LC2:
.string "\t\tMaximum sizes of x- and y- dimension of thread block = 512\n"
.align 8
.LC3:
.string "\t\tMaximum size of each dimension of grid of thread blocks = 65535\n"
.align 8
.LC4:
.string "Enter size of array in one dimension (square array), currently %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%d"
.section .rodata.str1.8
.align 8
.LC6:
.string "\nEnter nuumber of blocks per grid in x dimension), currently %d : "
.align 8
.LC7:
.string "\nEnter nuumber of blocks per grid in y dimension), currently %d : "
.align 8
.LC8:
.string "\nEnter nuumber of threads per block in x dimension), currently %d : "
.align 8
.LC9:
.string "\nEnter nuumber of threads per block in y dimension), currently %d : "
.align 8
.LC10:
.string "Error -- number of threads in x dimension less than number of elements in arrays, try again\n"
.align 8
.LC11:
.string "Error -- number of threads in y dimension less than number of elements in arrays, try again\n"
.align 8
.LC12:
.string "Error -- too many threads in block, try again\n"
.align 8
.LC13:
.string "Number of threads not used = %d\n"
.align 8
.LC14:
.string "Time to calculate results on GPU: %f ms.\n"
.align 8
.LC15:
.string "Time to calculate results on CPU: %f ms.\n"
.align 8
.LC16:
.string "*********** ERROR in results, CPU and GPU create different answers ********\n"
.align 8
.LC17:
.string "\nEnter c to repeat, return to terminate\n"
.section .rodata.str1.1
.LC18:
.string "%c"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 48(%rsp)
leaq .LC5(%rip), %r12
jmp .L34
.L40:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
movl 48(%rsp), %r14d
cmpl %r13d, %ebx
cmovg %r13d, %ebx
cmpl %ebx, %r14d
jg .L28
cmpl $512, %ebp
jle .L39
.L28:
movl 32(%rsp), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 36(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 36(%rsp), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 40(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 44(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 44(%rsp), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 40(%rsp), %ebp
movl %ebp, %ebx
imull 32(%rsp), %ebx
movl 44(%rsp), %eax
movl %eax, %r13d
imull 36(%rsp), %r13d
imull %eax, %ebp
movl 48(%rsp), %eax
cmpl %ebx, %eax
jg .L40
cmpl %r13d, %eax
jg .L41
cmpl $512, %ebp
jle .L24
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L41:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L24:
movl %ebx, %edx
imull %r13d, %edx
imull %eax, %eax
subl %eax, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L39:
movl 32(%rsp), %eax
movl %eax, 96(%rsp)
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl 40(%rsp), %eax
movl %eax, 108(%rsp)
movl 44(%rsp), %eax
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
movl %r14d, %r13d
imull %r14d, %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
movq %r13, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %r14d, %r14d
jle .L29
movslq %r14d, %rsi
leaq 0(,%rsi,4), %rdi
negq %rsi
salq $2, %rsi
movq %rdi, %rcx
movl $0, %edx
.L30:
leaq (%rcx,%rsi), %rax
.L31:
movl %edx, 0(%rbp,%rax)
movl %edx, (%rbx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L31
addl $1, %edx
addq %rdi, %rcx
cmpl %edx, %r14d
jne .L30
.L29:
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl 116(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movq 96(%rsp), %rdi
movl 104(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L32:
movl $2, %ecx
movq %r13, %rdx
movq 72(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %r13
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq %r13, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl 48(%rsp), %ecx
movq 8(%rsp), %r14
movq %r14, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z13cpu_matrixaddPiS_S_i
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq %r13, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 48(%rsp), %eax
imull %eax, %eax
testl %eax, %eax
jle .L33
movl (%r14), %eax
cmpl %eax, (%r15)
jne .L43
.L33:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 31(%rsp), %r14
movq %r14, %rsi
leaq .LC18(%rip), %r13
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %r14, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpb $99, 31(%rsp)
jne .L44
.L34:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 48(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC6(%rip), %r15
jmp .L28
.L42:
movl 48(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z38__device_stub__Z13gpu_matrixaddPiS_S_iPiS_S_i
jmp .L32
.L43:
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L33
.L44:
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L45
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z13gpu_matrixaddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z13gpu_matrixaddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "2_Matrix_addition.hip"
.globl _Z28__device_stub__gpu_matrixaddPiS_S_i # -- Begin function _Z28__device_stub__gpu_matrixaddPiS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__gpu_matrixaddPiS_S_i,@function
_Z28__device_stub__gpu_matrixaddPiS_S_i: # @_Z28__device_stub__gpu_matrixaddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13gpu_matrixaddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__gpu_matrixaddPiS_S_i, .Lfunc_end0-_Z28__device_stub__gpu_matrixaddPiS_S_i
.cfi_endproc
# -- End function
.globl _Z13cpu_matrixaddPiS_S_i # -- Begin function _Z13cpu_matrixaddPiS_S_i
.p2align 4, 0x90
.type _Z13cpu_matrixaddPiS_S_i,@function
_Z13cpu_matrixaddPiS_S_i: # @_Z13cpu_matrixaddPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movq %rax, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%r10), %r11d
addl (%rdi,%r10), %r11d
movl %r11d, (%rdx,%r10)
addq %rcx, %r10
decq %r9
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r8
addq $4, %rdx
addq $4, %rsi
addq $4, %rdi
cmpq %rax, %r8
jne .LBB1_2
.LBB1_5: # %._crit_edge18
retq
.Lfunc_end1:
.size _Z13cpu_matrixaddPiS_S_i, .Lfunc_end1-_Z13cpu_matrixaddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1, 8(%rsp)
movl $1, 20(%rsp)
movl $1, 16(%rsp)
movl $1, 12(%rsp)
movl $10, (%rsp)
leaq 8(%rsp), %r15
leaq 20(%rsp), %r13
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_27: # in Loop: Header=BB2_1 Depth=1
movl $.Lstr.8, %edi
callq puts@PLT
movl $.L.str.18, %edi
leaq 7(%rsp), %r14
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.18, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
cmpb $99, 7(%rsp)
jne .LBB2_28
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_14 Depth 2
# Child Loop BB2_15 Depth 3
# Child Loop BB2_21 Depth 2
# Child Loop BB2_22 Depth 3
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl (%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movq %rsp, %rsi
xorl %eax, %eax
callq __isoc23_scanf
.p2align 4, 0x90
.LBB2_2: # %.critedge
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl 8(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl 20(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl 16(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
leaq 16(%rsp), %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
leaq 12(%rsp), %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl 16(%rsp), %eax
movl 8(%rsp), %ebp
imull %eax, %ebp
movl 12(%rsp), %ebx
movl 20(%rsp), %r14d
imull %ebx, %r14d
imull %eax, %ebx
movl (%rsp), %eax
cmpl %eax, %ebp
jge .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=2
movl $.Lstr.6, %edi
callq puts@PLT
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=2
cmpl %eax, %r14d
jge .LBB2_6
# %bb.5: # in Loop: Header=BB2_2 Depth=2
movl $.Lstr.5, %edi
callq puts@PLT
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_2 Depth=2
cmpl $513, %ebx # imm = 0x201
jl .LBB2_8
# %bb.7: # in Loop: Header=BB2_2 Depth=2
movl $.Lstr.4, %edi
callq puts@PLT
jmp .LBB2_9
.LBB2_8: # in Loop: Header=BB2_2 Depth=2
movl %r14d, %esi
imull %ebp, %esi
imull %eax, %eax
subl %eax, %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_2 Depth=2
movl (%rsp), %r12d
cmpl %r12d, %ebp
jl .LBB2_2
# %bb.10: # in Loop: Header=BB2_2 Depth=2
cmpl %r12d, %r14d
jl .LBB2_2
# %bb.11: # in Loop: Header=BB2_2 Depth=2
cmpl $512, %ebx # imm = 0x200
jg .LBB2_2
# %bb.12: # in Loop: Header=BB2_1 Depth=1
movl 8(%rsp), %r13d
movl 16(%rsp), %eax
movq %rax, 88(%rsp) # 8-byte Spill
movl 12(%rsp), %r15d
movl %r12d, %eax
imull %r12d, %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %rbp
movq %r14, %rdi
callq malloc
movq %rax, 96(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB2_17
# %bb.13: # %.preheader.preheader
# in Loop: Header=BB2_1 Depth=1
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_14: # %.preheader
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_15 Depth 3
movl %eax, %esi
leaq (,%rsi,4), %rdx
addq %rbp, %rdx
leaq (%rbx,%rsi,4), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_15: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_14 Depth=2
# => This Inner Loop Header: Depth=3
movl %ecx, (%rsi,%rdi,4)
movl %ecx, (%rdx,%rdi,4)
incq %rdi
cmpq %rdi, %r12
jne .LBB2_15
# %bb.16: # %._crit_edge
# in Loop: Header=BB2_14 Depth=2
incq %rcx
addl %r12d, %eax
cmpq %r12, %rcx
jne .LBB2_14
.LBB2_17: # %._crit_edge75
# in Loop: Header=BB2_1 Depth=1
movq %r13, %r12
shlq $32, %r12
orq %r13, %r12
shlq $32, %r15
addq 88(%rsp), %r15 # 8-byte Folded Reload
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 64(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 96(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_19
# %bb.18: # in Loop: Header=BB2_1 Depth=1
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movl (%rsp), %esi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 76(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 76(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movl $_Z13gpu_matrixaddPiS_S_i, %edi
leaq 176(%rsp), %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_19: # in Loop: Header=BB2_1 Depth=1
movq 48(%rsp), %rsi
movq %r13, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 44(%rsp), %r14
movq %r14, %rdi
callq hipEventElapsedTime
movss 44(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%rsp), %eax
testl %eax, %eax
leaq 8(%rsp), %r15
movq %r13, %r12
leaq 20(%rsp), %r13
jle .LBB2_24
# %bb.20: # %.preheader.lr.ph.i
# in Loop: Header=BB2_1 Depth=1
leaq (,%rax,4), %rcx
movq %rbx, %rdx
movq %rbp, %rsi
movq 80(%rsp), %rdi # 8-byte Reload
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_21: # %.preheader.i
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_22 Depth 3
xorl %r9d, %r9d
movq %rax, %r10
.p2align 4, 0x90
.LBB2_22: # %.lr.ph.i
# Parent Loop BB2_1 Depth=1
# Parent Loop BB2_21 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rsi,%r9), %r11d
addl (%rdx,%r9), %r11d
movl %r11d, (%rdi,%r9)
addq %rcx, %r9
decq %r10
jne .LBB2_22
# %bb.23: # %._crit_edge.i
# in Loop: Header=BB2_21 Depth=2
incq %r8
addq $4, %rdi
addq $4, %rsi
addq $4, %rdx
cmpq %rax, %r8
jne .LBB2_21
.LBB2_24: # %_Z13cpu_matrixaddPiS_S_i.exit
# in Loop: Header=BB2_1 Depth=1
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
movq %r14, %rdi
callq hipEventElapsedTime
movss 44(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
cmpl $0, (%rsp)
je .LBB2_27
# %bb.25: # in Loop: Header=BB2_1 Depth=1
movl (%r12), %eax
movq 80(%rsp), %rcx # 8-byte Reload
cmpl (%rcx), %eax
je .LBB2_27
# %bb.26: # in Loop: Header=BB2_1 Depth=1
movl $.Lstr.7, %edi
callq puts@PLT
jmp .LBB2_27
.LBB2_28:
movq %rbx, %rdi
callq free
movq %rbp, %rdi
callq free
movq %r12, %rdi
callq free
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpu_matrixaddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13gpu_matrixaddPiS_S_i,@object # @_Z13gpu_matrixaddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z13gpu_matrixaddPiS_S_i
.p2align 3, 0x0
_Z13gpu_matrixaddPiS_S_i:
.quad _Z28__device_stub__gpu_matrixaddPiS_S_i
.size _Z13gpu_matrixaddPiS_S_i, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Enter size of array in one dimension (square array), currently %d\n"
.size .L.str.4, 67
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\nEnter nuumber of blocks per grid in x dimension), currently %d : "
.size .L.str.6, 68
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\nEnter nuumber of blocks per grid in y dimension), currently %d : "
.size .L.str.7, 68
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\nEnter nuumber of threads per block in x dimension), currently %d : "
.size .L.str.8, 70
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\nEnter nuumber of threads per block in y dimension), currently %d : "
.size .L.str.9, 70
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Number of threads not used = %d\n"
.size .L.str.13, 33
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Time to calculate results on GPU: %f ms.\n"
.size .L.str.14, 42
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Time to calculate results on CPU: %f ms.\n"
.size .L.str.15, 42
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "%c"
.size .L.str.18, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13gpu_matrixaddPiS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Device characteristics -- some limitations (compute capability 1.0)"
.size .Lstr, 68
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\t\tMaximum number of threads per block = 512"
.size .Lstr.1, 44
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\t\tMaximum sizes of x- and y- dimension of thread block = 512"
.size .Lstr.2, 61
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\t\tMaximum size of each dimension of grid of thread blocks = 65535"
.size .Lstr.3, 66
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error -- too many threads in block, try again"
.size .Lstr.4, 46
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Error -- number of threads in y dimension less than number of elements in arrays, try again"
.size .Lstr.5, 92
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Error -- number of threads in x dimension less than number of elements in arrays, try again"
.size .Lstr.6, 92
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "*********** ERROR in results, CPU and GPU create different answers ********"
.size .Lstr.7, 76
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "\nEnter c to repeat, return to terminate"
.size .Lstr.8, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__gpu_matrixaddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13gpu_matrixaddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernExp(double* A, double* bias) {
int b = blockIdx.y * gridDim.x + blockIdx.x;
int i = b * blockDim.x + threadIdx.x;
A[i] = exp(A[i] - *bias);
} | code for sm_80
Function : _Z7kernExpPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R10, c[0x0][0x168] ; /* 0x00005a00000a7a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fe400078e0203 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc400078e00ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fe400078e0205 */
/*00a0*/ LDG.E.64 R4, [R10.64] ; /* 0x000000040a047981 */
/* 0x000ea4000c1e1b00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ HFMA2.MMA R8, -RZ, RZ, 1323, -4.565715789794921875e-05 ; /* 0x652b82feff087435 */
/* 0x000fe200000001ff */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff097424 */
/* 0x000fe200078e00ff */
/*00f0*/ MOV R14, 0x69ce2bdf ; /* 0x69ce2bdf000e7802 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff0f7424 */
/* 0x000fe200078e00ff */
/*0110*/ BSSY B0, 0x330 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0120*/ DADD R4, -R4, R6 ; /* 0x0000000004047229 */
/* 0x004e0c0000000106 */
/*0130*/ DFMA R6, R4, R8, 6.75539944105574400000e+15 ; /* 0x433800000406742b */
/* 0x001e0c0000000008 */
/*0140*/ DADD R8, R6, -6.75539944105574400000e+15 ; /* 0xc338000006087429 */
/* 0x001e0c0000000000 */
/*0150*/ DFMA R12, R8, c[0x2][0x0], R4 ; /* 0x00800000080c7a2b */
/* 0x001e0c0000000004 */
/*0160*/ DFMA R8, R8, c[0x2][0x8], R12 ; /* 0x0080020008087a2b */
/* 0x001e0c000000000c */
/*0170*/ DFMA R12, R8, R14, c[0x2][0x10] ; /* 0x00800400080c762b */
/* 0x001e0c000000000e */
/*0180*/ DFMA R12, R8, R12, c[0x2][0x18] ; /* 0x00800600080c762b */
/* 0x001e0c000000000c */
/*0190*/ DFMA R12, R8, R12, c[0x2][0x20] ; /* 0x00800800080c762b */
/* 0x001e0c000000000c */
/*01a0*/ DFMA R12, R8, R12, c[0x2][0x28] ; /* 0x00800a00080c762b */
/* 0x001e0c000000000c */
/*01b0*/ DFMA R12, R8, R12, c[0x2][0x30] ; /* 0x00800c00080c762b */
/* 0x001e0c000000000c */
/*01c0*/ DFMA R12, R8, R12, c[0x2][0x38] ; /* 0x00800e00080c762b */
/* 0x001e0c000000000c */
/*01d0*/ DFMA R12, R8, R12, c[0x2][0x40] ; /* 0x00801000080c762b */
/* 0x001e0c000000000c */
/*01e0*/ DFMA R12, R8, R12, c[0x2][0x48] ; /* 0x00801200080c762b */
/* 0x001e0c000000000c */
/*01f0*/ DFMA R12, R8, R12, c[0x2][0x50] ; /* 0x00801400080c762b */
/* 0x001e22000000000c */
/*0200*/ FSETP.GEU.AND P0, PT, |R5|, 4.1917929649353027344, PT ; /* 0x4086232b0500780b */
/* 0x000fca0003f0e200 */
/*0210*/ DFMA R12, R8, R12, 1 ; /* 0x3ff00000080c742b */
/* 0x001e0c000000000c */
/*0220*/ DFMA R12, R8, R12, 1 ; /* 0x3ff00000080c742b */
/* 0x001e14000000000c */
/*0230*/ LEA R9, R6, R13, 0x14 ; /* 0x0000000d06097211 */
/* 0x001fe200078ea0ff */
/*0240*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000c */
/*0250*/ @!P0 BRA 0x320 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0260*/ FSETP.GEU.AND P1, PT, |R5|, 4.2275390625, PT ; /* 0x408748000500780b */
/* 0x000fe20003f2e200 */
/*0270*/ DADD R8, R4, +INF ; /* 0x7ff0000004087429 */
/* 0x000fc80000000000 */
/*0280*/ DSETP.GEU.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e0c0003f0e000 */
/*0290*/ FSEL R8, R8, RZ, P0 ; /* 0x000000ff08087208 */
/* 0x001fe40000000000 */
/*02a0*/ @!P1 LEA.HI R0, R6, R6, RZ, 0x1 ; /* 0x0000000606009211 */
/* 0x000fe400078f08ff */
/*02b0*/ FSEL R9, R9, RZ, P0 ; /* 0x000000ff09097208 */
/* 0x000fe40000000000 */
/*02c0*/ @!P1 SHF.R.S32.HI R5, RZ, 0x1, R0 ; /* 0x00000001ff059819 */
/* 0x000fc80000011400 */
/*02d0*/ @!P1 IADD3 R4, R6, -R5, RZ ; /* 0x8000000506049210 */
/* 0x000fe20007ffe0ff */
/*02e0*/ @!P1 IMAD R13, R5, 0x100000, R13 ; /* 0x00100000050d9824 */
/* 0x000fc600078e020d */
/*02f0*/ @!P1 LEA R5, R4, 0x3ff00000, 0x14 ; /* 0x3ff0000004059811 */
/* 0x000fe400078ea0ff */
/*0300*/ @!P1 MOV R4, RZ ; /* 0x000000ff00049202 */
/* 0x000fcc0000000f00 */
/*0310*/ @!P1 DMUL R8, R12, R4 ; /* 0x000000040c089228 */
/* 0x00004c0000000000 */
/*0320*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0330*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0340*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0350*/ BRA 0x350; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernExp(double* A, double* bias) {
int b = blockIdx.y * gridDim.x + blockIdx.x;
int i = b * blockDim.x + threadIdx.x;
A[i] = exp(A[i] - *bias);
} | .file "tmpxft_00044c48_00000000-6_kernExp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7kernExpPdS_PdS_
.type _Z28__device_stub__Z7kernExpPdS_PdS_, @function
_Z28__device_stub__Z7kernExpPdS_PdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernExpPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z7kernExpPdS_PdS_, .-_Z28__device_stub__Z7kernExpPdS_PdS_
.globl _Z7kernExpPdS_
.type _Z7kernExpPdS_, @function
_Z7kernExpPdS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7kernExpPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7kernExpPdS_, .-_Z7kernExpPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7kernExpPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernExpPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernExp(double* A, double* bias) {
int b = blockIdx.y * gridDim.x + blockIdx.x;
int i = b * blockDim.x + threadIdx.x;
A[i] = exp(A[i] - *bias);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernExp(double* A, double* bias) {
int b = blockIdx.y * gridDim.x + blockIdx.x;
int i = b * blockDim.x + threadIdx.x;
A[i] = exp(A[i] - *bias);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernExp(double* A, double* bias) {
int b = blockIdx.y * gridDim.x + blockIdx.x;
int i = b * blockDim.x + threadIdx.x;
A[i] = exp(A[i] - *bias);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernExpPdS_
.globl _Z7kernExpPdS_
.p2align 8
.type _Z7kernExpPdS_,@function
_Z7kernExpPdS_:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_load_b64 s[0:1], s[2:3], 0x0
s_mov_b32 s3, 0x3e5ade15
s_mov_b32 s2, 0x6a5dcb37
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], -s[0:1]
s_mov_b32 s1, 0x3ff71547
s_mov_b32 s0, 0x652b82fe
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mul_f64 v[4:5], v[2:3], s[0:1]
s_mov_b32 s1, 0xbfe62e42
s_mov_b32 s0, 0xfefa39ef
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[4:5], v[4:5]
v_fma_f64 v[6:7], v[4:5], s[0:1], v[2:3]
s_mov_b32 s1, 0xbc7abc9e
s_mov_b32 s0, 0x3b39803f
v_cvt_i32_f64_e32 v10, v[4:5]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[6:7], v[4:5], s[0:1], v[6:7]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], s[2:3], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v10
v_cndmask_b32_e32 v5, 0x7ff00000, v5, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0, v4, vcc_lo
v_cndmask_b32_e64 v3, 0, v5, s0
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernExpPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernExpPdS_, .Lfunc_end0-_Z7kernExpPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernExpPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernExpPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernExp(double* A, double* bias) {
int b = blockIdx.y * gridDim.x + blockIdx.x;
int i = b * blockDim.x + threadIdx.x;
A[i] = exp(A[i] - *bias);
} | .text
.file "kernExp.hip"
.globl _Z22__device_stub__kernExpPdS_ # -- Begin function _Z22__device_stub__kernExpPdS_
.p2align 4, 0x90
.type _Z22__device_stub__kernExpPdS_,@function
_Z22__device_stub__kernExpPdS_: # @_Z22__device_stub__kernExpPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7kernExpPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__kernExpPdS_, .Lfunc_end0-_Z22__device_stub__kernExpPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernExpPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernExpPdS_,@object # @_Z7kernExpPdS_
.section .rodata,"a",@progbits
.globl _Z7kernExpPdS_
.p2align 3, 0x0
_Z7kernExpPdS_:
.quad _Z22__device_stub__kernExpPdS_
.size _Z7kernExpPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kernExpPdS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernExpPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernExpPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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