code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module seq_sub (
a,
b,
out,
reset,
clk
);
input [`DWIDTH-1:0] a;
input [`DWIDTH-1:0] b;
input reset;
input clk;
output [`DWIDTH-1:0] out;
reg [`DWIDTH-1:0] a_flopped;
reg [`DWIDTH-1:0] b_flopped;
wire [`DWIDTH-1:0] sub_out_temp;
reg [`DWIDTH-1:0] sub_out_temp_reg;
always @(... | 7.452798 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat... | 6.905513 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANT... | 6.969233 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bit... | 6.969233 |
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B; // Input B, a 32-bit floating point number
input [2*`EXPONENT-1:0] ShiftDet;
// Output por... | 6.969233 |
module FPAddSub_PrealignModule (
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B; // Input B, a 32-bit floating point number
input operation;
// ... | 7.069212 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 7/7/2022 Mina Hanna final version
//----------------------------------------------... | 8.923686 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 8/7/2022 Mina Hanna final version
//----------------------------------------------... | 8.923686 |
module serclk_generator (
input reset,
input clk,
input [3:0] speed_select,
output clkout
);
// Clock divider.
reg [7:0] divider;
assign clkout = speed_select[3] ? divider[speed_select[2:0]] : clk;
initial begin
divider = 0;
end
// Increment clock divider with each Z80 clock cycle. ... | 7.503819 |
module SerCom_LCD (
input sys_clk,
input rst,
output reg SPDA,
output reg SPCLK,
output reg SPENB
);
reg [4:0] counter2 = 0;
reg [11:0] counter1 = 0;
reg [19:0] counterFLAG = 0;
reg FLAG;
reg FLAG2;
reg FLAG3;
initial begin
SPCLK = 0;
SPENB = 1;
SPDA = 0;
FLAG3 = 1... | 6.606341 |
module deserializer #(
parameter WIDTH = 8, // Width of each data chunk
parameter N = 2 // Number of data chunks to deserialize
) (
input clock,
input reset,
input [ WIDTH-1:0] data_in,
input data_in_valid,
output [WIDTH*N-1:0] data_out,
... | 8.075096 |
module serializer #(
parameter WIDTH = 8, // Width of each data chunk
parameter N = 2 // Number of data chunks to serialize
) (
input clock,
input reset,
input [WIDTH*N-1:0] data_in,
input data_in_valid,
output [ WIDTH... | 9.107476 |
module serdes #(
parameter TXFIFOSIZE = 9,
parameter RXFIFOSIZE = 9
) (
input clk,
input rst,
// TX side
output ser_tx_clk,
output [15:0] ser_t,
output ser_tklsb,
output ser_tkmsb,
input [31:0] rd_dat_i,
input [3:0] rd_flags_i,
output rd_ready_o,
input rd_ready_i,
... | 7.958426 |
module Serdes_1x8_DDR (
input CLK,
input CLKB,
input CLKDIV,
input BITSLIP,
input D_p,
input D_n,
input RST,
output [7:0] Q
);
// have not been tested
wire clkb = ~CLK;
// ISERDESE2: Input SERial/DESerializer with Bitslip
// 7 Series
// Xilinx HDL Libraries Guide, version 14... | 6.701369 |
module serdes_4b_7to1_wrapper (
input clk, // clock
input clkx3p5, // 3.5 times clock
input clkx3p5not, // not 3.5 times clock
input [27:0] datain, // input data
input rst, // reset
output [7:0] dataout, // output data
output [1:0] clkout
); // output clock (1x)
(* RLOC = "x0y0" *)... | 7.085022 |
module serdes_5_to_1 (
ioclk,
serdesstrobe,
reset,
gclk,
datain,
iob_data_out
);
input ioclk; // IO Clock network
input serdesstrobe; // Parallel data capture strobe
input reset; // Reset
input gclk; // Global clock
input [4:0] datain; // Data for output
output iob_data_out; /... | 8.08769 |
module serdes_fc_rx #(
parameter LWMARK = 64,
parameter HWMARK = 320
) (
input clk,
input rst,
input [15:0] fifo_space,
output reg send_xon,
output reg send_xoff,
input sent
);
reg [15:0] countdown;
reg send_xon_int, send_xoff_int;
always @(posedge clk)
if (rst) begin
s... | 7.88001 |
module serdes_lvds_v1_0 (
input wire clk,
input wire reset_n,
// TX
input wire [39:0] txdin,
input wire [ 1:0] serd_cmd,
output wire [23:0] txdout1,
output wire [15:0] txdout2,
// RX
input wire [23:0] rxdin1,
input wire [15:0] rxdin2,
output wire [23:0] rxdout1,
o... | 6.621879 |
module serdes_output_to_fin1216 #(
parameter N = 3
) (
input wire reset,
input wire clk,
input wire clk_x7,
input wire [N*7-1:0] in_data,
output wire out_clk_p,
output wire out_clk_n,
output wire [N-1:0] out_data_p,
output wire [N-1:0] out_data_n
);
assign out_clk_p = c... | 8.123874 |
module serdes_clk_model #(
parameter IS_MASTER = 1,
parameter real CLK_PER_NS = 0.0625
) (
input wire enable,
input wire idle,
output reg ready,
output reg bitclk
);
initial begin
bitclk = 0;
end
always #((CLK_PER_NS / 2.0) * 1ns) bitclk <= enable && ~idle && IS_MASTER ? ~bitclk ... | 6.649423 |
module serdes_tx_model #(
parameter DATA_WIDTH = 8
) (
input wire bitclk,
input wire enable,
output wire txclk,
input wire [DATA_WIDTH-1:0] tx_data,
input wire tx_reset,
output wire tx_dirdy,
output reg ... | 7.903265 |
module serdes_rx_model #(
parameter DATA_WIDTH = 8,
parameter UI_PS = 125
) (
input wire bitclk,
input wire enable,
output reg rxclk,
input wire rx_align,
output reg [DATA_WIDTH-1:0] rx_data,
input wire rx_res... | 7.33196 |
module serdes_top (
input clk,
input rst_n,
input [7:0] parallel_data_in,
output [7:0] parallel_data_out
);
wire [7:0] parallel_data_in = 8'b11010101;
reg [7:0] parallel_data_out;
latch_8bit data_in_latch (
.clk(clk),
.rst_n(rst_n),
.data_8b_in(parallel_data),
... | 7.208512 |
module top_module (
input clk,
input in,
input reset,
output [7:0] out_byte,
output done
);
reg [7:0] mayukh;
reg [3:0] state, next_state;
parameter start = 4'h0;
parameter data1 = 4'h1;
parameter data2 = 4'h2;
parameter data3 = 4'h3;
parameter data4 = 4'h4;
parameter data5 = 4'h5;
... | 7.203305 |
module tristate (
inout pin,
input enable,
input data_out,
output data_in
);
SB_IO #(
.PIN_TYPE(6'b1010_01) // tristatable output
) buffer (
.PACKAGE_PIN(pin),
.OUTPUT_ENABLE(enable),
.D_IN_0(data_in),
.D_OUT_0(data_out)
);
endmodule
| 6.741184 |
module serial (
input wire clk,
input wire reset,
input wire A,
input wire CE,
input wire WREN,
input wire REN,
input wire rx,
output wire tx,
output wire rx_int,
output wire tx_int,
output reg [7:0] to_CPU,
input wire [7:0] from_CPU
);
//Note that the latency for this ... | 6.507399 |
module fa (
s,
cout,
a,
b,
cin
);
input a, b, cin;
output s, cout;
assign {cout, s} = a + b + cin;
endmodule
| 7.769241 |
module dff (
q,
d,
clk
);
input d, clk;
output q;
reg q;
initial begin
q = 1'b0;
end
always @(posedge clk) begin
q = d;
end
endmodule
| 8.035763 |
module serial adder//
module serial(sum,cout,a,b,clk);
input [3:0] a,b;
input clk;
wire [3:0] x,z;
output [3:0] sum;
output cout;
wire s,cin;
//input cin;
//initial begin
//cin=cinp;
//end
fa k(s,cout,x[0],z[0],cin); //1 bit full adder
dff q(cin,cout,clk); //d flipflop to store the cou... | 7.785557 |
module SerialAdder4 (
input [3:0] InputA,
input [3:0] InputB,
input InputCarry,
output [3:0] Output,
output OutputCarry
);
wire C1, C2, C3;
FullAdder FA0 (
InputA[0],
InputB[0],
InputCarry,
Output[0],
C1
);
FullAdder FA1 (
InputA[1],
InputB[1],
... | 6.53239 |
module: SerialAdder4
//
// Dependencies: SerialAdder4
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module SerialAdder4Test;
// Inputs
reg [3:0] InputA;
reg [3:0] InputB;
reg InputCarry;
// Outputs
... | 6.884042 |
module serialAdder_4bit (
output [3:0] serOut1,
output sm,
input serInp,
input shiftCtrl,
input clear,
input clk
);
wire cout, coutLatched, sm;
wire [3:0] serOut1, serOut2;
shift_reg_4bit_lab sreg1 (
sm,
shiftCtrl,
serOut1,
clk
);
shift_reg_4bit_lab sreg2 (
... | 7.203225 |
module serialAsyncReceiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters a... | 6.857377 |
module serialAsyncTransmitter (
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
// TxD_data is latched so that it doesn't have to stay valid while it is being sent
parameter ... | 7.922572 |
module: SerialController
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module serialBufferTest;
// Inputs
reg Clock;
reg Send;
reg [15:0] DataIn;
reg Receive;
reg Read;
// Output... | 6.730315 |
module SerialChico (
CLK50, //Entrada de reloj de 50 MHz
DIN, //Entrada en serial del ADC
CLK, //Reloj para el ADC y la ASM
CS, //Chip Select
SerialBit, //Salida en serial del valor digital
LEDS //LEDs que muestran los 8 bits ms significativos
);
//Asignamos a los puertos de qu tipo son
... | 6.532747 |
module Serial_CRC (
input [`WIDTH-9:0] i_data,
input i_clk,
input i_rst_n,
output [`WIDTH-1:0] o_crcOutput
);
//**************************************************************************
parameter S0 = 3'b000; //BIT[0]
parameter S1 = 3'b001; //BIT[1]
parameter S2 = 3'b010; //BIT[2]
paramet... | 7.728427 |
module SerialDataCtrl (
input clk, // clock Input
input reset, // reset Input
input data_in_rx_fifo, // 1 when there is input data to process, 0 otherwise
input tx_busy, //1 when the transmit module is sending, 0 otherwise
input [7:0] rx_data, // input data recieved (as cached by fifo)
inpu... | 6.519955 |
module performs unsigned division by computing one bit of the quotient per cycle and
* serially shifting those bits in a register.
* The serial divider is not pipelined and can only perform one division at a time.
*
* Inputs:
*
* clk the clock
* clken an active-high clock enable
* resetn an active-low... | 6.977649 |
module DFlipFlop (
clk,
resetn,
enable,
D,
Q
);
parameter n = 8;
input clk;
input resetn;
input enable;
input [n-1:0] D;
output reg [n-1:0] Q;
always @(posedge clk, negedge resetn)
if (resetn == 0) Q <= 0;
else if (enable) Q <= D;
endmodule
| 7.170064 |
module ShiftLeftRegister (
clk,
resetn,
load,
parallel_in,
enable,
shift_in,
Q
);
parameter n = 8;
input clk;
input resetn;
input load;
input [n-1:0] parallel_in;
input enable;
input shift_in;
output reg [n-1:0] Q;
integer k;
always @(posedge clk, negedge resetn) begi... | 7.655862 |
module DownwardsRunningCounter (
clk,
resetn,
enable,
Q
);
parameter log2n = 3;
input clk;
input resetn;
input enable;
output reg [log2n-1:0] Q;
always @(posedge clk)
if (resetn == 0) Q <= {log2n{1'b1}};
else if (enable) Q <= Q - 1;
endmodule
| 6.808571 |
module serialGPIO (
input clk,
input rst,
input RxD,
input [`addrW-1:0] addr,
output reg [`width-1:0] GPout, // general purpose outputs
output reg RAM_full
);
wire RxD_data_ready;
wire [`width-1:0] RxD_data;
wire buf_full;
wire [`buf_size*`width-1:0] buf_out;
wire [`buf_size*`widt... | 7.163481 |
module SerialIf (
input CLK,
input SERIAL_IN,
output [7:0] BYTE_OUT,
output BYTE_RDY
);
// sampling clock
// 50MHz / 6 = 8.33Mbps (921.6Kbps x 9 over sampling)
reg [3:0] sp_cnt;
reg sp_clk;
always @(posedge CLK) begin
if (sp_cnt == 6) begin
sp_cnt = 0;
sp_clk = 1;
end else... | 6.881973 |
module sipo ( /*reinicio,*/
clk,
serial_in,
parallel_out
);
//reinicio:reinicia el segmento(limpia); clk:reloj; serial_in:entrada en serie
input /*reinicio,*/ clk, serial_in;
output [9:0] parallel_out; //salida en paralelo
reg [9:0] parallel_out;
/*always @ (reinicio)
begin
if (reinicio ... | 6.870241 |
module SerialIODecoder (
input unsigned [15:0] Address,
input IOSelect_H,
input ByteSelect_L,
output reg Bluetooth_Port_Enable,
output reg Wifi_Port_Enable
);
always @(Address, IOSelect_H, ByteSelect_L) begin
// default values for the IO chip enables (default = disabled)
// they are ove... | 7.983192 |
module serialize #(
parameter dwi = 28 // result width
) (
input clk, // timespec 8.4 ns
input samp, // Snap signal for data_in
input signed [dwi-1:0] data_in,
input signed [dwi-1:0] stream_in,
output signed [dwi-1:0] stream_out,
input gate_in,
output gate_out,
output strobe_out
)... | 7.646107 |
module Serialized_ALU (
clk,
reset,
rd_d, //alu result will be written to rd (rd_d == rd data)
rs1_d, //data in from rs1
rs2_d, //data in from rs2
ALU_Sel, //op code
OpStart, //signals sent to or from controller
count, //signals sent to or from controller
reg_write //signals... | 6.663315 |
module originally
// written by Sameer Puri. It is a verilog version
// with all HDMI logic removed, hard coded to
// 3 data channels and uses no vendor IP blocks. It
// also uses a 10x pixel to drive serialization rather
// than a 5x clock. It is expected the tmds and
// tmds_clock outputs will be passed to a differe... | 7.474321 |
module serializer_10to1_tb ();
reg rst;
reg clk;
reg clk_5x;
reg clk_lock; // clocks locked?
wire rst_oserdes;
reg [9:0] tmds_data_1;
reg [9:0] tmds_data_2;
reg [9:0] tmds_data_3;
wire tmds_data_1_serial;
wire tmds_data_2_serial;
wire tmds_data_3_serial;
initial begin
$display($time, " <... | 7.519845 |
module serializer (
input clk,
input reset_n,
input wire [39:0] din,
input wire [1:0] serd_cmd,
output wire [23:0] dout1,
output wire [15:0] dout2
);
// internal wires and registers
wire [39:0] encode;
reg [39:0] data;
always @(posedge clk) begin
if (reset_n == 1'b0) data[39:0... | 7.228287 |
module serializer_multichannel #(
parameter n_chan = 8, // Number of channels to serialize
parameter dw = 16,
parameter l_to_r = 1 // l_to_r=1: Channel shifting starts with CH0 (default)
// l_to_r=0: Channel shifting starts with last CH
) (
input clk,
input sample_in, //... | 7.832395 |
module serializer_testbench;
// Inputs
reg clk;
reg rst_n;
reg filt_i2so_rts;
reg [15:0] filt_i2so_lft;
reg [15:0] filt_i2so_rgt;
reg sck_transition;
// Outputs
wire i2so_sd;
wire i2so_ws;
wire filt_i2so_rtr;
// Instantiate the Unit Under Test (UUT)
i2so_serializer uut (
.clk(clk),
... | 6.510764 |
module serializing (
output reg dout,
output reg dout_valid,
input [7:0] din,
input indicator,
input clk,
input reset_n
);
localparam WAITING = 0, SENDING = 1;
reg state;
wire next_state;
reg [2:0] count;
wire [2:0] next_count;
// Here we update only on posedge clk to avoid hazar... | 6.790343 |
module serialMap #(
parameter pBytesKey = 8'd6,
parameter pBytesValue = 8'd2,
parameter pBitsFromHash = 6
) (
CLOCK,
key,
query,
found,
notfound,
data
);
parameter [3:0] sIDLE = 4'b000;
parameter [3:0] sKEYRD = 4'b001;
parameter [3:0] sKHASH = 4'b010;
parameter [3:0] sTEST =... | 6.938286 |
module serialParity (
z,
x,
clk
);
output reg z;
input x, clk;
parameter EVEN = 0, ODD = 1;
always @(posedge clk) begin
case (z)
EVEN: z <= x ? ODD : EVEN;
ODD: z <= x ? EVEN : ODD;
default: z <= EVEN;
endcase
end
endmodule
| 7.796879 |
module testbench;
reg x,clk;
wire z;
integer i;
reg [7:0] const;
serialParity DUT (z,x,clk);
always #5 clk = ~clk;
initial begin
$dumpfile ("waveform.vcd");
$dumpvars (0,testbench);
clk = 0;
const = 8'hBC;
for (i=0;i<8;i=i+1) begin
x = const[i]; #10
if (z == 0) $display ($time,": %b : x = %b, s... | 7.0362 |
module SerialPort (
input wire clk,
input wire [7:0] din,
output reg [7:0] dout,
input wire wrin,
output reg wrout,
output reg rdout,
output wire txd,
input wire rxd
);
// Передающая часть
reg [8:0] div;
reg [9:0] shift;
assign txd = |shift ? shift[0] : 1'b1;
always @(p... | 7.433639 |
module processor_slave (
clk,
rxReady,
rxData,
txBusy,
txStart,
txData,
readdata,
newgotdata,
gotdata
);
input clk;
input [7:0] rxData;
input rxReady;
input txBusy;
output reg txStart;
output reg [7:0] txData;
output reg [7:0] readdata; //first byte we got
input newg... | 7.408242 |
module USBSerial_RX (
input wire clk,
input wire UART_TXD_IN,
output reg [1727:0] OutData,
output reg ReadCompletedSig
);
// This is the length of the data we want to read in bytes.
localparam MSG_LEN = 216;
// This calculates how many bits we will need to store those bytes (during synthesis, of... | 7.241324 |
module SerialRXPackage #(
parameter AddressWidth = 2,
parameter WordWidth = 8,
parameter SerialTimerWidth = 8,
parameter QueueAddressWidth = 3
) (
input clk,
input rst,
input rx,
input pull,
output [2**AddressWidth*WordWidth-1:0]Q,
output void,
output full
);
wire [WordWidth-1:0]serialData;
wire serialFin... | 7.079715 |
module SerialRXPackageTest;
parameter AddressWidth = 2;
parameter WordWidth = 8;
parameter SerialTimerWidth = 3;
parameter QueueAddressWidth = 2;
reg clk;
reg rst;
reg ce;
reg pull;
reg [2**AddressWidth*WordWidth-1:0]txData;
wire [2**AddressWidth*WordWidth-1:0]rxData;
wire void;
wire full;
wire txBusy;... | 7.079715 |
module SerialRxTest;
reg clk, ce, rst;
reg [7:0] dtx;
wire s, txBusy, rxFinish;
wire [7:0] drx;
SerialTx #(8, 8) stx (
clk,
rst,
ce,
dtx,
s,
txBusy
);
SerialRx #(8, 8) srx (
clk,
rst,
s,
drx,
rxFinish
);
integer i;
initial begin
... | 7.601162 |
module SerialRxTx_1led (
clk,
RxD,
TxD,
LED
);
input clk;
input RxD;
output TxD;
parameter NumberOfLEDs = 1;
output [NumberOfLEDs-1:0] LED;
parameter ClkFrequency = 24000000; // make sure this matches the clock frequency on your board
// RxD
wire RxD_data_ready;
wire [7:0] RxD_data... | 7.067006 |
module SerialRxTx_2leds (
clk,
RxD,
TxD,
LED
);
input clk;
input RxD;
output TxD;
parameter NumberOfLEDs = 2;
output [NumberOfLEDs-1:0] LED;
parameter ClkFrequency = 24000000; // make sure this matches the clock frequency on your board
// RxD
wire RxD_data_ready;
wire [7:0] RxD_dat... | 7.110014 |
module: SerialController
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module SerialTester;
// Inputs
reg Clock;
reg Send;
reg [15:0] DataIn;
reg Receive;
// Outputs
wire Valid;
... | 6.730315 |
module SerialTXPackage #(
parameter AddressWidth = 2,
parameter WordWidth = 8,
parameter SerialTimerWidth = 8,
parameter QueueAddressWidth = 3
) (
input clk,
input rst,
input ce,
input [2**AddressWidth*WordWidth-1:0] data,
output tx,
output busy
);
wire txCe;
wire [WordWidth... | 7.162074 |
module SerialTXPackageTest;
parameter AddressWidth = 2;
parameter WordWidth = 8;
parameter SerialTimerWidth = 3;
parameter QueueAddressWidth = 1;
reg clk;
reg rst;
reg ce;
reg [2**AddressWidth*WordWidth-1:0] data;
wire tx;
wire busy;
SerialTXPackage #(AddressWidth, WordWidth, SerialTimerWidth, ... | 7.162074 |
module serial_2_parallel (
input clk,
input rst,
input start,
input serial_in,
input data_flag,
output [3:0] parallel_data
);
//parameter
parameter idle = 2'b00;
parameter loop = 2'b01;
parameter shift = 2'b10;
//register
reg [3:0] shift_reg, data_reg;
reg [1:0] bit_cnt;
//cont... | 6.838546 |
module Reg8_1 (
out,
in,
clk,
ctrl
);
input ctrl;
output [7:0] out;
input [7:0] in;
reg [7:0] Regs;
input clk;
assign out[0] = Regs[0];
assign out[1] = Regs[1];
assign out[2] = Regs[2];
assign out[3] = Regs[3];
assign out[4] = Regs[4];
assign out[5] = Regs[5];
assign out[6] = Reg... | 6.75854 |
module Reg8_2 (
out,
in,
clk
);
output [7:0] out;
input [7:0] in;
reg [7:0] Regs;
input clk;
assign out[0] = Regs[0];
assign out[1] = Regs[1];
assign out[2] = Regs[2];
assign out[3] = Regs[3];
assign out[4] = Regs[4];
assign out[5] = Regs[5];
assign out[6] = Regs[6];
assign out[7] = ... | 6.827413 |
module testmul;
reg [ 2:0] Shift_amt;
reg [ 7:0] in;
wire [15:0] out;
Multiplier m1 (
out,
in,
Shift_amt
);
initial begin
Shift_amt = 3'b011;
in = 8'b11101011;
//#10 $display("out: %b",out);
//#10 $display("out: %b",out);
//#10 $finish;
end
endmodule
| 6.716264 |
module testcomp;
reg [15:0] in;
reg sign;
wire [15:0] out;
Complement cmp (
out,
in,
sign
);
initial begin
// in=16'b0110101111010011;
// sign = 1'b1;
// #10 $display ("out: %b",out);
// sign = 1'b0;
// #10 $display ("out: %b",out);
// #10 $finish;
end
endmodule
| 6.940555 |
module Mux8 (
out,
in1,
in2,
sel
);
input [7:0] in1, in2;
input sel;
output [7:0] out;
not n1 (selNot, sel);
semimux m1 (
out[0],
in1[0],
in2[0],
sel,
selNot
);
semimux m2 (
out[1],
in1[1],
in2[1],
sel,
selNot
);
semimux m3 (
... | 6.721134 |
module testadder;
// reg [7:0] in1,in2;
// reg sign, ctrl;
// wire [7:0] out;
// Clock c(clk);
// SerialAdder Add(out,clk,in1,in2,sign,ctrl);
// initial begin
// ctrl=1'b1;
// sign=1'b1;
// in1=8'b00101101;
// in2=8'b11101111;
// #10 ctrl=1'b0;in1=8'b00000... | 6.668018 |
module mux (
out,
a,
b,
sel
);
output out;
input a, b, sel;
not not1 (selNot, sel);
semimux m1 (
out,
a,
b,
sel,
selNot
);
endmodule
| 7.812393 |
module PE_Conv_test;
reg [7:0] xOrW, yIn;
reg [2:0] ctrl;
wire [7:0] yOut, xOut;
PE_Conv PE (
yOut,
xOut,
xOrW,
yIn,
clk,
ctrl
);
Clock c (clk);
reg [3:0] W;
reg [15:0] X1, X2, X3;
reg [15:0] Y1, Y2, Y3;
initial begin
W = 4'b1011;
X1 = 8'b10110101;
X2 ... | 6.683229 |
module ShiftReg (
in,
en,
clock,
q
);
parameter n = 4;
input in, en, clock;
output [n-1:0] q;
reg [n-1:0] q;
initial q = 4'd10;
always @(posedge clock) begin
if (en) q = {in, q[n-1:1]};
end
endmodule
| 8.65434 |
module DFlipFlop_Async_Clear (
d,
not_clear,
clock,
q
);
input d, not_clear, clock;
output q;
reg q;
always @(negedge not_clear or posedge clock) begin
if (!not_clear) q <= 1'b0;
else q <= d;
end
endmodule
| 6.933649 |
module FADDER_1bit (
Cout,
Sum,
In1,
In2,
Cin
);
input In1, In2, Cin;
output Cout;
output Sum;
assign {Cout, Sum} = In1 + In2 + Cin;
endmodule
| 7.261032 |
module Serial_Adder_4bit (
SO1,
sum,
SI,
shiftCtrl,
clear,
clock
);
initial begin
$dumpfile("Serial_Adder_4bit.vcd");
$dumpvars;
end
output [3:0] SO1;
output sum;
input SI, shiftCtrl, clear, clock;
wire cout, q, sum;
wire [3:0] SO1, SO2;
ShiftReg SR1 (
sum,
... | 7.49586 |
module tb_Serial_Adder;
reg SI, shiftCtrl, clear, clock;
wire [3:0] a;
wire sum;
reg [0:3] b;
integer i;
Serial_Adder_4bit SA (
a,
sum,
SI,
shiftCtrl,
clear,
clock
);
always @(posedge clock)
$display(
$time,
" ShftCtrl = %b ",
shiftCtrl... | 7.690827 |
module Serial_Adder_top (
input [7:0] Data_A,
input [7:0] Data_B,
input CLK,
input Start,
output [7:0] Sum,
output Cout,
output Done
);
wire a_w;
wire b_w;
wire sum_w;
wire load_w;
shift_in_8bit U1 (
.Data_A(Data_A),
.Data_B(Data_B),
.CLK(CLK_w),
.Load(load_... | 7.49586 |
module control (
input CLK,
input Start,
output reg Done,
output reg CLK_out,
output reg Load
);
reg [3:0] count;
reg [2:0] state;
initial begin
state = 0;
count = 0;
Done = 0;
Load = 0;
CLK_out = 0;
end
parameter Idle = 0, Loading = 1, Shifting = 2;
always @(... | 7.715617 |
module shift_reg_8bit (
input S_in,
input CLK,
input CLR,
output reg [7:0] Data_out
);
initial begin
Data_out = 0;
end
always @(negedge CLK or posedge CLR) begin
if (CLR) Data_out = 0;
Data_out = {S_in, Data_out[7:1]};
end
endmodule
| 6.716095 |
module shift_in_8bit (
input [7:0] Data_A,
input [7:0] Data_B,
input CLK,
input Load,
output A,
output B
);
reg [7:0] Data_A_reg;
reg [7:0] Data_B_reg;
initial begin
Data_A_reg = 0;
Data_B_reg = 0;
end
always @(negedge CLK or posedge Load) begin
if (Load) begin
{Data... | 7.318316 |
module
* Copyright (C) 2010 Donna Polehn <dpolehn@verizon.net>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at ... | 8.090543 |
module
* Copyright (C) 2010 Donna Polehn <dpolehn@verizon.net>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at ... | 8.090543 |
module serial_audio_decoder #(
parameter audio_width = 32
) (
input wire sclk,
input wire reset,
input wire lrclk,
input wire sdin,
input wire is_i2s,
input wire lrclk_polarity,
output reg is_error,
output reg o_valid,
input wire o_ready,
output reg o_is_left,
output reg ... | 7.302502 |
module serial_audio_decoder_tb ();
parameter STEP = 1000000000 / (44100 * 128);
reg reset;
reg clk128;
initial begin
clk128 = 1'b0;
forever #(STEP / 2) clk128 = ~clk128;
end
reg lrclk = 0;
reg sclk = 0;
reg sdin = 0;
wire o_valid;
reg o_ready = 1'b1;
wire o_is_left;
wire [31:0] o_au... | 7.302502 |
module serial_audio_encoder #(
parameter audio_width = 16
) (
input wire reset,
input wire clk,
input wire is_i2s,
input wire lrclk_polarity,
input wire i_valid,
output wire i_ready,
input wire i_is_left,
input wire [audio_width-1:0] i_audio,
output reg is_underrun,
output wi... | 7.302502 |
module serial_audio_encoder_loopback_tb ();
localparam CLK_SCLK = 1000000000 / (44100 * 32); // 44.1KHz * 64
localparam lrclk_polarity = 1'b1;
localparam is_i2s = 1'b1;
localparam audio_width = 32;
initial begin
$dumpfile("serial_audio_encoder_loopback_tb.vcd");
$dumpvars;
end
reg Clock;
in... | 7.302502 |
module serial_audio_encoder_tb ();
localparam CLK_SCLK = 1000000000 / (44100 * 32); // 44.1KHz * 32
localparam lrclk_polarity = 1'b0;
localparam is_i2s = 1'b0;
localparam audio_width = 16;
initial begin
$dumpfile("serial_audio_encoder_tb.vcd");
$dumpvars;
end
reg Clock;
initial begin
Clo... | 7.302502 |
module mux (
out,
a,
b,
sel
);
output out;
input a, b, sel;
not not1 (selNot, sel);
semimux m1 (
out,
a,
b,
sel,
selNot
);
endmodule
| 7.812393 |
module dff (
q,
clk,
reset,
d
);
output q;
input clk, d, reset;
reg q;
always @(posedge clk) begin
q <= d & (~reset);
end
endmodule
| 8.035763 |
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