code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module servax // top level for nexys 2 (Xilinx's Spartan-3E based) target board
(
input wire i_clk,
output wire q
);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
parameter PLL = "NONE";
wire wb_clk;
wire wb_rst;
servax_clock_gen clock_gen (
.i_clk(i_clk),
.o_clk... | 8.266025 |
module servclone10 (
input wire i_clk,
input wire i_rst,
output wire q,
output wire uart_txd
);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
wire wb_clk;
wire wb_rst;
assign uart_txd = q;
servclone10_clock_gen clock_gen (
.i_clk(i_clk),
.i_rst(i_rst),
... | 7.604631 |
module servclone10_clock_gen (
input wire i_clk,
input wire i_rst,
output wire o_clk,
output wire o_rst
);
wire [4:0] clk;
wire clk_fb;
wire locked;
reg [9:0] r;
assign o_clk = clk[0];
assign o_rst = r[9];
always @(posedge o_clk)
if (locked) r <= {r[8:0], 1'b0};
... | 6.562102 |
module service (
input wire i_clk,
output wire q
);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
parameter PLL = "NONE";
wire wb_clk;
wire wb_rst;
servant_clock_gen #(
.PLL(PLL)
) clock_gen (
.i_clk(i_clk),
.o_clk(wb_clk),
.o_rst(wb_rst)
);
ser... | 6.916673 |
module service_go_board (
input wire i_clk,
output wire o_led1,
output wire o_led2 = 1'b0,
output wire o_led3 = 1'b0,
output wire o_led4 = 1'b0,
output wire o_uart_tx
);
parameter memfile = "blinky.hex";
parameter memsize = 512;
// Assert reset for 64 clock cycles. Use the 7th bit as th... | 7.686978 |
module service_window (
input CLK,
INIT,
input [15:0] SWLEN,
output reg SWSTAT
);
reg [15:0] q;
initial begin
q = 0;
SWSTAT = 1;
end
always @(negedge INIT) begin
if (INIT == 0) begin
SWSTAT = 0;
q = 0;
end
end
always @(posedge CLK) begin
if (q == SWLEN) beg... | 7.15998 |
module service_window_tb ();
localparam T = 20;
reg clk = 0, init = 0;
reg [15:0] swlen;
wire swstat;
service_window UUT (
.CLK(clk),
.INIT(init),
.SWLEN(swlen),
.SWSTAT(swstat)
);
always begin
clk = 1'b1;
#(T / 2);
clk = 1'b0;
#(T / 2);
end
initial begin
s... | 7.15998 |
module serving_arbiter (
input wire [31:0] i_wb_cpu_dbus_adr,
input wire [31:0] i_wb_cpu_dbus_dat,
input wire [ 3:0] i_wb_cpu_dbus_sel,
input wire i_wb_cpu_dbus_we,
input wire i_wb_cpu_dbus_stb,
output wire [31:0] o_wb_cpu_dbus_rdt,
output wire o_wb_cpu_dbus_ack,
... | 6.945087 |
module serving_mux (
input wire i_clk,
input wire i_rst,
input wire [31:0] i_wb_cpu_adr,
input wire [31:0] i_wb_cpu_dat,
input wire [ 3:0] i_wb_cpu_sel,
input wire i_wb_cpu_we,
input wire i_wb_cpu_stb,
output wire [31:0] o_wb_cpu_rdt,
output wire o_wb_cpu_a... | 6.704936 |
module serving_ram #( //Memory parameters
parameter depth = 256,
parameter aw = $clog2(depth),
parameter memfile = ""
) (
input wire i_clk,
input wire [aw-1:0] i_waddr,
input wire [7:0] i_wdata,
input wire i_wen,
input wire [aw-1:0] i_raddr,
output wire [7:0] o_rdata,
input ... | 7.38149 |
module servis (
input wire i_clk,
output wire q
);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
parameter PLL = "NONE";
wire wb_clk;
wire wb_rst;
servis_clock_gen clock_gen (
.i_clk(i_clk),
.o_clk(wb_clk),
.o_rst(wb_rst)
);
servant #(
.memfile(me... | 7.534329 |
module servive (
input wire i_clk,
input wire i_rst_n,
output wire q,
output wire uart_txd
);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
wire wb_clk;
wire wb_rst;
assign uart_txd = q;
servive_clock_gen clock_gen (
.i_clk(i_clk),
.i_rst(!i_rst_n),
... | 7.863926 |
module servive_clock_gen (
input wire i_clk,
input wire i_rst,
output wire o_clk,
output wire o_rst
);
wire locked;
reg [9:0] r;
assign o_rst = r[9];
always @(posedge o_clk)
if (locked) r <= {r[8:0], 1'b0};
else r <= 10'b1111111111;
wire [5:0] clk;
assign o_clk = clk[0]... | 7.100563 |
module servix (
input wire i_clk,
`ifdef WITH_RESET
input wire i_rst_n,
`endif
output wire q
);
parameter frequency = 32;
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
parameter PLL = "NONE";
wire wb_clk;
wire wb_rst;
servix_clock_gen #(
.frequency(frequency)
)... | 7.651798 |
module servix_clock_gen (
input wire i_clk,
input wire i_rst,
output wire o_clk,
output reg o_rst
);
parameter frequency = 32;
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(16),
.CLKIN1_PERIOD(10.0), //100MHz
.CLKOU... | 6.506166 |
module servix_ebaz4205 (
input wire i_clk,
output wire q
);
parameter frequency = 32;
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
parameter PLL = "NONE";
wire wb_clk;
wire wb_rst;
servix_ebaz4205_clock_gen #(
.frequency(frequency)
) clock_gen (
.i_clk(i_clk)... | 7.169891 |
module servix_ebaz4205_clock_gen (
input wire i_clk,
output wire o_clk,
output reg o_rst
);
parameter frequency = 32;
wire clkfb;
wire locked;
reg locked_r;
// (33.333 * 48) / 50 => 31.9996 MHz
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(48),
.CLKIN1_PERIOD(30.0... | 7.169891 |
module ServoAngle (
input wire clk,
rst_n,
input wire pw_true,
output reg [7:0] rotate_angle
);
parameter T_DELAY = 28'd60000000;
reg delay_rst;
reg [27:0] cnt_delay;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rotate_angle <= 8'd90;
delay_rst <= 1'b1;
e... | 6.890484 |
module ServoControl (
//////////// CLOCK //////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
//////////// KEY //////////
input [7:0] KEY,
//////////// LED //////////
output [7:0] LED,
//////////// SW //////////
input [3:0] SW,
//////////// GPIO_1, GPI... | 6.715083 |
module servoDriver #(
parameter minPulse = 500,
maxPulse = 2500,
clkDiv = 100,
minAngle = 0,
maxAngle = 270
) (
input wire [8:0] angle,
output wire servoPwm,
input wire rst_n,
clk
);
localparam slope = ((maxPulse - minPulse)) / ((maxAngle - minAngle));
reg [11:0] transVal;
p... | 7.692323 |
module ServoDriver_24MHz_30ms (
input clk,
enable,
input wire [7:0] data,
output reg servo_pulse
);
/*
INPUTS:
clk - clock
enable - an enable bit
data - the data describing the pulse to the servo, 8-bit (0-255) instruction
OUTPUTS:
servo_pulse - the servo pulse output
*/
//Assignments:
//par... | 6.989891 |
module ServoTx #(
parameter Resolution = 8,
parameter AddressWidth = 2,
parameter Frequency = ((2 ** Resolution) * 1000)
) (
input clk,
input rst,
input we,
input [Resolution-1:0] D,
input [AddressWidth-1:0] addr,
input servoclk,
output [(2**AddressWidth)-1:0] servo
);
reg [R... | 7.216356 |
module ServoTxTest;
reg clk, ce, rst, servoclock;
reg [7:0] data;
reg [1:0] addr;
wire [3:0] out;
ServoTx #(
.Resolution (8),
.AddressWidth(2)
) servoTx (
clk,
rst,
ce,
data,
addr,
servoclock,
out
);
initial begin
$dumpfile("test/io/ServoT... | 6.929174 |
module servo_controller_tb ();
// Inputs
reg clk_100M;
reg rst;
reg [7 : 0] angle;
reg [3 : 0] speed;
// Output
wire out_sig;
// 100 MHz clock gen
initial clk_100M = 1'b0;
always #5 clk_100M <= ~clk_100M;
servo_controller dut (
.clk_100M(clk_100M),
.rst (rst),
.en (... | 6.594136 |
module shift_8x64_taps (
clk,
shift,
shift_data,
tap0,
tap1,
tap2,
tap3,
tap4,
tap5,
tap6,
tap7
);
input clk, shift;
input [7:0] shift_data;
output [7:0] tap0, tap1, tap2, tap3, tap4, tap5, tap6, tap7;
reg [7:0] sr[63:0];
integer n;
always @(posedge clk) beg... | 7.32977 |
module servo_speed_control #(
parameter CNTR_BITS = 16
) (
input [CNTR_BITS - 1:0] start_pos,
input [CNTR_BITS - 1:0] end_pos,
input [CNTR_BITS - 1:0] prescale,
input go,
input clk,
output rdy,
output [CNTR_BITS - 1:0] out_cmp
);
reg [CNTR_BITS - 1:0] current; // kimenethez tartozo ... | 6.939328 |
module servo_speed_control_test;
reg clk;
reg go;
reg [15:0] start_pos;
reg [15:0] end_pos;
reg [15:0] prescale;
servo_speed_control SSCTest (
.start_pos(start_pos),
.end_pos(end_pos),
.prescale(prescale),
.go(go),
.clk(clk)
);
initial begin
go = 0;
clk = 0;
... | 6.939328 |
module servus (
input wire i_clk_p,
input wire i_clk_n,
output wire o_uart_tx,
output wire q
);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
wire i_clk;
wire clk;
wire rst;
assign o_uart_tx = q;
IBUFDS ibufds (
.I (i_clk_p),
.IB(i_clk_n),
.O (i_... | 7.21123 |
module instance
// generated by configure.py
module serv_0(
`ifdef USE_POWER_PINS
inout vdd, // User area 5.0V supply
inout vss, // User area ground
`endif
// IOs
input [4:0] io_in,
output [4:0] io_out,
output [4:0] io_oeb,
);
wire clk = io_in[0];
wire reset = io_in[1];
wire data =... | 6.778253 |
module instance
// generated by configure.py
module serv_1(
`ifdef USE_POWER_PINS
inout vdd, // User area 5.0V supply
inout vss, // User area ground
`endif
// IOs
input [4:0] io_in,
output [4:0] io_out,
output [4:0] io_oeb,
);
wire clk = io_in[0];
wire reset = io_in[1];
wire data =... | 6.778253 |
module instance
// generated by configure.py
module serv_2(
`ifdef USE_POWER_PINS
inout vdd, // User area 5.0V supply
inout vss, // User area ground
`endif
// IOs
input [4:0] io_in,
output [4:0] io_out,
output [4:0] io_oeb,
);
wire clk = io_in[0];
wire reset = io_in[1];
wire data =... | 6.778253 |
module serv_aligner (
input wire clk,
input wire rst,
// serv_top
input wire [31:0] i_ibus_adr,
input wire i_ibus_cyc,
output wire [31:0] o_ibus_rdt,
output wire o_ibus_ack,
// serv_rf_top
output wire [31:0] o_wb_ibus_adr,
output wire o_wb_i... | 9.991661 |
module serv_alu (
input wire clk,
input wire i_rst,
input wire i_en,
input wire i_rs1,
input wire i_rs2,
input wire i_imm,
input wire i_op_b_rs2,
input wire i_buf,
input wire i_init,
input wire i_cnt_done,
... | 6.996629 |
module serv_bufreg2 (
input wire i_clk,
//State
input wire i_en,
input wire i_init,
input wire i_cnt_done,
input wire [ 1:0] i_lsb,
input wire i_byte_valid,
output wire o_sh_done,
output wire o_sh_done_r,
//Control
input ... | 8.136256 |
module serv_csr (
input wire i_clk,
input wire i_run,
input wire [4:2] i_cnt,
input wire [3:2] i_cnt_r,
input wire i_e_op,
input wire i_ebreak,
input wire i_mem_cmd,
input wire i_mem_misalign,
//From mpram
input wire i_rf_csr_out... | 7.073851 |
module serv_ctrl (
input wire clk,
input wire i_rst,
//State
input wire i_pc_en,
input wire [ 4:2] i_cnt,
input wire [ 2:1] i_cnt_r,
input wire i_cnt_done,
//Control
input wire i_jump,
input wire i_jal_or_jalr,
input wire ... | 6.968922 |
module serv_mem_if (
input wire i_clk,
input wire i_rst,
input wire i_en,
input wire i_init,
input wire i_mem_op,
input wire i_signed,
input wire i_word,
input wire i_half,
input wire [ 1:0] i_bytecnt,
input wire ... | 7.584547 |
module serv_rf_if (
input wire i_clk,
input wire i_rst,
//RF Interface
output wire [5:0] o_wreg0,
output wire [5:0] o_wreg1,
output wire o_wen0,
output wire o_wen1,
output wire o_wdata0,
output wire o_wdata1,
output wire [5:0] o_rreg0,
output wire [5:... | 7.100451 |
module serv_rf_ram #(
parameter width = 0,
parameter depth = 32 * 36 / width
) (
input wire i_clk,
input wire [$clog2(depth)-1:0] i_waddr,
input wire [ width-1:0] i_wdata,
input wire i_wen,
input wire [$clog2(depth)-1:0] i_raddr,
output... | 8.309429 |
module serv_rf_ram #(
parameter width = 8,
parameter csr_regs = 4,
parameter depth = 32 * (32 + csr_regs) / width
) (
input wire i_clk,
input wire [$clog2(depth)-1:0] i_waddr,
input wire [ width-1:0] i_wdata,
input wire i_wen,
input wir... | 8.309429 |
module serv_rf_ram_if #(
parameter width = 8,
parameter depth = 32 * 36 / width
) (
//SERV side
input wire i_clk,
input wire i_rst,
input wire i_wreq,
input wire i_rreq,
output wire o_... | 6.898182 |
module serv_rf_ram_if #(
parameter width = 8,
parameter reset_strategy = "MINI",
parameter csr_regs = 4,
parameter depth = 32 * (32 + csr_regs) / width,
parameter l2w = $clog2(width)
) (
//SERV side
input wire i_clk,
input wire i_rst,... | 6.898182 |
module serv_shift (
input wire i_clk,
input wire i_load,
input wire [4:0] i_shamt,
input wire i_shamt_msb,
input wire i_signbit,
input wire i_right,
output wire o_done,
input wire i_d,
output wire o_q
);
reg signbit;
r... | 7.426933 |
module serv_state (
input wire i_clk,
input wire i_rst,
input wire i_new_irq,
output wire o_trap_taken,
output reg o_pending_irq,
input wire i_dbus_ack,
input wire i_ibus_ack,
output wire o_rf_rreq,
output wire o_rf_wreq,
... | 8.885811 |
module serv_synth_wrapper #(
/* Register signals before or after the decoder
0 : Register after the decoder. Faster but uses more resources
1 : (default) Register before the decoder. Slower but uses less resources
*/
parameter PRE_REGISTER = 1,
/* Amount of reset applied to design
"NON... | 7.788418 |
module ser_add (
input wire clk,
input wire rst,
input wire a,
input wire b,
input wire clr,
output wire q,
output wire o_v
);
reg c_r;
wire axorb = a ^ b;
assign o_v = (axorb & c_r) | (a & b);
assign q = axorb ^ c_r;
always @(posedge clk)
if (rst) c_r <= 1'b0;
... | 6.784316 |
module seseg (
seseg,
num
);
output reg [6:0] seseg;
input [3:0] num;
always @(num) begin
case (num)
0: seseg = 7'b1000000;
1: seseg = 7'b1111001;
2: seseg = 7'b0100100;
3: seseg = 7'b0110000;
4: seseg = 7'b0011001;
5: seseg = 7'b0010010;
6: seseg = 7'b000001... | 6.634921 |
module setbit (
output A
);
wire A;
assign A = 1;
endmodule
| 8.044466 |
module setbit_tb;
// Aケーブルを定義
wire A;
setbit SB1 (
// AケーブルをAピン(setbit.vでモジュールを定義)に接続
.A(A)
);
initial begin
$dumpfile("setbit_tb.vcd");
$dumpvars(0, setbit_tb);
#10
if (A != 1) $display("ERROR! Output does not 1");
else $display("Healthy");
#10 $finish;
end
endmodule... | 7.100034 |
module setcc (
input [`ICODEBUS] icode,
output set_cc
);
assign set_cc = icode == `IOPQ;
endmodule
| 7.024217 |
module SetFlager (
operator,
in_flags,
flags
);
input [3:0] operator;
input [3:0] in_flags;
wire carry, overflow, zero, negative;
output reg [3:0] flags;
//assign flags = {carry, overflow, zero, negative};
always @(operator or in_flags) begin
flags = in_flags;
case (operator)
//`... | 6.809464 |
module setPulse (
uclock,
num0,
num1,
num2,
num3,
switch,
switch2,
b0state,
pnum0,
pnum1,
pnum2,
pnum3
);
input [3:0] num0, num1, num2, num3;
input uclock, switch, switch2, b0state;
output reg [3:0] pnum0, pnum1, pnum2, pnum3;
reg [25:0] pulseTime;
reg pulsestat... | 6.837014 |
module setRegIO (
input wire [`icodeBus] icode,
input wire [ `regBus] srcA,
srcB,
output reg [ `regBus] d_srcA,
d_srcB,
output reg [ `regBus] d_dstE,
d_dstM
);
/***************************ȷd_srcAȡֵ*********************************/
always @(*) begin
case (icode)
`Rmmovq... | 7.430115 |
module SetSizeMem (
input wire [ 1:0] SizeMem_Ctrl,
input wire [31:0] MDR,
input wire [31:0] B,
output wire [31:0] Data_out
);
// 00 = byte
// 01 = halfword
// 10 = word
wire [31:0] byte_half;
assign byte_half = (SizeMem_Ctrl[0]) ? {MDR[31:16], B[15:0]} : {MDR[31:8], B[7:0]};
as... | 6.533237 |
module SetSizeReg (
input wire [ 1:0] Size_Ctrl,
input wire [31:0] MDR,
output wire [31:0] Data_out
);
// 00 = byte
// 01 = halfword
// 10 = word
wire [31:0] byte_half;
assign byte_half = (Size_Ctrl[0]) ? {16'd0, MDR[15:0]} : {24'd0, MDR[7:0]};
assign Data_out = (Size_Ctrl[1]) ? MDR... | 6.706864 |
module is to determine wheher to modify the date and time or not, and also, which one to be modified.
// Input functions:
// |-control: control is connected to the control button. Pressing of the control button will have the output 0_state toggled.
// |-left: left is connected to the left button. Pressing of the left b... | 7.88583 |
module testbench;
//----------Type declaration----------//
reg clk;
reg rst;
reg en;
reg [23:0] central;
reg [11:0] radius;
reg [1:0] mode;
wire busy;
wire valid;
wire [7:0] candidate;
//----------Module instance----------//
SET SET0 (
clk,
rst,
en,
central,
radiu... | 7.015571 |
module settings_bus #(
parameter AWIDTH = 16,
parameter DWIDTH = 32
) (
input wb_clk,
input wb_rst,
input [AWIDTH-1:0] wb_adr_i,
input [DWIDTH-1:0] wb_dat_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
output reg strobe,
output reg [7:0] addr,
output reg [31:0] da... | 7.903693 |
module settings_bus_16LE #(
parameter AWIDTH = 16,
RWIDTH = 8
) (
input wb_clk,
input wb_rst,
input [AWIDTH-1:0] wb_adr_i,
input [15:0] wb_dat_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
output strobe,
output reg [7:0] addr,
output reg [31:0] data
);
reg stb... | 8.330051 |
module takes the settings bus on one clock domain and crosses it over to another domain
// Typically it will be used with the input settings bus on the wishbone clock, and either
// the system or dsp clock on the output side
module settings_bus_crossclock
(input clk_i, input rst_i, input set_stb_i, input [7:0] set_... | 7.481591 |
module settings_bus_mux #(
parameter PRIO = 0, // 0 = Round robin, 1 = Lower ports get priority (see axi_mux)
parameter AWIDTH = 8,
parameter DWIDTH = 32,
parameter FIFO_SIZE = 1,
parameter NUM_BUSES = 2
) (
input clk,
input reset,
input clear,
input [NUM_BUSES-1:0] in_set_stb,
... | 8.330051 |
module settings_bus_mux_crossclock #(
parameter PRIO = 0, // 0 = Round robin, 1 = Lower ports get priority
parameter AWIDTH = 8,
parameter DWIDTH = 32,
parameter NUM_BUSES = 2
) (
input [NUM_BUSES-1:0] in_clk,
input [NUM_BUSES-1:0] in_rst,
input [NUM_BUSES-1:0] in_set_stb,
input [NUM_BU... | 8.330051 |
module settings_bus_timed_fifo #(
parameter BASE = 0,
parameter RANGE = 256,
parameter AWIDTH = 8,
parameter DWIDTH = 32,
parameter SIZE = 6
) (
input clk,
input reset,
input [63:0] vita_time,
input set_stb,
input [AWIDTH-1:0] set_addr,
input [DWIDTH-1:0] set_data,
i... | 8.330051 |
module settings_controller (
input clk,
reset_n,
input count_en,
count_up,
select,
output reg [19:0] phi_inc,
output reg [9:0] amplitude
);
//
parameter INCREMENT_MINIMUM = 20'd210;
parameter INCREMENT_MAXIMUM = 20'd20975;
parameter INITIAL_PHI_INC = 20'd10_000;
parameter INITIAL... | 7.56376 |
module in conjunction with settings_bus.v to add stateful reads
// to the settings bis. This enables you to do things like have registers reset atomicly
// as they are read. It also pipelines the address path to ease timing.
//
module settings_readback
#(parameter AWIDTH=16, parameter DWIDTH=32, parameter RB_ADDRW=2... | 9.196226 |
module setting_delay (
clk,
rst,
up,
down,
out,
display_delay
);
input clk, rst, up, down;
output out;
output [6:0] display_delay;
//变量类型
wire rst_n;
wire [1:0] state;
wire [1:0] next;
wire clkout0;
wire clkout1;
wire clkout2;
reg [1:0] nextl;
reg out;
reg [6:0] display... | 8.589358 |
module setting_mode (
clk,
up,
down,
hole_rst,
display_mode,
times
);
input clk, up, down;
output [9:0] hole_rst;
output [6:0] display_mode;
output [5:0] times;
//变量类型
wire [3:0] mode;
//实例化
FSM_hole U0 (
up,
down,
clk,
mode,
hole_rst
);
Display ... | 6.735684 |
module setting_reg #(
parameter my_addr = 0,
parameter width = 32,
parameter at_reset = 32'd0
) (
input clk,
input rst,
input strobe,
input wire [7:0] addr,
input wire [31:0] in,
output reg [width-1:0] out,
output reg changed
);
always @(posedge clk)
if (rst) begin
o... | 7.886667 |
module setting_reg_masked (
input clock,
input reset,
input strobe,
input wire [6:0] addr,
input wire [31:0] in,
output reg [31:0] out,
output reg changed
);
/* upper 16 bits are mask, lower 16 bits are value
* Note that you get a 16 bit register, not a 32 bit one */
parameter my_addr... | 7.381373 |
module setting_view (
input clk,
input rst,
input [2:0] view,
input [2:0] state,
input [2:0] player_count,
input [3:0] question_count,
input [6:0] answer_time,
input [6:0] win_socre,
input [3:0] success_score,
input [3:0] fail_score,
output [7:0] seg_out,
output [7:0] s... | 7.339908 |
module setupSystem (
CLOCK_50,
SW,
UART_TXD,
UART_RXD,
LEDR
);
input CLOCK_50;
input [17:0] SW;
output UART_TXD;
input UART_RXD;
output [17:0] LEDR;
wire CLOCK_100;
system systemUnit (
.clk(CLOCK_100),
.rst(SW[0]),
.TxD(UART_TXD),
.RxD(UART_RXD)
);
//TopCont... | 6.739893 |
module setup_tb ();
reg clk = 1'b0;
always begin
#10 clk = ~clk;
end
reg plus = 1'b0;
reg minus = 1'b0;
reg reset = 1'b0;
wire [3:0] hi;
wire [3:0] lo;
wire seconds;
setup setup (
clk,
plus,
minus,
reset,
hi,
lo,
seconds
);
initial begin
$du... | 6.983657 |
module set_64_1 (
input [6-1:0] sel,
input [64-1:0] din,
output reg [64-1:0] dout
);
always @* begin
dout = din;
dout = dout | (1 << sel);
end
endmodule
| 6.585318 |
module set_alarm (
input signal,
input load,
input moveRightBtn,
moveLeftBtn,
incrementBtn,
decrementBtn,
output reg [3:0] load_seconds,
output reg [2:0] load_minutes
);
reg currentPos = 0;
initial begin
load_seconds = 0;
load_minutes = 2;
end
always @(posedge signal) ... | 7.179009 |
module set_Alloc (
output reg alloc_e,
alloc_w,
alloc_n,
alloc_s,
alloc_j,
input e_vc_grant,
w_vc_grant,
n_vc_grant,
s_vc_grant,
j_vc_grant,
reset,
input [2:0] e_req,
w_req,
n_req,
s_req,
j_req
);
// inputs requests for outputs
always @(*) begin
... | 7.870448 |
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
| 6.939007 |
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
| 6.939007 |
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
| 6.939007 |
module set_m_stat (
input wire [`STAT_BUS] M_stat_i,
input wire mem_error_i,
output reg [`STAT_BUS] m_stat_o
);
always @(*) begin
if (mem_error_i == `FALSE) begin
m_stat_o = M_stat_i;
end else begin
m_stat_o = `SADR;
end
end
endmodule
| 6.729093 |
module Set_Number_Controler (
input wire clk,
input wire rst,
input wire buttonUp,
input wire buttonCentre,
input wire buttonDown,
input wire buttonLeft,
input wire buttonRight,
output reg up,
output reg set,
output reg down,
output reg left,
output reg right
... | 7.039206 |
module Set_Number_Controler_tb ();
reg clk;
reg rst;
reg signal;
wire edgeDetected;
EdgeDetector edgedetector_tb (
.clk(clk),
.rst(rst),
.signal(signal),
.detected(edgeDetected)
);
integer i = 0;
initial begin
$monitor("%100d\n", $time);
$dumpfile("Set_Number_Cont... | 7.039206 |
module set_om (
//Input
input iClk,
input iReset_n,
input iRun,
//Output
output oFinish,
output reg [12:0] oAddr_OM,
output reg oWrreq_OM,
output reg [31:0] oData_to_OM
);
//=============================REGISTERS================... | 8.496468 |
module Set_Ram (
input clk,
input [7:0] character,
output reg [15:0] row0,
output reg [15:0] row1,
output reg [15:0] row2,
output reg [15:0] row3,
output reg [15:0] row4,
output reg [15:0] row5,
output reg [15:0] row6,
output reg [15:0] row7,
output reg [15:0] row8,
outpu... | 6.626504 |
module set_reset_sync (
input wire clock,
input wire set,
input wire reset,
output reg q = initial_state
);
parameter initial_state = 1'b0;
reg tmp = 0;
always @(posedge set or posedge q) begin
if (q) tmp <= 1'b0;
else tmp <= 1'b1;
end
always @(posedge clock) begin
if (rese... | 6.686921 |
module set_ships (
input clk,
input reset,
input place,
input [35:0] pressed_key,
output reg [35:0] ships
);
wire [5:0] index;
find_one_hot_index IDX (
pressed_key,
index
);
always @(posedge clk or negedge reset) begin
if (~reset) ships <= 0;
else if (place) ships[index... | 6.986448 |
module set_signal_detect (
input wire clk,
input wire rst_n,
input wire other_btn,
input wire second_clk,
input wire set_btn,
output reg set_status // 检测是否是 set 阶段的输出
);
reg set_done = 0;
reg [2:0] fives_count = 0;
wire second_clk_pos;
// set_status
/*
当 set... | 7.996508 |
module set_xm_inputs (
rd,
xm_o_in,
ir,
exception,
ALUout,
PC1
);
input [31:0] ir, ALUout, PC1;
input exception;
output [4:0] rd;
output [31:0] xm_o_in;
wire [4:0] opcode, aluop, rd_og, rd_1;
assign opcode = ir[31:27];
assign aluop = ir[6:2];
assign rd_og = ir[26:22];
wire ... | 6.854057 |
module is used to synchronize signals cross clock domain
//
// Modification History
// ******************************************************************************
// Date BY Version Change Description
// -------------------------------------------------------------------------
// 2019-10... | 7.817486 |
module Seven_segment_Decrementer (
input clock,
input reset, // reset
// Basys3 uses a common anode 7-segment display, but each of the 4 common-anode
// lines are connected, so you can only illuminate one display at once
output reg [3:0] anode_activation,
output reg [6:0] LED_segment
); // cor... | 7.316611 |
module seven (
input clk,
output [2:0] choice,
output [6:0] Outcode
);
reg [6:0] Outcode;
reg [1:0] choice = 2'b01;
integer i;
always @(posedge clk) begin
case (choice)
2'b01: Outcode = 7'b1011011;
2'b10: Outcode = 7'b0111111;
2'b11: Outcode = 7'b1111111;
endcase
if (ch... | 7.224734 |
module sevenBitFourInMux (
input [6:0] in0, // mux inputs
input [6:0] in1, // mux inputs
input [6:0] in2, // mux inputs
input [6:0] in3, // mux inputs
input [1:0] sel, // select line
output [6:0] out // output from mux
);
//-------------Code Starts Here-------
reg [6:0] tmp;
a... | 7.921357 |
module sevenDecoder (
output reg [6:0] Y,
input [3:0] I
);
always @(I) begin
case (I)
4'b0000: Y = 7'b1111110;
4'b0001: Y = 7'b0110000;
4'b0010: Y = 7'b1101101;
4'b0011: Y = 7'b1111001;
4'b0100: Y = 7'b0110011;
4'b0101: Y = 7'b1011011;
4'b0110: Y = 7'b1011111;
... | 6.568799 |
module sevenseg_decimal (
data,
ledsegments
);
input [3:0] data;
output reg [6:0] ledsegments;
always @(data)
case (data)
// gfe_dcba -> 654_3210
// 1 -> off, 0 -> on
0: ledsegments = 7'b100_0000;
1: ledsegments = 7'b111_1001;
2: ledsegments = 7'b010_0100;
3: ledse... | 7.173378 |
module SevenSegDisp (
Display7,
SevenSegDisplays
);
input [31:0] Display7;
output [55:0] SevenSegDisplays;
HexDecoder dsp0 (
Display7[3:0], //Input
SevenSegDisplays[6:0]
);
HexDecoder dsp1 (
Display7[7:4], //Input
SevenSegDisplays[13:7]
);
HexDecoder dsp2 (
Display... | 6.875626 |
module SevenSegDisplay (
input [31:0] x,
input clk,
output reg [6:0] seg,
output reg [7:0] an,
output wire dp
);
wire [ 2:0] s;
reg [ 3:0] digit;
wire [ 7:0] aen;
reg [19:0] clkdiv;
assign dp = 1;
assign s = clkdiv[19:17];
assign aen = 8'b11111111; // all turned off initially... | 8.532227 |
module sevenSegDisplayer (
output [6:0] seg,
output [3:0] an,
input clk,
input [15:0] number
);
wire targetClk;
clockDivisorBundle #(18) cdb (
targetClk,
clk
);
wire [1:0] state;
counter #(2) ct (
state,
targetClk
);
activeLowDecoder #(2) ald (
an,
sta... | 8.192834 |
module SevenSegDriver (
D3,
D2,
D1,
D0,
Display,
Reset,
Clock,
Select
);
input [7:0] D3, D2, D1, D0;
input Reset, Clock;
output [7:0] Display;
output [3:0] Select;
//module DisplayMux(D3, D2, D1, D0, Select, Display, Reset, Clock) ;
DisplayMux DisplayInput (
D3,
... | 6.623853 |
module SevenSegEnc (
output reg [6:0] Disp,
input [3:0] BCD
);
////////////SIMPLE BCD TO 7seg Encoder////////
// abc_defg
parameter BLANK = 7'b111_1111;
parameter ZERO = 7'b000_0001;
parameter ONE = 7'b100_1111;
parameter TWO = 7'b001_0010;
parameter THREE = 7'b000_0110;
para... | 8.555683 |
module SevenSegEncoder (
input [3:0] m,
output [6:0] n
);
//a is the most significant bit, d is the least significant bit
wire a, b, c, d;
assign a = m[3];
assign b = m[2];
assign c = m[1];
assign d = m[0];
//n[0]-n[6] = LED0-LED6, respectively
assign n[0] = (~a & ~b & ~c & d) | (~a & b & ~c ... | 6.826575 |
module sevenSegment (
floor,
seg
);
input [3:0] floor;
output reg [6:0] seg;
// schematic 7 segment display
// b1
// b6 b2
// b7
// b5 b3
// b4
always @(floor) begin
case (floor)
0: seg = 7'b0111111;
1: seg = 7'b0000110;
2: seg = 7'b1011011... | 6.908148 |
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