code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module test_serialadder;
reg reset, a, b, sign, ctrl;
serialadder se1 (
sum,
clk,
a,
b,
sign,
ctrl
);
clkout y (clk);
initial begin
reset = 1'b1;
a = 1'b1;
b = 1'b0;
sign = 1'b1;
ctrl = 1'b1;
#5 reset = 1'b0;
#5 ctrl = 1'b0;
#5 a = 1'b1;
... | 6.57834 |
module shiftreg_8_serial (
out,
in,
clk,
ctrl
);
output out;
input in, clk, ctrl;
reg [7:0] Regs;
assign out = Regs[0];
always @(posedge clk) begin
if (!ctrl) begin
Regs[0] <= Regs[1];
Regs[1] <= Regs[2];
Regs[2] <= Regs[3];
Regs[3] <= Regs[4];
Regs[4] <= Regs... | 7.22057 |
module shiftreg_15_serial (
out,
in,
clk
);
output out;
input in, clk, reset;
reg [14:0] Regs;
assign out = Regs[0];
always @(posedge clk) begin
Regs[0] <= Regs[1];
Regs[1] <= Regs[2];
Regs[2] <= Regs[3];
Regs[3] <= Regs[4];
Regs[4] <= Regs[5];
Regs[5] <= Regs[6];
... | 6.955747 |
module testserialreg;
reg [7:0] in;
reg inp;
clkout y (clk);
reg reset, ctrl;
shiftreg_8_serial Reg1 (
out,
inp,
clk,
ctrl
);
initial begin
ctrl = 1'b0;
reset = 1'b1;
in = 8'b011001x0;
#10 inp = in[0];
reset = 1'b0;
#10 inp = in[1];
#10 inp = in[2];
... | 6.569215 |
module serial_bitwise_pe (
xOut,
yOut,
xOrW,
yIn,
ctrl,
clk
);
output yOut, xOut;
input xOrW, yIn, clk;
input [2:0] ctrl;
wire [5:0] WtoMul;
wire ctrl_not;
not n1 (ctrl_not, ctrl[0]);
mux m1 (
IN,
xOrW,
1'b0,
ctrl[1]
);
shiftreg_8_serial Reg1 (
Reg... | 7.208086 |
module serial_buffer (
input clock,
input reset,
input [31:0] addr_in,
output reg [31:0] data_out,
input re_in,
input [31:0] data_in,
input we_in,
input s_data_valid_in, //data to be read is available
input [7:0] s_data_in,
input s_data_ready_in, //ready to recieve write data... | 7.607398 |
module serial_ck #(
parameter P_Y_INIT = 0
) (
input clk, // clock
input rst, // active high resset
input y0, // idle output level
input [7:0] ncyc, // number of data bits, minimum valid value is 1
input [31:0] n0, // number of cnt cycles in getting started, minimum valid value is 1
in... | 8.416623 |
module serial_config (
input clk,
input rst,
input [15:0] config_data,
input [ 3:0] config_addr,
input config_start,
output config_idle,
output config_done,
output adc3wire_clk,
output adc3wire_data,
output adc3wire_strobe
);
wire clk_d... | 6.695446 |
module serial_core #(
parameter CLOCK = 25000000,
BAUD = 57600,
SAMPLE_POINT = 8
) (
clk,
rx,
tx,
rx_ready,
tx_ready,
midstate,
data2,
word,
tx_busy,
rx_busy
);
// IO Declaration
//===================================================
input clk;
input rx;
out... | 6.519333 |
module serial_crc_ccitt (
clk,
reset,
enable,
init,
data_in,
crc_out
);
//-----------Input Ports---------------
input clk;
input reset;
input enable;
input init;
input data_in;
//-----------Output Ports---------------
output [15:0] crc_out;
//------------Internal Variables-----... | 7.23712 |
module serial_crc_ccitt (
clk,
reset,
enable,
init,
data_in,
crc_out
);
input clk;
input reset;
input enable;
input init;
input data_in;
output [15:0] crc_out;
reg [15:0] lfsr;
assign crc_out = lfsr;
always @(posedge clk)
if (reset) begin
lfsr <= 16'hFFFF;
end ... | 7.23712 |
module: Serial_CRC_eq2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Serial_CRC_eq2_test;
// Inputs
reg clk;
reg reset;
reg [5:0] data_in;
// Outputs
wire [4:0] data_out;
... | 6.734226 |
module: CRC_serial
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
///SERIAL CRC WORKING
//Verilog test bench code for generator polynomial 1+y+y8+y9
//Serial CRC circuit
module serial_CR... | 6.964889 |
module controls the serial modules.
//
// Alex Marschner
// 2007.02.20
`timescale 1 ns / 100 ps
module serial_ctrl (
fsl_data_i, fsl_senddata_i, fsl_cts_o,
fsl_data_o, fsl_rxdata_o, fsl_cts_i,
rs232_tx_data_o, rs232_rx_data_i, rs232_rts_i, rs232_cts_o,
clock, reset
);
parameter CLOCK_FREQ_MHZ = 50;
parameter ... | 7.843499 |
module serial_Dflipflop (
set,
data,
clk,
reset,
s1,
s2
);
parameter SIZE = 1;
input [SIZE-1:0] set, data;
input clk, reset;
output [SIZE-1:0] s1, s2;
if (SIZE > 1)
Dflipflop inst0 (
set[0],
data[0],
reset,
s1[0],
s2[0]
);
if (SIZE > 2... | 6.981932 |
module serial_div (
input wire clk,
input wire rst,
input wire signed_div_i,
input wire [31:0] opdata1_i,
input wire [31:0] opdata2_i,
input wire start_i,
input wire annul_i,
output reg [63:0] result_o,
output reg ready_o
);
wire [32:0] div_temp;
r... | 6.932986 |
module serial_Dlatch (
D,
clk,
Q,
QN
);
parameter WIRE = 1;
input clk;
input [WIRE -1:0] D;
output [WIRE -1:0] Q, QN;
if (WIRE > 0)
Dlatch latch1 (
D[0],
clk,
Q[0],
QN[0]
);
if (WIRE > 1)
serial_Dlatch #(
.WIRE(WIRE - 1)
) recall (
... | 6.906728 |
module serial_Dlatch_rst (
data,
clk,
rst,
Q,
QN
);
parameter WIRE = 1;
input [WIRE -1:0] data;
input clk, rst;
output [WIRE -1:0] Q, QN;
if (WIRE > 0)
Dlatch_rst latch1 (
data[0],
clk,
rst,
Q[0],
QN[0]
);
if (WIRE > 1)
serial_Dlatch_... | 6.906728 |
module/serial_tx.v"
`include "../serial_module/serial_rx.v"
module serial_echo (
input ser_rx,
output led_red,
output led_green,
output led_blue,
output ser_tx,
output spi_ssn
);
//Due to using UART, the SPI_SSN pin must be held high to avoid interfering with further programming of the fla... | 7.012184 |
module serial_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_o... | 6.737823 |
module serial_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_o... | 6.737823 |
module Serial_Generate_tb;
// Inputs
reg clk;
reg rst;
reg enable;
// Outputs
wire serial_data;
wire div_clk;
// Instantiate the Unit Under Test (UUT)
Serial_Generate uut (
.clk(clk),
.enable(enable),
.serial_data(serial_data),
.div_clk(div_clk),
.rst(rst)
);
i... | 6.890771 |
module slave_receive (
clk,
RxD,
nonce,
new_nonce,
reset
);
// Serial receive buffer for a 4-byte nonce
input clk;
input RxD;
wire RxD_data_ready;
wire [7:0] RxD_data;
async_receiver deserializer (
.clk(clk),
.RxD(RxD),
.RxD_data_ready(RxD_data_ready),
.R... | 6.902762 |
module serial_in #(
parameter CLK_FREQUENCY_HZ = 50_000_000,
parameter SERIAL_BPS = 230_400,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire reset,
input wire rx,
output reg [DATA_WIDTH - 1:0] data,
output reg oe
);
// Definitions to make code easier to read and understand.
... | 7.745591 |
module serial_inputs_logic_control (
serial_clock_i,
serial_reset_i_b,
serial_br_i,
serial_br_trans_i,
serial_scon0_ri_i,
serial_scon1_ti_i,
serial_scon3_tb8_i,
serial_scon4_ren_i,
serial_scon7_sm0_i,
serial_serial_tx_i,
serial_data_sbuf_i,
serial_p3_0_i,
serial_cloc... | 7.417511 |
module serial_in_parallel_out (
input clk,
input reset,
input a,
output reg [7:0] out
);
/*
clk: Clock
reset: Reset bit of the module
a: Input bit of the module
out: 8-bit output of the module
*/
// Sequential Control (FLIP FLOP CONTROL)
// Asynchronous reset
always @(posedge cl... | 7.359173 |
module
module serial_in_parallel_out_tb;
// Initialising inputs and outputs
reg clk, reset;
reg a;
wire [7:0] out;
// Instantiate the Unit Under Test (UUT)
serial_in_parallel_out UUT(.clk(clk), .reset(reset), .a(a), .out(out));
// Testing the module with a stream of serial input
ini... | 7.525784 |
module serial_JKlatchUP_rst (
J,
K,
clk,
reset,
Q,
QN
);
parameter SIZE = 1;
input [SIZE -1:0] J, K;
input clk, reset;
output [SIZE -1:0] Q, QN;
JKlatchUP_rst JKlatchUP_rst_inst (
J[0],
K[0],
clk,
reset,
Q[0],
QN[0]
);
if (SIZE > 1)
serial_J... | 7.419968 |
module serial_JKlatchDown_rst (
J,
K,
clk,
reset,
Q,
QN
);
parameter SIZE = 1;
input [SIZE -1:0] J, K;
input clk, reset;
output [SIZE -1:0] Q, QN;
JKlatchDown_rst JKlatchDown_rst_inst (
J[0],
K[0],
clk,
Q[0],
QN[0]
);
if (SIZE > 1)
serial_JKlatchD... | 7.419968 |
module serial_multrom_mult_core #(
parameter HALF_WIDTH = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input [2 * HALF_WIDTH - 1:0] mult1,
mult2,
input start,
input [2 * HALF_WIDTH - 1:0] rom_dout,
output reg [2 * HALF_WIDTH - 1:0] rom_address,
output r... | 6.890702 |
module serial_multrom_mult_top #(
parameter HALF_WIDTH = 2
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input start,
input [2 * HALF_WIDTH - 1:0] mult1,
mult2,
output [4 * HALF_WIDTH - 1:0] dout
);
wire [2 * HALF_WIDTH - 1:0] rom_dout;
wire [2 * HALF_WIDTH - ... | 6.890702 |
module serial_m_lfs_XOR (
message,
cur_parity,
nxt_parity
);
//////////////////////////////////////////////////////////////////////
parameter PARITY_LENGTH = 480; // 32b * 15b/b = 480b
parameter [0:480] GEN_POLY = 481'b110111010011101111010001110111100011011111001010110010101111110111011101010011000... | 7.457128 |
module serial_nand (
out,
e1
);
parameter BEHAVIORAL = 1;
parameter WAY = 3; //nombre d'input (pour cette gate)
input [WAY-1:0] e1;
output out;
if (BEHAVIORAL == 1) begin
wire line;
serial_and #(
.WAY(WAY)
) serial_and_inst (
line,
e1
);
not inst_not0 (ou... | 7.146881 |
module generate_serial_nand (
out,
e1
);
parameter BEHAVIORAL = 1;
parameter WAY = 3;
parameter N1 = (WAY / 2) + (WAY % 2);
parameter N2 = WAY / 2;
input [WAY-1:0] e1;
output out;
wire W1, W2;
if (WAY == 1) //nombre d'input insuffisant (sera traiter a l'etage du dessus)
assign out = e1[0... | 6.749357 |
module serial_nor (
out,
e1
);
parameter BEHAVIORAL = 0;
parameter WAY = 3;
input [WAY-1:0] e1;
output out;
if (BEHAVIORAL == 1) begin
wire line;
serial_or #(
.WAY(WAY)
) serial_or_inst (
line,
e1
);
not inst_not0 (out, line);
end else
generate_seria... | 6.603991 |
module generate_serial_nor (
out,
e1
);
parameter BEHAVIORAL = 1;
parameter WAY = 3;
parameter N1 = (WAY / 2) + (WAY % 2);
parameter N2 = WAY / 2;
input [WAY-1:0] e1;
output out;
wire W1, W2;
if (WAY == 1) assign out = e1[0];
else if (WAY == 2) begin
if (BEHAVIORAL == 1) or inst_or1 (o... | 6.749357 |
module serial_not (
out,
in
);
parameter WIRE = 3;
parameter N1 = (WIRE / 2) + (WIRE % 2); //1+1 = 2
parameter N2 = WIRE / 2; // = 1
input in;
output [WIRE-1 : 0] out;
wire l1, l2;
if (WIRE == 1) assign out = in;
else if (WIRE > 1) begin
not not1 (l1, in);
not not2 (l2, in);
... | 7.148861 |
module serial_out #(
parameter CLK_FREQUENCY_HZ = 50_000_000,
parameter SERIAL_BPS = 230_400,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire reset,
input wire ie,
input wire [DATA_WIDTH - 1:0] data,
output reg tx,
output reg sending = 0
);
// Definitions to make code ea... | 9.721671 |
module serial_protocol_decoder (
//input clk_in,
input [7:0] serial_data_in,
input serial_data_ready_signal_in,
input gpu_working_status_signal_in,
output reg [1:0] buffer_select_out,
output reg gpu_command_start_signal_out,
output reg [3:0] gpu_command_out,
output reg [7:0] gpu_spr_sele... | 6.605005 |
module Serial_Ram #(
parameter DATA_WIDTH = 12,
parameter ADDR_WIDTH = 2048
) (
input [(DATA_WIDTH-1):0] data_a,
data_b,
input [(ADDR_WIDTH-1):0] addr_a,
addr_b,
input we_a,
we_b,
clk,
output reg [(DATA_WIDTH-1):0] q_a,
q_b
);
// Declare the RAM variable
reg [11:0] ram[2... | 8.638766 |
module serial_receiver (
clock,
extReset,
rx,
transmitting,
// outputs...
op,
data,
execute
);
parameter [31:0] FREQ = 100000000;
parameter [31:0] RATE = 115200;
input clock;
input extReset;
input rx;
input transmitting;
output [7:0] op;
output [31:0] data;
output exe... | 7.516637 |
module serial_receiver_32_w (
clk,
rx,
byte_out,
ready,
timeout
);
input clk, rx;
output reg [7:0] byte_out;
output reg ready, timeout;
localparam [3:0] IDLE = 4'b0000;
localparam [3:0] START_BIT = 4'b0001;
localparam [3:0] BIT_0 = 4'b0010;
localparam [3:0] BIT_1 = 4'b0011;
localp... | 7.516637 |
module serial_receiver_main_32_w (
clk,
rx,
reset,
data_0,
data_1,
data_2,
data_3,
data_4,
data_5,
data_6,
data_7,
data_8,
data_9,
data_10,
data_11,
data_12,
data_13,
data_14,
data_15,
data_16,
data_17,
data_18,
data_19,
dat... | 7.516637 |
module test;
localparam BAUD = `BTEST;
reg clk = 0;
reg [2:0] clk_div = 0;
always @(posedge clk) clk_div <= clk_div + 1;
wire slw_clk2 = clk_div[2];
wire slw_clk1 = clk_div[1];
wire slw_clk0 = clk_div[0];
reg reset = 1;
reg rcv = 0;
reg [39:0] rx_reg = 0;
reg [31:0] tx_reg = 0;
reg [2:0] rx_b... | 7.680846 |
module serial_reg_iface (
input reset_i,
input clk_i,
input rx_i,
output tx_o,
output reg cmdfifo_rxf,
output cmdfifo_txe,
input cmdfifo_rd,
input cmdfifo_wr,
output [7:0] cmdfifo_din,
input [7:0] cmdfifo_dout
);
wire clk;
wire tx_out;
wire rx_in;
assign clk = clk... | 6.807612 |
module serial_rx #(
parameter P_Y_INIT = 0,
parameter P_DATA_WIDTH = 256
) (
input clk, // clock
input rst, // active high resset
input a, // input data, msb first
input [7:0] nbits, // number of data bits, minimum valid value is 1
input [31:0] n0, // number of cnt cycles in getting sta... | 9.13625 |
module serial_rx2(
input clk, // timespec 7.2 ns
// input tick,
input bit,
output reg sync,
output reg [63:0] d,
output reg [7:0] errors
);
// handles the double-sampled input, automatic search for
// proper receive clock phase, and error counting.
// Multiplex between possible data sources
reg b1=0, b2=0;
alw... | 7.295134 |
module serial_rx_ctrl_32_w (
clk,
rx_done,
byte_in,
tmout,
crc_16,
crc_busy,
reset,
data_out,
selector,
data_strb,
validate,
errors_cnt,
crc_reset
);
input clk, rx_done, tmout, crc_busy, reset;
input [7:0] byte_in;
input [15:0] crc_16;
output reg data_strb, ... | 7.748381 |
module SERIAL_RX_FIFO #(
parameter DEPTH = 5
) (
input CLK_RX,
RST,
RX,
CLK_RD,
RD_EN,
output reg DATA_RDY,
output [7:0] DATA
);
localparam N = 2 ** DEPTH;
reg [7:0] FIFO[0:N-1];
reg [DEPTH-1:0] rd_cnt, wr_cnt, wr_cnt_sync, wr_cnt_sync1;
wire [7:0] rx_data;
reg rd_ack;
wire ... | 8.73306 |
module serial_send (
input RSTXS,
input RSTXF,
input CLKS,
input CLKSS,
input CLKF,
input CLKF_DATA,
input SERDESSTROBE,
input [15:0] DIN,
output [ 1:0] DOUT
);
reg [15:0] din_d1 = 16'd0;
always @(posedge CLKF) din_d1 <= D... | 6.728365 |
module serial_sender (
dout,
din,
strobe,
clk
);
output reg dout;
input [7:0] din;
input strobe, clk;
reg [8:0] shift_reg = 0; // If we do not initialize it here,
// it will become 0 after 7 clk posedge.
// So why not?
always @(posedg... | 7.353955 |
module serial_sende_tb;
wire dout;
reg [7:0] din = 0;
reg strobe = 0, clk = 0;
serial_sender sender (
dout,
din,
strobe,
clk
);
// Set clk.
always #5 clk = ~clk;
// Set strobe.
initial begin
#20 strobe = 1;
#10 strobe = 0;
#140 strobe = 1;
#10 strobe = 0;
... | 7.082851 |
module serial_shiftadder_multipcation #(
parameter WIDTH = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input multiplier_valid,
input [WIDTH - 1:0] multiplier1,
input [WIDTH - 1:0] multiplier2,
output reg product_valid,
output reg [2 * WIDTH - 1:0] product
... | 6.707834 |
module serial_tb ();
reg clk = 0;
reg [15:0] sw = 16'h0000;
wire [15:0] led;
reg [4:0] buttons = 1;
wire [7:0] seg;
wire [3:0] an;
reg RxD = 1;
wire TxD;
//length of bit in nanoseconds at 38400baud = (100,000,000Hz/38400Bps) * 10ns/C = 26041.6ns/B
parameter delay = 26042;
always #5 clk = ~clk;... | 6.557845 |
module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2016
// The RS-232 settings are fixed
// TX: 8-bit data, 2 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
//`define SIMULATION // in this mode, TX outputs one bit per clock cycle
// and RX... | 6.83375 |
module async_receiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are se... | 7.236243 |
module BaudTickGen (
input clk,
enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 25000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer log2(input integer v);
begin
log2 = 0;
while (v >> log2) log... | 7.463142 |
module serial_to_parallel (
clk,
rstN,
shift_enable,
serial_in,
data_out
);
input clk;
input rstN;
input shift_enable;
input serial_in;
output [7:0] data_out;
wire [7:7] data_out_dup_0;
OBUF \data_out_obuf(0) (
.O(data_out[0]),
.I(data_out_dup_0[7])
);
OBUF \data_o... | 7.424897 |
module serial_to_settings (
input clk,
input reset,
// Serial signals (async)
input scl,
input sda,
// Settngs bus out
output reg set_stb,
output reg [7:0] set_addr,
output reg [31:0] set_data,
// Debug
output [31:0] debug
);
reg [2:0] state;
localparam SEARCH = 3'h0;
... | 8.748676 |
module serial_to_settings_tb ();
reg clk;
reg reset;
wire scl;
wire sda;
wire set_stb;
wire [ 7:0] set_addr;
wire [31:0] set_data;
//
// These registers optionaly used
// to drive nets through procedural assignments in test bench.
// These drivers default ... | 8.748676 |
module serial_transceiver (
dout,
led,
cathodes,
anodes,
din,
sws,
clk
);
output dout;
output [7:0] led;
output [7:0] cathodes;
output [3:0] anodes;
input [1:0] sws;
input din, clk;
parameter BAUD_RATE = 9600, SAMPLE_RATIO = 16, CLK_FREQUENCY = 100_000_000, LED_SCAN_RATE = 1... | 6.655964 |
module serial_transceiver_tb;
wire dout;
reg din = 1, clk = 0;
serial_transceiver transceiver (
dout
,,,,
din,
2'b0,
clk
);
always #1 clk = ~clk;
initial begin
$monitor($time, " dout: %b, din: %b", dout, din);
#300000 din = 0;
#20832 din = 1;
#20832 din = 1... | 6.655964 |
module serial_transmitter (
input logic clk,
input logic rst,
input logic [7:0] data,
input logic send,
output logic done,
output logic val
);
logic [7:0] data_to_send;
//----------------------------------------------------------------------
// Controlle... | 8.418721 |
module serial_transmitter_32_w (
clk,
byte_in,
start,
reset,
tx,
ready
);
input clk, start, reset;
input [7:0] byte_in;
output reg tx, ready;
localparam [3:0] IDLE = 4'b0000;
localparam [3:0] ST_0 = 4'b0001;
localparam [3:0] ST_1 = 4'b0010;
localparam [3:0] ST_2 = 4'b0011;
loc... | 8.418721 |
module serial_transmitter_main_32_w (
clk,
data_0,
data_1,
data_2,
data_3,
data_4,
data_5,
data_6,
data_7,
data_8,
data_9,
data_10,
data_11,
data_12,
data_13,
data_14,
data_15,
data_16,
data_17,
data_18,
data_19,
data_20,
data_2... | 8.418721 |
module/baudgen.vh"
module serial_transmitter_tb ();
localparam BAUD = `B115200;
localparam BITRATE = (BAUD << 1);
localparam FRAME = (BITRATE * 11);
localparam FRAME_WAIT = (BITRATE * 4);
reg clk = 0;
wire tx;
reg data_availible = 0;
reg [16:0] decoded_data = 17'b10101010101010101;
reg [23:0] timestamp_last_d... | 6.673769 |
module serial_transmitter_wrapper (
//============ Wishbone ============
input logic wb_clk,
input logic wb_rst,
input logic wb_cyc,
input logic wb_stb,
input logic wb_we,
input logic [ 3:0] wb_sel,
input logic [31:0] wb_dat_i,
input logic [... | 8.418721 |
module serial_tx #(
parameter P_Y_INIT = 0,
parameter P_DATA_WIDTH = 256
) (
input clk, // clock
input rst, // active high resset
input y0, // idle output level
input [P_DATA_WIDTH-1:0] data, // data to be shifted out, msb first
input [7:0] nbits, // number of data bits, minimum valid ... | 9.16422 |
module serial_txd (
input clk_30,
input reset_n,
// WISHBONE slave
input [7:0] DAT_I,
output reg ACK_O,
input CYC_I,
input STB_I,
input WE_I,
//serial output
input uart_rxd,
input uart_rts,
output reg uart_txd,
output uart_cts
);
assign uart_cts = uart_rts;
r... | 7.291424 |
module serial_tx_ctrl (
clk,
data_in,
start,
tx_done,
crc_16,
reset,
byte_out,
reset_crc,
start_tx,
ready,
data_select,
data_lock,
state
);
input clk, start, tx_done, reset;
input [15:0] data_in, crc_16;
output reg [7:0] byte_out, data_select;
output reg sta... | 7.724739 |
module serial_tx_ctrl_32_w (
clk,
data_in,
start,
tx_done,
crc_16,
reset,
byte_out,
reset_crc,
start_tx,
ready,
data_select,
data_lock
);
input clk, start, tx_done, reset;
input [15:0] data_in, crc_16;
output reg [7:0] byte_out, data_select;
output reg start_tx,... | 7.724739 |
module serial_wb_io ( /*AUTOARG*/
// Outputs
tx_o,
data_o,
parport_o,
parport_readstrobe_o,
parport_writestrobe_o,
wbm_dat_o,
wbm_adr_o,
wbm_cyc_o,
wbm_lock_o,
wbm_sel_o,
wbm_stb_o,
wbm_we_o,
// Inputs
clk_i,
rst_i,
rx_i,
address_i,
data_i,
... | 6.947969 |
module serial_wb_top (
input wire clk_i,
rst_i,
rx_i,
output wire tx_o,
input wire [31:0] parport_i,
output wire [31:0] parport_o,
output wire parport_readstrobe_o,
output wire parport_writestrobe_o,
// Wishbone master interface wbm_*:
input wire [31:0] wbm_dat_i,
output wi... | 7.590039 |
module serial_xnor (
out,
e1
);
parameter BEHAVIORAL = 1;
parameter WAY = 3; //nombre d'input (pour cette gate)
input [WAY-1:0] e1;
output out;
if (BEHAVIORAL == 1) begin
wire line;
serial_xor #(
.WAY(WAY)
) serial_and_inst (
line,
e1
);
not inst_not0 (ou... | 7.202856 |
module generate_serial_xnor (
out,
e1
);
parameter BEHAVIORAL = 0;
parameter WAY = 3;
parameter N1 = (WAY / 2) + (WAY % 2);
parameter N2 = WAY / 2;
input [WAY-1:0] e1;
output out;
wire W1, W2;
if (WAY == 1) //nombre d'input insuffisant (sera traiter a l'etage du dessus)
assign out = e1[0... | 6.749357 |
module series7_clocks (
input rst,
input sysclk_p,
input sysclk_n,
output clk_eth,
output clk_eth_90,
output pll_lock,
output clk_1x_90,
output clk_2x_0,
output mmcm_lock
);
parameter clkin_period = 5; // PLLE2_BASE CLKIN1_PERIOD in ns. default 200MHz input.
parameter pll_mul... | 7.063196 |
module serif_tap (
input clk,
input din,
output dout,
output [7:0] rx_byte,
output rx_byte_valid,
input [7:0] tx_byte,
input tx_byte_valid,
output reg tx_byte_ack
);
//////////////////////////////////////
// RX bit to byte
reg [8:0] din_sr = 9'h1ff;
always @(posedge clk) b... | 7.263747 |
module serout (
clk,
rst,
rs232tx,
ptdata,
en,
ready
);
input clk;
input rst;
input en;
input [127:0] ptdata;
output rs232tx;
output ready;
reg ready;
wire txbusy;
reg txen;
reg [7:0] txdata;
reg [4:0] sentbytes;
reg [7:0] busywait;
async_transmitter rs232 (
clk... | 6.621478 |
module serv_shift (
input wire clk,
input wire rst_n,
input wire i_load,
input wire [4:0] i_shamt,
input wire i_shamt_msb,
input wire i_signbit,
input wire i_right,
output wire o_done,
input wire i_d,
output wire o_q
)... | 7.426933 |
module serv_alu (
input wire clk,
input wire rst_n,
input wire i_en,
input wire i_shift_op,
input wire i_cnt0,
input wire i_rs1,
input wire i_rs2,
input wire i_imm,
input wire i_op_b_rs2,
input wire i_buf,
... | 6.996629 |
module serv_ctrl #(
parameter RESET_PC = 32'd0,
parameter WITH_CSR = 1
) (
input wire clk,
input wire rst_n,
//State
input wire i_pc_en,
input wire i_cnt12to31,
input wire i_cnt0,
input wire i_cnt2,
input wire i_cnt_done,
... | 7.710679 |
module serv_mem_if #(
parameter WITH_CSR = 1
) (
input wire clk,
input wire rst_n,
//State
input wire i_en,
input wire [ 1:0] i_bytecnt,
input wire [ 1:0] i_lsb,
output wire o_misalign,
//Control
input wire i_mem_op,
input wire ... | 8.245301 |
module serv_rf_if #(
parameter WITH_CSR = 1
) ( //RF Interface
output wire [4+WITH_CSR:0] o_wreg0,
output wire [4+WITH_CSR:0] o_wreg1,
output wire o_wen0,
output wire o_wen1,
output wire o_wdata0,
output wire o_wdata1,
output w... | 7.090096 |
module serv_rf_ram_if (
//SERV side
input wire clk,
input wire rst_n,
input wire i_wreq,
input wire i_rreq,
output wire o_ready,
input wire [4:0] i_wreg0,
input wire [4:0] i_wreg1,
input wire i_wen0,
input wire i_wen1,
input ... | 6.898182 |
module servant_arbiter (
input wire [31:0] i_wb_cpu_dbus_adr,
input wire [31:0] i_wb_cpu_dbus_dat,
input wire [ 3:0] i_wb_cpu_dbus_sel,
input wire i_wb_cpu_dbus_we,
input wire i_wb_cpu_dbus_cyc,
output wire [31:0] o_wb_cpu_dbus_rdt,
output wire o_wb_cpu_dbus_ack,
... | 6.900507 |
module servant_gpio (
input wire clk,
input wire rst_n,
input wire [1:0] i_wb_dat,
input wire i_wb_we,
input wire i_wb_cyc,
output wire [1:0] o_wb_rdt,
output reg [1:0] o_gpio
);
assign o_wb_rdt = o_gpio;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) o_gpio <= 2'b0;
... | 7.177402 |
module servant_mux (
input wire clk,
input wire rst_n,
input wire [31:0] i_wb_cpu_adr,
input wire [31:0] i_wb_cpu_dat,
input wire [ 3:0] i_wb_cpu_sel,
input wire i_wb_cpu_we,
input wire i_wb_cpu_cyc,
output wire [31:0] o_wb_cpu_rdt,
output reg ... | 6.899667 |
module servant_ac701 (
input wire sys_clk_p,
input wire sys_clk_n,
input wire btn,
output wire q
);
parameter frequency = 16;
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
parameter PLL = "NONE";
wire wb_clk;
reg wb_rst;
wire clk;
wire clkfb;
wire locked;
re... | 6.719159 |
module servant_arbiter (
input wire [31:0] i_wb_cpu_dbus_adr,
input wire [31:0] i_wb_cpu_dbus_dat,
input wire [ 3:0] i_wb_cpu_dbus_sel,
input wire i_wb_cpu_dbus_we,
input wire i_wb_cpu_dbus_cyc,
output wire [31:0] o_wb_cpu_dbus_rdt,
output wire o_wb_cpu_dbus_ack,
... | 6.900507 |
module servant_clock_gen (
input wire i_clk,
output wire o_clk,
output wire o_rst
);
parameter [79:0] PLL = "NONE";
generate
if ((PLL == "ICE40_CORE") || (PLL == "ICE40_PAD")) begin
ice40_pll #(
.PLL(PLL)
) pll (
.i_clk(i_clk),
.o_clk(o_clk),
.o... | 6.746628 |
module servant_cmod_a7 (
input wire i_clk,
input wire i_rst,
output wire o_uart_tx,
output wire q
);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
wire wb_clk;
wire wb_rst;
assign o_uart_tx = q;
servant_cmod_a7_clock_gen clock_gen (
.i_clk(i_clk),
.i_rst... | 7.233256 |
module servant_cmod_a7_clock_gen (
input wire i_clk,
input wire i_rst,
output wire o_clk,
output reg o_rst
);
wire clkfb;
wire locked;
reg locked_r;
MMCME2_BASE #(
.CLKIN1_PERIOD(83.333), //12MHz
/* Set VCO frequency to 12*64=768 MHz
Allowed values are 2.0 to 64.0. Resulting... | 7.233256 |
module servant_ecp5 (
input wire clk,
input wire btn0,
output wire wifi_gpio0,
output wire uart_txd,
output wire q
);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
wire wb_clk;
wire wb_rst;
assign wifi_gpio0 = btn0;
assign uart_txd = q;
servant_ecp5_clock_ge... | 6.831301 |
module servant_ecp5_clock_gen (
input i_clk,
input i_rst,
output o_clk,
output o_rst
);
wire locked;
reg [1:0] rst_reg;
always @(posedge o_clk)
if (i_rst) rst_reg <= 2'b11;
else rst_reg <= {!locked, rst_reg[1]};
assign o_rst = rst_reg[0];
pll pll (
.clki (i_clk),
.cl... | 6.765157 |
module servant_gpio (
input wire i_wb_clk,
input wire i_wb_dat,
input wire i_wb_we,
input wire i_wb_cyc,
output reg o_wb_rdt,
output reg o_gpio
);
always @(posedge i_wb_clk) begin
o_wb_rdt <= o_gpio;
if (i_wb_cyc & i_wb_we) o_gpio <= i_wb_dat;
end
endmodule
| 7.177402 |
module servant_lx9 (
input wire i_clk,
input wire i_rst,
output wire o_uart_tx,
output wire q
);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
wire wb_clk;
wire wb_rst;
assign o_uart_tx = q;
servant_lx9_clock_gen clock_gen (
.i_clk(i_clk),
.i_rst(i_rst),... | 7.527946 |
module servant_mux (
input wire i_clk,
input wire i_rst,
input wire [31:0] i_wb_cpu_adr,
input wire [31:0] i_wb_cpu_dat,
input wire [ 3:0] i_wb_cpu_sel,
input wire i_wb_cpu_we,
input wire i_wb_cpu_cyc,
output wire [31:0] o_wb_cpu_rdt,
output reg ... | 6.899667 |
module servant_ram #( //Memory parameters
parameter depth = 256,
parameter aw = $clog2(depth),
parameter RESET_STRATEGY = "",
parameter memfile = ""
) (
input wire i_wb_clk,
input wire i_wb_rst,
input wire [aw-1:2] i_wb_adr,
input wire [31:0] i_wb_dat,
input wire [3:0] i_wb_sel,
... | 7.373151 |
module servant_timer #(
parameter WIDTH = 16,
parameter RESET_STRATEGY = "",
parameter DIVIDER = 0
) (
input wire i_clk,
input wire i_rst,
output reg o_irq,
input wire [31:0] i_wb_dat,
input wire i_wb_we,
input wire i_wb_cyc,
output reg [... | 6.517634 |
module servant_upduino2 (
output wire g,
output wire b,
output wire r,
output wire q
);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
parameter PLL = "NONE";
wire clk;
wire clk48;
wire locked;
SB_HFOSC inthosc (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKH... | 7.015621 |
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