code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module \commonlib_muxn__N2__width2 (
input [1:0] in_data_0,
input [1:0] in_data_1,
input [0:0] in_sel,
output [1:0] out
);
wire [1:0] _join_out;
coreir_mux #(
.width(2)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N2__width1 (
input [0:0] in_data_0,
input [0:0] in_data_1,
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module lutN #(
parameter N = 1,
parameter init = 1
) (
input [N-1:0] in,
output out
);
assign out = init[in];
endmodule
| 7.756611 |
module RShift_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] lshr8_inst0_out;
coreir_lshr #(
.width(8)
) lshr8_inst0 (
.in0(I__0),
.in1(I__1),
.out(lshr8_inst0_out)
);
assign O = lshr8_inst0_out;
assign v... | 7.73328 |
module Partition_S_no4_ni1_tElSTuple_3_SSeq_3_Int___vTrue (
input clk,
input [7:0] I_0_0_0,
input [7:0] I_0_0_1,
input [7:0] I_0_0_2,
input [7:0] I_0_1_0,
input [7:0] I_0_1_1,
input [7:0] I_0_1_2,
input [7:0] I_0_2_0,
input [7:0] I_0_2_1,
input [7:0] I_0_2_2,
input [7:0] I_1_... | 6.630566 |
module Partition_S_no4_ni1_tElSTuple_3_Int__vTrue (
input clk,
input [7:0] I_0_0,
input [7:0] I_0_1,
input [7:0] I_0_2,
input [7:0] I_1_0,
input [7:0] I_1_1,
input [7:0] I_1_2,
input [7:0] I_2_0,
input [7:0] I_2_1,
input [7:0] I_2_2,
input [7:0] I_3_0,
input [7:0] I_3_1,
... | 6.630566 |
module Negate8 (
input [7:0] I,
output [7:0] O
);
wire [7:0] coreir_neg_inst0_out;
coreir_neg #(
.width(8)
) coreir_neg_inst0 (
.in (I),
.out(coreir_neg_inst0_out)
);
assign O = coreir_neg_inst0_out;
endmodule
| 7.306678 |
module NativeMapParallel_n4_unq2 (
input [7:0] I_0_0_0,
input [7:0] I_0_0_1,
input [7:0] I_0_0_2,
input [7:0] I_1_0_0,
input [7:0] I_1_0_1,
input [7:0] I_1_0_2,
input [7:0] I_2_0_0,
input [7:0] I_2_0_1,
input [7:0] I_2_0_2,
input [7:0] I_3_0_0,
input [7:0] I_3_0_1,
input ... | 7.274395 |
module NativeMapParallel_n4 (
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I0_2,
input [7:0] I0_3,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
input [7:0] I1_3,
output [7:0] O_0_0,
output [7:0] O_0_1,
output [7:0] O_1_0,
output [7:0] O_1_1,
output [7:0] O... | 7.274395 |
module NativeMapParallel_n3 (
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I0_2,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
output [7:0] O_0__0,
output [7:0] O_0__1,
output [7:0] O_1__0,
output [7:0] O_1__1,
output [7:0] O_2__0,
output [7:0] O_2__1,
outp... | 7.274395 |
module NativeMapParallel_n2 (
input [7:0] I_0,
input [7:0] I_1,
output [7:0] out_0,
output [7:0] out_1
);
wire [7:0] dehydrate_tArray_8_Bit__inst0_out;
wire [7:0] dehydrate_tArray_8_Bit__inst1_out;
\aetherlinglib_dehydrate__hydratedTypeBit8 dehydrate_tArray_8_Bit__inst0 (
.in (I_0),
... | 7.274395 |
module NativeMapParallel_n1_unq3 (
input [7:0] I_0__0,
input [7:0] I_0__1,
output [7:0] O_0,
output valid_down,
input valid_up
);
wire [7:0] RShift_Atom_inst0_O;
wire RShift_Atom_inst0_valid_down;
RShift_Atom RShift_Atom_inst0 (
.I__0(I_0__0),
.I__1(I_0__1),
.O(RShift_Atom_in... | 7.274395 |
module NativeMapParallel_n1_unq4 (
input [7:0] I_0_0__0,
input [7:0] I_0_0__1,
output [7:0] O_0_0,
output valid_down,
input valid_up
);
wire [7:0] NativeMapParallel_n1_inst0_O_0;
wire NativeMapParallel_n1_inst0_valid_down;
NativeMapParallel_n1_unq3 NativeMapParallel_n1_inst0 (
.I_0__0(I_... | 7.274395 |
module NativeMapParallel_n1_unq1 (
input [7:0] I0_0,
input [7:0] I1_0,
output [7:0] O_0__0,
output [7:0] O_0__1,
output valid_down,
input valid_up
);
wire [7:0] atomTupleCreator_t0Int_t1Int_inst0_O__0;
wire [7:0] atomTupleCreator_t0Int_t1Int_inst0_O__1;
wire atomTupleCreator_t0Int_t1Int_in... | 7.274395 |
module NativeMapParallel_n1_unq2 (
input [7:0] I0_0_0,
input [7:0] I1_0_0,
output [7:0] O_0_0__0,
output [7:0] O_0_0__1,
output valid_down,
input valid_up
);
wire [7:0] NativeMapParallel_n1_inst0_O_0__0;
wire [7:0] NativeMapParallel_n1_inst0_O_0__1;
wire NativeMapParallel_n1_inst0_valid_do... | 7.274395 |
module Mux_Array_8_Bit_t_2n (
input [7:0] data_0,
input [7:0] data_1,
output [7:0] out,
input [0:0] sel
);
wire [7:0] CommonlibMuxN_n2_w8_inst0_out;
wire [7:0] NativeMapParallel_n2_inst0_out_0;
wire [7:0] NativeMapParallel_n2_inst0_out_1;
wire [7:0] hydrate_tArray_8_Bit__inst0_out;
\commonl... | 7.171087 |
module Mux_Array_8_Bit_t_1n (
input [7:0] data_0,
output [7:0] out,
input [0:0] sel
);
Term_Bits_1_t Term_Bits_1_t_inst0 (.I(sel));
assign out = data_0;
endmodule
| 7.171087 |
module Mux2xOutBits3 (
input [2:0] I0,
input [2:0] I1,
output [2:0] O,
input S
);
wire [2:0] coreir_commonlib_mux2x3_inst0_out;
\commonlib_muxn__N2__width3 coreir_commonlib_mux2x3_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x3_inst0_out)
);... | 7.210649 |
module Mux2xOutBits2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
input S
);
wire [1:0] coreir_commonlib_mux2x2_inst0_out;
\commonlib_muxn__N2__width2 coreir_commonlib_mux2x2_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x2_inst0_out)
);... | 7.816223 |
module Mux2xOutBits1 (
input [0:0] I0,
input [0:0] I1,
output [0:0] O,
input S
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
\commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x1_inst0_out)
);... | 7.639545 |
module Map_T_n4_i0_unq3 (
input clk,
input [7:0] I_0_0_0,
input [7:0] I_0_0_1,
input [7:0] I_0_0_2,
input [7:0] I_1_0_0,
input [7:0] I_1_0_1,
input [7:0] I_1_0_2,
input [7:0] I_2_0_0,
input [7:0] I_2_0_1,
input [7:0] I_2_0_2,
input [7:0] I_3_0_0,
input [7:0] I_3_0_1,
... | 6.954784 |
module Map_T_n4_i0_unq2 (
input clk,
input [7:0] I_0_0,
input [7:0] I_0_1,
input [7:0] I_0_2,
input [7:0] I_1_0,
input [7:0] I_1_1,
input [7:0] I_1_2,
input [7:0] I_2_0,
input [7:0] I_2_1,
input [7:0] I_2_2,
input [7:0] I_3_0,
input [7:0] I_3_1,
input [7:0] I_3_2,
... | 6.954784 |
module Map_T_n4_i0_unq1 (
input clk,
input [7:0] I0_0_0,
input [7:0] I0_0_1,
input [7:0] I0_1_0,
input [7:0] I0_1_1,
input [7:0] I0_2_0,
input [7:0] I0_2_1,
input [7:0] I0_3_0,
input [7:0] I0_3_1,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
input [7:0] I1_3,... | 6.954784 |
module Map_T_n4_i0 (
input clk,
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I0_2,
input [7:0] I0_3,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
input [7:0] I1_3,
output [7:0] O_0_0,
output [7:0] O_0_1,
output [7:0] O_1_0,
output [7:0] O_1_1,
output [... | 7.799479 |
module Lt_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [0:0] O,
output valid_down,
input valid_up
);
wire coreir_ult8_inst0_out;
coreir_ult #(
.width(8)
) coreir_ult8_inst0 (
.in0(I__0),
.in1(I__1),
.out(coreir_ult8_inst0_out)
);
assign O = coreir_ult8_inst0_ou... | 7.118379 |
module LUT3_16 (
input I0,
input I1,
input I2,
output O
);
wire coreir_lut3_inst0_out;
lutN #(
.init(8'h10),
.N(3)
) coreir_lut3_inst0 (
.in ({I2, I1, I0}),
.out(coreir_lut3_inst0_out)
);
assign O = coreir_lut3_inst0_out;
endmodule
| 7.554919 |
module LUT2_8 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
lutN #(
.init(4'h8),
.N(2)
) coreir_lut2_inst0 (
.in ({I1, I0}),
.out(coreir_lut2_inst0_out)
);
assign O = coreir_lut2_inst0_out;
endmodule
| 7.722694 |
module LUT1_2 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h2),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 8.126826 |
module LUT1_1 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h1),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 7.409016 |
module LUT1_0 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h0),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 7.399772 |
module LShift_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] shl8_inst0_out;
coreir_shl #(
.width(8)
) shl8_inst0 (
.in0(I__0),
.in1(I__1),
.out(shl8_inst0_out)
);
assign O = shl8_inst0_out;
assign valid_... | 8.458485 |
module NativeMapParallel_n3_unq2 (
input [7:0] I_0__0,
input [7:0] I_0__1,
input [7:0] I_1__0,
input [7:0] I_1__1,
input [7:0] I_2__0,
input [7:0] I_2__1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
wire [7:0] LShift_Atom_inst0... | 7.274395 |
module NativeMapParallel_n3_unq3 (
input [7:0] I_0_0__0,
input [7:0] I_0_0__1,
input [7:0] I_0_1__0,
input [7:0] I_0_1__1,
input [7:0] I_0_2__0,
input [7:0] I_0_2__1,
input [7:0] I_1_0__0,
input [7:0] I_1_0__1,
input [7:0] I_1_1__0,
input [7:0] I_1_1__1,
input [7:0] I_1_2__0,... | 7.274395 |
module If_Atom_Intt (
input [0:0] I__0,
input [7:0] I__1__0,
input [7:0] I__1__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] Mux_Array_8_Bit_t_2n_inst0_out;
Mux_Array_8_Bit_t_2n Mux_Array_8_Bit_t_2n_inst0 (
.data_0(I__1__1),
.data_1(I__1__0),
.out(Mux_A... | 7.310169 |
module Register8 (
input clk,
input [7:0] I,
output [7:0] O
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst2_O;
wire DFF_init0_has_ce... | 6.73316 |
module Register_Array_8_Bit_t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I,
output [7:0] O
);
wire [7:0] Register8_inst0_O;
Register8 Register8_inst0 (
.clk(clk),
.I (I),
.O (Register8_inst0_O)
);
assign O = Register8_inst0_O;
endmodule
| 7.102239 |
module Register_Tuple_0_Array_8_Bit__1_Array_8_Bit__t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O__0,
output [7:0] O__1
);
wire [7:0] Register_Array_8_Bit_t_0init_FalseCE_FalseRESET_inst0_O;
wire [7:0] Register_Array_8_Bit_t_0init_FalseCE_FalseRESET_i... | 6.647526 |
module Register_Array_4_Array_8_Bit__t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
input [7:0] I_3,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output [7:0] O_3
);
wire [7:0] Register_Array_8_Bit_t_0init_FalseCE_FalseRESET_inst... | 7.102239 |
module Register_Array_1_Array_8_Bit__t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I_0,
output [7:0] O_0
);
wire [7:0] Register_Array_8_Bit_t_0init_FalseCE_FalseRESET_inst0_O;
Register_Array_8_Bit_t_0init_FalseCE_FalseRESET Register_Array_8_Bit_t_0init_FalseCE_FalseRESET_inst0(
.clk(clk),
... | 7.102239 |
module Register_Array_1_Array_1_Array_8_Bit___t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I_0_0,
output [7:0] O_0_0
);
wire [7:0] Register_Array_1_Array_8_Bit__t_0init_FalseCE_FalseRESET_inst0_O_0;
Register_Array_1_Array_8_Bit__t_0init_FalseCE_FalseRESET Register_Array_1_Array_8_Bit__t_0init_Fal... | 7.102239 |
module Register_Bitt_0init_FalseCE_FalseRESET (
input clk,
input I,
output O
);
wire [0:0] Register1_inst0_O;
Register1 Register1_inst0 (
.clk(clk),
.I (I),
.O (Register1_inst0_O)
);
assign O = Register1_inst0_O[0];
endmodule
| 7.503354 |
module Counter3_Mod5CE (
input CE,
input clk,
output [2:0] O
);
wire [2:0] Counter3CER_inst0_O;
wire LUT3_16_inst0_O;
wire and_inst0_out;
Counter3CER Counter3CER_inst0 (
.CE(CE),
.clk(clk),
.O(Counter3CER_inst0_O),
.RESET(and_inst0_out)
);
LUT3_16 LUT3_16_inst0 (
.I... | 6.549827 |
module Counter2_Mod4CE (
input CE,
input clk,
output [1:0] O
);
wire [1:0] Counter2CER_inst0_O;
wire LUT2_8_inst0_O;
wire and_inst0_out;
Counter2CER Counter2CER_inst0 (
.CE(CE),
.clk(clk),
.O(Counter2CER_inst0_O),
.RESET(and_inst0_out)
);
LUT2_8 LUT2_8_inst0 (
.I0(C... | 6.745207 |
module Add_Atom_unq1 (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] coreir_add8_inst0_out;
coreir_add #(
.width(8)
) coreir_add8_inst0 (
.in0(I__0),
.in1(I__1),
.out(coreir_add8_inst0_out)
);
assign O = coreir_a... | 6.880887 |
module Add_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O
);
wire [7:0] coreir_add8_inst0_out;
coreir_add #(
.width(8)
) coreir_add8_inst0 (
.in0(I__0),
.in1(I__1),
.out(coreir_add8_inst0_out)
);
assign O = coreir_add8_inst0_out;
endmodule
| 6.918465 |
module renamedForReduce (
input [7:0] in0,
input [7:0] in1,
output [7:0] out
);
wire [7:0] Add_Atom_inst0_O;
Add_Atom Add_Atom_inst0 (
.I__0(in0),
.I__1(in1),
.O(Add_Atom_inst0_O)
);
assign out = Add_Atom_inst0_O;
endmodule
| 7.384035 |
module ReduceParallel_n3 (
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
output [7:0] O
);
wire [7:0] renamedForReduce_inst0_out;
wire [7:0] renamedForReduce_inst1_out;
renamedForReduce renamedForReduce_inst0 (
.in0(I_1),
.in1(renamedForReduce_inst1_out),
.out(renamedForR... | 7.174445 |
module Reduce_S_n3 (
input clk,
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
output [7:0] O_0,
output valid_down,
input valid_up
);
wire [7:0] ReduceParallel_n3_inst0_O;
wire [7:0] Register_Array_1_Array_8_Bit__t_0init_FalseCE_FalseRESET_inst0_O_0;
wire [0:0] reg_P_inst0_out;
R... | 7.025687 |
module NativeMapParallel_n3_unq4 (
input clk,
input [7:0] I_0_0,
input [7:0] I_0_1,
input [7:0] I_0_2,
input [7:0] I_1_0,
input [7:0] I_1_1,
input [7:0] I_1_2,
input [7:0] I_2_0,
input [7:0] I_2_1,
input [7:0] I_2_2,
output [7:0] O_0_0,
output [7:0] O_1_0,
output [7:0... | 7.274395 |
module NativeMapParallel_n1 (
input [7:0] I_0__0,
input [7:0] I_0__1,
output [7:0] O_0
);
wire [7:0] Add_Atom_inst0_O;
Add_Atom Add_Atom_inst0 (
.I__0(I_0__0),
.I__1(I_0__1),
.O(Add_Atom_inst0_O)
);
assign O_0 = Add_Atom_inst0_O;
endmodule
| 7.274395 |
module renamedForReduce_unq1 (
input [7:0] in0_0,
input [7:0] in1_0,
output [7:0] out_0
);
wire [7:0] NativeMapParallel_n1_inst0_O_0;
NativeMapParallel_n1 NativeMapParallel_n1_inst0 (
.I_0__0(in0_0),
.I_0__1(in1_0),
.O_0(NativeMapParallel_n1_inst0_O_0)
);
assign out_0 = NativeMap... | 7.384035 |
module ReduceParallel_n3_unq1 (
input [7:0] I_0_0,
input [7:0] I_1_0,
input [7:0] I_2_0,
output [7:0] O_0
);
wire [7:0] renamedForReduce_inst0_out_0;
wire [7:0] renamedForReduce_inst1_out_0;
renamedForReduce_unq1 renamedForReduce_inst0 (
.in0_0(I_0_0),
.in1_0(renamedForReduce_inst1_... | 7.174445 |
module Reduce_S_n3_unq1 (
input clk,
input [7:0] I_0_0,
input [7:0] I_1_0,
input [7:0] I_2_0,
output [7:0] O_0_0,
output valid_down,
input valid_up
);
wire [7:0] ReduceParallel_n3_inst0_O_0;
wire [7:0] Register_Array_1_Array_1_Array_8_Bit___t_0init_FalseCE_FalseRESET_inst0_O_0_0;
wire ... | 7.107378 |
module NativeMapParallel_n4_unq6 (
input clk,
input [7:0] I_0_0_0,
input [7:0] I_0_0_1,
input [7:0] I_0_0_2,
input [7:0] I_0_1_0,
input [7:0] I_0_1_1,
input [7:0] I_0_1_2,
input [7:0] I_0_2_0,
input [7:0] I_0_2_1,
input [7:0] I_0_2_2,
input [7:0] I_1_0_0,
input [7:0] I_1_... | 7.274395 |
module Map_T_n4_i0_unq8 (
input clk,
input [7:0] I_0_0_0,
input [7:0] I_0_0_1,
input [7:0] I_0_0_2,
input [7:0] I_0_1_0,
input [7:0] I_0_1_1,
input [7:0] I_0_1_2,
input [7:0] I_0_2_0,
input [7:0] I_0_2_1,
input [7:0] I_0_2_2,
input [7:0] I_1_0_0,
input [7:0] I_1_0_1,
... | 6.954784 |
module Add8_cin (
input CIN,
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire bit_const_0_None_out;
wire [7:0] coreir_add8_inst0_out;
wire [7:0] coreir_add8_inst1_out;
corebit_const #(.value(0)) bit_const_0_None (.out(bit_const_0_None_out));
coreir_add #(
.width(8)
) coreir_add8_... | 8.416699 |
module Sub_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] Sub8_inst0_O;
Sub8 Sub8_inst0 (
.I0(I__0),
.I1(I__1),
.O (Sub8_inst0_O)
);
assign O = Sub8_inst0_O;
assign valid_down = valid_up;
endmodule
| 6.934876 |
module NativeMapParallel_n4_unq7 (
input clk,
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I0_2,
input [7:0] I0_3,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
input [7:0] I1_3,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output [7:0] O_3,
ou... | 7.274395 |
module Map_T_n4_i0_unq9 (
input clk,
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I0_2,
input [7:0] I0_3,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
input [7:0] I1_3,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output [7:0] O_3,
output vali... | 6.954784 |
module Sharpen (
input clk,
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
input [7:0] I_3,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output [7:0] O_3,
output valid_down
);
top t (
.clk(clk),
.valid_up(1'd1),
.I_0(I_0),
.I_1(I_1),
... | 7.189878 |
module stupleToSSeq_tSSeq_3_Int__n3 (
input [7:0] I_0_0,
input [7:0] I_0_1,
input [7:0] I_0_2,
input [7:0] I_1_0,
input [7:0] I_1_1,
input [7:0] I_1_2,
input [7:0] I_2_0,
input [7:0] I_2_1,
input [7:0] I_2_2,
output [7:0] O_0_0,
output [7:0] O_0_1,
output [7:0] O_0_2,
... | 6.674959 |
module stupleToSSeq_tInt_n3 (
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
assign O_0 = I_0;
assign O_1 = I_1;
assign O_2 = I_2;
assign valid_down = valid_up;
endmodule
| 6.674959 |
module sseqTupleAppender_tSSeq_3_Int__n2 (
input [7:0] I0_0_0,
input [7:0] I0_0_1,
input [7:0] I0_0_2,
input [7:0] I0_1_0,
input [7:0] I0_1_1,
input [7:0] I0_1_2,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
output [7:0] O_0_0,
output [7:0] O_0_1,
output [7:0] O_... | 7.061223 |
module sseqTupleAppender_tInt_n2 (
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
assign O_0 = I0_0;
assign O_1 = I0_1;
assign O_2 = I1;
assign valid_down = valid_up;
endmodule
| 7.061223 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module corebit_and (
input in0,
input in1,
output out
);
assign out = in0 & in1;
endmodule
| 8.125026 |
module coreir_ult #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 < in1;
endmodule
| 7.861561 |
module coreir_ugt #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 > in1;
endmodule
| 7.36211 |
module coreir_term #(
parameter width = 1
) (
input [width-1:0] in
);
endmodule
| 6.849594 |
module coreir_shl #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 << in1;
endmodule
| 8.595943 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_neg #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = -in;
endmodule
| 7.306788 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_mem #(
parameter has_init = 0,
parameter depth = 1,
parameter width = 1
) (
input clk,
input [width-1:0] wdata,
input [$clog2(depth)-1:0] waddr,
input wen,
output [width-1:0] rdata,
input [$clog2(depth)-1:0] raddr
);
reg [width-1:0] data[depth-1:0];
always @(posedge... | 7.482949 |
module coreir_lshr #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 >> in1;
endmodule
| 8.306547 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module \commonlib_muxn__N2__width8 (
input [7:0] in_data_0,
input [7:0] in_data_1,
input [0:0] in_sel,
output [7:0] out
);
wire [7:0] _join_out;
coreir_mux #(
.width(8)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N2__width3 (
input [2:0] in_data_0,
input [2:0] in_data_1,
input [0:0] in_sel,
output [2:0] out
);
wire [2:0] _join_out;
coreir_mux #(
.width(3)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N2__width2 (
input [1:0] in_data_0,
input [1:0] in_data_1,
input [0:0] in_sel,
output [1:0] out
);
wire [1:0] _join_out;
coreir_mux #(
.width(2)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N2__width1 (
input [0:0] in_data_0,
input [0:0] in_data_1,
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module lutN #(
parameter N = 1,
parameter init = 1
) (
input [N-1:0] in,
output out
);
assign out = init[in];
endmodule
| 7.756611 |
module RShift_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] lshr8_inst0_out;
coreir_lshr #(
.width(8)
) lshr8_inst0 (
.in0(I__0),
.in1(I__1),
.out(lshr8_inst0_out)
);
assign O = lshr8_inst0_out;
assign v... | 7.73328 |
module RAM1x64 (
input clk,
input [0:0] RADDR,
output [63:0] RDATA,
input [0:0] WADDR,
input [63:0] WDATA,
input WE
);
wire [63:0] coreir_mem1x64_inst0_rdata;
coreir_mem #(
.depth(1),
.has_init(0),
.width(64)
) coreir_mem1x64_inst0 (
.clk (clk),
.raddr(RADDR)... | 6.723651 |
module Partition_S_no8_ni1_tElSTuple_3_Int__vTrue (
input clk,
input [7:0] I_0_0,
input [7:0] I_0_1,
input [7:0] I_0_2,
input [7:0] I_1_0,
input [7:0] I_1_1,
input [7:0] I_1_2,
input [7:0] I_2_0,
input [7:0] I_2_1,
input [7:0] I_2_2,
input [7:0] I_3_0,
input [7:0] I_3_1,
... | 6.630566 |
module Negate8 (
input [7:0] I,
output [7:0] O
);
wire [7:0] coreir_neg_inst0_out;
coreir_neg #(
.width(8)
) coreir_neg_inst0 (
.in (I),
.out(coreir_neg_inst0_out)
);
assign O = coreir_neg_inst0_out;
endmodule
| 7.306678 |
module NativeMapParallel_n3 (
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I0_2,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
output [7:0] O_0__0,
output [7:0] O_0__1,
output [7:0] O_1__0,
output [7:0] O_1__1,
output [7:0] O_2__0,
output [7:0] O_2__1,
outp... | 7.274395 |
module NativeMapParallel_n2 (
input [7:0] I_0,
input [7:0] I_1,
output [7:0] out_0,
output [7:0] out_1
);
wire [7:0] dehydrate_tArray_8_Bit__inst0_out;
wire [7:0] dehydrate_tArray_8_Bit__inst1_out;
\aetherlinglib_dehydrate__hydratedTypeBit8 dehydrate_tArray_8_Bit__inst0 (
.in (I_0),
... | 7.274395 |
module NativeMapParallel_n1_unq3 (
input [7:0] I_0__0,
input [7:0] I_0__1,
output [7:0] O_0,
output valid_down,
input valid_up
);
wire [7:0] RShift_Atom_inst0_O;
wire RShift_Atom_inst0_valid_down;
RShift_Atom RShift_Atom_inst0 (
.I__0(I_0__0),
.I__1(I_0__1),
.O(RShift_Atom_in... | 7.274395 |
module NativeMapParallel_n1_unq4 (
input [7:0] I_0_0__0,
input [7:0] I_0_0__1,
output [7:0] O_0_0,
output valid_down,
input valid_up
);
wire [7:0] NativeMapParallel_n1_inst0_O_0;
wire NativeMapParallel_n1_inst0_valid_down;
NativeMapParallel_n1_unq3 NativeMapParallel_n1_inst0 (
.I_0__0(I_... | 7.274395 |
module NativeMapParallel_n1_unq1 (
input [7:0] I0_0,
input [7:0] I1_0,
output [7:0] O_0__0,
output [7:0] O_0__1,
output valid_down,
input valid_up
);
wire [7:0] atomTupleCreator_t0Int_t1Int_inst0_O__0;
wire [7:0] atomTupleCreator_t0Int_t1Int_inst0_O__1;
wire atomTupleCreator_t0Int_t1Int_in... | 7.274395 |
module NativeMapParallel_n1_unq2 (
input [7:0] I0_0_0,
input [7:0] I1_0_0,
output [7:0] O_0_0__0,
output [7:0] O_0_0__1,
output valid_down,
input valid_up
);
wire [7:0] NativeMapParallel_n1_inst0_O_0__0;
wire [7:0] NativeMapParallel_n1_inst0_O_0__1;
wire NativeMapParallel_n1_inst0_valid_do... | 7.274395 |
module Mux_Array_8_Bit_t_2n (
input [7:0] data_0,
input [7:0] data_1,
output [7:0] out,
input [0:0] sel
);
wire [7:0] CommonlibMuxN_n2_w8_inst0_out;
wire [7:0] NativeMapParallel_n2_inst0_out_0;
wire [7:0] NativeMapParallel_n2_inst0_out_1;
wire [7:0] hydrate_tArray_8_Bit__inst0_out;
\commonl... | 7.171087 |
module Mux_Array_8_Bit_t_1n (
input [7:0] data_0,
output [7:0] out,
input [0:0] sel
);
Term_Bits_1_t Term_Bits_1_t_inst0 (.I(sel));
assign out = data_0;
endmodule
| 7.171087 |
module Mux2xOutBits3 (
input [2:0] I0,
input [2:0] I1,
output [2:0] O,
input S
);
wire [2:0] coreir_commonlib_mux2x3_inst0_out;
\commonlib_muxn__N2__width3 coreir_commonlib_mux2x3_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x3_inst0_out)
);... | 7.210649 |
module Mux2xOutBits2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
input S
);
wire [1:0] coreir_commonlib_mux2x2_inst0_out;
\commonlib_muxn__N2__width2 coreir_commonlib_mux2x2_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x2_inst0_out)
);... | 7.816223 |
module Mux2xOutBits1 (
input [0:0] I0,
input [0:0] I1,
output [0:0] O,
input S
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
\commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x1_inst0_out)
);... | 7.639545 |
module Map_T_n2_i0 (
input clk,
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I0_2,
input [7:0] I0_3,
input [7:0] I0_4,
input [7:0] I0_5,
input [7:0] I0_6,
input [7:0] I0_7,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
input [7:0] I1_3,
input [7:0] I1_4... | 6.978824 |
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