code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Lt_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [0:0] O,
output valid_down,
input valid_up
);
wire coreir_ult8_inst0_out;
coreir_ult #(
.width(8)
) coreir_ult8_inst0 (
.in0(I__0),
.in1(I__1),
.out(coreir_ult8_inst0_out)
);
assign O = coreir_ult8_inst0_ou... | 7.118379 |
module LUT3_16 (
input I0,
input I1,
input I2,
output O
);
wire coreir_lut3_inst0_out;
lutN #(
.init(8'h10),
.N(3)
) coreir_lut3_inst0 (
.in ({I2, I1, I0}),
.out(coreir_lut3_inst0_out)
);
assign O = coreir_lut3_inst0_out;
endmodule
| 7.554919 |
module LUT2_8 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
lutN #(
.init(4'h8),
.N(2)
) coreir_lut2_inst0 (
.in ({I1, I0}),
.out(coreir_lut2_inst0_out)
);
assign O = coreir_lut2_inst0_out;
endmodule
| 7.722694 |
module LUT1_2 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h2),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 8.126826 |
module LUT1_1 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h1),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 7.409016 |
module LUT1_0 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h0),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 7.399772 |
module LShift_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] shl8_inst0_out;
coreir_shl #(
.width(8)
) shl8_inst0 (
.in0(I__0),
.in1(I__1),
.out(shl8_inst0_out)
);
assign O = shl8_inst0_out;
assign valid_... | 8.458485 |
module NativeMapParallel_n3_unq2 (
input [7:0] I_0__0,
input [7:0] I_0__1,
input [7:0] I_1__0,
input [7:0] I_1__1,
input [7:0] I_2__0,
input [7:0] I_2__1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
wire [7:0] LShift_Atom_inst0... | 7.274395 |
module NativeMapParallel_n3_unq3 (
input [7:0] I_0_0__0,
input [7:0] I_0_0__1,
input [7:0] I_0_1__0,
input [7:0] I_0_1__1,
input [7:0] I_0_2__0,
input [7:0] I_0_2__1,
input [7:0] I_1_0__0,
input [7:0] I_1_0__1,
input [7:0] I_1_1__0,
input [7:0] I_1_1__1,
input [7:0] I_1_2__0,... | 7.274395 |
module If_Atom_Intt (
input [0:0] I__0,
input [7:0] I__1__0,
input [7:0] I__1__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] Mux_Array_8_Bit_t_2n_inst0_out;
Mux_Array_8_Bit_t_2n Mux_Array_8_Bit_t_2n_inst0 (
.data_0(I__1__1),
.data_1(I__1__0),
.out(Mux_A... | 7.310169 |
module Register8 (
input clk,
input [7:0] I,
output [7:0] O
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst2_O;
wire DFF_init0_has_ce... | 6.73316 |
module Register_Array_8_Bit_t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I,
output [7:0] O
);
wire [7:0] Register8_inst0_O;
Register8 Register8_inst0 (
.clk(clk),
.I (I),
.O (Register8_inst0_O)
);
assign O = Register8_inst0_O;
endmodule
| 7.102239 |
module Register_Tuple_0_Array_8_Bit__1_Array_8_Bit__t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O__0,
output [7:0] O__1
);
wire [7:0] Register_Array_8_Bit_t_0init_FalseCE_FalseRESET_inst0_O;
wire [7:0] Register_Array_8_Bit_t_0init_FalseCE_FalseRESET_i... | 6.647526 |
module Register_Array_8_Array_8_Bit__t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
input [7:0] I_3,
input [7:0] I_4,
input [7:0] I_5,
input [7:0] I_6,
input [7:0] I_7,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
o... | 7.102239 |
module Register_Array_1_Array_8_Bit__t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I_0,
output [7:0] O_0
);
wire [7:0] Register_Array_8_Bit_t_0init_FalseCE_FalseRESET_inst0_O;
Register_Array_8_Bit_t_0init_FalseCE_FalseRESET Register_Array_8_Bit_t_0init_FalseCE_FalseRESET_inst0(
.clk(clk),
... | 7.102239 |
module Register_Array_1_Array_1_Array_8_Bit___t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I_0_0,
output [7:0] O_0_0
);
wire [7:0] Register_Array_1_Array_8_Bit__t_0init_FalseCE_FalseRESET_inst0_O_0;
Register_Array_1_Array_8_Bit__t_0init_FalseCE_FalseRESET Register_Array_1_Array_8_Bit__t_0init_Fal... | 7.102239 |
module Register_Bitt_0init_FalseCE_FalseRESET (
input clk,
input I,
output O
);
wire [0:0] Register1_inst0_O;
Register1 Register1_inst0 (
.clk(clk),
.I (I),
.O (Register1_inst0_O)
);
assign O = Register1_inst0_O[0];
endmodule
| 7.503354 |
module Counter3_Mod5CE (
input CE,
input clk,
output [2:0] O
);
wire [2:0] Counter3CER_inst0_O;
wire LUT3_16_inst0_O;
wire and_inst0_out;
Counter3CER Counter3CER_inst0 (
.CE(CE),
.clk(clk),
.O(Counter3CER_inst0_O),
.RESET(and_inst0_out)
);
LUT3_16 LUT3_16_inst0 (
.I... | 6.549827 |
module Counter2_Mod4CE (
input CE,
input clk,
output [1:0] O
);
wire [1:0] Counter2CER_inst0_O;
wire LUT2_8_inst0_O;
wire and_inst0_out;
Counter2CER Counter2CER_inst0 (
.CE(CE),
.clk(clk),
.O(Counter2CER_inst0_O),
.RESET(and_inst0_out)
);
LUT2_8 LUT2_8_inst0 (
.I0(C... | 6.745207 |
module Add_Atom_unq1 (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] coreir_add8_inst0_out;
coreir_add #(
.width(8)
) coreir_add8_inst0 (
.in0(I__0),
.in1(I__1),
.out(coreir_add8_inst0_out)
);
assign O = coreir_a... | 6.880887 |
module Add_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O
);
wire [7:0] coreir_add8_inst0_out;
coreir_add #(
.width(8)
) coreir_add8_inst0 (
.in0(I__0),
.in1(I__1),
.out(coreir_add8_inst0_out)
);
assign O = coreir_add8_inst0_out;
endmodule
| 6.918465 |
module renamedForReduce (
input [7:0] in0,
input [7:0] in1,
output [7:0] out
);
wire [7:0] Add_Atom_inst0_O;
Add_Atom Add_Atom_inst0 (
.I__0(in0),
.I__1(in1),
.O(Add_Atom_inst0_O)
);
assign out = Add_Atom_inst0_O;
endmodule
| 7.384035 |
module ReduceParallel_n3 (
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
output [7:0] O
);
wire [7:0] renamedForReduce_inst0_out;
wire [7:0] renamedForReduce_inst1_out;
renamedForReduce renamedForReduce_inst0 (
.in0(I_2),
.in1(renamedForReduce_inst1_out),
.out(renamedForR... | 7.174445 |
module Reduce_S_n3 (
input clk,
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
output [7:0] O_0,
output valid_down,
input valid_up
);
wire [7:0] ReduceParallel_n3_inst0_O;
wire [7:0] Register_Array_1_Array_8_Bit__t_0init_FalseCE_FalseRESET_inst0_O_0;
wire [0:0] reg_P_inst0_out;
R... | 7.025687 |
module NativeMapParallel_n3_unq4 (
input clk,
input [7:0] I_0_0,
input [7:0] I_0_1,
input [7:0] I_0_2,
input [7:0] I_1_0,
input [7:0] I_1_1,
input [7:0] I_1_2,
input [7:0] I_2_0,
input [7:0] I_2_1,
input [7:0] I_2_2,
output [7:0] O_0_0,
output [7:0] O_1_0,
output [7:0... | 7.274395 |
module NativeMapParallel_n1 (
input [7:0] I_0__0,
input [7:0] I_0__1,
output [7:0] O_0
);
wire [7:0] Add_Atom_inst0_O;
Add_Atom Add_Atom_inst0 (
.I__0(I_0__0),
.I__1(I_0__1),
.O(Add_Atom_inst0_O)
);
assign O_0 = Add_Atom_inst0_O;
endmodule
| 7.274395 |
module renamedForReduce_unq1 (
input [7:0] in0_0,
input [7:0] in1_0,
output [7:0] out_0
);
wire [7:0] NativeMapParallel_n1_inst0_O_0;
NativeMapParallel_n1 NativeMapParallel_n1_inst0 (
.I_0__0(in0_0),
.I_0__1(in1_0),
.O_0(NativeMapParallel_n1_inst0_O_0)
);
assign out_0 = NativeMap... | 7.384035 |
module ReduceParallel_n3_unq1 (
input [7:0] I_0_0,
input [7:0] I_1_0,
input [7:0] I_2_0,
output [7:0] O_0
);
wire [7:0] renamedForReduce_inst0_out_0;
wire [7:0] renamedForReduce_inst1_out_0;
renamedForReduce_unq1 renamedForReduce_inst0 (
.in0_0(I_2_0),
.in1_0(renamedForReduce_inst1_... | 7.174445 |
module Reduce_S_n3_unq1 (
input clk,
input [7:0] I_0_0,
input [7:0] I_1_0,
input [7:0] I_2_0,
output [7:0] O_0_0,
output valid_down,
input valid_up
);
wire [7:0] ReduceParallel_n3_inst0_O_0;
wire [7:0] Register_Array_1_Array_1_Array_8_Bit___t_0init_FalseCE_FalseRESET_inst0_O_0_0;
wire ... | 7.107378 |
module Add8_cin (
input CIN,
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire bit_const_0_None_out;
wire [7:0] coreir_add8_inst0_out;
wire [7:0] coreir_add8_inst1_out;
corebit_const #(.value(0)) bit_const_0_None (.out(bit_const_0_None_out));
coreir_add #(
.width(8)
) coreir_add8_... | 8.416699 |
module Sub_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] Sub8_inst0_O;
Sub8 Sub8_inst0 (
.I0(I__0),
.I1(I__1),
.O (Sub8_inst0_O)
);
assign O = Sub8_inst0_O;
assign valid_down = valid_up;
endmodule
| 6.934876 |
module NativeMapParallel_n8_unq7 (
input clk,
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I0_2,
input [7:0] I0_3,
input [7:0] I0_4,
input [7:0] I0_5,
input [7:0] I0_6,
input [7:0] I0_7,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
input [7:0] I1_3,
in... | 7.274395 |
module Map_T_n2_i0_unq9 (
input clk,
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I0_2,
input [7:0] I0_3,
input [7:0] I0_4,
input [7:0] I0_5,
input [7:0] I0_6,
input [7:0] I0_7,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
input [7:0] I1_3,
input [7:0]... | 6.888355 |
module Sharpen (
input clk,
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
input [7:0] I_3,
input [7:0] I_4,
input [7:0] I_5,
input [7:0] I_6,
input [7:0] I_7,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output [7:0] O_3,
output [7:0] O_4,
output... | 7.189878 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
... | 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
paramete... | 7.576841 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0... | 6.767428 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1... | 7.073756 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3,... | 7.759103 |
module sha_unit (
// Control
clk,
// Externally managed state
round,
Kt,
// SHA256 parameters
M,
H0,
// Result
H1
);
`define idx32(x) (32*(x+1)-1):(32*(x))
input wire clk;
input wire [5:0] round;
input wire [31:0] Kt;
input wire [511:0] M;
input wire [255:0] H0;
... | 7.22988 |
module AsyncResetRegVec_w1_i0 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30044.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30045.4]
input reset, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30046.4]
input io_d, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30047.4]
... | 6.68936 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30158.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30159.4]
input reset, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30160.4]
input io_d, // @[:shc.marmotcaravel.MarmotCaravelConfig.... | 6.605499 |
module AsyncValidSync ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30406.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30407.4]
input reset, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30408.4]
output io_out // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30409.4]
);
wire ... | 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30452.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30453.4]
input reset, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30454.4]
input io_d, // @[:shc.marmotcaravel.MarmotCaravelConfig.... | 6.605499 |
module AsyncValidSync_1 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30468.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30469.4]
input reset, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30470.4]
input io_in, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30471.4]
outp... | 6.70336 |
module AsyncValidSync_2 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30604.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30605.4]
input reset, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30606.4]
input io_in, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30607.4]
outp... | 6.70336 |
module SynchronizerShiftReg_w48_d1 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30866.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30867.4]
input [47:0] io_d, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@30869.4]
output [47:0] io_q // @[:shc.marmotcaravel.MarmotCar... | 6.820992 |
module IntSyncCrossingSource ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@114695.2]
input auto_in_0, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@114698.4]
output auto_out_sync_0 // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@114698.4]
);
assign auto_out_sync_0 = auto_in_0; // @[LazyModule.scala 1... | 6.689384 |
module SynchronizerShiftReg_w43_d1 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@116983.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@116984.4]
input [42:0] io_d, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@116986.4]
output [42:0] io_q // @[:shc.marmotcaravel.Marmot... | 6.820992 |
module SynchronizerShiftReg_w55_d1 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@196844.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@196845.4]
input [54:0] io_d, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@196847.4]
output [54:0] io_q // @[:shc.marmotcaravel.Marmot... | 6.820992 |
module SynchronizerShiftReg_w12_d1 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@198339.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@198340.4]
input [11:0] io_d, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@198342.4]
output [11:0] io_q // @[:shc.marmotcaravel.Marmot... | 6.820992 |
module SynchronizerShiftReg_w1_d3 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@218305.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@218306.4]
input io_d, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@218308.4]
output io_q // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@2183... | 6.820992 |
module IntSyncCrossingSink ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@218321.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@218322.4]
input auto_in_sync_0, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@218324.4]
output auto_out_0 // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@... | 6.689384 |
module IntSyncCrossingSink_1 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@218349.2]
input auto_in_sync_0, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@218352.4]
input auto_in_sync_1, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@218352.4]
output auto_out_0, // @[:shc.marmotcaravel.MarmotCarave... | 6.689384 |
module IntSyncCrossingSink_2 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@218365.2]
input auto_in_sync_0, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@218368.4]
output auto_out_0 // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@218368.4]
);
assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 1... | 6.689384 |
module AsyncResetRegVec_w2_i0 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@227712.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@227713.4]
input reset, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@227714.4]
input [1:0] io_d, // @[:shc.marmotcaravel.MarmotCaravelC... | 6.68936 |
module IntSyncCrossingSource_2 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@227745.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@227746.4]
input reset, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@227747.4]
input auto_in_0, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@227748... | 6.689384 |
module IntSyncCrossingSource_3 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@227802.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@227803.4]
input reset, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@227804.4]
input auto_in_0, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@227805... | 6.689384 |
module IsoZero ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@239259.2]
input io_in, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@239262.4]
input io_iso, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@239262.4]
output io_out // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@239262.4]
);
wire ... | 6.599484 |
module SynchronizerShiftReg_w80_d1 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@241265.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@241266.4]
input [79:0] io_d, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@241268.4]
output [79:0] io_q // @[:shc.marmotcaravel.Marmot... | 6.820992 |
module IntSyncCrossingSource_4 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@242608.2]
input auto_in_0, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@242611.4]
input auto_in_1, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@242611.4]
output auto_out_sync_0, // @[:shc.marmotcaravel.MarmotCaravelCo... | 6.689384 |
module SynchronizerShiftReg_w2_d3 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@243046.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@243047.4]
input [1:0] io_d, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@243049.4]
output [1:0] io_q // @[:shc.marmotcaravel.MarmotCara... | 6.820992 |
module IntSyncCrossingSink_4 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@243062.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@243063.4]
input auto_in_sync_0, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@243065.4]
input auto_in_sync_1, // @[:shc.marmotcaravel.MarmotCaravelConfi... | 6.689384 |
module SynchronizerShiftReg_w32_d3 ( // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@285048.2]
input clock, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@285049.4]
input [31:0] io_d, // @[:shc.marmotcaravel.MarmotCaravelConfig.fir@285051.4]
output [31:0] io_q // @[:shc.marmotcaravel.Marmot... | 6.820992 |
module shdw2mb(
// DO NOT EDIT BELOW THIS LINE ////////////////////
// Bus protocol ports, do not add or delete.
input FSL_Clk,
input FSL_Rst,
input FSL_S_Clk,
output reg FSL_S_Read,
input [31 : 0] FSL_S_Data,
input FSL_S_Control,
input FSL_S_Exists,
i... | 6.907026 |
module MusicScore(ReadOrWrite, Address, KeyInput, KeyOutput, TimeInput, TimeOutput,Clock, Reset);
//Start reading when Start=1. Read from StartAddress until the end when Keyoutput=0;
module MusicSheetReader(Start, EndofScore, StartAddress, KeyOutput, CurrentAddress, EndofNote, Clock, Reset);
input Clock, Reset, Start;
... | 6.803942 |
module
Modification History:
Date By Version Description
----------------------------------------------------------
180505 ctlvie 0.5 Module interface definition
180508 ctlvie 1.0 Initial coding complete (unverified)
180509 ctlvie 1.1 Corrected the reg conflict error(unverified)
180510 ctlvie 1.5 ... | 6.772892 |
module shft_mod (
input clk,
input rstn,
input load,
dir,
input [7:0] LD,
output cout
);
reg [7:0] shft_reg;
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
shft_reg <= 8'h00;
end else begin
if (load) shft_reg <= LD[7:0];
else if (dir) shft_reg[7:0] <... | 6.572761 |
module uni_shift_8b (
op,
clk,
rst_a,
load,
sh_ro_lt_rt,
ip
);
output reg [7:0] op;
input load;
input [1:0] sh_ro_lt_rt;
input [7:0] ip;
input clk, rst_a;
reg [7:0] temp;
always @(posedge clk or posedge rst_a) begin
if (rst_a) op = 0;
else
case (load)
1'b... | 7.288998 |
module shift_unit (
input [31:0] tbsh,
s,
output [31:0] sh
);
assign sh = tbsh << s;
endmodule
| 6.585245 |
module shift16b (
input [15:0] in,
input [ 4:0] amt,
// Control
input mode,
input dir,
output reg [15:0] out
);
always @(in, amt, mode, dir) begin
// Logic
if (dir == 1) begin
// Shift right
if (mode == 1) begin
// Arithmetic
out = $signed(in) >>> amt;
... | 8.872804 |
module shift16btest;
// Inputs
reg [15:0] in;
reg [4:0] amt;
reg mode;
reg dir;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
shift16b uut (
.in (in),
.amt (amt),
.mode(mode),
.dir (dir),
.out (out)
);
initial begin
// Initialize Inputs... | 7.228796 |
module top_module (
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q
);
always @(posedge clk) begin
if (load) begin
q <= data;
end else if (ena) begin
case (amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q[53:0... | 7.203305 |
module shift2 #(
parameter length = 32
) (
input [length-1:0] in,
output [length+1:0] out
);
assign out = in << 2;
endmodule
| 7.885508 |
module implements a shifter to multiply the input by 1 to 2^31.
//
// 158 LUTs and 78 registers are used. The maximum clock frequency is 454 MHz.
//
module shift24i55o(
input [23:0] d, // data input
output [54:0] q, // data output
input [4:0] n, // number of bits to shift left
input clk // master clock
);
// in... | 6.904081 |
module shift2bits #(
parameter DATA_WIDTH = 32
) (
input [DATA_WIDTH-1:0] i_op,
output [DATA_WIDTH-1:0] o_ans
);
assign o_ans = i_op << 2;
endmodule
| 8.3818 |
module shift2Reg (
input clk,
input rst,
input load,
input shift,
input [511:0] inData,
output [511:0] outData
);
reg [533:0] shiftReg;
reg [8:0] k = 0;
reg state = 0;
assign outData = shiftReg[511:0];
always @(posedge clk) begin
if (load & shift) begin
shiftReg[533:20] <= ... | 8.395232 |
module top_module (
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) begin
q <= 4'd0;
end else if (load) begin
q <= data;
end else if (e... | 7.203305 |
module shift4_tb ();
reg clk = 0;
wire [3:0] data;
shift4 #(
.NP (1),
.INI(4'b0001)
) C1 (
.clk (clk),
.data(data)
);
always #1 clk = ~clk;
initial begin
$dumpfile("shift4_tb.vcd");
$dumpvars(0, shift4_tb);
#30 $display("Start Simulator");
$finish;
end
endm... | 6.88484 |
module ArithmeticShiftTest;
reg signed [31:0] in;
reg [ 5:0] shift;
reg signed [31:0] out;
//calculate arithmetic barrel shift right
always @(*) out = in >>> shift;
initial begin
//set up inputs for always block
in = 32'sh80000000;//set to highest value negative number(-2147483648)
shif... | 7.778867 |
module shift8bitena_tb ();
reg [31:0] data_input;
reg ctrl_shiftdirection, ena;
wire [31:0] data_output;
shift8bitena sh8 (
data_input,
ctrl_shiftdirection,
ena,
data_output
);
initial begin
$monitor("%b %b %b", data_input, ena, data_output);
data_input = 32'b00001101011000... | 6.923798 |
module shift8reg (
input [7:0] in,
input en,
input rst1,
input rst2,
input rst3,
input clk,
input shiftL8,
output reg [63:0] out
);
always @(posedge clk, posedge rst1, posedge rst2) begin
if (en) out[7:0] = in;
if (shiftL8) out = out << 8;
if (rst1 || rst2 || rst3) out = 0... | 7.621783 |
module shiftA (
q,
clock,
d
);
output [1:0] q;
input clock, d;
reg [1:0] q;
always @(posedge clock) begin
q[0] = d;
q[1] = q[0];
end
endmodule
| 6.978587 |
module ShiftAdd3 (
data,
d_in,
d_out
);
parameter digits = 4;
input wire data;
input wire [4*digits - 1:0] d_in;
output wire [4*digits - 1:0] d_out;
wire [3:0] d[0:digits-1];
wire [digits-1:0] msb;
assign msb[0] = data;
genvar i;
generate
for (i = 1; i < digits; i = i + 1) begin : M... | 7.330426 |
module shiftAdder (
out,
pcLine,
immediate
);
input [31:0] pcLine, immediate;
output reg [31:0] out;
always @(pcLine, immediate) begin
out <= pcLine + (immediate * 4);
end
endmodule
| 7.483696 |
module shiftaddmpy (
i_clk,
i_ce,
i_a,
i_b,
o_r
);
parameter AWIDTH = 16, BWIDTH = 20;
input wire i_clk, i_ce;
input wire [(AWIDTH-1):0] i_a;
input wire [(BWIDTH-1):0] i_b;
output reg [(AWIDTH+BWIDTH-1):0] o_r;
reg [(AWIDTH-1):0] u_a;
reg [(BWIDTH-1):0] u_b;
reg sgn;
reg [(AWID... | 6.948303 |
module shiftaddmul (
mpr,
mpd,
prd
);
input [23:0] mpr, mpd;
output [47:0] prd;
integer i;
reg [47:0] product;
assign prd = product;
always @(mpr or mpd) begin
product = 0;
for (i = 0; i < 24; i = i + 1) if (mpr[i] == 1'b1) product = product + (mpd << i);
end
endmodule
| 7.459636 |
module ShiftAmount_Extend (
data_i,
data_o
);
//I/O ports
input [5-1:0] data_i;
output [32-1:0] data_o;
//Internal Signals
reg [32-1:0] data_o;
//Sign extended (actually, fill zero)
always @(*) begin
data_o <= {27'd0, data_i};
end
endmodule
| 7.613767 |
module shiftAndMask (
op,
oz,
a,
b,
mb,
me,
o,
mo
);
parameter WID = 64;
localparam DMSB = WID - 1;
input [1:0] op; // 0 = shl, 1 = rol, 2 = shr, 3 = asr
input oz; // zero the output
input [DMSB:0] a;
input [5:0] b;
input [5:0] mb;
input [5:0] me;
output [DMSB:0] o; ... | 6.70751 |
module shiftArithmetic (
data,
direction,
distance,
result
);
input [31:0] data;
input direction;
input [4:0] distance;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
lpm_clshift LPM_CLSHIFT_component (
.data(data),
.direction(direction),
... | 6.862737 |
module shiftArithmetic (
data,
direction,
distance,
result
);
input [31:0] data;
input direction;
input [4:0] distance;
output [31:0] result;
endmodule
| 6.862737 |
module shiftB (
q,
clock,
d
);
output [1:0] q;
input clock, d;
reg [1:0] q;
always @(posedge clock) begin
q[0] <= d;
q[1] <= q[0];
end
endmodule
| 7.373073 |
module shiftb1 (
input [28:1] in_l,
input [28:1] in_r,
output [28:1] out_l,
output [28:1] out_r
);
assign out_l = {in_l[27:1], in_l[28]};
assign out_r = {in_r[27:1], in_r[28]};
endmodule
| 6.503216 |
module shiftb2 (
input [28:1] in_l,
input [28:1] in_r,
output [28:1] out_l,
output [28:1] out_r
);
assign out_l = {in_l[26:1], in_l[28], in_l[27]};
assign out_r = {in_r[26:1], in_r[28], in_r[27]};
endmodule
| 7.12673 |
module mux16to1 (
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
d8,
d9,
d10,
d11,
d12,
d13,
d14,
d15,
s0,
s1,
s2,
s3,
f
);
input d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15;
input s0, s1, s2, s3;
output f;
mux8to1 mux... | 7.318793 |
module mux8to1 (
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
s0,
s1,
s2,
f
);
input d0, d1, d2, d3, d4, d5, d6, d7, s0, s1, s2;
output f;
mux4to1 mux0 (
d0,
d1,
d2,
d3,
s0,
s1,
w1
);
mux4to1 mux1 (
d4,
d5,
d6,
... | 7.465042 |
module mux4to1 (
d0,
d1,
d2,
d3,
s0,
s1,
f
);
input d0, d1, d2, d3, s0, s1;
output f;
mux2to1 mux0 (
d0,
d1,
s0,
w1
);
mux2to1 mux1 (
d2,
d3,
s0,
w2
);
mux2to1 mux2 (
w1,
w2,
s1,
f
);
endmodule
| 7.010477 |
module mux2to1 (
d0,
d1,
s0,
f
);
input d0, d1, s0;
output f;
and (w17, d1, s0);
not (w15, s0);
and (w18, w15, d0);
or (f, w17, w18);
endmodule
| 7.107199 |
module shiftbyte (
input [7:0] din,
output reg [7:0] dshift,
input [2:0] sh
);
always @*
case (sh)
0: dshift <= {din[6:0], 1'b0};
1: dshift <= {din[6:0], din[7]};
2: dshift <= {1'b0, din[7:1]};
3: dshift <= {din[0], din[7:1]};
4: dshift <= din;
5: dshift <= {din[6:... | 6.761237 |
module shiftCal (
input clk,
rst,
we,
input [71:0] kernel,
input [7:0] data_in,
output [7:0] data_out
);
reg [8055:0] shift_reg;
always @(posedge clk or posedge rst) begin
if (rst) shift_reg <= 0;
else if (we) shift_reg <= {shift_reg[8048:0], data_in};
end
wire [7:0] mul1;
wire... | 7.496747 |
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