code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q
);
always @(posedge clk) begin
if (shift_ena) q <= {q[2:0], data};
else if (count_ena) q <= q - 1'b1;
else q <= q;
end
endmodule
| 7.203305 |
module shiftCounter (
cOut,
Mcps,
LRbar,
numBits
);
input cOut;
input [23:0] Mcps;
output reg LRbar;
output reg [4:0] numBits;
reg [4:0] numBitsTemp;
always @(*) begin
if (cOut) begin
LRbar = 1'b0;
numBits = 1'b1;
end else begin
LRbar = 1'b1;
if (Mcps[... | 6.631317 |
module shifter12_128 (
clock,
shiftin,
shiftout,
taps
);
input clock;
input [11:0] shiftin;
output [11:0] shiftout;
output [11:0] taps;
wire [11:0] sub_wire0;
wire [11:0] sub_wire1;
wire [11:0] shiftout = sub_wire0[11:0];
wire [11:0] taps = sub_wire1[11:0];
altshift_taps ALTSHIFT_TA... | 6.737208 |
module shifter12_128 (
clock,
shiftin,
shiftout,
taps
);
input clock;
input [11:0] shiftin;
output [11:0] shiftout;
output [11:0] taps;
endmodule
| 6.737208 |
module SHIFTER16 (
input [1:0] Select,
input [BITS-1:0] B,
input InL,
input InR,
output [15:0] HOut
);
parameter BITS = 16;
reg [BITS-1:0] HOut_;
assign HOut = HOut_;
initial begin
HOut_ = 0;
end
always @(*) begin
case (Select)
0: HOut_ = B;
1: HOut_ = (InL << (B... | 8.10279 |
module shifter16_2048 (
clock,
shiftin,
shiftout,
taps
);
input clock;
input [15:0] shiftin;
output [15:0] shiftout;
output [127:0] taps;
wire [ 15:0] sub_wire0;
wire [127:0] sub_wire1;
wire [ 15:0] shiftout = sub_wire0[15:0];
wire [127:0] taps = sub_wire1[127:0];
altshift_taps ALTS... | 6.528337 |
module shifter16_2048 (
clock,
shiftin,
shiftout,
taps
);
input clock;
input [15:0] shiftin;
output [15:0] shiftout;
output [127:0] taps;
endmodule
| 6.528337 |
module shifter16_256 (
clock,
shiftin,
shiftout,
taps
);
input clock;
input [15:0] shiftin;
output [15:0] shiftout;
output [15:0] taps;
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire [15:0] shiftout = sub_wire0[15:0];
wire [15:0] taps = sub_wire1[15:0];
altshift_taps ALTSHIFT_TA... | 6.730898 |
module shifter16_256 (
clock,
shiftin,
shiftout,
taps
);
input clock;
input [15:0] shiftin;
output [15:0] shiftout;
output [15:0] taps;
endmodule
| 6.730898 |
module Shifter16_AR (
out,
shift,
in
);
input [3:0] shift; // shift할 bit 개수 체크 (4bit: 1~16bit Arthmetic Shift)
input [15:0] in; // 16bit 입력값
output [15:0] out; // 16bit Arthmetic Shift 출력
wire [15:0] ta; // 1bit Arthmetic Shift 결과
wire [15:0] tb; // 2bit Arthmetic Shift 결과
wire [15:0] tc; ... | 7.927283 |
module Shifter16_LR (
out,
shift,
lr,
in
);
input [3:0] shift; // shift할 bit 개수 체크 (4bit: 1~16bit shift)
input lr; // left 또는 right shift 방향 결정 (1: left, 0: right)
input [15:0] in; // 16bit 입력값
output [15:0] out; // 16bit shift된 출력
wire [15:0] ta; // 1bit shift 결과
wire [15:0] tb; // 2... | 6.818307 |
module: SHIFTER16
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module SHIFTER16_tb;
// Inputs
reg [1:0] Select;
reg [15:0] B;
reg InL;
reg InR;
// Outputs
wire [15:0] HOut;
int... | 6.719636 |
module shifter2 (
input [26:0] J_addr,
input [31:0] pc_addr,
output [31:0] pc_addr_J
);
parameter zero = 2'b00;
assign pc_addr_J = {pc_addr[31:29], J_addr[26:0], zero};
endmodule
| 6.953712 |
module shifter32 (
in,
op,
s,
out
);
input [31:0] in;
input [4:0] s;
input [1:0] op;
//SHL 00 Logic left shift
//SHR 01 Logic Right shift
//ASR 10 Arithmic Right shift
//ROR 11 Rotational Right shift
output [31:0] out;
wire [31:0] tmp1, tmp2, tmp3, tmp4, op1, in1, revin, out1, revou... | 6.692541 |
module mux22 (
in,
c,
out
);
input [1:0] in;
input c;
output out;
assign out = (c & in[0]) | (~c & in[1]);
endmodule
| 7.731017 |
module reverse (
in,
out
);
input [31:0] in;
output [31:0] out;
assign out = {
in[0],
in[1],
in[2],
in[3],
in[4],
in[5],
in[6],
in[7],
in[8],
in[9],
in[10],
in[11],
in[12],
in[13],
in[14],
in[15],
in[16],
in[17],
in[18],
in[1... | 6.661478 |
module extend_to_16 (
in,
out
);
input in;
output [15:0] out;
assign out = {in, in, in, in, in, in, in, in, in, in, in, in, in, in, in, in};
endmodule
| 7.057806 |
module extend_to_4 (
in,
out
);
input in;
output [3:0] out;
assign out = {in, in, in, in};
endmodule
| 6.561325 |
module extend_to_32 (
in,
out
);
input in;
output [31:0] out;
assign out = {
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
in,
... | 7.313618 |
module shifter32_32_l2 (
sh_a,
sh_y
); // 入出力ポート
input [31:0] sh_a; // 入力 32-bit
output [31:0] sh_y; // 出力 32-bit
//Body
//2-bit 左シフト
assign sh_y = {sh_a[29:0], 2'b00};
endmodule
| 8.658257 |
module shifter32_8_l2 (
sh_a,
sh_y
); // 入出力ポート
input [31:0] sh_a; // 入力 32-bit
output [7:0] sh_y; // 出力 8-bit
//Body
//2-bit 左シフト
assign sh_y = {sh_a[5:0], 2'b00};
endmodule
| 8.386454 |
module SHIFTER32_L2 (
X,
Sh
);
input [31:0] X;
output [31:0] Sh;
parameter z = 2'b00;
assign Sh = {X[29:0], z};
endmodule
| 7.27685 |
module shifter4 (
In,
Cnt,
Op,
Out
);
input [15:0] In;
input [3:0] Cnt;
input [1:0] Op;
output [15:0] Out;
wire [15:0] op_res;
mux4_1 op_mux0 (
.S (Op),
.InA(In[12]),
.InB(1'b0),
.InC(In[4]),
.InD(In[4]),
.Out(op_res[0])
);
mux4_1 op_mux1 (
... | 7.36925 |
module shifter64 (
input [63:0] A,
B,
output [63:0] X,
input [6:0] shamt,
input insn30,
input insn29,
input insn26,
input insn14,
input insn3
);
`ifdef NO_WMODE
wire wmode = 0;
`else
wire wmode = insn3;
`endif
reg [63:0] bb;
reg [ 6:0] sh;
always @* begin
sh = shamt;
... | 7.200792 |
module shifter8 (
In,
Cnt,
Op,
Out
);
input [15:0] In;
input [3:0] Cnt;
input [1:0] Op;
output [15:0] Out;
/*
Your code goes here
*/
wire [15:0] op_res;
mux4_1 op_mux0 (
.S (Op),
.InA(In[8]),
.InB(1'b0),
.InC(In[8]),
.InD(In[8]),
.Out(op_res[0]... | 6.962233 |
module shiftere (
input [30:0] e,
input [5:0] exp_f,
output reg [30:0] x_f1
);
always @(exp_f or e) begin
case (exp_f)
6'b000101: x_f1 <= e >> 5;
6'b000100: x_f1 <= e >> 4;
6'b000011: x_f1 <= e >> 3;
6'b000010: x_f1 <= e >> 2;
6'b000001: x_f1 <= e >> 1;
6'b000000: ... | 6.854169 |
module shifter_tb ();
wire [31:0] in, out;
wire [1:0] shift;
wire overflow, carry;
//declare instances of dut and tester modules
barrelShifter dut (
out,
overflow,
carry,
in,
shift
); // dut (out,in,in)
shiftTester test0 (
out,
overflow,
carry,
in,
... | 6.659417 |
module ShifterL (
shift_statusL,
shiftipL,
shiftopL
);
input shift_statusL;
input [39:0] shiftipL;
output reg [39:0] shiftopL;
always @(shift_statusL or shiftipL) begin
if (shift_statusL == 1) shiftopL = $signed(shiftipL) >>> 1;
else shiftopL = 0;
end
endmodule
| 6.788101 |
module
module shifter(a, clk, leftShift, rightShift);
input [15:0] a;
output [15:0] leftShift;
output [15:0] rightShift;
always @(posedge clk)
leftShift = a << 1;
rightShift = a >> 1;
endmodule
| 8.024265 |
module shifterModule_24 (
input [15:0] x,
input [3:0] b,
input alufn,
output reg [15:0] shiftOutput
);
reg [15:0] w;
reg [15:0] y;
reg [15:0] z;
always @* begin
if (alufn == 1'h0 | (alufn == 1'h1 & x[0+0-:1] == 1'h0)) begin
case (b[3+0-:1])
1'h0: begin
w = x;
... | 6.620459 |
module ShifterR (
shift_statusR,
shiftipR,
shiftopR
);
input shift_statusR;
input [39:0] shiftipR;
output reg [39:0] shiftopR;
always @(shift_statusR or shiftipR) begin
if (shift_statusR == 1) shiftopR = $signed(shiftipR) >>> 1;
else shiftopR = 0;
end
endmodule
| 6.977436 |
module testBarrel ();
reg [15:0] in;
reg [ 3:0] sh;
wire [31:0] out;
barrel #(16) dut (
.in (in),
.sh (sh),
.out(out)
);
initial begin
$display("--------------------------------------------------");
$display("Barrel shifter tests starting...");
in = 16'hABCD;
sh = 4'h4... | 7.056073 |
module arith_shift (
clk,
P,
Q
);
// [n:0] for (n+1) bits. Replace n value to suit your code
input [n:0] P;
output reg [n:0] Q;
input clk;
// shift left
always @(posedge clk) begin
Q = P <<< m; // replace m with the number of
// place you want to shift each time
Q[m-1:0] = Q[m:1]... | 7.935292 |
module circular_shift (
clk,
P,
Q
);
// [n:0] for (n+1) bits. Replace n value to suit your code
input [n:0] P;
input clk;
output reg [n:0] Q;
// shift left, rotate right
always @(posedge clk) begin
Q <= P << m; // replace m with the number of
// place you want to shift each time
Q... | 6.652056 |
module circular_shift (
P,
Q
);
// [n:0] for (n+1) bits. Replace n value to suit your code
input [n:0] P;
output reg [n:0] Q;
// shift left, rotate right
assign Q[n:m] = P[n-m:0];
assign Q[m-1:0] = P[n:n-m+1];
// shift right, rotate left
assign Q[n-m:0] = P[n:m];
assign Q[n:n-m+1] = P[m-1:0]... | 6.652056 |
module shiftery_f (
input [19:0] y_f,
input [4:0] exp_ff,
output reg [22:0] ff
);
always @(exp_ff or y_f) begin
case (exp_ff)
5'b00011: ff <= y_f << 3;
5'b00010: ff <= y_f << 2;
5'b00001: ff <= y_f << 1;
5'b00000: ff <= y_f;
5'b11111: ff <= y_f >> 1;
5'b11110: ff <... | 7.04187 |
module shifter_100ge_gbx #(
parameter WORD_WIDTH = 66,
parameter MAX_SHL = 66,
parameter MIN_SHL = MAX_SHL - 14,
parameter TARGET_CHIP = 2,
parameter LD_MASK = 64'h0000000842108421,
parameter ADD_SKEW = 0
) (
input clk,
input [WORD_WIDTH+14-1:0] din_sh,
input [WORD_WIDTH+14-1:0] din_... | 7.758374 |
module shifter_128bit (
output result,
input [127:0] load_val,
input load_n,
input shift,
input reset,
input clock
);
reg [127:0] pixel;
assign result = pixel[127];
always @(posedge clock) begin
if (reset == 1'b1) pixel <= {128{1'b0}};
else if (load_n == 1'b1) pixel <= load_val;... | 7.330276 |
module shifter_16_10 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
input [0:0] sim_error,
output reg [15:0] out
);
always @* begin
case (alufn[0+1-:2])
default: begin
out = a;
end
2'h0: begin
if (sim_error == 1'h0) begin
out = a << b[0+3-:... | 6.54318 |
module shifter_16_11 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn[0+1-:2])
default: begin
out = a;
end
2'h0: begin
out = a << b[0+3-:4];
end
2'h2: begin
out = $signed(a) <<< b[0+3... | 6.819323 |
module shifter_16_13 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn[0+1-:2])
default: begin
out = a;
end
2'h0: begin
out = a << b[0+3-:4];
end
2'h2: begin
out = $signed(a) <<< b[0+3... | 6.839871 |
module shifter_16_18 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn[0+1-:2])
default: begin
out = a;
end
2'h0: begin
out = a << b[0+3-:4];
end
2'h2: begin
out = $signed(a) <<< b[0+3... | 6.846441 |
module shifter_18 (
input [15:0] a,
input [3:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn)
default: begin
out = a;
end
6'h20: begin
out = a << b;
end
6'h21: begin
out = a >> b;
end
6'h23: begin
... | 6.995787 |
module shifter_20 (
input [15:0] a,
input [3:0] b,
input [5:0] alufn_signal,
output reg [15:0] out
);
always @* begin
case (alufn_signal)
default: begin
out = a;
end
6'h20: begin
out = a << b;
end
6'h21: begin
out = a >> b;
end
... | 8.046615 |
module shifter_21 (
input [15:0] a,
input [3:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn)
default: begin
out = a;
end
6'h20: begin
out = a << b;
end
6'h21: begin
out = a >> b;
end
6'h23: begin
... | 7.460468 |
module Shifter_4 (
data,
control,
dataOut
);
// 2^4的位移量(左移16bit)
input [31:0] data;
input [4:0] control;
output [31:0] dataOut;
assign dataOut[0] = (control[4] == 1) ? 1'b0 : data[0];
assign dataOut[1] = (control[4] == 1) ? 1'b0 : data[1];
assign dataOut[2] = (control[4] == 1) ? 1'b0 : da... | 6.804337 |
module shifter_48b (
a,
in_put,
G,
R,
S,
out
);
input [47:0] in_put;
input [7:0] a;
output [47:0] out;
output G, R, S;
wire [ 48:0] I0;
wire [ 50:0] I1;
wire [ 54:0] I2;
wire [ 62:0] I3;
wire [ 78:0] I4;
wire [110:0] I5;
wire [174:0] I6;
wire [302:0] I7;
assign I0 = a[... | 6.864511 |
module shifter_49 (
input [7:0] a,
input [7:0] b,
input [1:0] alufn,
output reg [7:0] out
);
always @* begin
case (alufn)
2'h0: begin
out = a << b;
end
2'h1: begin
out = a >> b;
end
2'h3: begin
out = $signed(a) >>> b;
end
defaul... | 6.586799 |
module shifter_8bit (
clk,
reset,
c_in,
c_out,
sel
);
input clk;
input reset;
input [7:0] c_in;
output reg [7:0] c_out;
input [2:0] sel;
always @(posedge clk) begin
if (reset == 1'b1) c_out = 8'b10000000;
else begin
case (sel)
3'd1: c_out = {c_out[6:0], 1'b0};
... | 7.546837 |
module shifter_bit (
out,
in,
load_val,
shift,
load_n,
clock,
reset_n
);
input in, load_val, shift, load_n, clock, reset_n;
output out;
wire m0_to_m1, m1_to_flipflop;
mux2to1 m0 (
.x(out),
.y(in),
.s(shift),
.m(m0_to_m1)
);
mux2to1 m1 (
.x(load_val... | 8.703414 |
module flipflop (
q,
d,
clock,
reset_n
);
input d, clock, reset_n;
output q;
reg q;
always @(posedge clock) begin
if (reset_n == 1'b0) q <= 0;
else q <= d;
end
endmodule
| 6.626138 |
module shifter_control (
input [3:0] func, //funcion que está realizado a ALU
input [4:0] bus_b, //Cantidad de bits para shiftear en SRL
output reg shift_right, // '1' si el shift es hacia la derecha, '0' si es hacia la izquerda
output reg [4:0] sa //Shift Amount
);
always @(*) begin
case (fu... | 7.25026 |
module shifter_for_jump (
instructs,
pc,
shifted_address
);
output reg [31:0] shifted_address;
input [31:0] instructs, pc;
always @(instructs or pc) begin
shifted_address = {{pc[31:28]}, {instructs[25:0]}, {2'b00}};
end
endmodule
| 6.814652 |
module shifter_for_jump_test ();
wire [31:0] shifted_address;
reg [31:0] instructs, pc;
shifter_for_jump shfj (
instructs,
pc,
shifted_address
);
initial begin
#400 instructs = 32'b0000001111111100_0000111000111011;
pc = 32'b1000000000000000_0000000000000000;
#400 $stop;
end
... | 6.814652 |
module shifter_grid (
startGameEn,
shoot,
clock,
gridUpdateEn,
user_x,
grid
);
input startGameEn; // reset the grid from SW[2]
input shoot; // shoot input from SW[1]
input clock; // default 50mhz clock input
input gridUpdateEn;
input [7:0] user_x; // player's position on the x plan... | 7.072791 |
module mux2to1 (
x,
y,
s,
m
);
input x; // first value to choose from
input y; // second value to choose from
input s; // signal uses to determine which value to output
output m; // where to store selection
// s = 1'b0 => x
// s = 1'b1 => y
assign m = s & y | ~s & x;
endmodule
| 7.107199 |
module flipflop (
d,
q,
clock,
reset_n
);
// note: that this is a 1 bit register
input d; // input d we're going to store in our flip flop
input clock; // clock input
input reset_n; // reset signal, synchronous high reset
output reg q; // register value we're going to store values in
al... | 6.626138 |
module shifter_bit (
in,
load_val,
shift,
load_n,
ignore_load_n,
clk,
reset_n,
out
);
// Note that these should all be 1 bit inputs as we're really only handling/storing one bit of information in shifter bit
input in; // connected to out port of left shifter, 0 otherwise on left mos... | 8.703414 |
module around the barrel shifter to combine it with the clock and
reset.
*/
module shifter_hier(In, Cnt, Op, Out);
// declare constant for size of inputs, outputs (N) and # bits to shift (C)
parameter N = 16;
parameter C = 4;
parameter O = 2;
input [N-1:0] In;
input [C-1:0] Cnt;
input [O-... | 7.926948 |
module shifter_hier_bench;
// declare constant for size of inputs, outputs (N) and # bits to shift (C)
parameter N = 16;
parameter C = 4;
parameter O = 2;
reg [N-1:0] In;
reg [C-1:0] Cnt;
reg [O-1:0] Op;
wire [N-1:0] Out;
reg fail;
reg [ 31:0] Expected;
integer ... | 7.058456 |
module shifter_left #(
parameter N = 32,
SA = 5
) (
input [N-1:0] in,
input [ 4:0] shamt,
output [N-1:0] out
);
assign out = in << shamt;
endmodule
| 7.974361 |
module shifter_module (
CLOCK_32,
de,
cs,
load,
data,
rw,
addr,
r,
g,
b
);
input CLOCK_32;
input de, cs, load, rw;
inout [15:0] data;
input [4:0] addr;
wire [3:0] shifter_r;
wire [3:0] shifter_g;
wire [3:0] shifter_b;
output [3:0] r;
output [3:0] g;
output ... | 7.004633 |
module shifter_right_arithmetic #(
parameter N = 32,
SA = 5
) (
input [N-1:0] in,
input [ 4:0] shamt,
output [N-1:0] out
);
assign out = (in >>> shamt);
endmodule
| 8.190638 |
module shifter_right_logical #(
parameter N = 32,
SA = 5
) (
input [N-1:0] in,
input [ 4:0] shamt,
output [N-1:0] out
);
assign out = in >> shamt;
endmodule
| 8.190638 |
module shifter_rotater (
in_data,
shift_amt_reg,
shift_control,
shift_amt_imm,
enable,
carry_flag,
out_data,
carry_out_flag
);
input [31:0] in_data, shift_amt_reg;
input [2:0] shift_control;
input [4:0] shift_amt_imm;
input enable, carry_flag;
output [31:0] out_data;
output c... | 7.381781 |
module shifter_rotater_tb ();
wire [31:0] out_data;
wire carry_out_flag;
reg [31:0] in_data, shift_amt_reg;
reg [2:0] shift_control;
reg [4:0] shift_amt_imm;
reg enable, carry_flag;
shifter_rotater shifter_rotater1 (
in_data,
shift_amt_reg,
shift_control,
shift_amt_imm,
enab... | 7.381781 |
module shifter_row (
input clk,
input rst_n,
input enable,
input [15:0] data_in,
input [ 7:0] index,
output wire [15:0] data_out
);
reg [15:0] shifter[15:0];
always @(posedge clk or negedge rst_n or posedge enable) begin
if (!rst_n) begin
shifter[0] <= 16'h... | 7.818571 |
module shifter_tb ();
reg dir;
reg [31:0] dataIn;
wire [31:0] out;
shifter UUT (
.out(out),
.dataIn(dataIn),
.dir(dir)
);
initial begin
$monitor("DIR = %b | IN = %h | OUT = %h", dir, dataIn, out);
#10 dir = 1;
dataIn = 32'hABCD_FFFF;
#10 dir = 0;
#10;
$finish;... | 6.659417 |
module shifter_test (
input wire [2:0] btn,
input wire [7:0] sw,
output wire [7:0] led
);
// instantiate shifter
barrel_shifter_stage shift_unit (
.a (sw),
.amt(btn),
.y (led)
);
endmodule
| 7.00903 |
module shifter_test (
input wire [1:0] btn,
input wire [3:0] sw,
output wire [3:0] led
);
//instantiate shifter
barrel_shifter_stage shift_unit (
.a (sw),
.amt(btn),
.y (led)
);
endmodule
| 7.00903 |
module shifter_unit (
input wire clk,
input wire clk_en,
input wire [4:0] offset_x,
input wire [4:0] offset_y,
input wire [127:0] img,
output reg [127:0] shifted
);
integer i;
reg [127:0] tmp;
always @(posedge clk) begin
if (clk_en == 1'b1) begin
if (offset_x[4] == 1'b0) begin
... | 7.177662 |
module shifter_video (
input clk32,
input nReset,
input pixClkEn,
input DE,
input LOAD,
input [1:0] rez,
input monocolor,
input [15:0] DIN,
input scroll,
output reg Reload,
output [3:0] color_index
);
// edge detectors
reg LOAD_D;
always @(posedge clk32) begin : edged... | 6.507107 |
module shifter_video_async (
input clk32,
input nReset,
input pixClk,
input DE,
input LOAD,
input [1:0] rez,
input monocolor,
input [15:0] DIN,
output [3:0] color_index
);
// shift array
wire [15:0] shdout0, shdout1, shdout2, shdout3;
wire [15:0] shcout0, shcout1, shcout2, sh... | 6.507107 |
module shifter_cell_a (
input clk32,
input pixClk,
input LOAD,
input Reload,
input Shin,
output reg Shout,
input Din,
output reg Dout
);
always @(posedge LOAD) begin
Dout <= Din;
end
always @(posedge pixClk) begin
Shout <= Reload ? Dout : Shin;
end
endmodule
| 7.308129 |
module shifter_w1_d128 (
clk,
sclr,
d,
q
) /* synthesis syn_black_box syn_noprune=1 */;
input clk;
input sclr;
input [0 : 0] d;
output [0 : 0] q;
// synthesis translate_off
wire \U0/i_synth/i_bb_inst/Mshreg_f1.only_clb.srl_sig_63_0_6 ;
wire \U0/i_synth/i_bb_inst/N1 ;
wire \U0/i_synth/... | 6.513695 |
module shiftin #(
parameter DATA_WIDTH = 8,
COUNTER_WIDTH = 4
) (
X_in,
Sx,
reset,
Clk,
X_parallel,
Fx
);
input X_in, Sx, reset, Clk;
output [DATA_WIDTH-1:0] X_parallel;
output Fx;
reg [DATA_WIDTH-1:0] X_parallel;
reg Fx;
reg [COUNTER_WIDTH-1:0] counter;
reg new_shift_in;
... | 7.131144 |
module shifting_block (
input amin,
input cmin,
input aplus,
input cplus,
input select1,
input select0,
output y
);
wire wmux[2:0], garbage[5:0];
fredGate
leftMux (
select1,
amin,
cmin,
garbage[0],
wmux[0],
garbage... | 6.950312 |
module shifting_register (
Clk,
Din,
Mode,
Drc,
Num,
Dout
);
input Clk; //时钟信号
input [7:0] Din; //输入的8位2进制数
input [2:0] Num; //需要移动的位数
input Drc; //移动方向：0左1右
input [1:0] Mode; //工作模式：00逻辑；01算数；10循环；11扭环；
output reg [7:0] Dout; //移动后的8位2进制数
reg [2:0] count; //计数器
reg [7:0] ... | 6.744719 |
module shifting_register_2 (
Clk,
Din,
Mode,
Drc,
Num,
Dout
);
input Clk; //时钟信号
input [7:0] Din; //输入的8位2进制数
input [3:0] Num; //需要移动的位数
input Drc; //移动方向：0左1右
input [1:0] Mode; //工作模式：00逻辑；01算数；10循环；11扭环；
output reg [7:0] Dout; //移动后的8位2进制数
reg [31:0] count; //计数器
reg [ 7... | 6.744719 |
module shifting_window (
input clock,
input reset,
input shift_up, // shift all rows up
input shift_left, // to load new pixel into bottom row
input [`CAMERA_PIXEL_BITWIDTH:0] pixel_in,
output [`BUFFER_OUT_VECTOR_BITWIDTH:0] buffer_out
);
// paremeters
// wire declarations
wire [`CAME... | 7.48882 |
module shiftL2 (
shiftin,
shiftout
);
input [63:0] shiftin;
output [63:0] shiftout;
assign shiftout = shiftin << 2;
endmodule
| 7.422149 |
module shiftleft (
input wire [31:0] in,
output wire [31:0] out
);
assign out = (in << 2);
endmodule
| 7.37725 |
module ShiftLeft16b (
from,
to
);
input wire [31:0] from;
output wire [31:0] to;
assign to = {from[15:0], 16'b0};
endmodule
| 7.066858 |
module ShiftLeft2 (
input [31:0] DataInput,
output reg [31:0] DataOutput
);
always @(DataInput) DataOutput = {DataInput[29:0], 1'b0, 1'b0};
endmodule
| 6.743548 |
module (PC Loop)
//
// The jump target address is obtained by shifting the lower
// 26 bits of the jump instruction left 2 bits, and then
// concatenating the upper 4 bits of PC+4 as the high-order
// bits leading to a 32-bit address.
`timescale 1ns/1ns
module ShiftLeft2PC(instr, PC4, out1);
input [25:0] inst... | 9.616139 |
module ShiftLeft2_PC (
input wire [25:0] Instruction_25_0,
output wire [27:0] Data_out
);
assign Data_out = Instruction_25_0 << 2;
endmodule
| 7.520022 |
module ShiftLeft4 (
input wire [15:0] Instruction_15_0,
output wire [31:0] Data_out
);
assign Data_out = Instruction_15_0 << 16;
endmodule
| 7.436609 |
module ShiftLeftBranch (
in,
out
);
input wire [31:0] in;
output [31:0] out;
assign out = in << 2;
endmodule
| 7.75218 |
module shiftLeftBy2 (
i_data,
o_data
);
parameter WIDTH = 32;
input [WIDTH-1:0] i_data;
output [WIDTH-1:0] o_data;
assign o_data[WIDTH-1:0] = i_data[WIDTH-1:0] << 2;
endmodule
| 7.445418 |
module ShiftLeftJump (
in,
out
);
input wire [25:0] in;
output [27:0] out;
assign out = in << 2;
endmodule
| 7.564176 |
module shiftleftmodule (
input_shiftleftmodule,
output_shiftleftmodule
);
input [25:0] input_shiftleftmodule;
output reg [27:0] output_shiftleftmodule;
//always @(*) begin
always begin
output_shiftleftmodule = input_shiftleftmodule << 2;
end
endmodule
| 7.454755 |
module ShiftLeftN (
from,
shamt,
to
);
input wire [31:0] from;
input wire [4:0] shamt;
output wire [31:0] to;
assign to = from << shamt;
endmodule
| 7.086537 |
module ShiftLeftNBit #(
parameter N = 32
) (
input [N-1:0] A,
output [N-1:0] B
);
assign B = {A[N-2:0], 1'b0};
endmodule
| 7.903728 |
module shiftLeftTest;
reg [31:0] TinA, TinB;
wire [31:0] Tout;
initial begin
$dumpfile("shiftLeftTest.vcd");
$dumpvars(0, shiftLeftTest);
$monitor($time,, Tout,, TinA,, TinB);
TinA = 32'b1;
TinB = 32'd2;
#500;
TinB = 32'd4;
#500;
TinB = 32'd8;
#500;
TinA = 32'hffffffff... | 6.851466 |
module to be used in */
/* program counter manipulating for dealing with the */
/* jump and offset immediate values instructions. */
/********************************************************/
module ShiftLeftTwice #
(
parameter DATA_WIDTH = 32
)
(
input wire [DATA_WIDTH-1:0] IN ,
... | 7.785841 |
module ShiftLeftTwo (
input clk,
input reset,
input [63:0] SLInput,
output reg [63:0] SLOutput
);
always @(posedge clk) begin
SLOutput = SLOutput << 2;
end
endmodule
| 7.545511 |
module shiftleft_2bit (
in,
out
);
input [7:0] in;
output [7:0] out;
assign out = {in[5:0], 2'b00};
endmodule
| 8.207069 |
module shiftleft_4bit (
in,
out
);
input [7:0] in;
output [7:0] out;
assign out = {in[3:0], 4'b0000};
endmodule
| 7.472644 |
module shiftleft16_add (
in,
ena,
out
);
input [24:0] in;
input ena;
output [24:0] out;
assign out = ena ? {in[8:0], 16'b0} : in;
endmodule
| 7.208939 |
module shiftleft4_add (
in,
ena,
out
);
input [24:0] in;
input ena;
output [24:0] out;
assign out = ena ? {in[20:0], 4'b0} : in;
endmodule
| 6.813068 |
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