code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Sign_16_32_extend (
input [15:0] in,
output reg [31:0] out
);
always @(*) begin
if (in[15] == 1) begin
out = {16'b1111111111111111, in};
end else begin
out = {16'b0000000000000000, in};
end
end
endmodule
| 7.004835 |
module Sign_21_32_extend (
input [20:0] in,
output reg [31:0] out
);
always @(*) begin
if (in[20] == 1) begin
out = {11'b11111111111, in};
end else begin
out = {11'b00000000000, in};
end
end
endmodule
| 6.811238 |
module: SignExtend_24
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Sign_24_Test;
// Inputs
reg [23:0] immediate_24;
// Outputs
wire [31:0] immediate_32;
// Instantiate the... | 6.937983 |
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //A signed overflow occurs when adding two positive numbers produces a negative result,
//or adding two negative numbers produces a positive result(a=b(last bits) and difference between input(a or b) with s.
ass... | 7.203305 |
module full_add (
in1,
in2,
cin,
s,
cout
);
input in1;
input in2;
input cin;
output s, cout;
assign s = (in1 ^ in2) ^ cin;
assign cout = ((in1 & in2) | ((in1 ^ in2) & cin));
endmodule
| 7.176667 |
module change (
in,
out
);
input [5:0] in;
output [5:0] out;
assign out = ~in;
endmodule
| 8.215554 |
module delay2 (
in,
clk,
out
);
input in, clk;
output reg out;
reg r_data;
always @(posedge clk) begin
r_data <= in;
out <= r_data;
end
endmodule
| 6.536161 |
module delay5 (
in,
clk,
out
);
input in, clk;
output reg out;
reg [3:0] r_data;
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
r_data[3] <= r_data[2];
out <= r_data[3];
end
endmodule
| 6.609939 |
module delay8 (
in,
clk,
out
);
input in, clk;
output reg out;
reg [6:0] r_data;
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
r_data[3] <= r_data[2];
r_data[4] <= r_data[3];
r_data[5] <= r_data[4];
r_data[6] <= r_data[5];... | 6.615059 |
module change_sign (
in,
out
);
input [5:0] in;
output [5:0] out;
assign out[4:0] = in[4:0];
assign out[5] = ~in[5];
endmodule
| 7.905136 |
module sign_computation (
input eff_op,
input s_a_number,
input s_b_number,
input a_greater_exponent,
input b_greater_exponent,
input adder_mantissa_ovf,
output sign
);
wire [4:0] sign_cases;
reg intermediar_sign;
assign sign_cases = {eff_op, s_a_number, s_b_number, a_greater_e... | 6.956121 |
module sign_ex (
in,
out
);
parameter INPUT_WIDTH = 16;
parameter OUTPUT_WIDTH = 32;
input [INPUT_WIDTH-1:0] in;
output [OUTPUT_WIDTH-1:0] out;
localparam MSB_POSITION = INPUT_WIDTH - 1;
localparam MSB_REP_COUNT = OUTPUT_WIDTH - INPUT_WIDTH;
assign out = {{MSB_REP_COUNT{in[MSB_POSITION]}}, in[I... | 7.506945 |
module sign_ext #(
parameter P_IN_WIDTH = 14,
P_OUT_WIDTH = 16
) (
input [ P_IN_WIDTH-1:0] data_in,
output [P_OUT_WIDTH-1:0] data_out
);
assign data_out = {{(P_OUT_WIDTH - P_IN_WIDTH) {data_in[P_IN_WIDTH-1]}}, data_in};
endmodule
| 8.136289 |
module sign_extend (
in,
out
);
parameter bits_in = 0; // FIXME Quartus insists on a default
parameter bits_out = 0;
input [bits_in-1:0] in;
output [bits_out-1:0] out;
assign out = {{(bits_out - bits_in) {in[bits_in-1]}}, in};
endmodule
| 7.581479 |
module sign_extend16 #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] immediate,
output [(WIDTH*2)-1:0] extended
);
//sign extend our 16 bit immediate to a 32 bit immediate
assign extended = (immediate[WIDTH-1]) ? {16'hff, immediate} : {16'h00, immediate};
endmodule
| 7.111358 |
module sign_extend16to32 (
input wire [15:0] data_in,
output wire [31:0] data_out
);
assign data_out = (data_in[15]) ? {{16{1'b1}}, data_in} : {{16{1'b0}}, data_in};
endmodule
| 7.111358 |
module sign_extend16to32_testbench ();
reg [15:0] A;
wire [31:0] R;
//module sign_extend16to32(bit_32 ,bit_16);
sign_extend16to32 se16to32tb (
R,
A
);
initial begin
A = 16'b0000101011000001;
#`DELAY;
A = 16'b1110101010000001;
#`DELAY;
A = 16'b0100000000000000;
#`DELA... | 7.111358 |
module sign_extend1to32 (
input wire data_in,
output wire [31:0] data_out
);
assign data_out = (data_in) ? {{31{1'b1}}, data_in} : {{31{1'b0}}, data_in};
endmodule
| 7.446524 |
module sign_extend8to32 (
input wire [ 7:0] data_in,
output wire [31:0] data_out
);
assign data_out = (data_in[15]) ? {{24{1'b1}}, data_in} : {{24{1'b0}}, data_in};
endmodule
| 7.674261 |
module sign_extended (
//Entrada
input [15:0] Entrada16b,
//Salida
output reg [31:0] Salida32b
);
always @(*) Salida32b = {{16{Entrada16b[15]}}, Entrada16b};
endmodule
| 8.005427 |
module sign_extend_12bit_32bit (
input [31:0] immediate_data,
output [31:0] sign_extended_data,
input beq_signal,
input sw_D_signal
);
reg [31:0] data_reg;
always @(*) begin
if (beq_signal == 1) begin
data_reg = {
{21{immediate_data[31]}}, immediate_data[7], immediate_data[30:25], ... | 7.115926 |
module sign_extend_12_32 (
input wire [11:0] iwOrig,
output wire [31:0] owExtended
);
assign owExtended[11:0] = iwOrig;
assign owExtended[31:12] = iwOrig[11] ? 20'hfffff : 20'h00000;
endmodule
| 7.115926 |
module sign_extend_13_32 (
input wire [12:0] iwOrig,
output wire [31:0] owExtended
);
assign owExtended[12:0] = iwOrig;
assign owExtended[31:13] = iwOrig[11] ? 20'hfffff : 20'h00000;
endmodule
| 7.115926 |
module Sign_Extend_16to32 (
input [15:0] immediate,
output [31:0] extendedImmediate
);
assign extendedImmediate = {{16{immediate[15]}}, immediate};
endmodule
| 6.704766 |
module Sign_Extend_16to32_TB;
reg [15:0] immediate;
wire [31:0] extendedImmediate;
Sign_Extend_16to32 uut (
.immediate(immediate),
.extendedImmediate(extendedImmediate)
);
initial begin
$display("-------------------------------------------");
$display("!!!!!!!!!!!!!!SIGN EXTENDED!!... | 6.704766 |
module sign_extend_16_32 (
input wire [15:0] iwOrig,
output wire [31:0] owExtended
);
assign owExtended[15:0] = iwOrig;
assign owExtended[31:16] = iwOrig[15] ? 16'hffff : 16'h0000;
endmodule
| 7.115926 |
module sign_extend_1to32 (
input wire data_in,
output wire [31:0] data_out
);
assign data_out = {{31{1'b0}}, data_in};
endmodule
| 7.115926 |
module sign_extend_20_32 (
input wire [19:0] iwOrig,
output wire [31:0] owExtended
);
assign owExtended[19:0] = iwOrig;
assign owExtended[31:20] = iwOrig[19] ? 12'hfff : 12'h000;
endmodule
| 6.85784 |
module sign_extend_21_32 (
input wire [20:0] iwOrig,
output wire [31:0] owExtended
);
assign owExtended[20:0] = iwOrig;
assign owExtended[31:21] = iwOrig[20] ? 11'h7ff : 11'h000;
endmodule
| 6.85784 |
module sign_extend_8bit (
in,
out
);
input [3:0] in;
output [7:0] out;
assign out = {4'b0, in};
endmodule
| 6.773742 |
module sign_extend_8_32 (
input wire [ 7:0] iwOrig,
output wire [31:0] owExtended
);
assign owExtended[7:0] = iwOrig;
assign owExtended[31:8] = iwOrig[7] ? 24'hffffff : 24'h000000;
endmodule
| 6.773742 |
module register (
d,
clk,
resetn,
en,
q
);
//parameter WIDTH=32;
// this initialization of a register has WIDTH = 2
input clk;
input resetn;
input en;
input [1:0] d;
output [1:0] q;
reg [1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn == ... | 6.542519 |
module load_data_translator (
d_readdatain,
d_address,
load_size,
load_sign_ext,
d_loadresult
);
//parameter WIDTH=32;
input [`WIDTH-1:0] d_readdatain;
input [1:0] d_address;
input [1:0] load_size;
input load_sign_ext;
output [`WIDTH-1:0] d_loadresult;
wire d_adr_one;
assign d_adr... | 9.105161 |
module Sign_Extend_Operands (
optype,
op1_in,
op2_in,
op3_in,
op1_out,
op2_out,
op3_out
);
input [2:0] optype;
input signed [7:0] op1_in, op2_in, op3_in;
output reg signed [15:0] op1_out, op2_out, op3_out;
always @(*) begin
if (optype[2] == 1) begin //se o operando for um e... | 7.379106 |
module Sign_Extend_Shift_Left_2 (
op1,
op1_extended
);
input [7:0] op1;
output signed [15:0] op1_extended;
assign op1_extended = ($signed(op1)) << 1;
endmodule
| 6.55171 |
module SignExtension (
In,
Out
);
/////////////////////////////////////////
// INPUT/OUTPUT DEFINITIONS GO HERE
////////////////////////////////////
//
input signed [15:0] In;
output signed [31:0] Out;
/////////////////////////////////////////
// ASSIGN STATEMENTS GO HERE
///////////////////... | 6.562271 |
module Sign_Extension_10bit (
input clk,
rst,
input [9:0] data_in,
output reg [15:0] data_out
);
always @(posedge rst, posedge clk) begin
if (rst) begin
data_out <= 16'b0;
end else begin
if (data_in[8] == 1'b1) begin
data_out <= {6'b111111, data_in};
end else if (dat... | 6.651391 |
module Sign_Extension_10bit_tb;
reg clk;
reg rst;
reg [9:0] data_in;
wire [15:0] data_out;
Sign_Extension_10bit se10b (
.clk(clk),
.rst(rst),
.data_in(data_in),
.data_out(data_out)
);
localparam CLK_PERIOD = 100;
localparam RUNNING_CYCLES = 10;
initial begin
clk = 0;
... | 6.651391 |
module Sign_Extension_9bit (
input clk,
rst,
input [8:0] data_in,
output reg [15:0] data_out
);
always @(posedge clk, posedge rst) begin
if (rst) begin
data_out <= 16'd0;
end else begin
if (data_in[8] == 1'b1) begin
data_out <= {7'b1111111, data_in};
end else if (dat... | 6.651391 |
module Sign_Extension_9bit_tb;
reg clk;
reg rst;
reg [8:0] data_in;
wire [15:0] data_out;
Sign_Extension_9bit se9b (
.clk(clk),
.rst(rst),
.data_in(data_in),
.data_out(data_out)
);
localparam CLK_PERIOD = 100;
localparam RUNNING_CYCLES = 10;
initial begin
clk = 0;
rep... | 6.651391 |
module Sign_extension_b (
input [31:0] Instruction_code,
//input [19:0] Immediate12, // 12 bit input to be sign extended for branch
output reg [31:0] Sign_ext_b // 32 bit sign extended output for branch
);
reg [11:0] Immediate12_branch;
always @(Instruction_code) begin
... | 9.21925 |
module Sign_extension_j (
input [31:0] Instruction_code,
//input [19:0] Immediate20, // 20 bit input to be sign extended for jal
output reg [31:0] Sign_ext_j // 32 bit sign extended output for jal
);
reg [19:0] Immediate20;
always @(Instruction_code) begin
Immediate2... | 9.21925 |
module sign_extention #(
parameter in_width = 16,
out_width = 32
) (
input [in_width-1:0] in,
output reg [out_width-1:0] out
);
always @(*) begin
out = {{in_width{in[in_width-1]}}, in};
end
endmodule
| 7.662311 |
module sign_ext_16_to_32 (
in,
out
);
input [15:0] in;
output reg [31:0] out;
always @(in) begin
out = {{16{in[15]}}, in};
end
endmodule
| 7.323539 |
module sign_ext_test ();
reg [15:0] in;
wire [31:0] out;
sign_ext_16_to_32 sign_ext_test (
in,
out
);
initial begin
in = 16'b00001111_11111111;
#1000 in = 16'b10001111_11111111;
#1000;
end
endmodule
| 7.133965 |
module SIGN_EXT_tb ();
reg [11:0] unex;
wire [15:0] ext;
SIGN_EXT #(
.IN_SIZE(11)
) DUT (
.in (unex),
.out(ext)
);
initial begin
unex = 8'b00110110;
#10;
unex = 8'b11110101;
#10;
end
initial begin
$dumpvars;
$display(" unex | ext ");
$monitor(" %b ... | 7.018429 |
module sign_inverter #(
parameter W = 32
) (
input wire [W-1:0] data,
input wire [1:0] shift_region_flag,
input wire operation,
output reg [W-1:0] data_out
);
always @* begin
if(operation == 1'b0)//coseno
begin
if(shift_region_flag == 2'b00 || shift_region_flag == 2'b11)//no hay desp... | 7.462062 |
module Sign_Logical_Extend (
ZorS,
Instr15_0,
SZSE_Out
);
input [15:0] Instr15_0;
input [1:0] ZorS;
output reg [31:0] SZSE_Out;
always @(*) begin
if (ZorS == 0) begin
if (Instr15_0[15] == 2'b00) SZSE_Out <= {16'b0000000000000000, Instr15_0};
else SZSE_Out <= {16'b1111111111111111, I... | 7.045211 |
module sign_lookup (
input [3:0] in_width,
input [3:0] weight_width,
output reg [3:0] in_signed,
output reg [3:0] weight_signed
);
always @(*) begin
case (in_width)
4'b0001, 4'b0010: in_signed = 4'b1111;
4'b0100: in_signed = 4'b1010;
4'b1000: in_signed = 4'b1000;
default: ... | 7.188999 |
module sign_made (
sys_clk,
IRF,
IRF_sign
);
//---Ports declearation: generated by Robei---
input sys_clk;
input IRF;
output IRF_sign;
wire sys_clk;
wire IRF;
reg IRF_sign;
//----Code starts here: integrated by Robei-----
//parameter MADE1 = 800000000;
parameter MADEFZ = 800000... | 6.686209 |
module sign_magnitude_to_twos_complement (
twos_complement,
sign_magnitude
);
output [15:0] twos_complement;
input [15:0] sign_magnitude;
assign twos_complement = sign_magnitude[15] ?
{sign_magnitude[15], ~sign_magnitude[14:0]} + 16'b1 :
sign_magnitude;
... | 6.977678 |
module sign_magnitude_to_twos_complement_tb;
wire signed [15:0] twos_complement;
reg [15:0] sign_magnitude = 0;
sign_magnitude_to_twos_complement translator (
twos_complement,
sign_magnitude
);
initial begin
$monitor("%d - sign_magnitude: %b, 2's complement: %b", twos_complement, sign_magni... | 6.977678 |
module sign_mag_add #(
parameter N = 4 // number of bits per input/output
) (
input wire [N-1:0] a,
b,
output reg [N-1:0] sum
);
// signal declaration
reg [N-2:0] mag_a, mag_b, mag_sum, max, min;
reg sign_a, sign_b, sign_sum;
// body
always @* begin
// separate magnitude and sign
... | 8.211188 |
module sign_mag_adder (
input [7:0] a,
input [7:0] b,
output [8:0] sum
);
// Variable Declarion
wire sign_a;
wire sign_b;
wire [6:0] mag_a;
wire [6:0] mag_b;
wire compare;
wire c_out;
wire [6:0] outmux1;
wire [6:0] outmux2;
wire [6:0] outmux3;
wire [6:0] outmux4;
wire [6:0] outmux... | 6.769108 |
module: sign_mag_adder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sign_mag_adder_tb;
// Inputs
reg [7:0] a;
reg [7:0] b;
// Outputs
wire [8:0] sum;
// Instantiate the U... | 7.070984 |
module Sign_of_z (
input wire Sx,
Sy,
EOP,
cmp,
zero_d,
sign_d,
output reg Sz
);
always @(*) begin
if (zero_d == 1) begin
if (EOP == 0) begin
Sz = Sx;
end
else if (cmp==0) // EOP =1
begin
Sz = Sx;
end else // EOP =1 & cmp =1
begin
... | 7.129743 |
module Sign_of_z_new (
input wire Sx,
Sy,
EOP,
cmp,
zero_d,
sign_d,
output wire Sz
);
//internal signals
wire Sz_0, Sz_1, Sz_2, Sz_3;
//instances
mux_2_in_1_out mux_2_in_1_out_inst_1 (
Sz_1,
Sz_0,
zero_d,
Sz
);
mux_2_in_1_out mux_2_in_1_out_inst_2 (
... | 6.614697 |
module sign_reg (
clk,
flag,
key_value,
out_sign
);
input clk, flag;
input [4:0] key_value;
output reg [2:0] out_sign = 3'b111;
/*żĴģ*/
//궨ֵ
parameter add = 3'b000;
parameter minus = 3'b001;
parameter multiply = 3'b010;
parameter division = 3'b011;
parameter reset = 3'b100;
parame... | 8.547158 |
module sign_tb ();
reg [15:0] inst;
wire [31:0] data;
sign s0 (
.inst(inst),
.data(data)
);
initial begin
inst = 0;
#100 inst = 1;
#100 inst = -1;
#100 inst = 2;
#100 inst = -2;
#100 inst = 14;
#100 inst = -14;
end
endmodule
| 6.925157 |
module sign_test;
parameter WORD_WIDTH = `WORD_WIDTH;
parameter clock_period = `CLOCK_PERIOD;
reg [WORD_WIDTH-1:0] in;
wire [ 1:0] out;
reg [ 8*4:1] operator;
//-----instance of sign module
sign #(
.WORD_WIDTH(WORD_WIDTH)
) sign_inst (
.ans(in),
.sign_ans(out)
... | 6.537471 |
module sign_unit (
output wire sign,
input wire sign1,
input wire sign2
);
assign sign = ((sign1 ^ sign2) == 1) ? 1 : 0;
endmodule
| 7.522445 |
module sign_xshift (
OFF_IN,
OFF_SHIFT
);
input [5:0] OFF_IN;
output [7:0] OFF_SHIFT;
wire [7:0] OFF_X;
assign OFF_X[7:0] = {OFF_IN[5], OFF_IN[5], OFF_IN[5:0]};
assign OFF_SHIFT[7:0] = {OFF_X[6:0], 1'b0};
endmodule
| 6.615328 |
module sign_zero_ext (
input wire [15:0] in,
output wire [31:0] out,
input wire modee
);
assign out = modee ? {{16{1'b0}}, in[15:0]} : {{16{in[15]}}, in[15:0]};
endmodule
| 7.389804 |
module sign_zero_extend (
input [15:0] immediate,
input ExtSel,
output [31:0] extendImmediate
);
assign extendImmediate = {ExtSel && immediate[15] ? 16'hffff : 16'h0000, immediate};
endmodule
| 7.389804 |
module sig_adder (
clk,
sw,
sig_square,
sig_saw,
sig_tri,
sig_sine,
sig
);
input clk; // 1MHz clock
input [4:0] sw; // Switches on FPGA
input [15:0] sig_square;
input [15:0] sig_saw;
input [15:0] sig_tri;
input [15:0] sig_sine;
output reg [15:0] sig; // Total output signal
... | 7.407082 |
module sig_chain_tb;
// Signals
reg rst = 1;
reg clk = 0;
reg data_valid;
reg [11:0] data_in;
wire [11:0] data_out;
wire [11:0] data_comb_3;
wire [14:0] cfg_delay;
// Setup recording
initial begin
$dumpfile("sig_chain_tb.vcd");
$dumpvars(0, sig_chain_tb);
end
// Reset pulse
initial... | 7.067766 |
module sig_combine #(
parameter integer D_WIDTH = 12,
parameter integer S_WIDTH = 16,
parameter integer S_FRAC = 14
) (
// Input
input wire [D_WIDTH-1:0] in_data_0,
input wire [S_WIDTH-1:0] in_scale_0,
input wire [D_WIDTH-1:0] in_chain_0,
// Output
output wire [D_WIDTH-1:0] out_3,
... | 6.774488 |
module sig_control (
output reg [1:0] hwy,
cntry,
input wire x,
clk,
clear
);
parameter RED= 2'd0,
YELLOW= 2'd1,
GREEN= 2'd2,
S0= 3'd0,
S1= 3'd1,
S2= 3'd2,
S3= 3'd3,
S4= 3'd4;
reg [2:0] state, next_state;
... | 6.551114 |
module sig_counter #(
parameter WIDTH = 1,
parameter EDGE = 0
) (
input wire clk,
input wire rst_n,
input wire [(WIDTH-1):0] sig,
output reg [7:0] cnt
);
reg [(WIDTH-1):0] sig_last;
reg [7:0] cnt_nxt;
always @(posedge clk) begin
if (!rst_n) begin
sig_last <= 0;
cnt <= 0;... | 6.859968 |
module sig_control (
hwy,
cntry,
X,
clock,
clear
);
//I/O ports
output [1:0] hwy, cntry;
//2 bit output for 3 states of signal
//GREEN, YELLOW, RED;
reg [1:0] hwy, cntry;
//declare output signals are registers
input X;
//if TRUE, indicates that there is car on
//the country road,... | 6.551114 |
module sig_delay #(
parameter integer WIDTH = 12
) (
input wire data_valid,
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out,
input wire [14:0] delay,
input wire clk,
input wire rst
);
// Signals
// -------
reg [14:0] wr_addr;
reg [14:0] rd_addr;
wire ce;
// C... | 6.929854 |
module sig_delay_TB;
// Inputs
reg clk;
reg [1:0] i_bus;
// Outputs
wire [1:0] o_bus;
// Instantiate the Unit Under Test (UUT)
sig_delay #(
.BUS_BITS(2),
.DELAY (5)
) uut (
.clk (clk),
.i_bus(i_bus),
.o_bus(o_bus)
);
// ------------ Clock --------------
param... | 6.784166 |
module signal_edge (
input clk,
input button,
output button_edge
);
reg button_r1, button_r2;
always @(posedge clk) button_r1 <= button;
always @(posedge clk) button_r2 <= button_r1;
assign button_edge = button_r1 & (~button_r2);
endmodule
| 6.590149 |
module SIG_IS_INTB (
port_a,
port_b,
outp
);
input [1:0] port_a;
input port_b;
output [1:0] outp;
assign outp = port_b ? port_a : 2'bzz;
endmodule
| 7.22153 |
module Sig_ROM #(
parameter inWidth = 10,
dataWidth = 16
) (
input clk,
input [ inWidth-1:0] x,
output [dataWidth-1:0] out
);
reg [dataWidth-1:0] mem[2**inWidth-1:0];
reg [ inWidth-1:0] y;
initial begin
$readmemb("sigContent.mif", mem);
end
always @(posedge clk) ... | 7.098289 |
module sii_pos (
input wire clk,
input wire rst_n,
input wire data,
output wire data_pos
);
reg data_r1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_r1 <= 1'b0;
end else begin
data_r1 <= data;
end
end
assign data_pos = data && !data_r1;
endm... | 6.948314 |
module sii_sync (
input wire clk,
input wire rst_n,
input wire data,
output reg data_sync
);
reg data_r1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_r1 <= 1'b0;
data_sync <= 1'b0;
end else begin
data_r1 <= data;
data_sync <= data_r1;... | 7.099887 |
module Testbench();
reg clk = 1'b0, rst = 1'b0;
reg rx = 1'b1;
reg [1:0] dataBits = 2'd0;
reg hasParity = 1'b0;
reg [1:0] parityMode = 2'd0;
reg extraStopBit = 1'b0;
reg [23:0] clockDivisor = 24'd2;
wire [8:0] dataOut;
wire dataReceived;
wire parityError;
wire overflow;
wire break;
reg re... | 6.616812 |
module top (
`ifdef VGA
// VGA
output out_video_clock,
output reg [`COLOR_DEPTH-1:0] out_video_r,
output reg [`COLOR_DEPTH-1:0] out_video_g,
output reg [`COLOR_DEPTH-1:0] out_video_b,
output out_video_hs,
output out_video_v... | 6.934442 |
module M_rv32i_cpu__cpu_mem_xregsA (
input [ 5-1:0] in_xregsA_addr0,
output reg signed [32-1:0] out_xregsA_rdata0,
output reg signed [32-1:0] out_xregsA_rdata1,
input [32-1:0] in_xregsA_wenable1,
input [32-1:0] in_xregsA_wdata1,
input [ 5-1:0] in_x... | 7.083036 |
module M_rv32i_cpu__cpu_mem_xregsB (
input [ 5-1:0] in_xregsB_addr0,
output reg signed [32-1:0] out_xregsB_rdata0,
output reg signed [32-1:0] out_xregsB_rdata1,
input [32-1:0] in_xregsB_wenable1,
input [32-1:0] in_xregsB_wdata1,
input [ 5-1:0] in_x... | 7.083036 |
module top (
`ifdef VGA
// VGA
output out_video_clock,
output reg [`COLOR_DEPTH-1:0] out_video_r,
output reg [`COLOR_DEPTH-1:0] out_video_g,
output reg [`COLOR_DEPTH-1:0] out_video_b,
output out_video_hs,
output out_video_v... | 6.934442 |
module top (
`ifdef VGA
// VGA
output out_video_clock,
output reg [`COLOR_DEPTH-1:0] out_video_r,
output reg [`COLOR_DEPTH-1:0] out_video_g,
output reg [`COLOR_DEPTH-1:0] out_video_b,
output out_video_hs,
output out_video_v... | 6.934442 |
module M_div16__div0 (
in_inum,
in_iden,
out_ret,
in_run,
out_done,
reset,
out_clock,
clock
);
input signed [15:0] in_inum;
input signed [15:0] in_iden;
output signed [15:0] out_ret;
input in_run;
output out_done;
input reset;
output out_clock;
input clock;
assign out_c... | 6.713805 |
module top (
`ifdef VGA
// VGA
output out_video_clock,
output reg [`COLOR_DEPTH-1:0] out_video_r,
output reg [`COLOR_DEPTH-1:0] out_video_g,
output reg [`COLOR_DEPTH-1:0] out_video_b,
output out_video_hs,
output out_video_v... | 6.934442 |
module M_rv32i_cpu__cpu_mem_xregsA (
input [ 1-1:0] in_xregsA_wenable,
input signed [32-1:0] in_xregsA_wdata,
input [ 5-1:0] in_xregsA_addr,
output reg signed [32-1:0] out_xregsA_rdata,
input clock
);
reg signed [32-1:0] buffer[32-1:0];
always @(... | 7.083036 |
module M_rv32i_cpu__cpu_mem_xregsB (
input [ 1-1:0] in_xregsB_wenable,
input signed [32-1:0] in_xregsB_wdata,
input [ 5-1:0] in_xregsB_addr,
output reg signed [32-1:0] out_xregsB_rdata,
input clock
);
reg signed [32-1:0] buffer[32-1:0];
always @(... | 7.083036 |
module top (
`ifdef VGA
// VGA
output out_video_clock,
output reg [`COLOR_DEPTH-1:0] out_video_r,
output reg [`COLOR_DEPTH-1:0] out_video_g,
output reg [`COLOR_DEPTH-1:0] out_video_b,
output out_video_hs,
output out_video_v... | 6.934442 |
module top (
`ifdef VGA
// VGA
output out_video_clock,
output reg [`COLOR_DEPTH-1:0] out_video_r,
output reg [`COLOR_DEPTH-1:0] out_video_g,
output reg [`COLOR_DEPTH-1:0] out_video_b,
output out_video_hs,
output out_video_v... | 6.934442 |
module top (
`ifdef VGA
// VGA
output out_video_clock,
output reg [`COLOR_DEPTH-1:0] out_video_r,
output reg [`COLOR_DEPTH-1:0] out_video_g,
output reg [`COLOR_DEPTH-1:0] out_video_b,
output out_video_hs,
output out_video_v... | 6.934442 |
module M_mul_cmp16_0__display_div_mc0 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FOR... | 6.534708 |
module M_mul_cmp16_0__display_div_mc1 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FOR... | 6.534708 |
module M_mul_cmp16_0__display_div_mc2 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FOR... | 6.534708 |
module M_mul_cmp16_0__display_div_mc3 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FOR... | 6.534708 |
module M_mul_cmp16_0__display_div_mc4 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FOR... | 6.534708 |
module M_mul_cmp16_0__display_div_mc5 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FOR... | 6.534708 |
module M_mul_cmp16_0__display_div_mc6 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FOR... | 6.534708 |
module M_mul_cmp16_0__display_div_mc7 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FOR... | 6.534708 |
module M_mul_cmp16_8__display_div_mc8 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FOR... | 6.509797 |
module M_mul_cmp16_8__display_div_mc9 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FOR... | 6.509797 |
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