code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module std_xor #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left ^ right;
endmodule
| 8.185133 |
module std_add #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 7.105468 |
module std_sub #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 7.29825 |
module std_gt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 7.445889 |
module std_lt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left < right;
endmodule
| 7.925865 |
module std_eq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left == right;
endmodule
| 8.155468 |
module std_neq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left != right;
endmodule
| 7.624981 |
module std_ge #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left >= right;
endmodule
| 6.896227 |
module std_le #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left <= right;
endmodule
| 8.161124 |
module std_lsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left << right;
endmodule
| 8.684363 |
module std_rsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left >> right;
endmodule
| 8.622539 |
module std_mux #(
parameter WIDTH = 32
) (
input wire logic cond,
input wire logic [WIDTH-1:0] tru,
input wire logic [WIDTH-1:0] fal,
output logic [WIDTH-1:0] out
);
assign out = cond ? tru : fal;
endmodule
| 9.56204 |
module std_reg #(
parameter WIDTH = 32
) (
input wire [ WIDTH-1:0] in,
input wire write_en,
input wire clk,
input wire reset,
// output
output logic [WIDTH - 1:0] out,
output logic done
);
always_ff @(posedge clk) begin
... | 7.672256 |
module std_mem_d1 #(
parameter WIDTH = 32,
parameter SIZE = 16,
parameter IDX_SIZE = 4
) (
input wire logic [IDX_SIZE-1:0] addr0,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0... | 8.560454 |
module std_mem_d2 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [ WIDTH-1:0] write_data,
in... | 8.570777 |
module std_mem_d3 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,... | 9.018781 |
module std_mem_d4 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D3_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4,
parameter D3_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE... | 9.168498 |
module main (
input logic go,
input logic clk,
input logic reset,
output logic done,
output logic mem0_addr0,
output logic [3:0] mem0_write_data,
output logic mem0_write_en,
output logic mem0_clk,
input logic [3:0] mem0_read_data,
input logic mem0_done
);
logic identity_go_in;
... | 7.081372 |
module SIGNED (
iX1,
iX2,
oY
);
input signed [3:0] iX1;
input signed [3:0] iX2;
output signed [7:0] oY;
assign oY = iX1 * iX2;
endmodule
| 7.071844 |
module displaysigned ();
reg signed [7:0] foo;
reg [7:0] bar;
initial begin
foo = -8'sd2;
bar = foo;
$display("foo=%0d bar=%0d $signed(bar)=%0d", foo, bar, $signed(bar));
$finish;
end
endmodule
| 7.539073 |
module top;
// Does this have to be signed?
wire signed [7:0] out;
// Either of these will not expand correctly.
// assign out = 'sh1f;
assign out = 5'sh1f;
initial #1 $displayb(out);
endmodule
| 6.928906 |
module mult58s (
input [4:0] a,
input signed [7:0] b,
output signed [15:0] p
);
wire signed [12:0] pt;
wire signed [ 5:0] ta;
assign ta = a;
assign pt = b * ta;
assign p = pt;
endmodule
| 6.796468 |
module assignsigned ();
parameter foo = 10;
reg signed [15:0] bar = -1;
wire baz;
assign baz = (bar < $signed(foo));
initial begin
#1 $display("bar=%h(%0d), foo=%0d, baz = %b", bar, bar, foo, baz);
if (baz !== 1'b1) begin
$display("FAILED -- Compare returns %b instead of 1.", baz);... | 7.512528 |
module SignedAdder ( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input [15:0] io_in0, // @[:@6.4]
input [15:0] io_in1, // @[:@6.4]
output [15:0] io_out // @[:@6.4]
);
assign io_out = $signed(io_in0) + $signed(io_in1); // @[Adder.scala 89:20:@13.4]
endm... | 6.579491 |
module SignedAdder (
input clock,
input reset,
input [15:0] io_in0,
input [15:0] io_in1,
output [15:0] io_out
);
assign io_out = $signed(io_in0) + $signed(io_in1); // @[Adder.scala 89:20]
endmodule
| 6.579491 |
module SignedCastModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire signed [15:0] ShortValue,
output wire [7:0] ByteValue,
output wire signed [7:0] SByteValue,
output wire [15:0] UShortValue,
output wire signed [31:0] IntValue,
output wire [31:0] UIntValue
);
// [... | 8.518234 |
module SignedDec2Hex #(
parameter WIDTH = 8
) (
input wire signed [WIDTH-1:0] signed_dec_i,
output reg [WIDTH-1:0] hex_o
);
reg [WIDTH-1:0] dec_c;
always @(signed_dec_i) begin
if (signed_dec_i[WIDTH-1]) hex_o = (~signed_dec_i) + 1'b1;
else hex_o = signed_dec_i;
end
endmodule
| 8.488558 |
module SignedExt (
input signed [15:0] input_num,
output signed [31:0] output_num
);
assign output_num = input_num;
endmodule
| 7.429631 |
module to do signed extension operation on a given
* data. The default input data width is 16bit, output data width is 32bit.
*/
module signedextend #(parameter INWIDTH = 16, parameter OUTWIDTH = 32)(
input wire [INWIDTH-1:0] din,
output reg [OUTWIDTH-1:0] dout);
always... | 9.53866 |
module SignedModule ( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input [9:0] io_in, // @[:@6.4]
output [9:0] io_out // @[:@6.4]
);
wire _T_7 = $signed(io_in) < 10'sh0; // @[SIntTypeClass.scala 66:35:@12.4]
wire [9:0] _T_17 = 10'sh0 - $signed(io_in); // @[SInt... | 7.014553 |
module SignedModule (
input clock,
input reset,
input [9:0] io_in,
output [9:0] io_out
);
wire _T_7 = $signed(io_in) < 10'sh0; // @[SIntTypeClass.scala 66:35]
wire [9:0] _T_17 = 10'sh0 - $signed(io_in); // @[SIntTypeClass.scala 28:50]
wire [9:0] _T_18 = io_in[9] ? $signed(_T_17) :... | 7.014553 |
module signedmul (
input clk,
input [15:0] a,
input [15:0] b,
output [15:0] c
);
wire [31:0] result;
wire [15:0] a_new;
wire [15:0] b_new;
reg [15:0] a_ff;
reg [15:0] b_ff;
reg [31:0] result_ff;
reg a_sign, b_sign, a_sign_ff, b_sign_ff;
assign c = (b_sign_ff == a_sign_ff) ? result_... | 6.6402 |
module twoBitMultiplier (
input [1:0] a,
input [1:0] b,
output [3:0] c
);
wire m0, m1, m2, m3, m4, m5;
and and0 (c[0], a[0], b[0]);
and and1 (m0, a[1], ~a[0], b[0]);
and and2 (m1, a[1], ~b[1], b[0]);
and and3 (m2, b[1], ~a[1], a[0]);
and and4 (m3, a[0], ~b[0], b[1]);
or or0 (c[1], m0, m1, m... | 6.540566 |
module fourBitMultiplier (
input [3:0] a,
input [3:0] b,
output [7:0] c
);
wire [3:0] p1, p2, p3, p4;
twoBitMultiplier mul1 (
a[1:0],
b[1:0],
p1
);
twoBitMultiplier mul2 (
a[3:2],
b[1:0],
p2
);
twoBitMultiplier mul3 (
a[1:0],
b[3:2],
p3
... | 7.452549 |
module signed_add #(
parameter WIDTH = 13
) (
input signed [WIDTH-1:0] dataa,
input signed [WIDTH-1:0] datab,
output [WIDTH-1:0] result
);
wire [WIDTH:0] temp_result;
assign temp_result = dataa + datab;
assign result = {temp_result[WIDTH], temp_result[WIDTH-2:0]};
endmodule
| 7.167122 |
module signed_array_multiplier (
inA,
inB,
init,
clock,
out
);
// Aka 2's complement Multiplier
// Declaring bi-width parameter
parameter n = 32;
// Assigning ports as in/out
input [(n/2)-1:0] inA, inB;
input init, clock;
output [n-1:0] out;
// Initializing necessary registers
r... | 7.656409 |
module signed_comparator (
input wire signed [7:0] a,
b,
output wire out
);
assign out = a > b ? 1'b1 : 1'b0;
endmodule
| 8.882766 |
module signed_cplx_expand (
ire,
iim,
ore,
oim
);
parameter IWIDTH = 16;
parameter OWIDTH = 16;
parameter IPRE = 0;
input [IWIDTH-1:0] ire;
input [IWIDTH-1:0] iim;
output [OWIDTH-1:0] ore;
output [OWIDTH-1:0] oim;
signed_expand #(
.IWIDTH(IWIDTH),
.OWIDTH(OWIDTH),
.IP... | 6.915568 |
module signed_cplx_trunc (
ire,
iim,
ore,
oim
);
parameter IWIDTH = 16;
parameter OWIDTH = 16;
parameter IPRE = 0;
input [IWIDTH-1:0] ire;
input [IWIDTH-1:0] iim;
output [OWIDTH-1:0] ore;
output [OWIDTH-1:0] oim;
signed_trunc #(
.IWIDTH(IWIDTH),
.OWIDTH(OWIDTH),
.IPRE... | 8.373072 |
module signed_data_chopper #(
INPUT_FIRST_BIT = 60,
OUTPUT_WIDTH = 8
) (
input wire [63:0] i_data,
output wire [OUTPUT_WIDTH - 1:0] o_data
);
assign o_data = {i_data[62], i_data[INPUT_FIRST_BIT-:(OUTPUT_WIDTH-1)]};
endmodule
| 7.751344 |
module signed_expand (
idata,
odata
);
parameter IWIDTH = 8;
parameter OWIDTH = 16;
parameter IPRE = 4;
input [IWIDTH-1:0] idata;
output [OWIDTH-1:0] odata;
assign odata = {{IPRE{idata[IWIDTH-1]}}, idata, {OWIDTH - IWIDTH - IPRE{1'b0}}};
endmodule
| 7.780099 |
module signed_expansion (
input [LENGTH-1:0] in,
output reg [TARGET-1:0] out
);
parameter LENGTH = 10;
parameter TARGET = 32;
always @(in) begin
out[LENGTH-2:0] = in[LENGTH-2:0];
case (in[LENGTH-1])
1'b1: out[TARGET-1:LENGTH-1] = -1;
1'b0: out[TARGET-1:LENGTH-1] = 0;
endcase
en... | 6.555474 |
module signed_mult_const_asic (
rstn,
clk,
valid,
a,
p
);
parameter N = 8;
input rstn;
input clk;
input valid;
input [N-1:0] a; // variable - positive/negative
output [N : 0] p; // product output
// FHT constant
//wire [8:0] mult_constant; // always positive
//assign mult_const... | 7.218537 |
module signed_mult_const_fpga (
rstn,
clk,
valid,
a,
p
);
parameter N = 8;
input rstn;
input clk;
input valid;
input signed [N-1:0] a; // variable - positive/negative
output signed [N : 0] p; // product output
// FHT constant
// wire [8:0] mult_constant; // always positive
// a... | 7.218537 |
module Signed_Mult_tap (
input [1:0] rxin, //[1] :signed bit of imaginary part, [0] :signed bit of real part,
input [1:0] preamble, //[1] :signed bit of imaginary part, [0] :signed bit of real part,
output [1:0] mult_out_Re,
mult_out_Im
);
wire cmp1_Re = (rxin[0] == preamble[0]);
wire cmp2... | 7.236413 |
module signed_mult_tb ();
//激励信号定义
reg tb_clk;
reg tb_rst_n;
reg signed [ 7:0] tb_din0;
reg signed [ 7:0] tb_din1;
reg tb_din_vld;
//输出信号定义
wire signed [15:0] tb_dout0;
wire signed [15:0] tb_dout1;
wire tb_dout_vld;
reg signed [ 7:... | 7.408037 |
module signed_sub #(
parameter WIDTH = 13
) (
input signed [WIDTH-1:0] dataa,
input signed [WIDTH-1:0] datab,
output [WIDTH-1:0] result
);
wire [WIDTH:0] temp_result;
assign temp_result = dataa - datab;
assign result = {temp_result[WIDTH], temp_result[WIDTH-2:0]};
endmodule
| 7.053686 |
module signed_to_20b_signed (
input [LENGTH-1:0] in,
output reg [19:0] out
);
parameter LENGTH = 10;
always @(in) begin
out[LENGTH-2:0] = in[LENGTH-2:0];
case (in[LENGTH-1])
1'b1: out[19:LENGTH-1] = -1;
1'b0: out[19:LENGTH-1] = 0;
endcase
end
endmodule
| 7.326232 |
module: signed_to_20b_signed
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module signed_to_20b_signed_test;
// Inputs
reg [9:0] in;
// Outputs
wire [19:0] out;
// Instantiate the... | 6.869805 |
module signed_to_abs #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] num,
output [WIDTH-1:0] abs_value,
output sign
);
assign sign = num[WIDTH-1];
assign abs_value = sign ? -num : num;
endmodule
| 7.03442 |
module signed_to_unsigned #(
WIDTH = 16
) (
input wire i_clk,
input wire i_valid,
input wire signed [WIDTH - 1 : 0] i_data,
output reg unsigned [WIDTH - 1 : 0] o_data,
output reg o_valid
);
always @(posedge i_clk) begin
o_data <= (i_valid ? i_data : o_data);
o_valid <= i_valid; //... | 8.617111 |
module signed_trunc (
idata,
odata
);
parameter IWIDTH = 16;
parameter OWIDTH = 8;
parameter IPRE = 4;
input [IWIDTH-1:0] idata;
output [OWIDTH-1:0] odata;
assign odata = idata[IWIDTH-IPRE-1:IWIDTH-IPRE-OWIDTH];
endmodule
| 7.379785 |
module SignEx (
input [15:0] A,
output reg [31:0] B
);
initial begin
B = 32'd0;
end
always @* begin
B = {16'd0, A};
end
endmodule
| 8.203663 |
module signex6 (
inp,
outp
);
input [`extend6size-1:0] inp;
output [`datasize-1:0] outp;
assign outp = {{10{inp[`extend6size-1]}}, inp};
endmodule
| 6.674197 |
module SignExpand (
input [15:0] data_16bit,
output reg [31:0] data_32bit
);
always @(data_16bit)
if (data_16bit[15] == 0) data_32bit = {16'b0000_0000_0000_0000, data_16bit};
else data_32bit = {16'b1111_1111_1111_1111, data_16bit};
endmodule
| 7.151199 |
module signext (
input [15:0] inst,
output [31:0] data
);
assign data = (inst[15]) ? {16'hffff, inst} : {16'h0000, inst};
endmodule
| 7.970829 |
module signext (
input wire [15:0] a,
output wire [31:0] y
);
assign y = {{16{a[15]}}, a};
endmodule
| 7.970829 |
module SignExt1 #(
parameter WIDTH = 32
) (
a,
y
);
input a;
output [WIDTH-1:0] y;
assign y = {0 + WIDTH{a}};
endmodule
| 8.376368 |
module signext16 (
in,
out
);
input [15:0] in;
output [31:0] out;
assign out[30] = in[15];
assign out[31] = in[15];
assign out[29] = in[15];
assign out[28] = in[15];
assign out[27] = in[15];
assign out[26] = in[15];
assign out[25] = in[15];
assign out[24] = in[15];
assig... | 7.934159 |
module signext16_32 (
sign_ext,
a16,
y32
); // 入出力ポート
input sign_ext; // 入力 1-bit
input [15:0] a16; // 入力 16-bit
output [31:0] y32; // 出力 32-bit
//Body
//符号拡張
assign y32 = (sign_ext == 1'b1) ?
{a16[15], a16[15], a16[15], a16[15],
a16[15], a16[15], a16[15], a16... | 8.214224 |
module signextend26 (
extendout,
in
);
input [25:0] in;
output [31:0] extendout;
reg [31:0] extendout;
always @(in)
if (in[25] == 1) extendout = {6'b111111, in};
else extendout = {6'b000000, in};
endmodule
| 6.549319 |
module signextended (
signextendedin,
signextendedout
);
input [31:0] signextendedin;
output reg [63:0] signextendedout;
always @(signextendedin) begin
if (signextendedin[31:26]==6'b000101) // B-type
begin
signextendedout[25:0] = signextendedin[25:0];
signext... | 6.910602 |
module SignExtender (
BusImm,
Imm32
);
output reg [63:0] BusImm;
input [31:0] Imm32;
reg extBit;
always @(*)
if ((Imm32[31:26] == `B) | (Imm32[31:26] == `BL)) begin
extBit = Imm32[25];
BusImm = {{38{extBit}}, Imm32[25:0]};
end else if ((Imm32[31:24] == `CBZ) | (Imm32[31:24] == `CBNZ... | 6.554609 |
module SignExtender_16to32 (
inputData,
outputData
);
input [15:0] inputData;
output [31:0] outputData;
reg [31:0] outputData;
always @(inputData) begin
outputData[15:0] = inputData[15:0];
outputData[31:16] = {16{inputData[15]}};
end
endmodule
| 7.250125 |
module Sign_Extender (
out,
in
);
input [15:0] in;
output [31:0] out;
assign out = {{16{in[15]}}, in};
endmodule
| 7.411001 |
module TBSignExtender;
reg [15:0] in;
wire [31:0] out;
Sign_Extender se (
out,
in
);
initial begin
$monitor($time, " :Input = %b,\t Output = %b.", in, out);
#0 in = 16'hF000;
#100 in = 16'h011;
#100 in = 16'h8310;
#100 in = 16'h9999;
#200 $finish;
end
endmodule
| 7.004811 |
module SignExtender_Example (
BusImm,
Imm16,
Ctrl
);
output [31:0] BusImm;
input [15:0] Imm16;
input Ctrl;
wire extBit;
assign extBit = (Ctrl ? 1'b0 : Imm16[15]);
assign BusImm = {{16{extBit}}, Imm16};
endmodule
| 7.250125 |
module signExtend (
in,
out
); //16 bit shift
input [15:0] in;
output [31:0] out;
assign out[31:16] = 1'b0;
assign out[15:0] = in[15:0];
endmodule
| 7.397526 |
module SignExtendTB ();
reg [15:0] unextended;
wire [31:0] extended;
SignExtend uut (
.unextended,
.extended
);
initial begin
#1 assign unextended = 16'b1000000000000000;
#1 assign unextended = 16'b0111111111111111;
end
endmodule
| 7.435243 |
module SignExtendTest ();
reg [15:0] OriginSignal;
wire [31:0] Data_out;
SignExtend dut (
.OriginSignal(OriginSignal),
.SignExtendOutput(Data_out)
);
initial begin
$dumpfile("memAddrMuxTest.vcd");
$dumpvars;
end
initial begin
OriginSignal = 16'b1001001001001001;
#5 OriginS... | 6.963307 |
module SignExtend_1_32 (
input wire LT,
output wire [31:0] SignExtendOutput
);
assign SignExtendOutput = {31'b0, LT};
endmodule
| 8.035313 |
module SignExtend_24 (
input [23:0] immediate_24,
output [31:0] immediate_32
);
reg [31:0] immediate_32 = 0;
always @* begin
immediate_32[31:0] <= {{8{immediate_24[23]}}, immediate_24[23:0]};
end
endmodule
| 8.107815 |
module signExtend_test;
reg i_sign;
reg [15:0] i_data;
wire [31:0] o_data;
signExtend signExtend (
.i_data(i_data),
.i_sign(i_sign),
.o_data(o_data)
);
initial begin
i_sign = 0;
i_data = 2;
#50 i_data = -1;
#50 i_data = -50;
i_sign = 1;
#50 i_data = -16;
#50... | 6.541404 |
module signExtend_testbench ();
reg [15:0] inp;
wire [31:0] result;
signExtend test (
inp,
result
);
initial begin
// MSB = 0
inp[0] = 0;
inp[1] = 1;
inp[2] = 1;
inp[3] = 1;
inp[4] = 0;
inp[5] = 0;
inp[6] = 0;
inp[7] = 0;
inp[8] = 0;
inp[9... | 6.541404 |
module: signExtend
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module signExtend_tf;
// Inputs
reg [15:0] in;
// Output
wire [31:0] out;
// Instantiate the Unit Under Test (UUT)
... | 6.52184 |
module SignExtension (
in,
out
);
/* A 16-Bit input word */
input [15:0] in;
/* A 32-Bit output word */
output reg [31:0] out;
always @(*) begin
if (in[15] == 1) begin
out <= {16'b1111111111111111, in};
end else begin
out <= {16'b0, in};
end
end
endmodule
| 6.562271 |
module SignExtensionJump (
in,
out
);
/* A 16-Bit input word */
input [25:0] in;
/* A 32-Bit output word */
output reg [31:0] out;
always @(*) begin
out <= {6'b0, in};
end
endmodule
| 6.562271 |
module SignExtensionUnit (
// input zeroCU,
input [25:0] instruction,
input [1:0] seuSignal, // 00 -> AluImmediate , 01 ->BranchAddres , 10 ->CondBranchAddres , 11 -> DtAddress
output reg [63:0] seuOutput
);
always @(instruction, seuSignal) begin
case (seuSignal)
2'b00: begin
seuOut... | 6.562271 |
module SignExtension_tb ();
wire [63:0] SignExtendOut;
SignExtension SE (
32'b11111000010000010000000000000111,
SignExtendOut
);
always @(*) begin
$monitor(SignExtendOut);
end
endmodule
| 6.562271 |
module SignExtEXC (
in,
out
);
input [7:0] in;
output [31:0] out;
assign out[31:8] = 24'd0;
assign out[7:0] = in;
endmodule
| 8.431621 |
module signextTest ();
wire [31:0] signextimm;
reg [15:0] immediate;
signextend dut (
.signextimm(signextimm),
.immediate (immediate)
);
initial begin
immediate = 16'b0111111111111111;
#1 if (signextimm != 32'b00000000000000000111111111111111) $display("Error");
end
endmodule
| 8.216256 |
module zerosignextend (
output [31:0] zerosignextimm,
input [15:0] immediate
);
reg [31:0] zerosignext;
reg [31:0] zerosignextimm;
always @* begin
zerosignext <= {16'b0};
zerosignextimm <= {zerosignext, immediate};
end
endmodule
| 8.993906 |
module SignExtImmediate (
in,
out
);
input [15:0] in;
output [31:0] out;
assign out[15:0] = in;
assign out[31:16] = (in[15]) ? 16'b1111111111111111 : 16'd0;
endmodule
| 7.433887 |
module SignextL (
Sclk,
sign_statusL,
signinL,
signoutL
);
input Sclk, sign_statusL;
input [15:0] signinL;
output reg [39:0] signoutL;
reg [39:0] padL;
always @(posedge Sclk) begin
if (sign_statusL == 1) begin
if (signinL[15] == 1) begin
padL = 40'hFF00000000;
pad... | 6.710501 |
module SignExtLT (
in,
out
);
input wire in;
output [31:0] out;
assign out[31:0] = {31'd0, in};
endmodule
| 6.823821 |
module SignextSigned8x8 (
input wire [35:0] gen,
input wire [ 3:0] sign,
output wire [11:0] pp00,
pp03,
output wire [12:0] pp01,
pp02
);
wire [3:0] e, ne;
assign e = ~{gen[35], gen[26], gen[17], gen[8]};
assign ne = ~e;
assign pp00 = {e[0], ne[0], ne[0], gen[8:0]};
assign pp01 = {... | 7.644284 |
module signextendTB;
reg [ 7:0] in;
wire [12:0] out;
signextend instance1 (
in[7:0],
out[12:0]
);
initial begin
$monitor($time, "In = %b and Out = %b", in[7:0], out[12:0]);
in[7:0] = 11100101;
#5;
in[7:0] = 00100111;
#5;
in[7:0] = 10100001;
#5;
end
endmodule
| 6.725884 |
module SignextUnsigned7x7 (
input wire [31:0] gen,
input wire [ 2:0] sign,
output wire [10:0] pp00,
output wire [11:0] pp01,
pp02,
output wire [ 9:0] pp03
);
wire [2:0] ns;
assign ns = ~sign;
assign pp00 = {ns[0], sign[0], sign[0], gen[7:0]};
assign pp01 = {1'b1, ns[1], gen[15:8],... | 7.677 |
module signExt_16T32 (
input [15:0] i,
output [31:0] o
);
assign o = i[15] ? {16'hFFFF, i[15:0]} : {16'h0000, i[15:0]};
endmodule
| 7.578335 |
module: signext_16
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module signext_16_test;
// Inputs
reg [15:0] in;
// Outputs
wire [31:0] out;
// Instantiate the Unit Under Test (U... | 6.658726 |
module.
////////////////////////////////////////////////////////////////////////////////
module SignExt_sim();
reg [15:0] in;
wire [31:0] out;
SignExt u0(
.in(in), .out(out)
);
initial begin
#100 in <= 16'h0004;
#20 $display("in=%h, out=%h", in, out);
#100 in <= 16'h70... | 6.641851 |
module signext_tb ();
reg [15:0] inst;
wire [31:0] data;
signext u0 (
inst,
data
);
initial begin
inst = 16'h0000;
#100 inst = 16'h0001;
#100 inst = 16'hffff;
#100 inst = 16'h0002;
#100 inst = 16'hfffe;
end
endmodule
| 6.707045 |
module signext_tb ();
reg [15 : 0] Inst;
wire [31 : 0] Data;
signext u0 (
.inst(Inst),
.data(Data)
);
initial begin
Inst = 0;
// 200 ns
#200;
Inst = 1;
// 400 ns
#200;
Inst = -1;
// 600 ns
#200;
Inst = 2;
// 800 ns
#200;
Inst = -2;
end
... | 6.707045 |
module significantout (
A,
B,
C
);
input [3:0] A, B;
output [7:0] C;
assign C = {A, ~B};
endmodule
| 7.602612 |
module signLogic (
aSign,
bSign,
cSign,
dSign,
expComp,
signIfComp,
sign,
op
);
input aSign, bSign, cSign, dSign, expComp, signIfComp, op;
output sign;
wire abSign, cdSign, abSignExpComp, abSignSignIfComp, nExpComp, nSignIfComp, nCdSign, oPBar;
wire abcdSign, cdSignNexpCompNsignI... | 6.612353 |
module signmag (
inp,
sign,
mag
);
input signed [7:0] inp;
output sign;
output reg signed [6:0] mag;
assign sign = inp[7];
always @(*) begin
if (sign == 0) mag = inp[6:0];
else if (sign == 1) mag = -(inp[6:0]);
end
endmodule
| 7.705219 |
module signext (
inst,
data
);
input [15:0] inst;
output [31:0] data;
assign data = (inst[15]) ? {16'hffff, inst} : {16'h0000, inst};
endmodule
| 7.970829 |
module signext (
input [15:0] a,
output [31:0] y
);
assign y = {{16{a[15]}}, a};
endmodule
| 7.970829 |
module SignOrZeroExtend (
input [15:0] in,
input ExtSel,
output [31:0] out
);
assign out[15:0] = in[15:0];
assign out[31:16] = (ExtSel && in[15]) ? 16'hFFFF : 16'h0000;
endmodule
| 7.660866 |
module SignToText (
red_ch,
green_ch,
blue_ch,
palm_height_test,
BACKGROUND_DIFFERENCE,
clk,
rst
);
/*
Top level module
INPUT:
red_ch - 8 bit, red component of image.
green_ch - 8 bit, green component of image.
blue_ch - 8 bit, blue component of image.
palm_hei... | 7.878199 |
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