code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module M_mul_cmp16_8__display_div_mc10 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FO... | 6.509797 |
module M_mul_cmp16_8__display_div_mc11 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FO... | 6.509797 |
module M_mul_cmp16_8__display_div_mc12 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FO... | 6.509797 |
module M_mul_cmp16_8__display_div_mc13 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FO... | 6.509797 |
module M_mul_cmp16_8__display_div_mc14 (
in_num,
in_den,
out_beq,
out_clock,
clock
);
input [15:0] in_num;
input [15:0] in_den;
output [0:0] out_beq;
output out_clock;
input clock;
assign out_clock = clock;
reg [16:0] _t_nk;
reg [ 0:0] _t_beq;
assign out_beq = _t_beq;
`ifdef FO... | 6.509797 |
module top (
`ifdef VGA
// VGA
output out_video_clock,
output reg [`COLOR_DEPTH-1:0] out_video_r,
output reg [`COLOR_DEPTH-1:0] out_video_g,
output reg [`COLOR_DEPTH-1:0] out_video_b,
output out_video_hs,
output out_video_v... | 6.934442 |
module sillyfunction (
a,
b,
c,
y
);
input wire a;
input wire b;
input wire c;
output wire y;
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule
| 7.469041 |
module silly_kernel (
input clk_i,
input [9:0] SW_i,
input reset,
output [6:0] HEX_1_o,
output [6:0] HEX_2_o
);
reg [31:0] instruction_addr;
wire [31:0] instruction;
reg [31:0] WD3;
wire [31:0] RD_1;
wire [31:0] RD_2;
wire [31:0] result;
wire comparsion_result;
... | 7.505051 |
module silly_kernel_tb ();
reg clk_i;
reg [9:0] SW_i;
reg reset;
wire [6:0] HEX_1_o;
wire [6:0] HEX_2_o;
silly_kernel krk (
clk_i,
SW_i,
reset,
HEX_1_o,
HEX_2_o
);
localparam CLK_FREQ_MHZ = 5; //100MHz
localparam CLK_SEMI = CLK_FREQ_MHZ / 2;
task si... | 7.104841 |
module cnn (
input [ 7:0] in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
in8,
input [17:0] w0,
w1,
w2,
w3,
w4,
w5,
w6,
w7,
w8,
output [18:0] result
);
wire [63:0] result01, result23, result45, result67, result8;
fixedDSP conv0_01 (
.ax({... | 6.745405 |
module compare #(
parameter BD = 18
) (
input clk,
reset,
input mpen,
wincnt,
input [BD-1:0] q0,
q1,
output reg [BD-1:0] d
);
always @(negedge clk) begin
if (reset) begin
d <= 0;
end else begin
if (mpen && !wincnt) begin
if (q0[BD-1] == 1'b0 && q1[BD-1] ==... | 7.271545 |
module alarm_clock ( input CLK, input [7:0] SW, input [3:0] BTN, output [7:0] LED, output [6:0] SEG,
// output DP, output [7:0] AN );
module sim1();
reg CLK;
reg [7:0] SW;
reg [3:0] BTN;
wire [7:0] LED;
wire [6:0] SEG;
wire DP;
wire [7:0] AN;
// Inistiantiate t... | 7.934292 |
module sim3 ();
reg clk = 0;
reg rst = 1;
reg [23:0] sw = 24'b0;
wire [23:0] led;
reg [4:0] bt = 5'b0;
wire [7:0] seg_out;
wire [7:0] seg_en;
Top test (
rst,
clk,
sw,
led,
bt,
seg_out,
seg_en
);
initial begin
#5000 rst = 0;
sw = 24'b0000_0000_0000_... | 7.13044 |
module \$_BUF_ (
A,
Y
);
input A;
output Y;
assign Y = A;
endmodule
| 7.144235 |
module \$_NOT_ (
A,
Y
);
input A;
output Y;
assign Y = ~A;
endmodule
| 6.984644 |
module \$_AND_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = A & B;
endmodule
| 7.391345 |
module \$_NAND_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = ~(A & B);
endmodule
| 7.696307 |
module \$_OR_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = A | B;
endmodule
| 7.534826 |
module \$_NOR_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = ~(A | B);
endmodule
| 7.432741 |
module \$_XOR_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = A ^ B;
endmodule
| 8.065982 |
module \$_XNOR_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = ~(A ^ B);
endmodule
| 7.480268 |
module \$_ANDNOT_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = A & (~B);
endmodule
| 7.550602 |
module \$_ORNOT_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = A | (~B);
endmodule
| 7.288639 |
module \$_MUX_ (
A,
B,
S,
Y
);
input A, B, S;
output Y;
assign Y = S ? B : A;
endmodule
| 7.162711 |
module \$_MUX4_ (
A,
B,
C,
D,
S,
T,
Y
);
input A, B, C, D, S, T;
output Y;
assign Y = T ? (S ? D : C) : (S ? B : A);
endmodule
| 7.189082 |
module \$_MUX8_ (
A,
B,
C,
D,
E,
F,
G,
H,
S,
T,
U,
Y
);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
assign Y = U ? T ? (S ? H : G) : (S ? F : E) : T ? (S ? D : C) : (S ? B : A);
endmodule
| 7.043596 |
module \$_MUX16_ (
A,
B,
C,
D,
E,
F,
G,
H,
I,
J,
K,
L,
M,
N,
O,
P,
S,
T,
U,
V,
Y
);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
output Y;
assign Y = V ? U ? T ? (S ? P : O) :
(S ? N : M... | 7.231216 |
module \$_AOI3_ (
A,
B,
C,
Y
);
input A, B, C;
output Y;
assign Y = ~((A & B) | C);
endmodule
| 7.882481 |
module \$_OAI3_ (
A,
B,
C,
Y
);
input A, B, C;
output Y;
assign Y = ~((A | B) & C);
endmodule
| 7.931676 |
module \$_AOI4_ (
A,
B,
C,
D,
Y
);
input A, B, C, D;
output Y;
assign Y = ~((A & B) | (C & D));
endmodule
| 8.28659 |
module \$_OAI4_ (
A,
B,
C,
D,
Y
);
input A, B, C, D;
output Y;
assign Y = ~((A | B) & (C | D));
endmodule
| 8.541444 |
module \$_SR_PN_ (
S,
R,
Q
);
input S, R;
output reg Q;
always @(posedge S, negedge R) begin
if (R == 0) Q <= 0;
else if (S == 1) Q <= 1;
end
endmodule
| 6.690407 |
module \$_DFF_N_ (
D,
C,
Q
);
input D, C;
output reg Q;
always @(negedge C) begin
Q <= D;
end
endmodule
| 7.090598 |
module \$_DFF_NN0_ (
D,
C,
R,
Q
);
input D, C, R;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0) Q <= 0;
else Q <= D;
end
endmodule
| 6.560896 |
module \$_DFF_PN0_ (
D,
C,
R,
Q
);
input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0) Q <= 0;
else Q <= D;
end
endmodule
| 6.500064 |
module \$_DFF_PN1_ (
D,
C,
R,
Q
);
input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0) Q <= 1;
else Q <= D;
end
endmodule
| 6.619954 |
module \$_DFFSR_NNN_ (
C,
S,
R,
D,
Q
);
input C, S, R, D;
output reg Q;
always @(negedge C, negedge S, negedge R) begin
if (R == 0) Q <= 0;
else if (S == 0) Q <= 1;
else Q <= D;
end
endmodule
| 6.671801 |
module \$_DFFSR_NNP_ (
C,
S,
R,
D,
Q
);
input C, S, R, D;
output reg Q;
always @(negedge C, negedge S, posedge R) begin
if (R == 1) Q <= 0;
else if (S == 0) Q <= 1;
else Q <= D;
end
endmodule
| 6.752491 |
module \$_DFFSR_NPN_ (
C,
S,
R,
D,
Q
);
input C, S, R, D;
output reg Q;
always @(negedge C, posedge S, negedge R) begin
if (R == 0) Q <= 0;
else if (S == 1) Q <= 1;
else Q <= D;
end
endmodule
| 6.797148 |
module \$_DFFSR_PNN_ (
C,
S,
R,
D,
Q
);
input C, S, R, D;
output reg Q;
always @(posedge C, negedge S, negedge R) begin
if (R == 0) Q <= 0;
else if (S == 0) Q <= 1;
else Q <= D;
end
endmodule
| 6.543661 |
module \$_DFFSR_PNP_ (
C,
S,
R,
D,
Q
);
input C, S, R, D;
output reg Q;
always @(posedge C, negedge S, posedge R) begin
if (R == 1) Q <= 0;
else if (S == 0) Q <= 1;
else Q <= D;
end
endmodule
| 6.56215 |
module \$_DFFSR_PPN_ (
C,
S,
R,
D,
Q
);
input C, S, R, D;
output reg Q;
always @(posedge C, posedge S, negedge R) begin
if (R == 0) Q <= 0;
else if (S == 1) Q <= 1;
else Q <= D;
end
endmodule
| 6.555277 |
module simClk ();
reg clk = 0;
reg [15:0] sw = 16'b0110000001111100;
reg [4:0] btns = 0;
wire jai;
wire [1:0] jao;
wire [7:0] jb;
wire [15:0] led;
wire [6:0] seg;
wire [3:0] an;
always begin
#5 clk = ~clk;
end
Top_Student ts (
clk,
jai,
btns,
sw,
jao,
jb,
... | 6.970065 |
module SIMD(mm, mm64, simd_op, out);
input [63:0] mm; //destination operand
input [63:0] mm64; //source operand
input [2:0] simd_op; //indicating SIMD op
output [63:0] out;
//paddw block, simd_op 000
wire dummy_carry;
assign dummy_carry = 0;
wire [63:0] paddw_out;
genvar i;
generate
for(i =... | 6.64703 |
module SIMDadd (
input [15:0] A,
input [15:0] B,
input H,
input O,
input Q,
input sub,
output [15:0] Cout
);
wire [15:0] B_real = sub ? (~B) : B;
wire [ 4:0] C0 = A[3:0] + B_real[3:0] + sub;
wire [ 4:0] C1 = A[7:4] + B_real[7:4] + (C0[4] & (O | H)) + (Q & sub);
wire [ 4:0] C2 = A[11:... | 6.772936 |
module SimDromajoCosimBlackBox #(
parameter COMMIT_WIDTH,
XLEN,
INST_BITS,
HARTID_LEN
) (
input clock,
input reset,
input [ (COMMIT_WIDTH) - 1:0] valid,
input [ (HARTID_LEN) - 1:0] hartid,
input [ (XLEN*COMMIT_WIDTH) - 1:0] pc,
input [(INST_BITS*COMMIT_WI... | 7.47245 |
module HA_95 (
I1,
I2,
sum,
carry
);
input I1, I2;
output sum, carry;
and2_1 U1 (
.a(I2),
.b(I1),
.x(carry)
);
exor2_1 U2 (
.a(I2),
.b(I1),
.x(sum)
);
endmodule
| 7.517754 |
module FA_2878 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.740422 |
module FA_2875 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_6 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.678424 |
module FA_2874 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.593232 |
module FA_2872 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.557306 |
module FA_2871 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.546707 |
module FA_2870 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.708511 |
module FA_2868 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 7.054684 |
module FA_2865 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_6 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.564725 |
module FA_2864 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.720365 |
module FA_2863 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_6 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.508394 |
module FA_2862 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.918269 |
module FA_2861 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.715454 |
module FA_2860 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.802152 |
module FA_2859 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.518918 |
module FA_2858 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.705765 |
module FA_2857 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.630532 |
module FA_2855 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_6 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.56047 |
module FA_2854 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.637625 |
module FA_2853 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.82911 |
module FA_2852 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 7.103398 |
module FA_2851 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.787289 |
module FA_2850 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.701329 |
module HA_94 (
I1,
I2,
sum,
carry
);
input I1, I2;
output sum, carry;
and2_1 U1 (
.a(I2),
.b(I1),
.x(carry)
);
exor2_1 U2 (
.a(I2),
.b(I1),
.x(sum)
);
endmodule
| 7.255806 |
module FA_2849 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.622107 |
module FA_2848 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.902588 |
module FA_2847 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_1 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.518992 |
module FA_2846 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.654988 |
module FA_2845 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.850718 |
module FA_2844 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.779937 |
module FA_2843 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.917063 |
module FA_2841 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.896809 |
module FA_2840 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.844885 |
module FA_2838 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.618845 |
module FA_2837 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.533556 |
module FA_2835 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_6 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.714675 |
module FA_2833 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.59644 |
module FA_2832 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_6 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.568599 |
module FA_2831 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.712797 |
module FA_2830 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.612315 |
module FA_2829 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.734243 |
module FA_2828 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.732498 |
module FA_2827 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.749672 |
module FA_2826 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.773083 |
module FA_2825 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.944247 |
module FA_2824 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.819374 |
module FA_2823 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.616141 |
module FA_2822 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.711216 |
module FA_2821 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.609009 |
module FA_2820 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.80135 |
module HA_93 (
I1,
I2,
sum,
carry
);
input I1, I2;
output sum, carry;
and2_1 U1 (
.a(I2),
.b(I1),
.x(carry)
);
exor2_1 U2 (
.a(I2),
.b(I1),
.x(sum)
);
endmodule
| 7.411343 |
module FA_2819 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.610454 |
module FA_2818 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.984543 |
module FA_2817 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.906423 |
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