code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module FA_2944 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.715579 |
module FA_2943 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.930002 |
module FA_2942 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.741412 |
module FA_2941 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.729832 |
module FA_2940 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.807766 |
module HA_97 (
I1,
I2,
sum,
carry
);
input I1, I2;
output sum, carry;
and2_1 U1 (
.a(I2),
.b(I1),
.x(carry)
);
exor2_1 U2 (
.a(I2),
.b(I1),
.x(sum)
);
endmodule
| 7.18614 |
module FA_2939 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.54318 |
module FA_2938 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.599581 |
module FA_2937 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.590486 |
module FA_2935 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.691588 |
module FA_2933 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.611597 |
module FA_2932 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_5 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.508939 |
module FA_2931 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.677594 |
module FA_2930 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.643462 |
module FA_2929 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_6 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.537939 |
module FA_2928 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.761561 |
module FA_2927 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.653441 |
module FA_2926 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_6 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.593312 |
module FA_2925 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_6 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.744954 |
module FA_2924 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.842691 |
module FA_2923 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.547005 |
module FA_2922 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_6 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.521214 |
module FA_2921 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.550302 |
module FA_2920 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.633839 |
module FA_2919 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.795286 |
module FA_2918 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.97852 |
module FA_2917 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.843978 |
module FA_2916 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.923664 |
module FA_2915 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.950231 |
module FA_2914 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.853583 |
module FA_2913 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.835951 |
module FA_2912 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.862833 |
module FA_2911 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.689865 |
module FA_2910 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.688745 |
module HA_96 (
I1,
I2,
sum,
carry
);
input I1, I2;
output sum, carry;
and2_1 U1 (
.a(I2),
.b(I1),
.x(carry)
);
exor2_1 U2 (
.a(I2),
.b(I1),
.x(sum)
);
endmodule
| 7.105052 |
module FA_2909 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_2 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_2 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.724686 |
module FA_2908 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.726445 |
module FA_2907 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.719814 |
module FA_2906 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.678258 |
module FA_2905 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.616399 |
module FA_2904 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.695775 |
module FA_2903 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.797722 |
module FA_2902 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
ao22_1 U2 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 7.100106 |
module FA_2901 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.640506 |
module FA_2900 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.526692 |
module FA_2897 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.58428 |
module FA_2896 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_6 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.556885 |
module FA_2895 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_6 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.586589 |
module FA_2894 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.544109 |
module FA_2893 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_1 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.731087 |
module FA_2892 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_3 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.839291 |
module FA_2889 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.572936 |
module FA_2887 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_1 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.593752 |
module FA_2884 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_1 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.621988 |
module FA_2883 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_1 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.564021 |
module FA_2882 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_1 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.603078 |
module FA_2881 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
ao22_2 U1 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(carry)
);
exor2_1 U2 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U3 (
.a(I3),
.b(n2),
.x(... | 6.583315 |
module FA_2880 (
I1,
I2,
I3,
sum,
carry
);
input I1, I2, I3;
output sum, carry;
wire n2;
exor2_1 U1 (
.a(I1),
.b(I2),
.x(n2)
);
exor2_1 U2 (
.a(I3),
.b(n2),
.x(sum)
);
ao22_1 U3 (
.a(I2),
.b(I1),
.c(n2),
.d(I3),
.x(ca... | 6.923466 |
module SimJTAG #(
parameter TICK_DELAY = 50
) (
input clock,
input reset,
input enable,
input init_done,
output jtag_TCK,
output jtag_TMS,
output jtag_TDI,
output jtag_TRSTn,
input jtag_TDO_data,
input jtag_TDO_driven,
output [31:0] exit
);
reg [31:0] tickCounter... | 7.133371 |
module \$add (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin : BLOCK1
assign Y = $si... | 7.120414 |
module BUF (
input in,
output out
);
assign out = in;
endmodule
| 7.602297 |
module TRIBUF (
input in,
enable,
output out
);
assign out = enable ? in : 1'bz;
endmodule
| 6.544954 |
module INV (
input in,
output out
);
assign out = ~in;
endmodule
| 7.585108 |
module AND2 #(
parameter SIZE = 2
) (
input [SIZE-1:0] in,
output out
);
assign out = ∈
endmodule
| 7.034115 |
module AND3 #(
parameter SIZE = 3
) (
input [SIZE-1:0] in,
output out
);
assign out = ∈
endmodule
| 6.890175 |
module AND4 #(
parameter SIZE = 4
) (
input [SIZE-1:0] in,
output out
);
assign out = ∈
endmodule
| 7.43112 |
module OR2 #(
parameter SIZE = 2
) (
input [SIZE-1:0] in,
output out
);
assign out = |in;
endmodule
| 7.203664 |
module OR3 #(
parameter SIZE = 3
) (
input [SIZE-1:0] in,
output out
);
assign out = |in;
endmodule
| 7.264237 |
module OR4 #(
parameter SIZE = 4
) (
input [SIZE-1:0] in,
output out
);
assign out = |in;
endmodule
| 7.526611 |
module NAND2 #(
parameter SIZE = 2
) (
input [SIZE-1:0] in,
output out
);
assign out = ~∈
endmodule
| 8.243676 |
module NAND3 #(
parameter SIZE = 3
) (
input [SIZE-1:0] in,
output out
);
assign out = ~∈
endmodule
| 7.814251 |
module NAND4 #(
parameter SIZE = 4
) (
input [SIZE-1:0] in,
output out
);
assign out = ~∈
endmodule
| 8.671625 |
module NOR2 #(
parameter SIZE = 2
) (
input [SIZE-1:0] in,
output out
);
assign out = ~|in;
endmodule
| 7.376253 |
module NOR3 #(
parameter SIZE = 3
) (
input [SIZE-1:0] in,
output out
);
assign out = ~|in;
endmodule
| 7.261208 |
module NOR4 #(
parameter SIZE = 4
) (
input [SIZE-1:0] in,
output out
);
assign out = ~|in;
endmodule
| 7.660701 |
module XOR2 #(
parameter SIZE = 2
) (
input [SIZE-1:0] in,
output out
);
assign out = ^in;
endmodule
| 6.988236 |
module XOR3 #(
parameter SIZE = 3
) (
input [SIZE-1:0] in,
output out
);
assign out = ^in;
endmodule
| 7.795481 |
module XOR4 #(
parameter SIZE = 4
) (
input [SIZE-1:0] in,
output out
);
assign out = ^in;
endmodule
| 7.572929 |
module XNOR2 #(
parameter SIZE = 2
) (
input [SIZE-1:0] in,
output out
);
assign out = ~^in;
endmodule
| 7.203002 |
module XNOR3 #(
parameter SIZE = 3
) (
input [SIZE-1:0] in,
output out
);
assign out = ~^in;
endmodule
| 6.786606 |
module XNOR4 #(
parameter SIZE = 4
) (
input [SIZE-1:0] in,
output out
);
assign out = ~^in;
endmodule
| 7.647948 |
module DEC1 (
input in,
enable,
output reg [1:0] out
);
always @(in or enable)
if (!enable) out = 2'b00;
else begin
case (in)
1'b0: out = 2'b01;
1'b1: out = 2'b10;
endcase
end
endmodule
| 6.586963 |
module DEC2 (
input [1:0] in,
input enable,
output reg [3:0] out
);
always @(in or enable)
if (!enable) out = 4'b0000;
else begin
case (in)
2'b00: out = 4'b0001;
2'b01: out = 4'b0010;
2'b10: out = 4'b0100;
2'b11: out = 4'b1000;
endcase
end
endmodule... | 6.98998 |
module DEC3 (
input [2:0] in,
input enable,
output reg [7:0] out
);
always @(in or enable)
if (!enable) out = 8'b00000000;
else begin
case (in)
3'b000: out = 8'b00000001;
3'b001: out = 8'b00000010;
3'b010: out = 8'b00000100;
3'b011: out = 8'b00001000;
... | 7.014998 |
module DEC4 (
input [3:0] in,
input enable,
output reg [15:0] out
);
always @(in or enable)
if (!enable) out = 16'b0000000000000000;
else begin
case (in)
4'b0000: out = 16'b0000000000000001;
4'b0001: out = 16'b0000000000000010;
4'b0010: out = 16'b0000000000000100;
... | 7.009009 |
module DEC5 (
input [4:0] in,
input enable,
output reg [31:0] out
);
always @(in or enable)
if (!enable) out = 32'b00000000000000000000000000000000;
else begin
case (in)
5'b00000: out = 32'b00000000000000000000000000000001;
5'b00001: out = 32'b0000000000000000000000000000001... | 6.929469 |
module MUX2 (
input [1:0] in,
input select,
output reg out
);
always @(in or select)
case (select)
0: out = in[0];
1: out = in[1];
endcase
endmodule
| 7.051899 |
module MUX4 (
input [3:0] in,
input [1:0] select,
output reg out
);
always @(in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule
| 6.65409 |
module ADD1 (
input in1,
in2,
cin,
output out,
cout
);
assign {cout, out} = in1 + in2 + cin;
endmodule
| 7.221959 |
module ADD2 #(
parameter SIZE = 2
) (
input [SIZE-1:0] in1,
in2,
input cin,
output [SIZE-1:0] out,
output cout
);
assign {cout, out} = in1 + in2 + cin;
endmodule
| 7.222422 |
module ADD4 #(
parameter SIZE = 4
) (
input [SIZE-1:0] in1,
in2,
input cin,
output [SIZE-1:0] out,
output cout
);
assign {cout, out} = in1 + in2 + cin;
endmodule
| 8.042391 |
module ADD8 #(
parameter SIZE = 8
) (
input [SIZE-1:0] in1,
in2,
input cin,
output [SIZE-1:0] out,
output cout
);
assign {cout, out} = in1 + in2 + cin;
endmodule
| 7.838307 |
module ADD16 #(
parameter SIZE = 16
) (
input [SIZE-1:0] in1,
in2,
input cin,
output [SIZE-1:0] out,
output cout
);
assign {cout, out} = in1 + in2 + cin;
endmodule
| 7.858131 |
module ADD32 #(
parameter SIZE = 32
) (
input [SIZE-1:0] in1,
in2,
input cin,
output [SIZE-1:0] out,
output cout
);
assign {cout, out} = in1 + in2 + cin;
endmodule
| 8.321464 |
module ADD64 #(
parameter SIZE = 64
) (
input [SIZE-1:0] in1,
in2,
input cin,
output [SIZE-1:0] out,
output cout
);
assign {cout, out} = in1 + in2 + cin;
endmodule
| 8.272771 |
module SUB1 (
input in1,
in2,
cin,
output out,
cout
);
assign {cout, out} = in1 - in2 - cin;
endmodule
| 6.938566 |
module SUB2 #(
parameter SIZE = 2
) (
input [SIZE-1:0] in1,
in2,
input cin,
output [SIZE-1:0] out,
output cout
);
assign {cout, out} = in1 - in2 - cin;
endmodule
| 6.573555 |
module SUB4 #(
parameter SIZE = 4
) (
input [SIZE-1:0] in1,
in2,
input cin,
output [SIZE-1:0] out,
output cout
);
assign {cout, out} = in1 - in2 - cin;
endmodule
| 7.238299 |
module SUB8 #(
parameter SIZE = 8
) (
input [SIZE-1:0] in1,
in2,
input cin,
output [SIZE-1:0] out,
output cout
);
assign {cout, out} = in1 - in2 - cin;
endmodule
| 7.402865 |
module SUB16 #(
parameter SIZE = 16
) (
input [SIZE-1:0] in1,
in2,
input cin,
output [SIZE-1:0] out,
output cout
);
assign {cout, out} = in1 - in2 - cin;
endmodule
| 6.881856 |
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