code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top_module (
input x,
input y,
output z
);
assign z = ~(x ^ y);
endmodule
| 7.203305 |
module xor2 (
X,
Y,
F
);
input X, Y;
output F;
reg F;
always @(X, Y) begin
F <= X ^ Y;
end
endmodule
| 7.002162 |
module SR_Latch (
set,
reset,
Q
);
input set, reset;
output Q;
wire set, reset;
wire Qprime, Q;
assign Q = !(reset | Qprime);
assign Qprime = !(set | Q);
/* always begin
#20 set<=0; reset<=0;
#20 set<=0; reset<=1;
#20 set<=1; reset<=0;
#20 set<=1; reset<=1;
end*/
endm... | 6.774545 |
module main();
reg A,B,C;
wire w1,w2,final;
and2 gate1(A,B,w1);
and2 gate2(A,C,w2);
xor2 gate3(w1,w2,final);
SR_Latch SR(A,B,final);
always begin
#20 A<=0; B<=0;
#20 A<=0; B<=1;
#20 A<=1; B<=0;
#20 A<=1; B<=1;
/* #20 A<=0; B<=0; C<=0;
#20 A<=0; B<=0; C<=1;
#20 A<=0; B<=1... | 6.710864 |
module SimpleCore (
clock,
reset,
dest,
curr,
level,
neg
);
input clock;
input reset;
input [7:0] dest, curr;
output reg [7:0] level;
output reg neg;
initial begin
level = 8'b0;
neg = 1'b0;
end
always @(negedge reset or posedge clock) begin
if (!reset) begin
... | 6.580444 |
module register (
i_clk,
wr_stb,
data,
result
);
input i_clk; // Do updates on rising i_clk
input wr_stb; // Update register if high
input [7:0] data; // Input data
output [7:0] result; // Output register value
reg [7:0] internal_value = 0; // Register's internal value
assign result = ... | 6.542519 |
module simplecpu (
i_clk
);
input i_clk; // System clock signal provided by testbench
// Internal wiring
wire [7:0] databus; // The data bus, connected to ROM, AR, IR, X
wire [7:0] addressbus; // The address bus, either PC or AR's value
wire [7:0] Memvalue; // Output of memory
wire [7:0] Xvalue; //... | 6.908909 |
module icarus_tb ();
reg i_clk;
// Initialise the clock, create the VCD file
initial begin
$dumpfile("test.vcd");
$dumpvars(0, icarus_tb);
i_clk = 0; // initial value of clk
#60 $finish; // Terminate simulation
end
// Clock generator
always begin
#1 i_clk = ~i_clk; // Toggle i_clk e... | 7.225195 |
module SimpleDataflowTest;
initial begin
$dumpfile("timing.vcd");
end
reg reset = 0;
reg clk = 0;
always #10 clk = ~clk;
SimpleDataflow ddf (
clk,
reset
);
initial begin
$dumpvars(0, ddf);
reset = 1;
#20 reset = 0;
// #3000000 $finish;
// Give components the c... | 7.274055 |
module SimpleDataMemory (
/* This is the 1K x 32 data memory for the Ethernet CPU. It
doesn't interact with the ring, but can be loaded from the
receive section of the design with the first 4 words of
the arriving Ethernet frame.
The transmit header is taken from an independent read port,
which means we need two... | 8.87571 |
module SimpleDspModule (
input clock,
input reset,
input [15:0] io_x,
input [15:0] io_y,
output [15:0] io_z
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg [16:0] _T_8; // @[Reg.scala 12:16]
reg [... | 7.451414 |
module SimpleDualPortRAM_generic (
clk,
enb,
wr_din,
wr_addr,
wr_en,
rd_addr,
rd_dout
);
parameter AddrWidth = 1;
parameter DataWidth = 1;
input clk;
input enb;
input [DataWidth - 1:0] wr_din; // parameterized width
input [AddrWidth - 1:0] wr_addr; // parameterized width
in... | 7.756659 |
module SimpleDualPortRAM_singlebit (
clk,
enb,
wr_din,
wr_addr,
wr_en,
rd_addr,
rd_dout
);
parameter AddrWidth = 1;
parameter DataWidth = 1;
input clk;
input enb;
input wr_din; // ufix1
input [AddrWidth - 1:0] wr_addr; // parameterized width
input wr_en; // ufix1
input [... | 7.756659 |
module, its ports, connections, and parameters.
*/ /*!\tikzmark{se_moduleheader}!*/
module SimpleExample (
// Declare our input and output ports
input A,
input B,
output wire Q
);
// Internal wire connection
wire A_n;
// Declare NOT gate primitive wit... | 7.956582 |
module simplefifo #(
parameter ELEMENTWIDTH = 8,
ELEMENTDEPTHBITS = 4
) (
input wire clk,
input wire reset,
input wire [ELEMENTWIDTH-1:0] DataWrite,
input wire WriteEnable,
output reg [ELEMENTWIDTH-1:0] DataRead,
input wire ReadEnable,
output reg Empty,
output reg Full
);
loca... | 6.706201 |
module SimpleFSM (
input clock,
input reset,
input io_din,
output io_risingEdge
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg stateReg; // @[SimpleFSM.scala 14:28]
wire _GEN_0 = io_din | stateReg; // @[SimpleFSM.scala 20:26 21:26 14:28]
assign io_rising... | 6.836455 |
module simplehamm_tb;
// Inputs
reg [15:0] m;
// Outputs
wire [20:0] e;
initial #500 $finish;
// Instantiate the Unit Under Test (UUT)
simplehamm uut (
.m(m),
.e(e)
);
initial begin
// Initialize Inputs
m = 16'b1111111111111111;
end
// Add stimulus here
endmodule
| 8.060134 |
module simplei2c (
input clk,
input clk_i2c_en,
input reset,
output req_next,
input start,
input restart,
input stop,
input mode_rw,
input ack_sda,
input [7:0] data_write,
output [7:0] data_read,
input i2c_sda_in,
output i2c_sda_out,
output i2c_sda_oen,
... | 6.532808 |
module simplei2c_wrapper (
input clk,
input reset_n,
output [7:0] data_out,
input [7:0] data_in,
input cs_n,
input rd_n,
input wr_n,
input [2:0] addr,
input i2c_sda_in,
output i2c_sda_out,
output i2c_sda_oen,
output i2c_scl_out
);
wire read_sel = !cs_n & !rd_n & wr_n;
... | 6.776195 |
module SimpleInitiator (
start,
clk,
REQ,
GNT,
FRAME,
IRDY,
I_AM_OWNER,
GLOBAL_IRDY,
GLOBAL_FRAME
);
input wire clk, GNT, start;
input wire GLOBAL_IRDY, GLOBAL_FRAME;
output reg REQ = 1, FRAME = 1, I_AM_OWNER = 0, IRDY = 1;
integer counter = 0;
wire IDLE;
assign IDLE =... | 6.543504 |
module simpleinterp #(
// {{{
parameter INW = 28, // Input width
CTRBITS = 32 // Bits in our counter
// }}}
) (
// {{{
input wire i_clk,
input wire i_ce,
input wire [(INW-1):0] i_data,
input wire [(CTRBITS-1):0] i_step,
output reg o_ce,
output wire [(INW-1):0] o_data
//... | 7.000392 |
module simpleio (
input clk,
input reset_n,
output [7:0] data_out,
input [7:0] data_in,
input cs_n,
input rd_n,
input wr_n,
input [1:0] addr,
output [7:0] P1_out,
input [7:0] P1_in,
output P1_oen,
output [7:0] P2_out,
input [7:0] P2_in,
output P2_oen
);
`define ... | 6.963447 |
module SimpleMacFifo (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] read_addr,
write_addr,
input we,
read_clock,
write_clock,
output reg [(DATA_WIDTH-1):0] q = 0
);
parameter DATA_WIDTH = 10;
parameter ADDR_WIDTH = 12;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram... | 8.089855 |
module mapram (
wclk,
wr,
wa,
i,
rclk,
ra0,
ra1,
ra2,
o0,
o1,
o2
);
input wclk;
input wr;
input [13:0] wa;
input [9:0] i;
input rclk;
input [13:0] ra0;
input [13:0] ra1;
input [13:0] ra2;
output [9:0] o0;
output [9:0] o1;
output [9:0] o2;
reg [9:0] ma... | 7.918203 |
module simpleMux (
A,
B,
mux_control,
mux_out
);
input A; /* Input Signals and Mux Control */
input B;
input mux_control;
output mux_out;
reg mux_out;
always @(A or B or mux_control)
case (mux_control)
0: mux_out = A;
1: mux_out = B;
default: mux_out = A;
endcase... | 7.969926 |
module simplemux_tb;
reg a_i;
reg b_i;
reg sel_i;
wire y_o;
simplemux DUT (
a_i,
b_i,
sel_i,
y_o
);
initial begin
a_i = 0;
b_i = 0;
sel_i = 0;
#300 $finish;
end
always #75 sel_i = ~sel_i;
always #10 a_i = ~a_i;
always #55 b_i = ~b_i;
initial be... | 7.353852 |
module simplenet_tb;
reg [1:0]x;
reg clk;
reg signed [3:0] w0;
reg signed [3:0] w1;
reg signed [3:0] w2;
reg signed [3:0] w3;
reg signed [3:0] w4;
reg signed [3:0] w5;
reg signed [3:0] w6;
reg signed [3:0] w7;
reg signed [3:0] w8;
wire signed [3:0] tVal;
wire signed [3"0] holder
wire y;
... | 6.838505 |
module SimplePodModel (
input wire [31:0] accel,
input wire running,
input wire clk_100khz,
input wire clk_1khz,
input wire clk_50Mhz,
output reg [63:0] position = 64'd15240000000, //Starts at 50 '
output reg [31:0] velocity = 0
);
wire [31:0] posStep;
//Could redo the core with more... | 6.925887 |
module SimpleProcessor_tb ();
// inputs
reg clock, ctrl_reset;
// outputs
wire imem_clock, dmem_clock, processor_clock, regfile_clock;
wire [31:0] data_readRegA, data_readRegB, q_dmem, q_imem;
wire [4:0] ctrl_writeReg, ctrl_readRegA, ctrl_readRegB;
wire [31:0] data_writeReg;
wire ctrl_writeEnable;
/... | 6.631059 |
module simpleRAM (
address,
data,
rw,
clock,
reset
);
inout [7:0] data; // in-out
input [2:0] address;
input rw;
input clock;
input reset;
// Does not support dual-port RAM logic!
// reg [7:0] RAM [2:0];
// Must have individual bytes & case
// statements :( <-- sad face
reg ... | 7.054935 |
module simpleRAM ( read-data, read-address, write-data, write-address,
memwrite, clock, reset);
// 3-bit addressable locations of 8 bit r/w memory
output [7:0] read-data;
input [2:0] read-address;
input [7:0] write-data;
input [2:0] write-address;
input memwrite;
input clock;
input reset;
reg [7:0] read-... | 9.132449 |
module SimpleRamTest;
`include "Framework.v"
reg reset;
reg clk;
reg [7:0] addrA;
reg [7:0] dataIn;
reg writeEnable;
reg [7:0] addrB;
wire [7:0] outA;
wire [7:0] outB;
wire busyA;
wire busyB;
SimpleRam ram (
clk,
reset,
addrA,
dataIn,
writeEnable,
addrB,
... | 6.873212 |
module SimpleRAM_Testbench #(
parameter ADDRW = 32,
parameter DATAW = 32,
parameter DEPTH = 2 ** 14
) ();
reg CLK = 1'b0; // 时钟输入
reg RST = 1'b1; // 复位输入
reg WEN = 1'b0; // 写入使能
reg CEN = 1'b1; /... | 8.356502 |
module has synchronous reset which clears the
-- output of the system, while reset is low input data
-- is transferred to the output register Q.
-- Designer: Tuna Biçim
-----------------------------------------------------*/
module simpleReg(Clock, Reset, Data, Q);
parameter W = 16;
input Clo... | 8.061632 |
module simpleRegister (
dataIn,
clock,
enable,
reset,
dataOut
);
input [1:0] dataIn;
input clock;
input enable;
input reset;
output [1:0] dataOut;
reg [1:0] dataOut;
always @(posedge clock or posedge reset)
if (reset) dataOut = 2'b00;
else if (enable) dataOut = dataIn;
endmo... | 6.584949 |
module contains a preconfigured ROM with some startup procedures
*/
module SimpleRom
#(parameter BUS_WIDTH = 8,
parameter SELECT_WIDTH = 32,
parameter SIZE = 128) // Size in byte
(
input wire clk,
input wire [SELECT_WIDTH-1:0] select,
input wire [SELECT_WIDTH-1:0] selectA,
output reg [BUS_WIDTH-1:... | 8.856291 |
module SimpleRomTest;
`include "Framework.v"
reg reset;
reg clk;
wire [7:0] dataOut;
wire [7:0] dataOutA;
reg [31:0] address;
reg [31:0] addressA;
SimpleRom rom (
clk,
address,
addressA,
dataOut,
dataOutA
);
always #10 clk = ~clk;
integer i;
initial begin
... | 6.656328 |
module simpler_ram (
clk_i,
wr_i,
addr_i,
data_i,
data_o
);
// Inputs:
// clk_i: Data is read/written on the rising edge of this clock input.
// wr_i: When high, data is written to the RAM; when low, data is read from the RAM.
// addr_i: Address bus for selecting which RAM location ... | 7.476565 |
module simplespi (
input clk,
input clk_spi_en,
input reset,
output req_next,
input start,
input finish,
input CPOL,
input CPHA,
input [7:0] data_write,
output [7:0] data_read,
output sclk,
output mosi,
input miso,
output cs
);
localparam STATE_IDLE = 0;... | 6.845331 |
module top_module (
input in,
input [1:0] state,
output [1:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
always @(*) begin
case (state)
A: next_state = (in == 0) ? A : B;
B: next_state = (in == 0) ? C : B;
C: next_state = (in == 0) ? A : D;
D: ne... | 7.203305 |
module simplest_gray #(
parameter gw = 4
) (
input clk,
output [gw-1:0] gray
);
reg [gw-1:0] gray1 = 0;
// The following three expressions compute the next Gray code based on
// the current Gray code. Vivado 2016.1, at least, is capable of
// reducing them to the desired four LUTs when gw==4.
/... | 7.069233 |
module FIFO #(
parameter WIDTH = 8
) (
input wire clk,
input wire reset,
input wire [(WIDTH - 1):0] dataIn,
input wire dataInWrite,
output wire [(WIDTH - 1):0] dataOut,
input wire dataOutRead,
output wire ... | 7.540168 |
module SimpleTff (
notQ,
clk,
reset,
Q
);
input notQ, clk, reset;
output Q;
reg Q;
always @(negedge reset or posedge clk) begin
if (!reset) Q <= 1'b0;
else Q <= notQ;
end
endmodule
| 6.780324 |
module simpleUARTtx (
input [7:0] data, // byte to transmit
input start, // set to one to start TX
input clk, // baud clock signal
output busy, // is 1 while sending
output line // serial data output
);
reg [ 3:0] counter = 0;
reg [11:0] shiftreg = 12'b1111... | 7.413782 |
module simpleuart_fifo_wb #(
parameter BASE_ADR = 32'h2000_0000,
parameter CLK_DIV = 8'h00,
parameter DATA = 8'h04,
parameter CONFIG = 8'h08
) (
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_adr_i, // (verify): input address was originaly 22 bits , why ? (max number of words ?)
i... | 7.050979 |
module simpleuart_wrapper (
input clk,
input reset_n,
output [7:0] data_out,
input [7:0] data_in,
input cs_n,
input rd_n,
input wr_n,
input [2:0] addr,
output tx,
input rx
);
wire read_sel = !cs_n & !rd_n & wr_n;
wire write_sel = !cs_n & rd_n & !wr_n;
reg [7:0] reg_status... | 6.75075 |
module SimpleVga #(
parameter CLK_PER_NS = 40
) (
input clk_i,
// input rst_i,
// VGA output
output red_o,
output green_o,
output blue_o,
output vsync_o,
output hsync_o
);
/* autogenerate reset */
reg reset;
rst_gen rst_inst (
.clk_i(clk_i),
.rst_i(1'b0),
... | 6.632404 |
module simplez_main (
input wire clk, //-- Reloj del sistema
input wire dtr, //-- Señal DTR del PC
input wire sw2, //-- Pulsador 2
output wire [7:0] leds, //-- leds
output wire stop, //-- Indicador de stop
output wire tx, //-- Salida serie para la pant... | 7.841924 |
module simplez_tb ();
//-- Programa en codigo maquina a cargar en la rom
parameter ROMFILE = "prog.list";
//-- Para la simulacion se usa un WAIT_DELAY de 3 ciclos de reloj
parameter WAIT_DELAY = 20;
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Datos de salida del componente
wire [7... | 7.042029 |
module simple_8_bit_register_behavioral (
input [7:0] data_in, // Data to load
input clk, // Clock
input ld_bar, // Load
input clr_bar, // Clear
output reg [7:0] data_out // Output Data
);
// 8-BIT REGISTER
// ALWAYS BLOCK with NON-BLOCKING PROCED... | 7.269997 |
module SIMPLE_8_BIT_REGISTER_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg [7:0] DATA_IN;
reg CLK;
reg LD_BAR;
reg CLR_BAR;
wire [7:0] DATA_OUT;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg [7:0] DATA_OUTEXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;... | 8.016851 |
module simple_add (
input [7:0] a,
input [7:0] b,
output signed [7:0] h
);
wire signed [7:0] as = a;
wire signed [7:0] bs = b;
wire [7:0] f = as + bs;
assign h = as + bs - as;
endmodule
| 6.857145 |
module
*/
module simple_arbiter #
(
parameter PORTS = 4,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 0
)
(
input wire clk,
input wire rst,
input wire [PORTS-... | 7.164597 |
module Simple_AXI_RAM #(
parameter NUM_SLOTS = 6,
parameter DATA_WIDTH_BYTES = 4
) (
clk,
rst,
ARVALID,
ARREADY,
ARADDR,
ARPROT,
RVALID,
RREADY,
RDATA,
RRESP,
AWVALID,
AWREADY,
AWADDR,
AWPROT,
WVALID,
WREADY,
WDATA,
WSTRB,
BVALID,
B... | 7.200149 |
module simple_biclk_bidir_ram #(
parameter width = 1,
parameter widthad = 1
) (
input clk,
input [widthad-1:0] address_a,
input wren_a,
input [ width-1:0] data_a,
output reg [ width-1:0] q_a,
input clk2,
input [widthad-1:0] a... | 7.005157 |
module simple_bidir_ram (
input clk,
input [widthad-1:0] address_a,
input wren_a,
input [ width-1:0] data_a,
output reg [ width-1:0] q_a,
input [widthad-1:0] address_b,
output reg [ width-1:0] q_b
);
parameter width = 1;
parameter widthad = 1;
re... | 7.104087 |
module simple_calc (
input [3:0] SW_X,
SW_Y,
input [1:0] SW_op_sel,
output [7:0] LED_output_result,
output LED_carry_out,
LED_overflow
);
wire [7:0] g0, g1; // Wires to connect to MUX from adder/subtractor and multplier
wire [3:0] g2;
assign g0 = {4'b0, g2}; // Converts 4 bit adder/su... | 6.677337 |
module simple_calculator (
Clk,
WEN,
RW,
RX,
RY,
DataIn,
Sel,
Ctrl,
busY,
Carry
);
input Clk;
input WEN;
input [2:0] RW, RX, RY;
input [7:0] DataIn;
input Sel;
input [3:0] Ctrl;
output [7:0] busY;
output Carry;
reg [7:0] alu_x;
wire [7:0] busX;
wire [7:0] ... | 6.979243 |
module ex_circuit (
A,
B,
C,
f
);
input A, B, C;
output f;
wire ap, bp, cp, o1, o2, o3, o4;
not a_not (ap, A);
not b_not (bp, B);
not c_not (cp, C);
and output_1 (o1, ap, bp, cp);
and output_2 (o2, ap, B, C);
and output_3 (o3, A, bp, C);
and output_4 (o4, A, B, cp);
or result (f, o... | 8.368697 |
module: ex_circuit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module simple_chip_master_tb;
// Inputs
reg A;
reg B;
reg C;
// Outputs
wire f;
// Instantiate the Unit Under Te... | 7.316492 |
module simple_cic (
clk,
reset,
g_in,
g_out,
d_in,
d_out
);
parameter in_width = 16;
parameter out_width = 18;
parameter cic_n = 4;
input clk;
input reset;
input g_in;
output g_out;
input signed [in_width-1:0] d_in;
output signed [out_width-1:0] d_out;
reg [out_width+1-in_w... | 6.641177 |
module simple_clkout #(
) (
input EU_BUTTON1,
output wire EU_AU_1, //Output wire for audio on europa
input wire EU_A1, //Analog in for measurement, VREF is hardware implied
output wire EU_REF_CLK //CLK for ramp output
// output wire digital_out
);
wire clk;
wire lf_osc;
wire... | 7.964925 |
module simple_comparator #(
) (
input EU_BUTTON0, //Simple button input
input EU_BUTTON1, //Second button
output EU_AU_0, //Audio output
input EU_A0, //Analog input
output EU_REF_CLK //External output for clk to generate ramp
);
wire lf_osc;
wire hf_osc;
wire trigger;
reg COMP_TRIGG... | 7.870277 |
module simple_comparator #(
) (
// outputs
output wire led_red, // Red
output wire led_blue, // Blue
output wire led_green, // Green
input EU_BUTTON0, //Simple button input
input EU_BUTTON1, //Second button
output EU_AU_0, //Audio output
input EU_A0, //Analog input
output EU... | 7.870277 |
module simple_comp_tb ();
reg clock, rst;
reg [15:0] a_in, b_in, c_in;
wire [15:0] d_out;
wire rdy;
initial begin
$display($time, " << Starting the Simulation >>");
a_in = 16'h0;
b_in = 16'h0;
c_in = 16'b0;
wait (rdy == 1'b1) begin
a_in = 16'h0;
b_in = 16'h0;
c_in = 1... | 7.409776 |
module simple_comp_tb ();
reg clock, rst;
reg [15:0] a_in, b_in, c_in;
wire [15:0] d_out;
initial begin
$display($time, " << Starting the Simulation >>");
a_in = 16'h0;
b_in = 16'h0;
c_in = 16'b0;
#30 a_in = 16'hfff;
b_in = 16'hfff;
c_in = 16'hfff;
#20 a_in = 16'h0;
b_in... | 7.409776 |
module simple_counter (
CLOCK_50,
counter_out
);
input CLOCK_50;
output [31:0] counter_out;
reg [31:0] counter_out;
always @ (posedge CLOCK_50) // on positive clock edge
begin
counter_out <= #1 counter_out + 1; // increment counter
end
endmodule
| 7.044904 |
module simple_counter_tb;
localparam W = 8;
reg clk;
reg rst_n;
wire [W-1:0] cnt;
simple_counter #(
.WIDTH(W)
) cnt1 (
// Outputs
.cnt (cnt),
// Inputs
.clk (clk),
.rst_n(rst_n)
);
//Clock generation
initial begin
clk = 0;
forever #1... | 7.044904 |
module simple_ds #(
parameter width = 8
) (
input [width-1:0] din,
input clk,
output bit_out
);
reg [width + 1 : 0] accumulator;
wire [width + 1 : 0] delta;
wire [width - 1 : 0] ddc;
assign ddc = bit_out ? {(width) {1'b1}} : {(width) {1'b0}};
assign delta = din - ddc;
always @(posedge... | 7.75571 |
module simple_debayer (
input wire clock,
input wire input_hsync,
input wire input_vsync,
input wire input_den,
input wire input_line_start,
input wire input_odd_line,
input wire [19:0] input_data,
input wire [19:0] input_prev_line_data,
output reg output_hsync,
output reg outpu... | 6.929013 |
module simple_design (
clk,
reset_,
a,
b,
c,
d,
z0,
z1
);
input clk;
input reset_;
input [7:0] a;
input [7:0] b;
input [2:0] c;
input [5:0] d;
output [7:0] z0;
output [7:0] z1;
always @(posedge clk, negedge reset_)
if (!reset_) begin
z0 <= 0;
z1 <= 0;... | 7.140153 |
module simple_dpram_sclk #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter ENABLE_BYPASS = 1
) (
input clk,
input [ADDR_WIDTH-1:0] raddr,
input re,
input [ADDR_WIDTH-1:0] waddr,
input we,
input [DATA_WIDTH-1:0]... | 7.845345 |
module simple_dp_bram #(
parameter RAM_WIDTH = 32,
parameter L2_RAM_DEPTH = 10
) (
input clka,
input wea,
input [L2_RAM_DEPTH-1:0] addra,
input [ RAM_WIDTH-1:0] dina,
input clkb,
input enb,
input ... | 7.993855 |
module simple_dual_dram (
input clka,
input rst_n,
input ena,
input [ 3:0] wea,
input [ 5:0] addra,
input [31:0] dina,
input clkb,
input [ 5:0] addrb,
output [31:0] doutb
);
reg [31:0] TAG[`SetNum-1:0];
reg [`SetNum-1:0] valid;
wire [31:0] ... | 8.584355 |
module simple_dual_port (
clk,
wr_en,
read_address,
write_address,
read_data,
write_data
);
parameter address_width = 9; //9 bits long address bus
parameter word_length = 40; //40 bits long word
input clk; //clock
input wr_en; //write enable
input [(address_width - 1):0] read_addre... | 8.990829 |
module simple_dual_port_BlockRAM (
clk,
wr_en,
d,
addr_a,
addr_b,
q_a,
q_b
);
parameter WIDTH = 64;
parameter ADDR_WIDTH = 8;
parameter DEPTH = 1 << ADDR_WIDTH;
input clk;
input wr_en;
input [WIDTH-1:0] d;
input [ADDR_WIDTH-1:0] addr_a;
input [ADDR_WIDTH-1:0] addr_b;
output... | 8.990829 |
module simple_dual_port_framebuffer #(
parameter DATA_WIDTH = 1,
parameter ADDR_WIDTH = 19
) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] read_addr,
write_addr,
input we,
read_clock,
write_clock,
output reg [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DA... | 8.990829 |
module : simple_dual_port_ram
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* i... | 8.864734 |
module simple_dual_port_ram_dual_clock #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 6
) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] read_addr,
write_addr,
input we,
re,
clk,
rst,
output reg [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WI... | 8.990829 |
module simple_dual_port_ram_single_clock (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] read_addr,
write_addr,
input we,
clk,
output reg [(DATA_WIDTH-1):0] q
);
parameter DATA_WIDTH = 1;
parameter ADDR_WIDTH = 13;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_... | 8.990829 |
module is a simple dual port RAM. This RAM is implemented in such a
way that Xilinx's tools will recognize it as a RAM and implement large
instances in block RAM instead of flip-flops.
The parameter SIZE is used to specify the word size. That is the size of
each entry in the RAM.
The parameter D... | 9.489103 |
module is a simple dual port RAM. This RAM is implemented in such a
way that Xilinx's tools will recognize it as a RAM and implement large
instances in block RAM instead of flip-flops.
The parameter SIZE is used to specify the word size. That is the size of
each entry in the RAM.
The parameter D... | 9.489103 |
module is a simple dual port RAM. This RAM is implemented in such a
way that Xilinx's tools will recognize it as a RAM and implement large
instances in block RAM instead of flip-flops.
The parameter SIZE is used to specify the word size. That is the size of
each entry in the RAM.
The parameter D... | 9.489103 |
module is a simple dual port RAM. This RAM is implemented in such a
way that Xilinx's tools will recognize it as a RAM and implement large
instances in block RAM instead of flip-flops.
The parameter SIZE is used to specify the word size. That is the size of
each entry in the RAM.
The parameter D... | 9.489103 |
module main (
clk,
counter
);
input clk;
output counter;
wire [31:0] looper;
wire out_wire;
adder add (
.left (looper),
.right(4),
.res (out_wire)
);
assign counter = out_wire;
endmodule
| 7.779865 |
module adder (
left,
right,
res
);
input left, right;
output res;
assign res = left + right;
endmodule
| 6.541942 |
module simple_fifo #(
parameter width = 1,
parameter widthu = 1
) (
input clk,
input rst_n,
input sclr,
input rdreq,
input wrreq,
input [width-1:0] data,
output empty,
output reg full,
output [ width-1:0] q,
out... | 7.282468 |
module simple_fifo_mlab
#(
parameter width = 1,
parameter widthu = 1
)
(
input clk,
input rst_n,
input sclr,
input rdreq,
input wrreq,
input [width-1:0] data,... | 6.641328 |
module counter1 #(
parameter N = 6
) (
clock,
rst,
count
);
input clock;
input rst;
output reg [N-1:0] count;
always @(posedge clock, posedge rst)
if (rst) count <= 10'h0;
else count <= count + 10'h1;
endmodule
| 6.761208 |
module simple_flop (
input c,
input d,
output reg q
);
always @(posedge c) q <= d;
endmodule
| 7.325014 |
module simple_fsm (
input wire sys_clk, //系统时钟50MHz
input wire sys_rst_n, //全局复位
input wire pi_money, //投币方式可以为：不投币（0）、投1元（1）
output reg po_cola //po_cola为1时出可乐，po_cola为0时不出可乐
);
//********************************************************************//
//****************** Parameter and Inte... | 8.56957 |
module simple_function ();
function myfunction;
input a, b, c, d;
begin
myfunction = ((a + b) + (c - d));
end
endfunction
endmodule
| 6.540619 |
module simple_gate (
inout clk, // unused
input a,
input b,
output out
);
assign out = a ^ b;
endmodule
| 6.633461 |
module simple_gemac (
input clk125,
input reset,
// GMII
output GMII_GTX_CLK,
output GMII_TX_EN,
output GMII_TX_ER,
output [7:0] GMII_TXD,
input GMII_RX_CLK,
input GMII_RX_DV,
input GMII_RX_ER,
input [7:0] GMII_RXD,
// Flow Control Interface
input pause_req,
inpu... | 7.287357 |
module wb_reg #(
parameter ADDR = 0,
parameter DEFAULT = 0,
parameter WIDTH = 32
) (
input clk,
input rst,
input [5:0] adr,
input wr_acc,
input [31:0] dat_i,
output reg [WIDTH-1:0] dat_o
);
always @(posedge clk)
if (rst) dat_o <= DEFAULT;
else if (wr_acc & (adr == ADDR)) d... | 8.4043 |
module inc (
in,
out
);
input [7:0] in;
output [7:0] out;
assign out = in + 1;
endmodule
| 7.003463 |
module simple_gpio (
clk_i,
rst_i,
cyc_i,
stb_i,
adr_i,
we_i,
dat_i,
dat_o,
ack_o,
gpio
);
//
// Inputs & outputs
//
parameter io = 8; // number of GPIOs
// 8bit WISHBONE bus slave interface
input clk_i; // clock
input rst_i; // reset (asynchronous active low)
... | 7.792637 |
module leaf1 (
input [15:0] x,
output [15:0] y
);
assign y = (x == 16'h0) ? x : 16'h3;
endmodule
| 6.522702 |
module leaf2 (
input [15:0] x,
input [15:0] y,
output [15:0] sum
);
wire [15:0] wy;
leaf1 sub_l1 (
.x(x),
.y(wy)
);
assign sum = x + y + wy;
endmodule
| 6.522383 |
module simple_i2c_core #(
//settings register base address
parameter BASE = 0,
//i2c line level at reset
parameter ARST_LVL = 1
) (
//clock and synchronous reset
input clock,
input reset,
//32-bit settings bus inputs
input set_stb,
input [7:0] set_addr,
input [31:0] set_dat... | 9.003686 |
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