code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SUB32 #(
parameter SIZE = 32
) (
input [SIZE-1:0] in1,
in2,
input cin,
output [SIZE-1:0] out,
output cout
);
assign {cout, out} = in1 - in2 - cin;
endmodule
| 7.115856 |
module SUB64 #(
parameter SIZE = 64
) (
input [SIZE-1:0] in1,
in2,
input cin,
output [SIZE-1:0] out,
output cout
);
assign {cout, out} = in1 - in2 - cin;
endmodule
| 7.404895 |
module MUL1 #(
parameter SIZE = 1
) (
input in1,
in2,
output [2*SIZE-1:0] out
);
assign out = in1 * in2;
endmodule
| 6.532903 |
module MUL2 #(
parameter SIZE = 2
) (
input [ SIZE-1:0] in1,
in2,
output [2*SIZE-1:0] out
);
assign out = in1 * in2;
endmodule
| 6.767446 |
module MUL4 #(
parameter SIZE = 4
) (
input [ SIZE-1:0] in1,
in2,
output [2*SIZE-1:0] out
);
assign out = in1 * in2;
endmodule
| 7.212139 |
module MUL8 #(
parameter SIZE = 8
) (
input [ SIZE-1:0] in1,
in2,
output [2*SIZE-1:0] out
);
assign out = in1 * in2;
endmodule
| 7.673058 |
module MUL16 #(
parameter SIZE = 16
) (
input [ SIZE-1:0] in1,
in2,
output [2*SIZE-1:0] out
);
assign out = in1 * in2;
endmodule
| 7.752848 |
module MUL32 #(
parameter SIZE = 32
) (
input [ SIZE-1:0] in1,
in2,
output [2*SIZE-1:0] out
);
assign out = in1 * in2;
endmodule
| 7.676746 |
module MUL64 #(
parameter SIZE = 64
) (
input [ SIZE-1:0] in1,
in2,
output [2*SIZE-1:0] out
);
assign out = in1 * in2;
endmodule
| 7.744213 |
module DIV1 #(
parameter SIZE = 1
) (
input in1,
in2,
output out,
rem
);
assign out = in1 / in2;
assign rem = in1 % in2;
endmodule
| 7.155718 |
module DIV2 #(
parameter SIZE = 2
) (
input [SIZE-1:0] in1,
in2,
output [SIZE-1:0] out,
rem
);
assign out = in1 / in2;
assign rem = in1 % in2;
endmodule
| 7.374063 |
module DIV4 #(
parameter SIZE = 4
) (
input [SIZE-1:0] in1,
in2,
output [SIZE-1:0] out,
rem
);
assign out = in1 / in2;
assign rem = in1 % in2;
endmodule
| 7.68064 |
module DIV8 #(
parameter SIZE = 8
) (
input [SIZE-1:0] in1,
in2,
output [SIZE-1:0] out,
rem
);
assign out = in1 / in2;
assign rem = in1 % in2;
endmodule
| 7.449194 |
module DIV16 #(
parameter SIZE = 16
) (
input [SIZE-1:0] in1,
in2,
output [SIZE-1:0] out,
rem
);
assign out = in1 / in2;
assign rem = in1 % in2;
endmodule
| 8.044859 |
module DIV32 #(
parameter SIZE = 32
) (
input [SIZE-1:0] in1,
in2,
output [SIZE-1:0] out,
rem
);
assign out = in1 / in2;
assign rem = in1 % in2;
endmodule
| 7.884689 |
module DIV64 #(
parameter SIZE = 64
) (
input [SIZE-1:0] in1,
in2,
output [SIZE-1:0] out,
rem
);
assign out = in1 / in2;
assign rem = in1 % in2;
endmodule
| 7.948937 |
module RFF (
input d,
clk,
reset,
output reg q
);
always @(posedge clk or posedge reset)
if (reset) q <= 0;
else q <= d;
endmodule
| 6.884361 |
module SFF (
input d,
clk,
set,
output reg q
);
always @(posedge clk or posedge set)
if (set) q <= 1;
else q <= d;
endmodule
| 6.740562 |
module RSFF (
input d,
clk,
set,
reset,
output reg q
);
always @(posedge clk or posedge reset or posedge set)
if (reset) q <= 0;
else if (set) q <= 1;
else q <= d;
endmodule
| 6.503851 |
module SRFF (
input d,
clk,
set,
reset,
output reg q
);
always @(posedge clk or posedge set or posedge reset)
if (set) q <= 1;
else if (reset) q <= 0;
else q <= d;
endmodule
| 6.618955 |
module RLATCH (
input d,
reset,
enable,
output reg q
);
always @(d or enable or reset)
if (enable)
if (reset) q <= 0;
else q <= d;
endmodule
| 7.214313 |
module LSHIFT1 #(
parameter SIZE = 1
) (
input in,
shift,
val,
output reg out
);
always @(in, shift, val) begin
if (shift) out = val;
else out = in;
end
endmodule
| 7.400209 |
module LSHIFT2 #(
parameter SIZE = 2
) (
input [SIZE-1:0] in,
input [SIZE-1:0] shift,
input val,
output reg [SIZE-1:0] out
);
always @(in or shift or val) begin
out = in << shift;
if (val) out = out | ({SIZE - 1{1'b1}} >> (SIZE - 1 - shift));
end
endmodule
| 7.435767 |
module LSHIFT4 #(
parameter SIZE = 4
) (
input [SIZE-1:0] in,
input [2:0] shift,
input val,
output reg [SIZE-1:0] out
);
always @(in or shift or val) begin
out = in << shift;
if (val) out = out | ({SIZE - 1{1'b1}} >> (SIZE - 1 - shift));
end
endmodule
| 7.556514 |
module LSHIFT8 #(
parameter SIZE = 8
) (
input [SIZE-1:0] in,
input [3:0] shift,
input val,
output reg [SIZE-1:0] out
);
always @(in or shift or val) begin
out = in << shift;
if (val) out = out | ({SIZE - 1{1'b1}} >> (SIZE - 1 - shift));
end
endmodule
| 7.800802 |
module LSHIFT16 #(
parameter SIZE = 16
) (
input [SIZE-1:0] in,
input [4:0] shift,
input val,
output reg [SIZE-1:0] out
);
always @(in or shift or val) begin
out = in << shift;
if (val) out = out | ({SIZE - 1{1'b1}} >> (SIZE - 1 - shift));
end
endmodule
| 8.65228 |
module LSHIFT32 #(
parameter SIZE = 32
) (
input [SIZE-1:0] in,
input [5:0] shift,
input val,
output reg [SIZE-1:0] out
);
always @(in or shift or val) begin
out = in << shift;
if (val) out = out | ({SIZE - 1{1'b1}} >> (SIZE - 1 - shift));
end
endmodule
| 8.353233 |
module LSHIFT64 #(
parameter SIZE = 64
) (
input [SIZE-1:0] in,
input [6:0] shift,
input val,
output reg [SIZE-1:0] out
);
always @(in or shift or val) begin
out = in << shift;
if (val) out = out | ({SIZE - 1{1'b1}} >> (SIZE - 1 - shift));
end
endmodule
| 8.464621 |
module RSHIFT1 #(
parameter SIZE = 1
) (
input in,
shift,
val,
output reg out
);
always @(in, shift, val) begin
if (shift) out = val;
else out = in;
end
endmodule
| 6.997862 |
module RSHIFT2 #(
parameter SIZE = 2
) (
input [SIZE-1:0] in,
input [SIZE-1:0] shift,
input val,
output reg [SIZE-1:0] out
);
always @(in or shift or val) begin
out = in >> shift;
if (val) out = out | ({SIZE - 1{1'b1}} << (SIZE - 1 - shift));
end
endmodule
| 6.938293 |
module RSHIFT4 #(
parameter SIZE = 4
) (
input [SIZE-1:0] in,
input [2:0] shift,
input val,
output reg [SIZE-1:0] out
);
always @(in or shift or val) begin
out = in >> shift;
if (val) out = out | ({SIZE - 1{1'b1}} << (SIZE - 1 - shift));
end
endmodule
| 7.17 |
module RSHIFT8 #(
parameter SIZE = 8
) (
input [SIZE-1:0] in,
input [3:0] shift,
input val,
output reg [SIZE-1:0] out
);
always @(in or shift or val) begin
out = in >> shift;
if (val) out = out | ({SIZE - 1{1'b1}} << (SIZE - 1 - shift));
end
endmodule
| 7.311689 |
module RSHIFT16 #(
parameter SIZE = 16
) (
input [SIZE-1:0] in,
input [4:0] shift,
input val,
output reg [SIZE-1:0] out
);
always @(in or shift or val) begin
out = in >> shift;
if (val) out = out | ({SIZE - 1{1'b1}} << (SIZE - 1 - shift));
end
endmodule
| 8.247073 |
module RSHIFT32 #(
parameter SIZE = 32
) (
input [SIZE-1:0] in,
input [5:0] shift,
input val,
output reg [SIZE-1:0] out
);
always @(in or shift or val) begin
out = in >> shift;
if (val) out = out | ({SIZE - 1{1'b1}} << (SIZE - 1 - shift));
end
endmodule
| 8.048141 |
module RSHIFT64 #(
parameter SIZE = 64
) (
input [SIZE-1:0] in,
input [6:0] shift,
input val,
output reg [SIZE-1:0] out
);
always @(in or shift or val) begin
out = in >> shift;
if (val) out = out | ({SIZE - 1{1'b1}} << (SIZE - 1 - shift));
end
endmodule
| 8.259608 |
module CMP4 #(
parameter SIZE = 4
) (
input [SIZE-1:0] in1,
in2,
output reg equal,
unequal,
greater,
lesser
);
always @(in1 or in2) begin
if (in1 == in2) begin
equal = 1;
unequal = 0;
greater = 0;
lesser = 0;
end else begin
equal = 0;
unequ... | 6.506564 |
module CMP8 #(
parameter SIZE = 8
) (
input [SIZE-1:0] in1,
in2,
output reg equal,
unequal,
greater,
lesser
);
always @(in1 or in2) begin
if (in1 == in2) begin
equal = 1;
unequal = 0;
greater = 0;
lesser = 0;
end else begin
equal = 0;
unequ... | 7.184798 |
module CMP64 #(
parameter SIZE = 64
) (
input [SIZE-1:0] in1,
in2,
output reg equal,
unequal,
greater,
lesser
);
always @(in1 or in2) begin
if (in1 == in2) begin
equal = 1;
unequal = 0;
greater = 0;
lesser = 0;
end else begin
equal = 0;
une... | 6.547383 |
module INC1 #(
parameter SIZE = 1
) (
input in,
output [SIZE:0] out
);
assign out = in + 1;
endmodule
| 6.762593 |
module INC2 #(
parameter SIZE = 2
) (
input [SIZE-1:0] in,
output [ SIZE:0] out
);
assign out = in + 1;
endmodule
| 7.524687 |
module INC4 #(
parameter SIZE = 4
) (
input [SIZE-1:0] in,
output [ SIZE:0] out
);
assign out = in + 1;
endmodule
| 7.590344 |
module INC8 #(
parameter SIZE = 8
) (
input [SIZE-1:0] in,
output [ SIZE:0] out
);
assign out = in + 1;
endmodule
| 8.288711 |
module INC16 #(
parameter SIZE = 16
) (
input [SIZE-1:0] in,
output [ SIZE:0] out
);
assign out = in + 1;
endmodule
| 8.472741 |
module INC32 #(
parameter SIZE = 32
) (
input [SIZE-1:0] in,
output [ SIZE:0] out
);
assign out = in + 1;
endmodule
| 8.420537 |
module INC64 #(
parameter SIZE = 64
) (
input [SIZE-1:0] in,
output [ SIZE:0] out
);
assign out = in + 1;
endmodule
| 8.153188 |
module ADD4 (
DataA0,
DataA1,
DataA2,
DataA3,
DataB0,
DataB1,
DataB2,
DataB3,
Result0,
Result1,
Result2,
Result3,
Cout
);
input DataA0, DataA1, DataA2, DataA3;
input DataB0, DataB1, DataB2, DataB3;
output Result0, Result1, Result2, Result3, Cout;
assign {Cout,... | 7.405802 |
module BUF (
DATA,
RESULT
);
input DATA;
output RESULT;
assign RESULT = DATA;
endmodule
| 6.665194 |
module INV (
DATA,
RESULT
);
input DATA;
output RESULT;
assign RESULT = ~DATA;
endmodule
| 6.612525 |
module xor2 (
DATA0X0,
DATA1X0,
RESULT0
);
input DATA0X0;
input DATA1X0;
output RESULT0;
assign RESULT0 = DATA1X0 ^ DATA0X0;
endmodule
| 6.62784 |
module mux4_4_16 (
Sel0,
Sel1,
Sel2,
Sel3,
Result0,
Result1,
Result2,
Result3,
Data0x0,
Data0x1,
Data0x2,
Data0x3,
Data1x0,
Data1x1,
Data1x2,
Data1x3,
Data2x0,
Data2x1,
Data2x2,
Data2x3,
Data3x0,
Data3x1,
Data3x2,
Data3x3,
... | 6.526602 |
module mux1_5_32 (
Sel0,
Sel1,
Sel2,
Sel3,
Sel4,
Data0x0,
Data1x0,
Data2x0,
Data3x0,
Data4x0,
Data5x0,
Data6x0,
Data7x0,
Data8x0,
Data9x0,
Data10x0,
Data11x0,
Data12x0,
Data13x0,
Data14x0,
Data15x0,
Data16x0,
Data17x0,
Data1... | 6.935898 |
module _NOT_ (
A,
Y
);
input A;
output Y;
assign Y = ~A;
endmodule
| 7.126709 |
module _AND_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = A & B;
endmodule
| 7.298115 |
module _OR_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = A | B;
endmodule
| 7.476894 |
module _XOR_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = A ^ B;
endmodule
| 8.135663 |
module _MUX_ (
A,
B,
S,
Y
);
input A, B, S;
output reg Y;
always @* begin
if (S) Y = B;
else Y = A;
end
endmodule
| 7.295928 |
module _DFF_N_ (
D,
Q,
C
);
input D, C;
output reg Q;
always @(negedge C) begin
Q <= D;
end
endmodule
| 7.311718 |
module _DFF_P_ (
D,
Q,
C
);
input D, C;
output reg Q;
always @(posedge C) begin
Q <= D;
end
endmodule
| 7.189289 |
module _DFF_NN0_ (
D,
Q,
C,
R
);
input D, C, R;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0) Q <= 0;
else Q <= D;
end
endmodule
| 6.611847 |
module _DFF_NN1_ (
D,
Q,
C,
R
);
input D, C, R;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0) Q <= 1;
else Q <= D;
end
endmodule
| 6.539355 |
module _DFF_PN0_ (
D,
Q,
C,
R
);
input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0) Q <= 0;
else Q <= D;
end
endmodule
| 6.550934 |
module _DFF_PN1_ (
D,
Q,
C,
R
);
input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0) Q <= 1;
else Q <= D;
end
endmodule
| 6.749886 |
module Simm (
unextended,
extended
);
input signed [15:0] unextended;
output reg signed [31:0] extended;
always @(*) begin
extended = {{16{unextended[15]}}, unextended};
end
endmodule
| 6.900868 |
module SimonTest;
// Local Vars
reg clk = 0;
reg sysclk = 0;
reg rst = 0;
reg level = 0;
reg [3:0] pattern = 4'd0;
wire [2:0] mode_leds;
wire [3:0] pattern_leds;
// Error Counts
reg [7:0] errors = 0;
// LED Light Parameters
localparam LED_MODE_INPUT = 3'b001;
localparam LED_MODE_PLAYBACK = ... | 7.494954 |
module simon (
input clk,
input res_n,
input start,
input ctrl,
input [255:0] keys,
input [127:0] in,
output [127:0] out,
output done
);
wire [63:0] key_out;
wire key_done;
wire [6:0] key_rnd;
wire [6:0] rd_adr;
wire [63:0] data_out;
wire [4:0] state;
wire key_wr_en;
wir... | 7.119927 |
module SimonControlTest;
// Local Vars
reg clk = 0;
reg rst = 0;
// More vars here...
// LED Light Parameters
localparam LED_MODE_INPUT = 3'b001;
localparam LED_MODE_PLAYBACK = 3'b010;
localparam LED_MODE_REPEAT = 3'b100;
localparam LED_MODE_DONE = 3'b111;
// VCD Dump
initial begin
$dumpfil... | 7.012085 |
module SimonControl(
// External Inputs
input clk, // Clock
input rst, // Reset
// Datapath Inputs
// input localin1,
// Datapath Control Outputs
// output control1,
// External Outputs
// output [2:0] mode_leds
);
// Declare Local Vars Here
// reg [X:0] state;
/... | 6.949634 |
module simonRound (
PT,
Key,
CT
);
parameter WIDTH = 32;
output wire [0:(2*WIDTH)-1] CT;
input [0:(2*WIDTH)-1] PT;
input [0:WIDTH-1] Key;
wire [0:WIDTH-1] PT1, PT2, CT1;
wire [0:WIDTH-1] lShift1, lShift8, lShift2, andVal, xor1, xor2;
assign PT1 = PT[0:WIDTH-1];
assign PT2 = PT[WIDTH:(2*WI... | 7.615817 |
module
// Module Name: top_module_test.v
// Project Name: SIMON
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////... | 6.999332 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(clk,data_in,data_rdy,cipher_out);
input clk,d... | 7.088073 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_module(clk,data_in,data_rdy,cipher_out);
inpu... | 7.088073 |
module simon_fsm (
input clk,
input res_n,
input ctrl,
input start,
input key_done,
output reg [4:0] state
);
// FSM
parameter idle = 5'b00001;
parameter enc_gen = 5'b00010;
parameter enc_wait = 5'b00011;
parameter dec_gen = 5'b00100;
parameter enc = 5'b01000;
parameter dec = 5'b1... | 7.408318 |
module top_module (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 7.203305 |
module top_module (
input x,
input y,
output z
);
assign z = ~(x ^ y);
endmodule
| 7.203305 |
module simple_counter (
input clock,
output reg [31:0] counter_out
);
always @ (posedge clock)// on positive clock edge
begin
counter_out <= #1 counter_out + 1; // increment counter
end
endmodule
| 7.044904 |
module simple_counter2 (
input clock,
output reg [127:0] counter_out
);
always @ (posedge clock)// on positive clock edge
begin
counter_out <= #1 counter_out + 1; // increment counter
end
endmodule
| 7.044904 |
module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
parameter A = 0, B = 1;
reg present_state, next_state;
always @(posedge clk) begin
... | 6.89453 |
module top_module (
input clk,
input areset, // Asynchronous reset to state B
input in,
output out
); //
parameter A = 0, B = 1;
reg state, next_state;
always @(*) begin // This is a combinational always block
// State transition logic
case (state)
A: next_state = in ? A : ... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = j ? ON : OFF;
ON: next_state = ... | 7.203305 |
module top_module (
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = j ? ON : OFF;
ON: next_state ... | 7.203305 |
module top_module (
input clk,
input in,
input areset,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state, next_state;
// State transition logic
always @(*) begin // This is a combinational always block
case (state)
A: next_state = in ? B : A;
B: next_sta... | 7.203305 |
module top_module (
input clk,
input in,
input reset,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state, next_state;
// State transition logic
always @(*) begin // This is a combinational always block
case (state)
A: next_state = in ? B : A;
B: next_stat... | 7.203305 |
module top_module (
input in,
input [3:0] state,
output [3:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = state[0] & (~in) | state[2] & (~in);
assign next_state[B] = state[0] ... | 7.203305 |
module top_module (
input in,
input [1:0] state,
output [1:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: next_state = f(state, in)
always @(*) begin
case (state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: n... | 7.203305 |
module top;
wire clk;
(* BEL="IOTILE(04,09):alta_rio00", keep *)
/* PIN_46 */
GENERIC_IOB #(
.INPUT_USED (1),
.OUTPUT_USED(0)
) clk_ibuf (
.O(clk)
);
wire [7:0] leds;
(* BEL="IOTILE(02,01):alta_rio02", keep *)
/* PIN_11 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(... | 6.919222 |
module simpleadder (
input wire clk,
input wire en_i,
input wire ina,
input wire inb,
output reg en_o,
output reg out
);
integer counter, state;
reg [1:0] temp_a, temp_b;
reg [2:0] temp_out;
//Init
initial begin
counter = 0;
temp_a = 2'b00;
temp_b = 2'b00;
temp_out... | 6.961371 |
module simpleadder_tb ();
reg clk;
reg ina;
reg inb;
reg en_i;
wire out;
wire en_o;
reg [1:0] tx_ina;
reg [1:0] tx_inb;
integer state_drv;
integer counter_drv, counter_finish;
//Connect the DUT to the TB
simpleadder dut (
.clk (clk),
.ina (ina),
.inb (inb),
.en_i(en_i... | 8.139217 |
module SimpleALU (
input clock,
input reset,
input [3:0] io_a,
input [3:0] io_b,
input [1:0] io_opcode,
output [3:0] io_out
);
wire [3:0] _T_2 = io_a + io_b; // @[SimpleALU.scala 46:20]
wire [3:0] _T_5 = io_a - io_b; // @[SimpleALU.scala 48:20]
wire [3:0] _GEN_0 = io_opc... | 7.829684 |
module simpleArray (
input wire i_button,
input wire i_clk,
input wire i_microphone,
input wire i_serial,
output wire o_serial,
output wire o_micVCC,
output wire o_micGND,
output wire o_clk,
output wire [7:0] o_led
);
localparam l_rate = 9'd150; //Convert 6MHz/2 to 40kHz
localp... | 7.344691 |
module SimpleBitOps (
input clock,
input reset,
input [3:0] io_inp1,
input [3:0] io_inp2,
output [3:0] io_out_and,
output io_out_andr,
output [3:0] io_out_xor,
output io_out_xorr,
output [3:0] io_out_or,
output io_out_orr,
output [3:0] io_out... | 7.098221 |
module drawPLUSerase (
iCLOCK_50,
iresetn,
idrawEn,
ieraseEn,
ix_pos,
iy_pos,
ocolor_out,
ox,
oy,
owriteEn,
oDoneSignal
);
input iCLOCK_50, iresetn, idrawEn, ieraseEn;
input [8:0] ix_pos;
input [7:0] iy_pos;
output [2:0] ocolor_out;
output reg [8:0] ox;
output re... | 8.238208 |
module simpleBus #(
parameter n = 32,
m = 32
) (
input d_valid,
//input w_en_to_bus_for_dmem, // this comes directly from RISC-V controller
input [7:0] data_imem, // 8bit from imem, need 4 times to get 32-bit instr
input [m-1:0] addr_imem,
input [n-1:0] data_dmem,
input [m-1:0] addr_dme... | 8.675916 |
module bridge (
wb__dat_w,
wb__dat_r,
wb__sel,
wb__cyc,
wb__stb,
wb__we,
wb__ack,
rst,
clk,
csr__addr,
csr__r_stb,
csr__w_stb,
csr__w_data,
csr__r_data,
wb__adr
);
reg \$auto$verilog_backend.cc:2083:dump_module$1 = 0;
wire \$1 ;
wire \$11 ;
wire \$13 ... | 8.006498 |
module simplebus_host (
bus_in,
parity_in,
bus_out,
parity_out,
enabled,
wb_adr,
wb_dat_w,
wb_dat_r,
wb_sel,
wb_cyc,
wb_stb,
wb_we,
wb_ack,
wb_stall,
wb_ctrl_adr,
wb_ctrl_dat_w,
wb_ctrl_dat_r,
wb_ctrl_sel,
wb_ctrl_cyc,
wb_ctrl_stb,
wb_c... | 6.890892 |
module RAM_tb #(
parameter BITS = 64,
parameter WORDS = 512 * 1024 / 8,
parameter filename = "micropython.hex"
) (
input clk,
input write_enable,
input [BITS/8-1:0] write_sel,
input [$clog2(WORDS)-1:0] addr,
output reg [BITS-1:0] read_data,
input [BITS-1:0] write_data
);
integer ... | 7.764019 |
module simplebus_tb (
input clk,
input [7:0] ext_bus_in,
input ext_bus_pty_in,
output [7:0] ext_bus_out,
output ext_bus_pty_out
);
localparam [7:0] CMD_READ = 8'h2;
localparam [7:0] CMD_WRITE = 8'h3;
localparam [7:0] CMD_READ_ACK = 8'h82;
localparam [7:0] CMD_WRITE_ACK = 8'h83;
localpar... | 7.855631 |
module simplebus_tb (
input clk,
input [7:0] ext_bus_in,
input ext_bus_pty_in,
output [7:0] ext_bus_out,
output ext_bus_pty_out
);
localparam [7:0] CMD_READ = 8'h2;
localparam [7:0] CMD_WRITE = 8'h3;
localparam [7:0] CMD_READ_ACK = 8'h82;
localparam [7:0] CMD_WRITE_ACK = 8'h83;
localpar... | 7.855631 |
module simpleButton (
input button_i,
output led_o
);
assign led_o = button_i;
endmodule
| 7.044927 |
module SimpleCalculator (
GPIO_0,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
CLOCK_50,
LEDR,
LEDG,
SW
);
inout [24:10] GPIO_0;
input [17:0] SW;
input CLOCK_50;
output [17:0] LEDR;
output [8:0] LEDG;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX... | 7.239443 |
module top_module (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 7.203305 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.