code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module skinny_sbox8_dom1_rapid_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si0,
si1,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1;
(*equivalent_register_removal = "no" *) output [7:0] bo0;
(*equivalent_register_removal = "no" *) input [7:0] si... | 6.768095 |
module rapid_a4 ( /*AUTOARG*/
// Outputs
a4,
// Inputs
nb3,
nb2,
b1,
nb0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [1:0] a4;
(*equivalent_register_removal = "no" *) input [1:0] nb3, nb2, b1, nb0;
(*equivalent_register_removal = "no" *) input [1:0] r;
(*equiva... | 6.639348 |
module and4_dom1_ne ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b,
c,
d,
r,
clk
);
(*equivalent_register_removal = "no" *) output [1:0] z;
(*equivalent_register_removal = "no" *) input [1:0] a, b, c, d;
(*equivalent_register_removal = "no" *) input [6:0] r;
(*equivalent_reg... | 6.781134 |
module and4_dom1 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b,
c,
d,
r,
clk
);
(*equivalent_register_removal = "no" *) output [1:0] z;
(*equivalent_register_removal = "no" *) input [1:0] a, b, c, d;
(*equivalent_register_removal = "no" *) input [6:0] r;
(*equivalent_register_r... | 6.746187 |
module and3_dom1_ne ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b,
c,
r,
clk
);
(*equivalent_register_removal = "no" *) output [1:0] z;
(*equivalent_register_removal = "no" *) input [1:0] a, b, c;
(*equivalent_register_removal = "no" *) input [2:0] r;
(*equivalent_register_remo... | 6.5732 |
module and2_dom1 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b,
r,
clk
);
(*equivalent_register_removal = "no" *) output [1:0] z;
(*equivalent_register_removal = "no" *) input [1:0] a, b;
(*equivalent_register_removal = "no" *) input r;
(*equivalent_register_removal = "no" *) input clk... | 6.82235 |
module and2_dom1_ne ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b,
r,
clk
);
(*equivalent_register_removal = "no" *) output [1:0] z;
(*equivalent_register_removal = "no" *) input [1:0] a, b;
(*equivalent_register_removal = "no" *) input r;
(*equivalent_register_removal = "no" *) in... | 6.920642 |
module skinny_sbox8_dom1_sni_non_complete ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
cycle,
clk
);
output [7:0] bo1; // share 1
output [7:0] bo0; // share 0
input [7:0] si1; // share 1
input [7:0] si0; // share 0
input [7:0] r; // refreshing mask
inp... | 6.768095 |
module skinny_sbox8_dom1_sni_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal = ... | 6.768095 |
module skinny_sbox8_dom1_sni_non_pipelined_de ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal... | 6.768095 |
module skinny_sbox8_hpc2_1_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal = "n... | 6.768095 |
module skinny_sbox8_hpc2_1_non_pipelined_de ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal =... | 6.768095 |
module skinny_sbox8_hpc2_1_str_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal ... | 6.768095 |
module skinny_sbox8_hpc2_1_str_non_pipelined_de ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_remov... | 6.768095 |
module skinny_sbox8_isw1_bypass_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal... | 6.768095 |
module skinny_sbox8_isw1_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal = "no"... | 6.768095 |
module skinny_sbox8_isw1_non_pipelined_de ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal = "... | 6.768095 |
module skinny_sbox8_isw1_pini_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal =... | 6.768095 |
module skinny_sbox8_isw1_pini_non_pipelined_de ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_remova... | 6.768095 |
module skinny_sbox8_para1_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal = "no... | 6.768095 |
module skinny_sbox8_para1_non_pipelined_de ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal = ... | 6.768095 |
module skinny_sbox8_pini1_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal = "no... | 6.768095 |
module skinny_sbox8_pini1_non_pipelined_de ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal = ... | 6.768095 |
module skintone #(
parameter DATAIN_WIDTH = 32,
parameter DATAOUT_WIDTH = 32
) (
input clk,
input rst,
input datain_valid,
input [DATAIN_WIDTH-1:0] datain,
output reg datain_ready,
output reg dataout_valid,
output reg [DATAOUT_WIDTH-1:0] dataout,
input dataout_ready
);
loca... | 7.378467 |
module skin_detect (
//Input
input iClk,
input iReset_n,
input iInput_ready,
input [15:0] iRGB,
//Output
output reg [12:0] oAddr_SM,
output reg oWrreq_SM,
output oData_out
);
//===================================REGISTERS=... | 6.57255 |
module SkipLogic (
output cin_next,
input [3:0] a,
b,
input cin,
cout
);
wire p0, p1, p2, p3, P, e;
xor (p0, a[0], b[0]);
xor (p1, a[1], b[1]);
xor (p2, a[2], b[2]);
xor (p3, a[3], b[3]);
and (P, p0, p1, p2, p3);
and (e, P, cin);
or (cin_next, e, cout);
endmodule
| 6.567588 |
module Skip_PC (
input [31:0] PC,
input [31:0] ExtOut,
output [31:0] SkipPC
);
assign SkipPC = PC + (ExtOut << 2);
endmodule
| 8.041981 |
module greyblock (
output G,
P,
input Gi,
Pi,
Gip,
Pip
);
wire w;
and (w, Pi, Gip);
or (G, w, Gi);
endmodule
| 7.59809 |
module blackblock (
output G,
P,
input Gi,
Pi,
Gip,
Pip
);
wire w;
and (w, Pi, Gip);
or (G, w, Gi);
and (P, Pi, Pip);
endmodule
| 7.802727 |
module Sklansky_adder #(
parameter WIDTH = 16,
VALENCY = 2
) (
input [WIDTH:1] A,
input [WIDTH:1] B,
input Cin,
output [WIDTH:1] S,
output Cout
);
wire [WIDTH:0] G, P, Gi;
Bitwise_PG #(WIDTH) bit_PG (
A,
B,
Cin,
G,
P
);
Sklansky_grp_PG #(WIDTH, VALENCY... | 7.118159 |
module initialize_g_p (
input a,
input b,
output g,
output p
);
assign g = a & b;
assign p = a ^ b;
endmodule
| 7.400416 |
module merge (
input g_in1,
input p_in1,
input g_in2,
input p_in2,
output g_out,
output p_out
);
wire w;
assign w = p_in1 & g_in2;
assign g_out = w | g_in1;
assign p_out = p_in1 & p_in2;
endmodule
| 7.012276 |
module Sklansky_grp_PG #(
parameter WIDTH = 16,
VALENCY = 2
) (
input [WIDTH:0] G,
input [WIDTH:0] P,
output [WIDTH:0] Gi
);
parameter LEVELS = $clog2(WIDTH);
wire [WIDTH-1:0] gt[0:LEVELS], pt[0:LEVELS];
assign Gi[0] = G[0];
assign gt[0] = G;
assign pt[0] = P;
genvar i, j, k, p;
g... | 6.918895 |
module top;
wire [15:0] Sum;
wire cout;
reg [15:0] A;
reg [15:0] B;
reg cin;
sklansky adder (
cin,
A,
B,
Sum,
cout
);
initial begin
cin = 1'b0;
#0 A = 345;
B = 134;
#4 A = 4567;
B = 234;
#8 A = 23;
B = 10;
#12 A = 6409;
B = 0;
end
... | 6.919222 |
module DE10_LITE_Golden_Top (
//////////// CLOCK //////////
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
//////////// SDRAM //////////
output [12:0] DRAM_ADDR,
output [ 1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
ou... | 6.792785 |
module skullfet_nand (
`ifdef USE_POWER_PINS
input VGND,
input VPWR,
`endif // USE_POWER_PINS
input wire A,
input wire B,
output wire Y
);
`ifdef USE_POWER_PINS
wire power_good = VPWR == 1 && VGND == 0;
`else
wire power_good = 1'b1;
`endif // USE_POWER_PINS
wire nand_out = !(A & B);
wire ... | 7.016243 |
module skullfet_nand (
`ifdef USE_POWER_PINS
input VGND,
input VPWR,
`endif // USE_POWER_PINS
input A,
input B,
output Y
);
endmodule
| 7.016243 |
module sky (
clock,
reset,
update,
draw,
x,
y,
color,
finish_drawing,
ground
);
input clock, reset, update, draw;
output [7:0] x;
output [6:0] y;
output [2:0] color;
output finish_drawing;
output [59:0] ground;
wire [55:0] col1, col2, col3, col4, col5, col6, col7, col... | 6.604516 |
module sky130_fd_sc_hd__a2bb2o (
X,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire nor0_out;
wire or0_ou... | 7.212805 |
module sky130_fd_sc_hd__a2bb2o (
X,
A1_N,
A2_N,
B1,
B2
);
// Module ports
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Local signals
wire and0_out;
wire nor0_out;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out, B1, B2);
nor nor0 (nor0... | 7.212805 |
module sky130_fd_sc_hd__a2bb2o (
X,
A1_N,
A2_N,
B1,
B2
);
// Module ports
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire nor0_out;
wire or0_out_X;
... | 7.212805 |
module sky130_fd_sc_hd__a2bb2o_1 (
X,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),... | 7.212805 |
module sky130_fd_sc_hd__a2bb2o_1 (
X,
A1_N,
A2_N,
B1,
B2
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),... | 7.212805 |
module sky130_fd_sc_hd__a2bb2o_2 (
X,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),... | 7.212805 |
module sky130_fd_sc_hd__a2bb2o_2 (
X,
A1_N,
A2_N,
B1,
B2
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),... | 7.212805 |
module sky130_fd_sc_hd__a2bb2o_4 (
X,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),... | 7.212805 |
module sky130_fd_sc_hd__a2bb2o_4 (
X,
A1_N,
A2_N,
B1,
B2
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),... | 7.212805 |
module sky130_fd_sc_hd__a2bb2oi (
Y,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire nor0_out;
wire nor1_... | 7.212805 |
module sky130_fd_sc_hd__a2bb2oi (
Y,
A1_N,
A2_N,
B1,
B2
);
// Module ports
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
// Local signals
wire and0_out;
wire nor0_out;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out, B1, B2);
nor nor0 (n... | 7.212805 |
module sky130_fd_sc_hd__a2bb2oi (
Y,
A1_N,
A2_N,
B1,
B2
);
// Module ports
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire nor0_out;
wire nor1_out_Y;
... | 7.212805 |
module sky130_fd_sc_hd__a2bb2oi_1 (
Y,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N... | 7.212805 |
module sky130_fd_sc_hd__a2bb2oi_1 (
Y,
A1_N,
A2_N,
B1,
B2
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N... | 7.212805 |
module sky130_fd_sc_hd__a2bb2oi_2 (
Y,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N... | 7.212805 |
module sky130_fd_sc_hd__a2bb2oi_2 (
Y,
A1_N,
A2_N,
B1,
B2
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N... | 7.212805 |
module sky130_fd_sc_hd__a2bb2oi_4 (
Y,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N... | 7.212805 |
module sky130_fd_sc_hd__a2bb2oi_4 (
Y,
A1_N,
A2_N,
B1,
B2
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N... | 7.212805 |
module sky130_fd_sc_hd__a21bo (
X,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nand0_out;
wire nand1_out_X;
wire pwrgood_pp0_out_X;
// ... | 7.212805 |
module sky130_fd_sc_hd__a21bo (
X,
A1,
A2,
B1_N
);
// Module ports
output X;
input A1;
input A2;
input B1_N;
// Local signals
wire nand0_out;
wire nand1_out_X;
// Name Output Other arguments
nand nand0 (nand0_out, A2, A1);
nand nand1 (nand1_out_X, B1_N, nand0_out);
b... | 7.212805 |
module sky130_fd_sc_hd__a21bo (
X,
A1,
A2,
B1_N
);
// Module ports
output X;
input A1;
input A2;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire nand0_out;
wire nand1_out_X;
// Name Output Other argument... | 7.212805 |
module sky130_fd_sc_hd__a21bo_1 (
X,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VP... | 7.212805 |
module sky130_fd_sc_hd__a21bo_1 (
X,
A1,
A2,
B1_N
);
output X;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule... | 7.212805 |
module sky130_fd_sc_hd__a21bo_2 (
X,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VP... | 7.212805 |
module sky130_fd_sc_hd__a21bo_2 (
X,
A1,
A2,
B1_N
);
output X;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule... | 7.212805 |
module sky130_fd_sc_hd__a21bo_4 (
X,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VP... | 7.212805 |
module sky130_fd_sc_hd__a21bo_4 (
X,
A1,
A2,
B1_N
);
output X;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule... | 7.212805 |
module sky130_fd_sc_hd__a21boi (
Y,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire b;
wire and0_out;
wire nor0_out_Y;
wire pwrgood_pp0_out_Y;... | 7.212805 |
module sky130_fd_sc_hd__a21boi (
Y,
A1,
A2,
B1_N
);
// Module ports
output Y;
input A1;
input A2;
input B1_N;
// Local signals
wire b;
wire and0_out;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (b, B1_N);
and and0 (and0_out, A1, A2);
nor nor0 (nor0_out_Y,... | 7.212805 |
module sky130_fd_sc_hd__a21boi (
Y,
A1,
A2,
B1_N
);
// Module ports
output Y;
input A1;
input A2;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire b;
wire and0_out;
wire nor0_out_Y;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hd__a21boi_0 (
Y,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(... | 7.212805 |
module sky130_fd_sc_hd__a21boi_0 (
Y,
A1,
A2,
B1_N
);
output Y;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodu... | 7.212805 |
module sky130_fd_sc_hd__a21boi_1 (
Y,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(... | 7.212805 |
module sky130_fd_sc_hd__a21boi_1 (
Y,
A1,
A2,
B1_N
);
output Y;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodu... | 7.212805 |
module sky130_fd_sc_hd__a21boi_2 (
Y,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(... | 7.212805 |
module sky130_fd_sc_hd__a21boi_2 (
Y,
A1,
A2,
B1_N
);
output Y;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodu... | 7.212805 |
module sky130_fd_sc_hd__a21boi_4 (
Y,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(... | 7.212805 |
module sky130_fd_sc_hd__a21boi_4 (
Y,
A1,
A2,
B1_N
);
output Y;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodu... | 7.212805 |
module sky130_fd_sc_hd__a21o (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// ... | 7.212805 |
module sky130_fd_sc_hd__a21o (
X,
A1,
A2,
B1
);
// Module ports
output X;
input A1;
input A2;
input B1;
// Local signals
wire and0_out;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out, A1, A2);
or or0 (or0_out_X, and0_out, B1);
buf buf0 (X, or0_out_X);
... | 7.212805 |
module sky130_fd_sc_hd__a21o (
X,
A1,
A2,
B1
);
// Module ports
output X;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire or0_out_X;
// Name Output Other arguments
and and0... | 7.212805 |
module sky130_fd_sc_hd__a21o_1 (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
... | 7.212805 |
module sky130_fd_sc_hd__a21o_1 (
X,
A1,
A2,
B1
);
output X;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a21o base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__a21o_2 (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
... | 7.212805 |
module sky130_fd_sc_hd__a21o_2 (
X,
A1,
A2,
B1
);
output X;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a21o base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__a21o_4 (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
... | 7.212805 |
module sky130_fd_sc_hd__a21o_4 (
X,
A1,
A2,
B1
);
output X;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a21o base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__a21oi (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire nor0_out_Y;
wire pwrgood_pp0_out_Y;
// ... | 7.212805 |
module sky130_fd_sc_hd__a21oi (
Y,
A1,
A2,
B1
);
// Module ports
output Y;
input A1;
input A2;
input B1;
// Local signals
wire and0_out;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out, A1, A2);
nor nor0 (nor0_out_Y, B1, and0_out);
buf buf0 (Y, nor0_o... | 7.212805 |
module sky130_fd_sc_hd__a21oi (
Y,
A1,
A2,
B1
);
// Module ports
output Y;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire nor0_out_Y;
// Name Output Other arguments
and a... | 7.212805 |
module sky130_fd_sc_hd__a21oi_1 (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
... | 7.212805 |
module sky130_fd_sc_hd__a21oi_1 (
Y,
A1,
A2,
B1
);
output Y;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a21oi base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__a21oi_2 (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
... | 7.212805 |
module sky130_fd_sc_hd__a21oi_2 (
Y,
A1,
A2,
B1
);
output Y;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a21oi base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__a21oi_4 (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
... | 7.212805 |
module sky130_fd_sc_hd__a21oi_4 (
Y,
A1,
A2,
B1
);
output Y;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a21oi base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__a22o (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire and1_out;
wire or0_out_X;
wir... | 7.212805 |
module sky130_fd_sc_hd__a22o (
X,
A1,
A2,
B1,
B2
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire and0_out;
wire and1_out;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out, B1, B2);
and and1 (and1_out, A1, ... | 7.212805 |
module sky130_fd_sc_hd__a22o (
X,
A1,
A2,
B1,
B2
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire and1_out;
wire or0_out_X;
// Name ... | 7.212805 |
module sky130_fd_sc_hd__a22o_1 (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
... | 7.212805 |
module sky130_fd_sc_hd__a22o_1 (
X,
A1,
A2,
B1,
B2
);
output X;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a22o base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1),
... | 7.212805 |
module sky130_fd_sc_hd__a22o_2 (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
... | 7.212805 |
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