code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module single_port_ram (
input clk,
input rst,
input ena,
input wea,
input [31:0] din,
input [`WIDTH-2:0] addr,
output reg [31:0] dout,
output reg read_valid
);
parameter num = 32'b1 << `WIDTH;
reg [31:0] ram[num-1:0];
integer i;
always @(posedge clk) begin
if (rst) begin
... | 8.023817 |
module single_port_ram_128_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_128_8 8
`define DATA_WIDTH_128_8 128
input clk;
input [`DATA_WIDTH_128_8-1:0] data;
input we;
input [`ADDR_WIDTH_128_8-1:0] addr;
output [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] out;
r... | 8.023817 |
module single_port_ram_21_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_21_8 8
`define DATA_WIDTH_21_8 21
input clk;
input [`DATA_WIDTH_21_8-1:0] data;
input we;
input [`ADDR_WIDTH_21_8-1:0] addr;
output [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] out;
reg [`DAT... | 8.023817 |
module single_port_ram_8bit #(
parameter ADDR_WIDTH = 14
) (
input wire [ADDR_WIDTH - 1 : 0] addr,
input wire [ 7 : 0] din,
input wire write_en,
input wire clk,
output wire [ 7 : 0] dout
);
reg [ADDR_WIDTH - 1 : 0] addr_reg... | 8.023817 |
module single_port_ram_8bit_0 #(
parameter ADDR_WIDTH = 16
) (
input wire [ADDR_WIDTH - 1 : 0] addr,
input wire [ 7 : 0] din,
input wire write_en,
input wire clk,
output wire [ 7 : 0] dout
);
reg [ADDR_WIDTH - 1 : 0] addr_r... | 8.023817 |
module single_port_ram_8bit_1 #(
parameter ADDR_WIDTH = 14,
BYTE_INDEX = 0
) (
input wire [ADDR_WIDTH - 1 : 0] addr,
input wire [ 7 : 0] din,
input wire write_en,
input wire clk,
output wire [ 7 : 0] dout
);
reg [ADDR_W... | 8.023817 |
module single_port_ram_8bit_2 #(
parameter ADDR_WIDTH = 14,
BYTE_INDEX = 0
) (
input wire [ADDR_WIDTH - 1 : 0] addr,
input wire [ 7 : 0] din,
input wire write_en,
input wire clk,
output wire [ 7 : 0] dout
);
reg [ADDR_W... | 8.023817 |
module single_port_ram_8bit_3 #(
parameter ADDR_WIDTH = 14,
BYTE_INDEX = 0
) (
input wire [ADDR_WIDTH - 1 : 0] addr,
input wire [ 7 : 0] din,
input wire write_en,
input wire clk,
output wire [ 7 : 0] dout
);
reg [ADDR_W... | 8.023817 |
module single_port_ram_lattice #(
parameter ADDR_WIDTH = 14,
DATA_WIDTH = 16
) (
input wire [ ADDR_WIDTH - 1 : 0] addr,
input wire [ DATA_WIDTH - 1 : 0] din,
input wire [DATA_WIDTH / 8 - 1 : 0] write_en,
input wire clk,
output wire [ DATA_WIDTH - 1 : 0] ... | 8.023817 |
module single_port_ram_lattice_16Kx16 (
input wire [13 : 0] addr,
input wire [15 : 0] din,
input wire [ 1 : 0] write_en,
input wire clk,
output wire [15 : 0] dout
);
SP256K spram_i (
.AD (addr), // I
.DI (din), ... | 8.023817 |
module single_port_ram_sync #(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire we,
input wire [ADDR_WIDTH-1:0] addr_a,
input wire [DATA_WIDTH-1:0] din_a,
output wire [DATA_WIDTH-1:0] dout_a
);
reg [DATA_WIDTH-1:0] ram... | 8.023817 |
module single_port_ram_synchronous_behavioral (
input clk, // Clock
input we, // Write enable
input [ADDR_WIDTH-1:0] addr, // Address
input [DATA_WIDTH-1:0] data_in, // Data to write
output reg [DATA_WIDTH-1:0] data_out
); // Dat... | 8.023817 |
module SINGLE_PORT_RAM_SYNCHRONOUS_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg CLK;
reg WE;
reg [3:0] ADDR;
reg [7:0] DATA_IN;
wire [7:0] DATA_OUT;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg [7:0] DATA_OUTEXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
... | 7.158081 |
module single_port_ram_tb;
parameter CLOCK_PERIOD = 10;
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 3;
// input
reg clk;
reg [DATA_WIDTH-1:0] data;
reg [ADDR_WIDTH-1:0] addr;
reg we;
// output
wire [DATA_WIDTH-1:0] q;
single_port_ram #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_... | 8.023817 |
module single_port_rom #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 8
) (
input [(ADDR_WIDTH-1):0] addr,
input clk,
output reg [(DATA_WIDTH-1):0] q
);
// Declare the ROM variable
reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];
// Initialize the ROM with $readmemb. Put the memory content... | 8.023817 |
module single_ram #(
parameter PAYLOAD_BITS = 32,
parameter NUM_BRAM_ADDR_BITS = 7,
parameter NUM_ADDR_BITS = 7,
parameter RAM_TYPE = "block",
localparam BRAM_DEPTH = 2 ** (NUM_BRAM_ADDR_BITS)
//localparam BRAM_DEPTH = 128
) (
input clk,
input reset,
input wea,
input web,
inp... | 6.819943 |
module single_ram_asyn (
clk,
address,
we,
data
);
parameter DATA_WIDTH = 8;
parameter ADDRESS_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDRESS_WIDTH;
input clk;
input [ADDRESS_WIDTH-1:0] address;
input we;
inout [DATA_WIDTH-1:0] data;
reg [DATA_WIDTH-1:0] data_out;
reg [DATA_WIDTH-1:0]... | 8.894757 |
module single_ram_sy (
clk,
address,
we,
data
);
parameter DATA_WIDTH = 8;
parameter ADDRESS_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDRESS_WIDTH;
input clk;
input [ADDRESS_WIDTH-1:0] address;
input we;
inout [DATA_WIDTH-1:0] data;
reg [DATA_WIDTH-1:0] data_out;
reg [DATA_WIDTH-1:0] m... | 7.770775 |
module single_reg #(
parameter DATA_TYPE = 16
) (
input clk,
input [DATA_TYPE-1:0] data_in,
output [DATA_TYPE-1:0] data_out
);
reg [DATA_TYPE-1:0] data_out_reg;
always @(posedge clk) begin
data_out_reg <= data_in;
end
assign data_out = data_out_reg;
endmodule
| 8.596585 |
module single_signext (
in,
out
);
input [15:0] in;
output [31:0] out;
reg [31:0] out;
always @(in) begin
if (in[15] == 1'b1) out <= {{16'b1111111111111111}, in};
else out <= {{16'b0000000000000000}, in};
end
endmodule
| 7.221811 |
module single_sram #(
parameter DATA_WIDTH = 4, //width of data bus
parameter ADDR_WIDTH = 4 //width of addresses buses
) (
input [(DATA_WIDTH-1):0] data, //data to be written
input [(ADDR_WIDTH-1):0] addr, //address for write/read operation
input we, //write enable sig... | 9.281478 |
module has a latency of 2 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module single_to_int (
clk,
single_to_int_a,
single_to_int_z
);
input clk;
input [31:0] single_to_int_a;
output [31:0] single_to_int_z;
wire [31:0] s_0;
wire [31:0] s_1;
wire [31:0] s_2;
wire [31:0] s_3;
wire [31:0] s_4;
wire [31:0] s_5;
wire [23:0] s_6;
wire [ 0:0] s_7;
wire [ 0:0] ... | 7.971342 |
module single_to_int_tb;
reg clk;
reg [31:0] single_to_int_a;
wire [31:0] single_to_int_z;
integer single_to_int_a_file;
integer single_to_int_z_file;
integer single_to_int_a_count;
integer single_to_int_z_count;
single_to_int single_to_int1 (
clk,
single_to_int_a,
single_to_int_z
)... | 7.971342 |
module has a latency of 1 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module single_to_unsigned_int (
clk,
single_to_unsigned_int_a,
single_to_unsigned_int_z
);
input clk;
input [31:0] single_to_unsigned_int_a;
output [31:0] single_to_unsigned_int_z;
wire [31:0] s_0;
wire [31:0] s_1;
wire [31:0] s_2;
wire [23:0] s_3;
wire [ 0:0] s_4;
wire [ 0:0] s_5;
wire ... | 7.396908 |
module single_to_unsigned_int_tb;
reg clk;
reg [31:0] single_to_unsigned_int_a;
wire [31:0] single_to_unsigned_int_z;
integer single_to_unsigned_int_a_file;
integer single_to_unsigned_int_z_file;
integer single_to_unsigned_int_a_count;
integer single_to_unsigned_int_z_count;
single_to_unsigned_int sing... | 7.396908 |
module top (
input in,
output out
);
assign out = in;
endmodule
| 7.233807 |
module sign_Extend32 (
In16,
Out32
);
parameter in_size = 16;
parameter out_size = 32;
input [in_size-1:0] In16;
output [out_size-1:0] Out32;
assign Out32 = {{in_size{In16[in_size-1]}}, In16};
endmodule
| 7.991122 |
module sinModule (
phase,
sinOut
);
input [`phaseRes-1:0] phase;
output reg [`SinSize-1:0] sinOut;
always @(phase) begin
if (phase == `phaseRes'd0) sinOut = `SinSize'd0;
else if (phase == `phaseRes'd1) sinOut = `SinSize'd2896;
else if (phase == `phaseRes'd2) sinOut = `SinSize'd4095;
else... | 6.579274 |
module NABPSinogramAddresser
(
// global signals
input wire clk,
input wire reset_n,
// inputs from host
input wire hs_kick,
// inputs from filtered RAM
input wire [`kSLength-1:0] fr_s_val,
input wire fr_next_angle,
// outputs to host
output wire hs_done,
// outputs to filter... | 7.587813 |
module sintable (
i_clk,
i_reset,
ctrl,
iphase,
o_voltage
); //initalize function sine table
//
parameter TBL_BIT = 8, // Number of bits in the input phase
OUTPUT_SIZE = 8; // Number of output bits
//
input wire i_clk, i_reset, ctrl; //initializes inputs clock, reset, and control
in... | 6.731161 |
module sintable_tb;
task passTest; // test to see if output is same as expected value
input [31:0] actualOut, expectedOut; //actualout = output , expectedout = expected value
input [`STRLEN*8:0] testType; // string that names test
inout [31:0] passed; // passed indexer to see if it is passed
if (... | 6.72339 |
module tb ();
reg clk, reset;
reg [15:0] x;
wire [15:0] sineValue;
reg func;
initial begin
clk = 1'b0;
reset = 1'b1;
#30;
reset = 1'b0;
func = 1'b0;
#20;
x = 16'b0000_0000_0000_0000;
#20;
x = 16'b0000_1000_1100_0000;
#20;
x = 16'b0011_1111_1111_1110;
#20;... | 7.195167 |
module TP (
//////////// SW //////////
input [17:0] SW,
//////////// SEG7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7
);
//============================... | 6.784399 |
module MINIMO_3 (
a,
b,
c,
min
);
input [7:0] a, b, c;
output [7:0] min;
wire [7:0] min_a_b;
MINIMO_2 m1 (
a,
b,
min_a_b
);
wire [7:0] min_a_b_c;
MINIMO_2 m2 (
min_a_b,
c,
min_a_b_c
);
assign min = min_a_b_c;
endmodule
| 7.162935 |
module Sintetizador (
/*
* Entradas do CODEC de áudio da própria DE2.
*/
input wire AUD_DACLRCK,
input wire AUD_BCLK,
/*
* Comando de início/fim de uma nota.
*/
input wire NOTE_PLAY, // 1: Iniciará a nota definida por NOTE_PITCH; 0: Terminará a nota definida por NOTE_PITCH.
input wire... | 7.454007 |
module Sintetizador_Interface (
input iCLK,
input iCLK_50,
input Reset,
input wire AUD_DACLRCK,
input wire AUD_BCLK,
output [15:0] wsaudio_outL,
wsaudio_outR,
// Barramento de IO
input wReadEnable,
wWriteEnable,
input [3:0] wByteEnable,
input [31:0] wAddress,
wWriteD... | 7.716085 |
module SinLookUp (
clk,
reset,
eksi,
aci,
sin_normal_out,
sin_minus_out,
sin_out
);
input [2:0] aci; // 7 ADET ACI BULUNMAKTADIR
input eksi;
input clk, reset;
output reg signed [16:0] sin_normal_out; // FORMAT Q7.10
output reg signed [16:0] sin_minus_out; // FORMAT Q7.10
out... | 6.665689 |
module testbench;
parameter PERIOD = 20;
reg i_clk, i_rst_n;
wire [3:0] o_dac;
sinus_gen gen_inst (
.CLOCK_50(i_clk),
.KEY({i_rst_n, 1'b0}),
.VGA_R(o_dac)
);
initial begin
i_clk = 0;
forever #(PERIOD / 2) i_clk = ~i_clk;
end
initial begin
i_rst_n = 1'b0;
@(negedge... | 7.015571 |
module SinWave (
input clk,
output [15:0] Sinout,
input reset,
input [31:0] phase,
input [31:0] Step
);
reg [31:0] address;
reg [31:0] SynthesisedPhase;
initial begin
address = 32'd0;
end
/**********调用SinROM************/
SinROM ROM1 (
.address(SynthesisedPhase[31:20]),
.c... | 6.700329 |
module itoincrement (
input [4:0] index,
output reg [16:0] increment
);
//multiplexer
always @(*)
case (index)
5'd0: increment <= 17'd14999;
5'd1: increment <= 17'd15891;
5'd2: increment <= 17'd16836;
5'd3: increment <= 17'd17837;
5'd4: increment <= 17'd18898;
5'd5: ... | 7.224645 |
module counter32bit (
input clk,
input resetn,
input [16:0] increment,
output [7:0] address
);
reg [31:0] bigCounter;
always @(posedge clk)
if (!resetn) bigCounter <= 0;
else bigCounter <= bigCounter + increment;
assign address = bigCounter[31:24];
endmodule
| 8.281192 |
module sinWaveOneKey (
input [4:0] index,
input s,
input resetn,
input clk,
output signed [11:0] osound
);
wire [16:0] increment;
wire [7:0] address;
wire signed [11:0] psound;
itoincrement I (
index,
increment
);
counter32bit C (
.clk(clk),
.resetn(resetn),
... | 7.569309 |
module sinwave_gen (
input clock_50M,
input bclk, //IIS/PCM clock
input dacclk, //左右声道输出
output reg dacdat, //语音输出
input play_en, //播音使能信号
output reg wav_rden, //ddr语言数据读请求
input [31:0] wav_out_data //ddr语言输出数据
);
reg [7:0] data_num;
reg [31:0] audio_data;
reg wav_rden_req... | 6.859587 |
module sin_3phase_pwm #(
parameter PHASE_WIDTH = 10,
parameter COUNTER_WIDTH = 12
) (
input wire reset,
input wire clk,
input wire [PHASE_WIDTH-1:0] in_phase,
output wire pwm_x,
output wire pwm_y,
output wire pwm_z
);
wire [COUNTER_WIDTH-1:0] x_th;
wire [COUNTER_WIDTH-1:0] y_th... | 7.197635 |
modules: lookup_tables, SINE_LUT
*- Description: Generate arbitrary frequency 10-bit sin wave
*-
*- Example of Usage:
Refer to the STEPFPGA tutorial book Chapter 5 for more details
f_out = M * f_clk/(2^N), since f_clk = 12MHz, N = 32 bit, so we have:
M = f_out * 358
To obtain any desired frequency of the sin... | 6.976376 |
module sin_cos (
in,
sel,
result
);
////////////////////////////////////////////////////
input [31:0] in;
input sel;
output [31:0] result;
wire [31:0] out1, out2;
wire [31:0] temp_result;
////////////////////////////////////////////////////
taylor_sin SIN (
.in (in),
.out(out1)... | 6.543674 |
module sin_dds (
clk,
rst_n,
fword,
pword,
data_out,
data_change
);
`define OUT_WIDTH 8
`define ADDR_WIDTH 10
input clk; //定义系统时钟
input rst_n; //复位信号
input [`ADDR_WIDTH-1:0] fword; //定义频率控制字
input [`ADDR_WIDTH-1:0] pword; //定义相位控制字
output [`OUT_WIDTH-1:0] data_out; //输出波形数据
... | 6.823258 |
module Sin_Generator (
clk,
reset_n,
freq,
dataout
);
input clk;
input reset_n;
input [15:0] freq;
output reg [15:0] dataout;
(* ram_init_file = "sintable.mif" *) reg [15:0] sintable[1023:0] /*systhesis */;
reg [15:0] freq_counter; //16bit counter
always @(posedge clk) //change data at... | 7.128096 |
module sin_processing (
input clk_sys,
input clk_aud,
input clrn,
input ps2_clk,
input ps2_data,
output reg [15:0] final_data
);
parameter [15:0] freq_do_1 = 16'd714;
parameter [15:0] freq_re = 16'd802;
parameter [15:0] freq_mi = 16'd900;
parameter [15:0] freq_fa = 16'd954;
parameter ... | 7.882519 |
module sin_rom #(
parameter DATA_WIDTH = 12,
parameter ADDR_WIDTH = 12
) (
input [(ADDR_WIDTH-1):0] addr,
input clk,
output reg [(DATA_WIDTH-1):0] q
);
// Declare the ROM variable
reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];
// Initialize the ROM with $readmemb. Put the memory contents
//... | 7.565656 |
module Wave_ROM64 (
ADDR,
DATA
);
output [15:0] DATA;
input [5:0] ADDR;
reg [15:0] sine[0:63];
initial begin
sine[0] = 16'h0000;
sine[1] = 16'h0C8B;
sine[2] = 16'h18F8;
sine[3] = 16'h2527;
sine[4] = 16'h30FB;
sine[5] = 16'h3C56;
sine[6] = 16'h471C;
sine[7] = 16'h5... | 7.622679 |
module sio_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8
, parameter DEPTH = 4
, parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// P... | 6.795991 |
module part_SIP330_470_8 (
R2,
R3,
R4,
R5,
R6,
R7
);
output R2, R3, R4, R5, R6, R7;
pullup p2 (R2);
pullup p3 (R3);
pullup p4 (R4);
pullup p5 (R5);
pullup p6 (R6);
pullup p7 (R7);
endmodule
| 7.13582 |
module part_SIP220_330_8 (
R2,
R3,
R4,
R5,
R6,
R7
);
output R2, R3, R4, R5, R6, R7;
pullup p2 (R2);
pullup p3 (R3);
pullup p4 (R4);
pullup p5 (R5);
pullup p6 (R6);
pullup p7 (R7);
endmodule
| 7.027682 |
module sip4_demo_dphy_rx_wrap (
input wire reset_n_i,
input wire reset_byte_n_i,
input wire reset_byte_fr_n_i,
input wire clk_byte_fr_i,
inout wire clk_p_i,
inout wire clk_n_i,
inout wire d0_p_io,
inout wire d0_n_io,
inout wire d1_p_i,
inout wire d1_n_i,
inout wire d2_p_i,
... | 6.7986 |
module sipo_10bit (
input clk,
input rst_n,
input ser_in,
input shift_en,
output [9:0] par_out
);
reg [9:0] shift_reg;
always @(posedge clk) begin
if (!rst_n) begin
shift_reg <= 10'b0000000000;
end else begin
if (shift_en) begin
par_out <... | 6.724132 |
module sipo_harness #(
parameter WIDTH = 42,
parameter RAND_DELAY = 1
) ();
localparam CLK_PERIOD = 2 * 5;
localparam Thold = 2;
localparam WAIT_MIN = 5;
localparam WAIT_MAX = 21;
reg sysclk, load, data_in;
wire [WIDTH-1:0] data_out;
integer count;
sipo #(
.WIDTH(WIDTH)
) sr (
... | 7.017479 |
module dff (
d,
clk,
q
);
input d, clk;
output q;
reg q = 0;
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.361383 |
module SIPO_Shift_Register (
Sin,
Pout,
Clock,
Clear
);
input Sin, Clock, Clear;
output reg [3:0] Pout;
always @(posedge Clock or negedge Clear) begin
if (!Clear) Pout <= 4'b0;
else if (Clear) begin
Pout[3] <= Pout[2];
Pout[2] <= Pout[1];
Pout[1] <= Pout[0];
Pout[0]... | 7.173009 |
module SIPO_Shift_Register_TB;
reg Sin;
reg Clock;
reg Clear;
wire [3:0] Pout;
integer count;
SIPO_Shift_Register uut (
.Sin (Sin),
.Pout (Pout),
.Clock(Clock),
.Clear(Clear)
);
initial
$monitor(
"Clock Pulse = %d | Reset = %b | SIn = %b | Parallel_Out = %b", count,... | 7.173009 |
module sipo_y (
clk,
rst,
shift_v,
s_in_v,
s_in,
p_out_v,
p_out
);
input clk;
//input ce;
input rst; // reset of the FSM
//input rst; no reset port in the LUTRAM
input shift_v;
input s_in_v;
input [`DATA_WIDTH*2-1:0] s_in;
output p_out_v;
output [`PE_NUM*`DATA_WIDTH*2-1:... | 8.021671 |
module sip_interconnect(
input clk,
input rst_n,
input [:0] config_chipid_x,
input [:0] config_chipid_y,
<%
s = ""
for i in range(sip_nocs_num):
s += str_NEWS_intf(i) + '\n'
for i in range(soc_nocs_num):
s += (str_P_intf(i)) + '\n'
print(s[:-2])
%>
);
<%
s = ""
for i in range(sip_nocs_num)... | 6.693206 |
module sirena_policia (
input clk,
output reg speaker
);
reg [22:0] tone;
always @(posedge clk) tone <= tone + 1;
wire [ 6:0] ramp = (tone[22] ? tone[21:15] : ~tone[21:15]);
wire [14:0] clkdivider = {2'b01, ramp, 6'b000000};
reg [14:0] counter;
always @(posedge clk) begin
if (counter == 0) co... | 6.787059 |
module siren_generator (
input reset,
input clock,
output siren_out
);
parameter S_LOW_FREQ = 1'b0; //400hz- 67500 counts
parameter S_HIGH_FREQ = 1'b1; //700hz~ 38571 counts
parameter TWO_SECONDS = 25'd54000000;
parameter LOW_COUNT = 25'd67500;
parameter HIGH_COUNT = 25'd38572;
reg sir... | 8.347494 |
module: siren_generator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module siren_test;
// Inputs
reg siren_on;
reg clock;
reg reset;
// Outputs
wire siren_out;
// Instantiate ... | 7.419986 |
module control the 1 Cycle SRAM access requests
//
// ====================================================================
module sirv_1cyc_sram_ctrl #(
parameter DW = 32,
parameter MW = 4,
parameter AW = 32,
parameter AW_LSB = 3,
parameter USR_W = 3
)(
output sram_ctrl_active,
// The cgstop... | 7.626628 |
module sirv_aon_lclkgen_regs (
input clk,
input rst_n,
output lfxoscen,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [8 -1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input ... | 7.469129 |
module sirv_AsyncResetReg (
input d,
output reg q,
input en,
input clk,
input rst
);
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else if (en) begin
q <= d;
end
end
endmodule
| 7.02355 |
module sirv_AsyncResetRegVec (
input clock,
input reset,
input io_d,
output io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en (reg_0_en),
.q (reg_0_... | 7.02355 |
module sirv_AsyncResetRegVec_1 (
input clock,
input reset,
input [4:0] io_d,
output [4:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
... | 7.02355 |
module sirv_AsyncResetRegVec_36 (
input clock,
input reset,
input [2:0] io_d,
output [2:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
... | 7.02355 |
module sirv_DeglitchShiftRegister (
input clock,
input reset,
input io_d,
output io_q
);
reg T_8;
reg [31:0] GEN_0;
reg T_9;
reg [31:0] GEN_1;
reg sync;
reg [31:0] GEN_2;
reg last;
reg [31:0] GEN_3;
wire T_12;
assign io_q = T_12;
assign T_12 = sync & last;
always @(posedge clo... | 7.005769 |
module of the example APB slave
//
// ====================================================================
module sirv_expl_apb_slv #(
parameter AW = 32,
parameter DW = 32
)(
input [AW-1:0] apb_paddr,
input apb_pwrite,
input apb_pselx,
input apb_penable,
input [DW-1:0]... | 8.120395 |
module of the example AXI slave
//
// ====================================================================
module sirv_expl_axi_slv #(
parameter AW = 32,
parameter DW = 32
)(
input axi_arvalid,
output axi_arready,
input [AW-1:0] axi_araddr,
input [3:0] axi_arcache,
input [2:0] axi_arprot,
input... | 8.120395 |
module sirv_gnrl_pipe_stage #(
// When the depth is 1, the ready signal may relevant to next stage's ready, hence become logic
// chains. Use CUT_READY to control it
parameter CUT_READY = 0,
parameter DP = 1,
parameter DW = 32
) (
input i_vld,
output i_rdy,
input [DW-... | 8.495116 |
module
//
// ===========================================================================
module sirv_gnrl_sync # (
parameter DP = 2,
parameter DW = 32
) (
input [DW-1:0] din_a,
output [DW-1:0] dout,
input rst_n,
input clk
);
wire [DW-1:0] sync_dat [DP-1:0];
genvar i;
ge... | 6.874151 |
module for round-robin arbitration
//
// ===========================================================================
// ====================================================================
// Description:
// Verilog module sirv_gnrl cdc rx to receive the async handshake interface
//
// =============================... | 8.65877 |
module sirv_gnrl cdc tx to transmit the async handshake interface
//
// ===========================================================================
// Configuration-dependent macro definitions
//
module sirv_gnrl_cdc_tx
# (
parameter DW = 32,
parameter SYNC_DP = 2
) (
// The regular handshake interface at in-sid... | 9.033364 |
module as bypass buffer
//
// ====================================================================
module sirv_gnrl_bypbuf # (
parameter DP = 8,
parameter DW = 32
) (
input i_vld,
output i_rdy,
input [DW-1:0] i_dat,
output o_vld,
input o_rdy,
output [DW-1:0] o_da... | 6.92929 |
modules
//
// ====================================================================
//
//
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 1
//
// ===================================... | 6.530806 |
module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 0
//
// ===========================================================================
module sirv_gnrl_dfflr # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input ... | 7.450658 |
module sirv_gnrl DFF with Load-enable, no reset
//
// ===========================================================================
module sirv_gnrl_dffl # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk
);
reg [DW-1:0] qout_r;... | 7.450658 |
module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 1
//
// ===========================================================================
module sirv_gnrl_dffrs # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rs... | 7.450658 |
module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 0
//
// ===========================================================================
module sirv_gnrl_dffr # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst... | 7.450658 |
module to handle the simple-ICB bus to Wishbone bus conversion
// Note: in order to support the open source I2C IP, which is 8 bits
// wide bus and byte-addresable, so here this module is just ICB to
// wishbone 8-bits bus conversion
//
// =================================================================... | 8.375207 |
module to handle the simple-ICB bus to APB bus conversion
//
// ===========================================================================
module sirv_gnrl_icb2apb # (
parameter AW = 32,
parameter FIFO_OUTS_NUM = 8,
parameter FIFO_CUT_READY = 0,
parameter DW = 64 // 64 or 32 bits
) (
input i_i... | 8.375207 |
module
//
// ====================================================================
module sirv_gnrl_ram
#(parameter DP = 32,
parameter DW = 32,
parameter FORCE_X2ZERO = 1,
parameter MW = 4,
parameter AW = 15
) (
input sd,
input ds,
input ls,
input rst_n,
... | 6.874151 |
module sirv_LevelGateway (
input clock,
input reset,
input io_interrupt,
output io_plic_valid,
input io_plic_ready,
input io_plic_complete
);
reg inFlight;
reg [31:0] GEN_2;
wire T_12;
wire GEN_0;
wire GEN_1;
wire T_16;
wire T_17;
assign io_plic_valid = T_17;
assign T_12 =... | 6.638071 |
module is the mask ROM
//
// ====================================================================
module sirv_mrom # (
parameter AW = 12,
parameter DW = 32,
parameter DP = 1024
)(
input [AW-1:2] rom_addr,
output [DW-1:0] rom_dout
);
wire [31:0] mask_rom [0:DP-1];// 4KB = 1KW
assi... | 7.420294 |
module is to control the mask ROM
//
// ====================================================================
module sirv_mrom_top #(
parameter AW = 12,
parameter DW = 32,
parameter DP = 1024
)(
// * Bus cmd channel
input rom_icb_cmd_valid, // Handshake valid
output rom_icb_cmd_ready, // Handshak... | 7.154539 |
module of otp
//
// ====================================================================
module sirv_otp_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd... | 6.85414 |
module sirv_ResetCatchAndSync (
input clock,
input reset,
input test_mode,
output io_sync_reset
);
wire reset_n_catch_reg_clock;
wire reset_n_catch_reg_reset;
wire [2:0] reset_n_catch_reg_io_d;
wire [2:0] reset_n_catch_reg_io_q;
wire reset_n_catch_reg_io_en;
wire [1:0] T_6;
wire [2:0] T... | 7.151422 |
module sirv_ResetCatchAndSync_2 (
input clock,
input reset,
input test_mode,
output io_sync_reset
);
wire reset_n_catch_reg_clock;
wire reset_n_catch_reg_reset;
wire [19:0] reset_n_catch_reg_io_d;
wire [19:0] reset_n_catch_reg_io_q;
wire reset_n_catch_reg_io_en;
wire [18:0] T_6;
wire [1... | 7.151422 |
module sirv_sim1_ram #(
parameter DP = 512,
parameter FORCE_X2ZERO = 0,
parameter DW = 32,
parameter MW = 4,
parameter AW = 32
) (
input clk,
input [DW-1 : 0] din,
input [AW-1 : 0] addr,
input cs,
input we,
input [ MW-1:0] wem,
outp... | 7.890127 |
module sirv_sim_ram #(
parameter DP = 512,
parameter FORCE_X2ZERO = 0,
parameter DW = 32,
parameter MW = 4,
parameter AW = 32
) (
input clk,
input [DW-1 : 0] din,
input [AW-1 : 0] addr,
input cs,
input we,
input [ MW-1:0] wem,
outpu... | 8.126046 |
module sirv_uartgpioport (
input clock,
input reset,
input io_uart_txd,
output io_uart_rxd,
input io_pins_rxd_i_ival,
output io_pins_rxd_o_oval,
output io_pins_rxd_o_oe,
output io_pins_rxd_o_ie,
output io_pins_rxd_o_pue,
output io_pins_rxd_o_ds,
input io_pins_txd_i_ival,... | 6.56998 |
module sirv_uarttx (
input clock,
input reset,
input io_en,
output io_in_ready,
input io_in_valid,
input [7:0] io_in_bits,
output io_out,
input [15:0] io_div,
input io_nstop
);
reg [15:0] prescaler;
reg [31:0] GEN_6;
wire pulse;
reg [3:0] counter;
reg [31:0] GEN_7;
reg [8... | 6.760457 |
module SISA #(
parameter n = 8
) (
clk,
rst,
en,
poly,
seed,
Sin,
data
);
input clk, rst, en, Sin;
input [n - 1:0] seed;
input [n - 1:0] poly;
output reg [n - 1:0] data;
reg [23:0] test_data;
integer i;
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) data ... | 6.875935 |
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