code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sisc_tb_2;
parameter tclk = 10.0;
reg clk;
reg rst_f;
//reg [31:0] ir;
// component instantiation
// "uut" stands for "Unit Under Test"
sisc uut (
.CLK (clk),
.RST_F(rst_f)
);
// clock driver
initial begin
clk = 0;
end
always begin
#(tclk / 2);
clk = ~clk;
... | 6.985163 |
module sisc_tb;
parameter tclk = 10.0;
reg clk;
reg rst_f;
reg [31:0] ir;
// component instantiation
// "uut" stands for "Unit Under Test"
sisc uut (
clk,
rst_f,
ir
);
// clock driver
initial begin
clk = 0;
end
always begin
#(tclk / 2.0);
clk = ~c... | 7.799756 |
module sisc_tb;
parameter tclk = 10.0;
reg clk;
reg rst_f;
//reg[31:0] ir;
// component instantiation
// "uut" stands for "Unit Under Test"
//sisc uut (.clk (clk),
// .rst_f (rst_f),
// .ir (ir));
sisc uut (
clk,
rst_f,
);
// clock driver
initial begin... | 7.799756 |
module sisc_tb;
parameter tclk = 10.0;
reg clk;
reg rst_f;
// component instantiation
// "uut" stands for "Unit Under Test"
// sisc uut (.clk (clk),
// .rst_f (rst_f),
// .ir (ir));
sisc uut (
clk,
rst_f
);
// clock driver
initial begin
clk = 0;
end
... | 7.799756 |
module main (
input J1,
output J3,
input CLKIN
);
wire inst0_O;
SISO1 inst0 (
.I (J1),
.O (inst0_O),
.CLK(CLKIN)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module main (
input J1,
output J3,
input CLKIN
);
wire inst0_O;
SISO2 inst0 (
.I (J1),
.O (inst0_O),
.CLK(CLKIN)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module main (
input J1,
output J3,
input CLKIN
);
wire inst0_O;
SISO3 inst0 (
.I (J1),
.O (inst0_O),
.CLK(CLKIN)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module main (
input J1,
output J3,
input CLKIN
);
wire inst0_O;
SISO4 inst0 (
.I (J1),
.O (inst0_O),
.CLK(CLKIN)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module main (
input J1,
output J3,
input CLKIN
);
wire inst0_O;
SISO5 inst0 (
.I (J1),
.O (inst0_O),
.CLK(CLKIN)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module main (
input J1,
output J3,
input CLKIN
);
wire inst0_O;
SISO6 inst0 (
.I (J1),
.O (inst0_O),
.CLK(CLKIN)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module main (
input J1,
output J3,
input CLKIN
);
wire inst0_O;
SISO7 inst0 (
.I (J1),
.O (inst0_O),
.CLK(CLKIN)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module main (
input J1,
output J3,
input CLKIN
);
wire inst0_O;
SISO8 inst0 (
.I (J1),
.O (inst0_O),
.CLK(CLKIN)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module for a simple serial in serial out
* left shifter
* -----------------------------------------------------------------------------------
MIT License
Copyright (c) 2020 k-sva
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated ... | 9.18418 |
module siso_right_Nb #(
parameter BUS_WIDTH = 8,
SISO_WIDTH = 4
) (
input RST,
input CLK,
input RSHIFT,
input [BUS_WIDTH-1:0] IN,
output [BUS_WIDTH-1:0] OUT
);
reg [BUS_WIDTH-1:0] siso_mem_p[SISO_WIDTH-1:0], siso_mem_n[SISO_WIDTH-1:0];
integer i = 0, j = 0;
always @(*) begin
if (... | 6.96141 |
module SISO_Shift_Register (
Sin,
Sout,
Clock,
Reset
);
input Sin, Clock, Reset;
output reg Sout;
reg [2:0] Q;
always @(posedge Clock or negedge Reset) begin
if (!Reset) begin
Sout <= 1'b0;
Q <= 3'b0;
end else if (Reset) begin
Sout <= Q[0];
Q[0] <= Q[1];
Q[1... | 6.735684 |
module siso_tb ();
// Signal Decleration
reg clk_i;
reg rst_i;
reg data_i;
wire data_o;
// Instantiation
siso dut (
.clk_i (clk_i),
.rst_i (rst_i),
.data_i(data_i),
.data_o(data_o)
);
// Clock generation
initial begin
clk_i = 1'b0;
forever #5 clk_i = ~clk_i;
e... | 7.30903 |
module Sistema;
// uno degli ogetti e' una variabile binaria di tipo wire (cioe' associata
// a un filo) e di nome locale w
wire w;
// oggetto di tipo Trasmettitore e di nome locale T
Trasmettitore T (w);
// oggetto di tipo Ricevitore e di nome locale R
Ricevitore R (x);
endmodule
| 6.600492 |
module Trasmettitore (
z
);
// questo statement ci dice poi che la variabile z e' una variabile di
// uscita associata a un filo
output z;
// descrizione della struttura interna
endmodule
| 7.552044 |
module Ricevitore (
x
);
// questo statement ci dice poi che questa variabile e' una variabile di
// ingresso associata a un filo
input x;
// descrizione della struttura interna
endmodule
| 6.714018 |
module SISO_Shift_Register_TB;
reg Sin;
reg Clock;
reg Reset;
wire Sout;
integer count;
SISO_Shift_Register uut (
.Sin (Sin),
.Sout (Sout),
.Clock(Clock),
.Reset(Reset)
);
initial $monitor("Clock Pulse = %d | Reset = %b | Sin = %b | SOut = %b", count, Reset, Sin, Sout);
init... | 6.735684 |
module SIT9122 (
output OE_ST,
input OUTN,
input OUTP,
input oe,
output clkp,
output clkn
);
// pin OUTN is MGTREFCLK0N_116 bank 116 bus_bmb7_Y4[1] D5
// pin OUTP is MGTREFCLK0P_116 bank 116 bus_bmb7_Y4[0] D6
// pin OE_ST is IO_L10P_T1_16 bank 16 bus_... | 6.516756 |
module adder (
a,
b,
cin,
s,
cout
);
input a, b, cin;
output cout, s;
assign s = a ^ b ^ cin;
assign cout = (a & b) | (a ^ b) & cin;
endmodule
| 7.4694 |
module six (
A,
B,
C,
F,
COUT
);
input [3:0] A, B;
input C;
output [3:0] F;
output COUT;
wire C1, C2, C3;
adder add1 (
A[0],
B[0],
C,
F[0],
C1
);
adder add2 (
A[1],
B[1],
C1,
F[1],
C2
);
adder add3 (
A[2],
B[... | 6.989162 |
module sixbitadd (
a,
b,
sum,
overflow
);
input [5:0] a;
input [5:0] b;
output [5:0] sum;
output overflow;
wire [5:0] carry;
fulladder fad1 (
a[0],
b[0],
0,
carry[0],
sum[0]
);
fulladder fad2 (
a[1],
b[1],
carry[0],
carry[1],
... | 6.729026 |
module SixBitCounterAsync (
clk,
resetn,
enable,
q
);
input clk;
input resetn;
input enable;
output [5:0] q;
T_FF_with_Enable_Async Five (
clk,
resetn,
enable,
q[0] & q[1] & q[2] & q[3] & q[4],
q[5]
);
T_FF_with_Enable_Async Four (
clk,
resetn,
... | 7.089739 |
module sixbitdiv (
dividend,
divisor,
quotient,
remainder,
err
);
input [5:0] dividend;
input [5:0] divisor;
output [5:0] quotient;
output [5:0] remainder;
output err;
wire [5:0] posdividend;
wire [5:0] posdivisor;
wire [5:0] posquotient;
wire [5:0] posremainder;
wire [5:0] sub... | 6.899618 |
module sixbitexp (
ain,
out,
overflow
);
input [5:0] ain;
output [5:0] out;
output overflow;
//We have to calculate 1 + ain + ain^2 / 2!;
wire [5:0] sum;
wire [3:0] ovf;
wire [5:0] pow;
wire [5:0] divisor;
wire [5:0] remainder;
sixbitadd add1 (
1,
ain,
sum,
ovf... | 6.539328 |
module sixbitpow (
ain,
bin,
out,
overflow
);
input [5:0] ain;
input [5:0] bin;
output [5:0] out;
output overflow;
wire [9:0] ovf;
wire [5:0] pow [10:0];
assign pow[0] = 1;
generate
genvar i;
for (i = 0; i < 10; i = i + 1) begin
sixbitmul mul1 (
pow[i],
... | 6.815072 |
module sixbitsub (
ain,
bin,
diff,
overflow
);
input [5:0] ain;
input [5:0] bin;
output [5:0] diff;
output overflow;
wire [5:0] notb = ~bin + 1;
sixbitadd ad1 (
ain,
notb,
diff,
overflow
);
endmodule
| 7.02238 |
module sixbittan (
ain,
out,
overflow
);
input [5:0] ain;
output [5:0] out;
output overflow;
//We have to calculate x + x^3 / 3 + 2 * x^5 / 15;
wire [6:0] ovf;
wire [5:0] pow_1;
wire [5:0] pow_2;
wire [5:0] divisor1;
wire [5:0] remainder1;
wire [5:0] divisor2;
wire [5:0] remainder2;
... | 6.678113 |
module nFdiv (
rst,
clk,
count,
out
);
input rst, clk;
input [31:0] count;
output reg out;
reg [31:0] counter;
always @(posedge clk or posedge rst) begin
if (rst) begin
counter <= 32'b0;
out <= 1'b0;
end else if (counter == count) begin
out <= ~out;
counter <= 3... | 7.777938 |
module nsDelay (
rst,
clk,
timeout
);
input rst, clk;
output reg timeout;
reg [31:0] counter;
always @(posedge clk, posedge rst) begin
if (rst) begin
counter <= 32'b0;
timeout <= 1'b0;
end
else if(counter == 32'd120000000)//32'd6
begin
timeout <= ~timeout;
coun... | 7.229897 |
module sixteen (
sw,
rst,
clk,
clk_O
);
input rst, clk;
input [1:0] sw;
output reg clk_O;
wire [31:0] count00, count01, count10;
assign count00 = 32'd20000000; //9
assign count01 = 32'd10000000; //4
assign count10 = 32'd5000000; //1
wire out00, out01, out10, timeout;
nFdiv Fdiv00 (
... | 6.818656 |
module ha (
input a,
b,
output s,
c
);
xor g1 (s, a, b);
and g2 (c, a, b);
endmodule
| 7.857591 |
module sixteen_bit (
input [4:0] select,
input [15:0] a,
input [15:0] b,
input Cin,
output Cout,
output [15:0] y
);
wire wcar[14:0];
one_bit
bit0 (
select,
a[0],
b[0],
a[15],
Cin,
a[1],
a[1],
Cin,
... | 6.577219 |
module sixteen_bit_tb;
wire [15:0] t_y;
wire t_Cout;
reg [4:0] t_select = 5'b00000;
reg [15:0] t_a;
reg [15:0] t_b;
reg t_Cin;
sixteen_bit dut (
.select(t_select),
.a(t_a),
.b(t_b),
.Cin(t_Cin),
.Cout(t_Cout),
.y(t_y)
);
initial begin
$monitor(t_a, t_b, t_Cin,... | 6.802558 |
module priority_encoder (
input [15:0] r,
output reg [3:0] code,
output reg active
);
always @*
fork
if (r[15] == 1'b1) code = 4'b1111;
else if (r[14] == 1'b1) code = 4'b1110;
else if (r[13] == 1'b1) code = 4'b1101;
else if (r[12] == 1'b1) code = 4'b1100;
else if (r[11] == 1'b1) co... | 7.114361 |
module sixthadd (
input [15:0] A,
B,
input c0,
output [15:0] S,
output c16,
output [15:0] G,
P
);
wire [16:0] ic;
genvar j;
generate
for (j = 0; j <= 12; j = j + 4) begin : row
fourbitadd SFA (
A[(j+3):j],
B[(j+3):j],
ic[j],
S[(j+3):j],... | 6.53154 |
module sixtyFour_reg #(
parameter n = 64
) (
input clk,
input S,
input [n-1:0] in,
input rst,
output [n-1:0] Q
);
genvar i;
generate
for (i = 0; i < n; i = i + 1) begin
onebitReg mod1 (
in[i],
S,
clk,
rst,
Q[i]
);
end
en... | 7.68434 |
module implements a multiplexor with six 16bit inputs.
// Dependencies: N/A
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sixway_16bitmux(in0,in1,in2,in3,in4,in5,sel,out);
input [2:0] sel;
input... | 6.904081 |
module creates a 6:3 compressor, it generates 3 signals out of 6 signals
// that can be used with 2 dsp blocks to implement a 6-input adder.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////... | 8.132522 |
module six_bit_adder (
a,
b,
carry_a,
sum,
carry
);
input [4:0] a;
input [3:0] b;
input carry_a;
output [5:0] sum;
output carry;
wire [5:0] sum;
wire carry;
wire c0, c1, c2, c3, c4;
full_adder FA0 (
a[0],
b[0],
1'b0,
sum[0],
c0
);
full_adder FA1 (... | 6.826936 |
module: six_bit_adder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module six_bit_adder_top;
// Inputs
reg [4:0] a;
reg [3:0] b;
reg carry_a;
// Outputs
wire [5:0] sum;
wire car... | 7.032037 |
module six_bit_to_8bit (
input wire [5:0] in,
output wire [7:0] out
);
//use 6 bit number but add two zeros on at the end so they
//still convert to the same decimal number and inequality holds true
assign out[7] = 0;
assign out[6] = 0;
assign out[5] = in[5];
assign out[4] = in[4];
assign out[3... | 7.312209 |
module six_input_adder #(
parameter WIDTH_IN = 45, // input bit width
WIDTH_OUT = 48 // output bit width
) (
input wire clk,
reset, // clock and reset siganls
input wire [WIDTH_IN-1:0] A,
B,
C,
D,
E,
F,
output wire [WIDTH_OUT-1:0] SUM
);
// Internal Signals declaration:... | 6.917835 |
module six_not_gate #(
parameter DELAY = 10
) (
input wire a1,
a2,
a3,
a4,
a5,
a6,
output wire y1,
y2,
y3,
y4,
y5,
y6
);
not #DELAY (y1, a1);
not #DELAY (y2, a2);
not #DELAY (y3, a3);
not #DELAY (y4, a4);
not #DELAY (y5, a5);
not #DELAY (y6, a6);
endmod... | 7.09002 |
module main; //: root_module
wire [7:0] w6; //: /sn:0 {0}#(693,390)(693,405){1}
wire w7; //: /sn:0 {0}(374,112)(389,112){1}
wire w14; //: /sn:0 {0}#(498,77)(483,77){1}
wire w4; //: /sn:0 {0}(409,529)(424,529){1}
wire w15; //: /sn:0 {0}#(392,82)(407,82){1}
wire w0; //: /sn:0 {0}(140,135)(155,135){1}
... | 6.5859 |
module generic_fifo_sc_a (
clk,
rst,
clr,
din,
we,
dout,
re,
full,
empty,
full_n,
empty_n,
full_r,
empty_r,
full_n_r,
empty_n_r,
level
);
/*
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
*/
input clk, rst, clr;
input [`... | 6.701278 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module generic_fifo_sc_b (
clk,
rst,
clr,
din,
we,
dout,
re,
full,
empty,
full_n,
empty_n,
full_r,
empty_r,
full_n_r,
empty_n_r,
level
);
/*
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
*/
input clk, rst, clr;
input [`... | 6.701278 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module generic_fifo_sc_c (
clk,
rst,
clr,
din,
we,
dout,
re,
full,
empty,
full_n,
empty_n,
full_r,
empty_r,
full_n_r,
empty_n_r,
level
);
/*
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
*/
input clk, rst, clr;
input [`... | 6.701278 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module generic_fifo_sc_x (
clk,
rst,
clr,
din,
we,
dout,
re,
full,
empty,
full_n,
empty_n,
full_r,
empty_r,
full_n_r,
empty_n_r,
level
);
/*
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
*/
input clk, rst, clr;
input [`... | 6.701278 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module sizetest (
input clock,
input reset,
input enable,
input [15:0] xi,
input [15:0] yi,
input [15:0] zi,
output [15:0] xo,
output [15:0] yo,
output [15:0] zo
// input [15:0] constant
);
wire [16:0] zo;
cordic_stage cordic_stage (
clock,
reset,
enab... | 6.650253 |
module size_fifo (
input wclk,
input rclk,
input resetn,
input [2:0] data_in,
input write_en,
input read_en,
output [2:0] data_out,
output full,
output empty
);
reg [2:0] ram [15:0];
reg [4:0] write_addr_wclk;
... | 7.66389 |
module SI_DEBOUNCE (
input SI_DEBOUNCE1_CLOCK_50,
SI_DEBOUNCE1_RESET_InLow,
SI_DEBOUNCE1_button_In, // inputs
output reg SI_DEBOUNCE1_button_Out // output
);
//// ---------------- internal constants --------------
parameter N = 11; // (2^ (21-1) )/ 38 MHz = ms debounce time
////----------... | 6.532196 |
module sjpll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire outclk_2, // outclk2.clk
output wire outclk_3, // outclk3.clk
output wire locked // locked.export
);
... | 7.025069 |
module sk (
upper,
lower,
a,
b,
c,
d
);
output upper, lower;
input a, b, c, d;
or (upper, a, b, c, d);
not (notC, c);
xor (lower, a, b, notC, d);
endmodule
| 6.873282 |
module skein_round (
input clk,
input [31:0] round,
input [511:0] p,
input [511:0] h,
input [63:0] t0,
input [63:0] t1,
output reg [511:0] po,
output reg [511:0] ho
);
reg [511:0] px, hx;
reg [63:0] t0x, t1x;
reg [31:0] roundx;
reg [63:0] p0, p1, p2, p3, p4, p5, p6, p7;
reg [... | 7.036381 |
module skein_round_1 (
input clk,
input even,
input [511:0] in,
output reg [511:0] out
);
wire [63:0] p0, p1, p2, p3, p4, p5, p6, p7;
wire [63:0] p0x, p1x, p2x, p3x, p4x, p5x, p6x, p7x;
assign p0 = in[511:448];
assign p1 = in[447:384];
assign p2 = in[383:320];
assign p3 = in[319:256];
... | 6.913726 |
module skein_round_2 (
input clk,
input even,
input [511:0] in,
output reg [511:0] out
);
wire [63:0] p0, p1, p2, p3, p4, p5, p6, p7;
wire [63:0] p0x, p1x, p2x, p3x, p4x, p5x, p6x, p7x;
assign p0 = in[511:448];
assign p1 = in[447:384];
assign p2 = in[383:320];
assign p3 = in[319:256];
... | 7.262194 |
module skein_round_3 (
input clk,
input even,
input [511:0] in,
output reg [511:0] out
);
wire [63:0] p0, p1, p2, p3, p4, p5, p6, p7;
wire [63:0] p0x, p1x, p2x, p3x, p4x, p5x, p6x, p7x;
assign p0 = in[511:448];
assign p1 = in[447:384];
assign p2 = in[383:320];
assign p3 = in[319:256];
... | 7.124852 |
module skein_round_4 (
input clk,
input even,
input [511:0] in,
output reg [511:0] out
);
wire [63:0] p0, p1, p2, p3, p4, p5, p6, p7;
wire [63:0] p0x, p1x, p2x, p3x, p4x, p5x, p6x, p7x;
assign p0 = in[511:448];
assign p1 = in[447:384];
assign p2 = in[383:320];
assign p3 = in[319:256];
... | 7.180182 |
module skein512_64_h_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 5;
parameter MEM_SIZE = 27;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
inp... | 7.284455 |
module skein512_64_h (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd27;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce... | 7.284455 |
module
// The round number used is 5.
module SkeinInjectKey_tb;
localparam STARTING_WORK = 2'b00, MIDDLE_SECTION = 2'b01, WAITING_ON_RESULTS = 2'b10;
genvar x;
// Reg
reg clk = 1'b0;
// Inputs
reg [1023:0] TestInput;
reg [1087:0] TestKey;
reg [191:0] TestType;
always #1 clk = ~clk;
wire [1023:0] ... | 6.562934 |
module SkeinMix8 (
output wire [511:0] OutEven,
output wire [511:0] OutOdd,
input wire [511:0] InEven,
input wire [511:0] InOdd
);
parameter R0 = 0, R1 = 0, R2 = 0, R3 = 0, R4 = 0, R5 = 0, R6 = 0, R7 = 0;
genvar x;
wire [511:0] TempEven, TempOdd;
for (x = 0; x < 8; x = x + 1) begin : MIXADD... | 6.980399 |
module!
*
* This skeleton file serves as a wrapper around the processor to provide certain control signals
* and interfaces to memory elements. This structure allows for easier testing, as it is easier to
* inspect which signals the processor tries to assert when.
*/
module skeleton_temp(clock, reset, imem_clock,... | 6.991097 |
module mux_2_5bit (
a,
b,
sel,
out
);
input [4:0] a, b;
input sel;
output [4:0] out;
assign out = sel ? b : a;
endmodule
| 7.730044 |
module mux_2_1bit (
a,
b,
sel,
out
);
input a, b;
input sel;
output out;
assign out = sel ? b : a;
endmodule
| 7.201898 |
module mux_2 (
a,
b,
sel,
out
);
input [31:0] a, b;
input sel;
output [31:0] out;
assign out = sel ? b : a;
endmodule
| 7.577158 |
module sketch (
CLOCK_50, // On Board 50 MHz
KEY, // Push Button[3:0]
SW, // DPDT Switch[17:0]
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK, // VGA BLANK
VGA_SYNC, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // ... | 8.212785 |
module colour_select (
user_given,
is_bottom,
colour,
resetn
);
input [2:0] user_given;
input is_bottom;
input resetn;
output reg [2:0] colour;
always @(*) begin
if (!resetn) colour <= 3'b000;
else if (is_bottom) colour <= ~user_given;
else colour <= user_given;
end
endmodule
| 7.125161 |
module binary_to_hex_7segDecoder (
n,
hex_decoder
);
input [3:0] n; // 4 bit binary number
output [6:0] hex_decoder; // to display a single digit of hex number
assign hex_decoder[0] = ~((n[0] & n[2] & (~n[3])) | ((~n[0]) & (~n[2])) | ((~n[0]) & n[3]) | (n[1] & n[2]) | (n[1] & (~n[3])) | ((~n[1]) & (~n[... | 7.148154 |
module
*/
module skew_adjust(
input Cal_ST,
input Cal_OL,
input Cal_FLAG,
input clk,
input rst,
input data_valid,
input [SF_WIDTH-1:0] chA_skew,
input [SF_WIDTH-1:0] chC_skew,
input [SF_WIDTH-1:0] chA_power,
input [SF_WIDTH-1:0] chC_power,
output reg [SF_WIDTH-1:0] chA_skew_adj,
output reg [SF_WI... | 6.980066 |
module en_reg #(
parameter DATA_WIDTH
) (
input clk,
input rst_n,
input en,
input [DATA_WIDTH - 1 : 0] din,
output [DATA_WIDTH - 1 : 0] dout
);
reg [DATA_WIDTH - 1 : 0] r;
always @(posedge clk) begin
if (rst_n) begin
if (en) begin
r <= din;
end
end else begin
... | 7.826276 |
module skew_registers #(
parameter DATA_WIDTH = 16,
parameter N = 4
) (
input clk,
input rst_n,
input en,
input signed [DATA_WIDTH - 1 : 0] din[N - 1 : 0],
output signed [DATA_WIDTH - 1 : 0] dout[N - 1 : 0]
);
wire [DATA_WIDTH - 1 : 0] d_w[N : 0][N - 1 : 0];
genvar y, x;
generate
... | 6.988406 |
module skew_registers_tb;
reg clk;
reg rst_n;
reg en_r;
reg signed [`DATA_WIDTH - 1 : 0] din_r[`N - 1 : 0];
wire signed [`DATA_WIDTH - 1 : 0] dout_w[`N - 1 : 0];
always #10 clk = ~clk;
skew_registers #(
.DATA_WIDTH(`DATA_WIDTH),
.N(`N)
) skew_resgiters_inst (
.clk(clk),
.rst_n... | 6.988406 |
module skid_buffer #(
parameter WORD_WIDTH = 0
) (
input wire clock,
// Slave interface
input wire s_valid,
output wire s_ready,
input wire [WORD_WIDTH-1:0] s_data,
// Master interface
output wire m_valid,
input wire ... | 8.065746 |
module skid_buffer_datapath #(
parameter WORD_WIDTH = 0
) (
input wire clock,
// Data
input wire [WORD_WIDTH-1:0] data_in,
output reg [WORD_WIDTH-1:0] data_out,
// Control
input wire data_out_wren,
input wire data_buffer_wren,
input wire use_buffered_data
);
// ---------------... | 8.123123 |
module skinny_sbox8_logic (
// Outputs
so,
// Inputs
si
);
output [7:0] so;
input [7:0] si;
wire [7:0] a;
skinny_sbox8_cfn b764 (
a[0],
si[7],
si[6],
si[4]
);
skinny_sbox8_cfn b320 (
a[1],
si[3],
si[2],
si[0]
);
skinny_sbox8_cfn b216 (
... | 6.768095 |
module skinny_sbox8_cfn (
// Outputs
f,
// Inputs
x,
y,
z
);
output f;
input x, y, z;
assign f = ((~x) & (~y)) ^ z;
endmodule
| 6.768095 |
module skinny_sbox8_logic (
// Outputs
so,
// Inputs
si
);
output [7:0] so;
input [7:0] si;
wire [7:0] a;
skinny_sbox8_cfn b764 (
a[0],
si[7],
si[6],
si[4]
);
skinny_sbox8_cfn b320 (
a[1],
si[3],
si[2],
si[0]
);
skinny_sbox8_cfn b216 (
... | 6.768095 |
module skinny_sbox8_cfn (
// Outputs
f,
// Inputs
x,
y,
z
);
output f;
input x, y, z;
assign f = ((~x) & (~y)) ^ z;
endmodule
| 6.768095 |
module skinny_sbox8_cms1_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal = "no"... | 6.768095 |
module skinny_sbox8_cms1_non_pipelined_de ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal = "... | 6.768095 |
module skinny_sbox8_cms1_rapid_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si0,
si1,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1;
(*equivalent_register_removal = "no" *) output [7:0] bo0;
(*equivalent_register_removal = "no" *) input [7:0] si... | 6.768095 |
module and4_cms1 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b,
c,
d,
r,
clk
);
output [1:0] z;
input [1:0] a, b, c, d;
input [15:0] r;
input clk;
(*equivalent_register_removal = "no" *) reg [15:0] comp;
always @(posedge clk) begin
comp[0] <= (a[0] & b[0] & c[0] & d[... | 6.645085 |
module and2_cms1 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b,
r,
clk
);
output [1:0] z;
input [1:0] a, b;
input [3:0] r;
input clk;
(*equivalent_register_removal = "no" *) reg [3:0] comp;
always @(posedge clk) begin
comp[0] <= (a[0] & b[0]) ^ r[0] ^ r[1];
comp[1] <= (a[... | 6.553996 |
module skinny_sbox8_cms1_rapid_non_pipelined_de ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si0,
si1,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1;
(*equivalent_register_removal = "no" *) output [7:0] bo0;
(*equivalent_register_removal = "no" *) input [7:0]... | 6.768095 |
module and4_cms1 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b,
c,
d,
r,
clk
);
output [1:0] z;
input [1:0] a, b, c, d;
input [15:0] r;
input clk;
(*equivalent_register_removal = "no" *) reg [15:0] comp;
always @(posedge clk) begin
comp[0] <= (a[0] & b[0] & c[0] & d[... | 6.645085 |
module and2_cms1 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b,
r,
clk
);
output [1:0] z;
input [1:0] a, b;
input [3:0] r;
input clk;
(*equivalent_register_removal = "no" *) reg [3:0] comp;
always @(posedge clk) begin
comp[0] <= (a[0] & b[0]) ^ r[0] ^ r[1];
comp[1] <= (a[... | 6.553996 |
module skinny_sbox8_dom1_dep_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal = ... | 6.768095 |
module skinny_sbox8_dom1_dep_non_pipelined_de ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal... | 6.768095 |
module skinny_sbox8_dom1_less_reg_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_remov... | 6.768095 |
module skinny_sbox8_dom1_less_reg_non_pipelined_de ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_re... | 6.768095 |
module skinny_sbox8_dom1_non_pipelined ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal = "no"... | 6.768095 |
module skinny_sbox8_dom1_non_pipelined_de ( /*AUTOARG*/
// Outputs
bo1,
bo0,
// Inputs
si1,
si0,
r,
clk
);
(*equivalent_register_removal = "no" *) output [7:0] bo1; // share 1
(*equivalent_register_removal = "no" *) output [7:0] bo0; // share 0
(*equivalent_register_removal = "... | 6.768095 |
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