code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module sky130_fd_sc_hdll__a221oi_4 (
Y,
A1,
A2,
B1,
B2,
C1
);
output Y;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a221oi base (
.Y (Y),
.A1(A1),
... | 7.212805 |
module sky130_fd_sc_hdll__a222oi (
Y,
A1,
A2,
B1,
B2,
C1,
C2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nand0_... | 7.212805 |
module sky130_fd_sc_hdll__a222oi (
Y,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire nand0_out;
w... | 7.212805 |
module sky130_fd_sc_hdll__a222oi (
Y,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a222oi (
Y,
A1,
A2,
B1,
B2,
C1,
C2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nand0_... | 7.212805 |
module sky130_fd_sc_hdll__a222oi (
Y,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Local signals
wire nand0_out;
wire nand1_out;
wire nand2_out;
wire and0_out_Y;
// Name Output Other... | 7.212805 |
module sky130_fd_sc_hdll__a222oi (
Y,
A1,
A2,
B1,
B2,
C1,
C2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a222oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
input C2,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a222oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
input C2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a222oi_1 (
Y,
A1,
A2,
B1,
B2,
C1,
C2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a222oi base (
.Y(Y),
... | 7.212805 |
module sky130_fd_sc_hdll__a222oi_1 (
Y,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a222oi base (
.Y (Y),
... | 7.212805 |
module sky130_fd_sc_hdll__a22o (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire and1_out;
wire or0_out_X;
w... | 7.212805 |
module sky130_fd_sc_hdll__a22o (
X,
A1,
A2,
B1,
B2
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire and1_out;
wire or0_out_X;
// Name... | 7.212805 |
module sky130_fd_sc_hdll__a22o (
X,
A1,
A2,
B1,
B2
);
output X;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a22o (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire and1_out;
wire or0_out_X;
w... | 7.212805 |
module sky130_fd_sc_hdll__a22o (
X,
A1,
A2,
B1,
B2
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire and0_out;
wire and1_out;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out, B1, B2);
and and1 (and1_out, A1... | 7.212805 |
module sky130_fd_sc_hdll__a22o (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a22oi (
Y,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nand0_out;
wire nand1_out;
wire and0_out_Y;... | 7.212805 |
module sky130_fd_sc_hdll__a22oi (
Y,
A1,
A2,
B1,
B2
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire nand0_out;
wire nand1_out;
wire and0_out_Y;
// ... | 7.212805 |
module sky130_fd_sc_hdll__a22oi (
Y,
A1,
A2,
B1,
B2
);
output Y;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a22oi (
Y,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nand0_out;
wire nand1_out;
wire and0_out_Y;... | 7.212805 |
module sky130_fd_sc_hdll__a22oi (
Y,
A1,
A2,
B1,
B2
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nand0_out;
wire nand1_out;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, A2, A1);
nand nand1 (... | 7.212805 |
module sky130_fd_sc_hdll__a22oi (
Y,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a22oi_1 (
Y,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)... | 7.212805 |
module sky130_fd_sc_hdll__a22oi_1 (
Y,
A1,
A2,
B1,
B2
);
output Y;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a22oi base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1... | 7.212805 |
module sky130_fd_sc_hdll__a22oi_2 (
Y,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)... | 7.212805 |
module sky130_fd_sc_hdll__a22oi_2 (
Y,
A1,
A2,
B1,
B2
);
output Y;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a22oi base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1... | 7.212805 |
module sky130_fd_sc_hdll__a22oi_4 (
Y,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)... | 7.212805 |
module sky130_fd_sc_hdll__a22oi_4 (
Y,
A1,
A2,
B1,
B2
);
output Y;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a22oi base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1... | 7.212805 |
module sky130_fd_sc_hdll__a22o_1 (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
... | 7.212805 |
module sky130_fd_sc_hdll__a22o_1 (
X,
A1,
A2,
B1,
B2
);
output X;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a22o base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1),... | 7.212805 |
module sky130_fd_sc_hdll__a22o_2 (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
... | 7.212805 |
module sky130_fd_sc_hdll__a22o_2 (
X,
A1,
A2,
B1,
B2
);
output X;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a22o base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1),... | 7.212805 |
module sky130_fd_sc_hdll__a22o_4 (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
... | 7.212805 |
module sky130_fd_sc_hdll__a22o_4 (
X,
A1,
A2,
B1,
B2
);
output X;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a22o base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1),... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2o (
X,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire nor0_out;
wire or0_... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2o (
X,
A1_N,
A2_N,
B1,
B2
);
// Module ports
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire nor0_out;
wire or0_out_X;
... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2o (
X,
A1_N,
A2_N,
B1,
B2
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a2bb2o (
X,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire nor0_out;
wire or0_... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2o (
X,
A1_N,
A2_N,
B1,
B2
);
// Module ports
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Local signals
wire and0_out;
wire nor0_out;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out, B1, B2);
nor nor0 (no... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2o (
X,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1,
input B2,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi (
Y,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire nor0_out;
wire nor... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi (
Y,
A1_N,
A2_N,
B1,
B2
);
// Module ports
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire nor0_out;
wire nor1_out_Y;... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi (
Y,
A1_N,
A2_N,
B1,
B2
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi (
Y,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire nor0_out;
wire nor... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi (
Y,
A1_N,
A2_N,
B1,
B2
);
// Module ports
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
// Local signals
wire and0_out;
wire nor0_out;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out, B1, B2);
nor nor0 ... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi (
Y,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1,
input B2,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi_1 (
Y,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi_1 (
Y,
A1_N,
A2_N,
B1,
B2
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi_2 (
Y,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi_2 (
Y,
A1_N,
A2_N,
B1,
B2
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi_4 (
Y,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2oi_4 (
Y,
A1_N,
A2_N,
B1,
B2
);
output Y;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2o_1 (
X,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2o_1 (
X,
A1_N,
A2_N,
B1,
B2
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2o_2 (
X,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2o_2 (
X,
A1_N,
A2_N,
B1,
B2
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2o_4 (
X,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2... | 7.212805 |
module sky130_fd_sc_hdll__a2bb2o_4 (
X,
A1_N,
A2_N,
B1,
B2
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2... | 7.212805 |
module sky130_fd_sc_hdll__a31o (
X,
A1,
A2,
A3,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input A3;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire or0_out_X;
wire pwrgood_pp0_o... | 7.212805 |
module sky130_fd_sc_hdll__a31o (
X,
A1,
A2,
A3,
B1
);
// Module ports
output X;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire or0_out_X;
// Name Output Othe... | 7.212805 |
module sky130_fd_sc_hdll__a31o (
X,
A1,
A2,
A3,
B1
);
output X;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a31o (
X,
A1,
A2,
A3,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input A3;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire or0_out_X;
wire pwrgood_pp0_o... | 7.212805 |
module sky130_fd_sc_hdll__a31o (
X,
A1,
A2,
A3,
B1
);
// Module ports
output X;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire and0_out;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out, A3, A1, A2);
or or0 (or0_out_X, and0_out, B1);
... | 7.212805 |
module sky130_fd_sc_hdll__a31o (
X,
A1,
A2,
A3,
B1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input A3;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a31o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a31o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a31oi (
Y,
A1,
A2,
A3,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input A3;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire nor0_out_Y;
wire pwrgood_pp0... | 7.212805 |
module sky130_fd_sc_hdll__a31oi (
Y,
A1,
A2,
A3,
B1
);
// Module ports
output Y;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire nor0_out_Y;
// Name Output O... | 7.212805 |
module sky130_fd_sc_hdll__a31oi (
Y,
A1,
A2,
A3,
B1
);
output Y;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a31oi (
Y,
A1,
A2,
A3,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input A3;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire nor0_out_Y;
wire pwrgood_pp0... | 7.212805 |
module sky130_fd_sc_hdll__a31oi (
Y,
A1,
A2,
A3,
B1
);
// Module ports
output Y;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire and0_out;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out, A3, A1, A2);
nor nor0 (nor0_out_Y, B1, and0_o... | 7.212805 |
module sky130_fd_sc_hdll__a31oi (
Y,
A1,
A2,
A3,
B1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input A3;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a31oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a31oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a31oi_1 (
Y,
A1,
A2,
A3,
B1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input A3;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3)... | 7.212805 |
module sky130_fd_sc_hdll__a31oi_1 (
Y,
A1,
A2,
A3,
B1
);
output Y;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a31oi base (
.Y (Y),
.A1(A1),
.A2(A2),
.A3(A3... | 7.212805 |
module sky130_fd_sc_hdll__a31oi_2 (
Y,
A1,
A2,
A3,
B1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input A3;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3)... | 7.212805 |
module sky130_fd_sc_hdll__a31oi_2 (
Y,
A1,
A2,
A3,
B1
);
output Y;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a31oi base (
.Y (Y),
.A1(A1),
.A2(A2),
.A3(A3... | 7.212805 |
module sky130_fd_sc_hdll__a31oi_4 (
Y,
A1,
A2,
A3,
B1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input A3;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3)... | 7.212805 |
module sky130_fd_sc_hdll__a31oi_4 (
Y,
A1,
A2,
A3,
B1
);
output Y;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a31oi base (
.Y (Y),
.A1(A1),
.A2(A2),
.A3(A3... | 7.212805 |
module sky130_fd_sc_hdll__a31o_1 (
X,
A1,
A2,
A3,
B1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input A3;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
... | 7.212805 |
module sky130_fd_sc_hdll__a31o_1 (
X,
A1,
A2,
A3,
B1
);
output X;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a31o base (
.X (X),
.A1(A1),
.A2(A2),
.A3(A3),... | 7.212805 |
module sky130_fd_sc_hdll__a31o_2 (
X,
A1,
A2,
A3,
B1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input A3;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
... | 7.212805 |
module sky130_fd_sc_hdll__a31o_2 (
X,
A1,
A2,
A3,
B1
);
output X;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a31o base (
.X (X),
.A1(A1),
.A2(A2),
.A3(A3),... | 7.212805 |
module sky130_fd_sc_hdll__a31o_4 (
X,
A1,
A2,
A3,
B1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input A3;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
... | 7.212805 |
module sky130_fd_sc_hdll__a31o_4 (
X,
A1,
A2,
A3,
B1
);
output X;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__a31o base (
.X (X),
.A1(A1),
.A2(A2),
.A3(A3),... | 7.212805 |
module sky130_fd_sc_hdll__a32o (
X,
A1,
A2,
A3,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input A3;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire and1_out;
... | 7.212805 |
module sky130_fd_sc_hdll__a32o (
X,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire and1_out;
wire or... | 7.212805 |
module sky130_fd_sc_hdll__a32o (
X,
A1,
A2,
A3,
B1,
B2
);
output X;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__a32o (
X,
A1,
A2,
A3,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input A3;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire and1_out;
... | 7.212805 |
module sky130_fd_sc_hdll__a32o (
X,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire and0_out;
wire and1_out;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out, A3, A1, A2);
... | 7.212805 |
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