code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hdll__and4bb (
X,
A_N,
B_N,
C,
D
);
// Module ports
output X;
input A_N;
input B_N;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire nor0_out;
wire and0_out_X;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__and4bb (
X,
A_N,
B_N,
C,
D
);
output X;
input A_N;
input B_N;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__and4bb (
X,
A_N,
B_N,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A_N;
input B_N;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nor0_out;
wire and0_out_X;
wire pwrgood_pp... | 7.212805 |
module sky130_fd_sc_hdll__and4bb (
X,
A_N,
B_N,
C,
D
);
// Module ports
output X;
input A_N;
input B_N;
input C;
input D;
// Local signals
wire nor0_out;
wire and0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out, A_N, B_N);
and and0 (and0_out_X, nor0_out, C... | 7.212805 |
module sky130_fd_sc_hdll__and4bb (
X,
A_N,
B_N,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A_N;
input B_N;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__and4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C,
input D,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__and4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C,
input D,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__and4bb_1 (
X,
A_N,
B_N,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A_N;
input B_N;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.... | 7.212805 |
module sky130_fd_sc_hdll__and4bb_1 (
X,
A_N,
B_N,
C,
D
);
output X;
input A_N;
input B_N;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__and4bb base (
.X (X),
.A_N(A_N),
.B_N(B_N),
... | 7.212805 |
module sky130_fd_sc_hdll__and4bb_2 (
X,
A_N,
B_N,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A_N;
input B_N;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.... | 7.212805 |
module sky130_fd_sc_hdll__and4bb_2 (
X,
A_N,
B_N,
C,
D
);
output X;
input A_N;
input B_N;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__and4bb base (
.X (X),
.A_N(A_N),
.B_N(B_N),
... | 7.212805 |
module sky130_fd_sc_hdll__and4bb_4 (
X,
A_N,
B_N,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A_N;
input B_N;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.... | 7.212805 |
module sky130_fd_sc_hdll__and4bb_4 (
X,
A_N,
B_N,
C,
D
);
output X;
input A_N;
input B_N;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__and4bb base (
.X (X),
.A_N(A_N),
.B_N(B_N),
... | 7.212805 |
module sky130_fd_sc_hdll__and4b_1 (
X,
A_N,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A_N;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
... | 7.212805 |
module sky130_fd_sc_hdll__and4b_1 (
X,
A_N,
B,
C,
D
);
output X;
input A_N;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__and4b base (
.X (X),
.A_N(A_N),
.B (B),
.C (C)... | 7.212805 |
module sky130_fd_sc_hdll__and4b_2 (
X,
A_N,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A_N;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
... | 7.212805 |
module sky130_fd_sc_hdll__and4b_2 (
X,
A_N,
B,
C,
D
);
output X;
input A_N;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__and4b base (
.X (X),
.A_N(A_N),
.B (B),
.C (C)... | 7.212805 |
module sky130_fd_sc_hdll__and4b_4 (
X,
A_N,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A_N;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
... | 7.212805 |
module sky130_fd_sc_hdll__and4b_4 (
X,
A_N,
B,
C,
D
);
output X;
input A_N;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__and4b base (
.X (X),
.A_N(A_N),
.B (B),
.C (C)... | 7.212805 |
module sky130_fd_sc_hdll__and4_1 (
X,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
... | 7.212805 |
module sky130_fd_sc_hdll__and4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
... | 7.212805 |
module sky130_fd_sc_hdll__and4_2 (
X,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
... | 7.212805 |
module sky130_fd_sc_hdll__and4_2 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
... | 7.212805 |
module sky130_fd_sc_hdll__and4_4 (
X,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
... | 7.212805 |
module sky130_fd_sc_hdll__and4_4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
... | 7.212805 |
module sky130_fd_sc_hdll__buf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output O... | 7.212805 |
module sky130_fd_sc_hdll__buf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule... | 7.212805 |
module sky130_fd_sc_hdll__buf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output O... | 7.212805 |
module sky130_fd_sc_hdll__buf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufbuf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__bufbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmod... | 7.212805 |
module sky130_fd_sc_hdll__bufbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufbuf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__bufbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufbuf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufbuf (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufbuf_16 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__bufbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufbuf_8 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__bufbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufinv (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__bufinv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
buf buf0 (Y, not0_out_Y);
endmod... | 7.212805 |
module sky130_fd_sc_hdll__bufinv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufinv (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__bufinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
buf buf0 (Y, not0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufinv (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufinv (
//# {{data|Data Signals}}
input A,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufinv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufinv_16 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufinv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__bufinv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufinv_8 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__bufinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__bufinv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_12 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_12 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_16 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_4 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_6 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_6 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_8 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__buf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__clkbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmod... | 7.212805 |
module sky130_fd_sc_hdll__clkbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__clkbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_12 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_12 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_16 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_4 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_6 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_6 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_8 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
buf buf0 (Y, not0_out_Y);
endmod... | 7.212805 |
module sky130_fd_sc_hdll__clkinv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
buf buf0 (Y, not0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv (
//# {{data|Data Signals}}
input A,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
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