code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module sky130_fd_sc_hdll__nand4b_4 (
Y,
A_N,
B,
C,
D
);
output Y;
input A_N;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nand4b base (
.Y (Y),
.A_N(A_N),
.B (B),
.C (C),
.D (D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nand4_1 (
Y,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nand4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nand4_2 (
Y,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nand4_2 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nand4_4 (
Y,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nand4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B);
buf buf0 (Y, nor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B);
buf buf0 (Y, nor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b (
Y,
A,
B_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out;
wire and0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out, A);
and and0 (and0_out_Y, not0_out, B_N);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
and0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b (
Y,
A,
B_N
);
// Module ports
output Y;
input A;
input B_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire not0_out;
wire and0_out_Y;
// Name Output Other arguments
not not0 (not0_out, A);
and and0 (and0_out_Y, not0_out, B_N);
buf buf0 (Y, and0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b (
Y,
A,
B_N
);
output Y;
input A;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b (
Y,
A,
B_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out;
wire and0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out, A);
and and0 (and0_out_Y, not0_out, B_N);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
and0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b (
Y,
A,
B_N
);
// Module ports
output Y;
input A;
input B_N;
// Local signals
wire not0_out;
wire and0_out_Y;
// Name Output Other arguments
not not0 (not0_out, A);
and and0 (and0_out_Y, not0_out, B_N);
buf buf0 (Y, and0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b (
Y,
A,
B_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b (
//# {{data|Data Signals}}
input A,
input B_N,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b (
//# {{data|Data Signals}}
input A,
input B_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b_1 (
Y,
A,
B_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b_1 (
Y,
A,
B_N
);
output Y;
input A;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor2b base (
.Y (Y),
.A (A),
.B_N(B_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b_2 (
Y,
A,
B_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b_2 (
Y,
A,
B_N
);
output Y;
input A;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor2b base (
.Y (Y),
.A (A),
.B_N(B_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b_4 (
Y,
A,
B_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2b_4 (
Y,
A,
B_N
);
output Y;
input A;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor2b base (
.Y (Y),
.A (A),
.B_N(B_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2_1 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2_2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2_4 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2_8 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor2_8 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3 (
Y,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B);
buf buf0 (Y, nor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3 (
Y,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B);
buf buf0 (Y, nor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3 (
Y,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b (
Y,
A,
B,
C_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input C_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nor0_out;
wire and0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out, A, B);
and and0 (and0_out_Y, C_N, nor0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
and0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b (
Y,
A,
B,
C_N
);
// Module ports
output Y;
input A;
input B;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire nor0_out;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out, A, B);
and and0 (and0_out_Y, C_N, nor0_out);
buf buf0 (Y, and0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b (
Y,
A,
B,
C_N
);
output Y;
input A;
input B;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b (
Y,
A,
B,
C_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input C_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nor0_out;
wire and0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out, A, B);
and and0 (and0_out_Y, C_N, nor0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
and0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b (
Y,
A,
B,
C_N
);
// Module ports
output Y;
input A;
input B;
input C_N;
// Local signals
wire nor0_out;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out, A, B);
and and0 (and0_out_Y, C_N, nor0_out);
buf buf0 (Y, and0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b (
Y,
A,
B,
C_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b (
//# {{data|Data Signals}}
input A,
input B,
input C_N,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b (
//# {{data|Data Signals}}
input A,
input B,
input C_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b_1 (
Y,
A,
B,
C_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b_1 (
Y,
A,
B,
C_N
);
output Y;
input A;
input B;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor3b base (
.Y (Y),
.A (A),
.B (B),
.C_N(C_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b_2 (
Y,
A,
B,
C_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b_2 (
Y,
A,
B,
C_N
);
output Y;
input A;
input B;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor3b base (
.Y (Y),
.A (A),
.B (B),
.C_N(C_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b_4 (
Y,
A,
B,
C_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3b_4 (
Y,
A,
B,
C_N
);
output Y;
input A;
input B;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor3b base (
.Y (Y),
.A (A),
.B (B),
.C_N(C_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3_1 (
Y,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3_2 (
Y,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3_4 (
Y,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor3_4 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4 (
Y,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D);
buf buf0 (Y, nor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4 (
Y,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D);
buf buf0 (Y, nor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4 (
Y,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4b (
Y,
A,
B,
C,
D_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input C;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out;
wire nor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out, D_N);
nor nor0 (nor0_out_Y, A, B, C, not0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4b (
Y,
A,
B,
C,
D_N
);
// Module ports
output Y;
input A;
input B;
input C;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire not0_out;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (not0_out, D_N);
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y, nor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4b (
Y,
A,
B,
C,
D_N
);
output Y;
input A;
input B;
input C;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4b (
Y,
A,
B,
C,
D_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input C;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out;
wire nor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out, D_N);
nor nor0 (nor0_out_Y, A, B, C, not0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4b (
Y,
A,
B,
C,
D_N
);
// Module ports
output Y;
input A;
input B;
input C;
input D_N;
// Local signals
wire not0_out;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (not0_out, D_N);
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y, nor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4b (
Y,
A,
B,
C,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4b (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D_N,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4b (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb (
Y,
A,
B,
C_N,
D_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input C_N;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nor0_out;
wire and0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out, A, B);
and and0 (and0_out_Y, nor0_out, C_N, D_N);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
and0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb (
Y,
A,
B,
C_N,
D_N
);
// Module ports
output Y;
input A;
input B;
input C_N;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire nor0_out;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out, A, B);
and and0 (and0_out_Y, nor0_out, C_N, D_N);
buf buf0 (Y, and0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb (
Y,
A,
B,
C_N,
D_N
);
output Y;
input A;
input B;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb (
Y,
A,
B,
C_N,
D_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input C_N;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nor0_out;
wire and0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out, A, B);
and and0 (and0_out_Y, nor0_out, C_N, D_N);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
and0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb (
Y,
A,
B,
C_N,
D_N
);
// Module ports
output Y;
input A;
input B;
input C_N;
input D_N;
// Local signals
wire nor0_out;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out, A, B);
and and0 (and0_out_Y, nor0_out, C_N, D_N);
buf buf0 (Y, and0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb (
Y,
A,
B,
C_N,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C_N;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb (
//# {{data|Data Signals}}
input A,
input B,
input C_N,
input D_N,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb (
//# {{data|Data Signals}}
input A,
input B,
input C_N,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb_1 (
Y,
A,
B,
C_N,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C_N;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb_1 (
Y,
A,
B,
C_N,
D_N
);
output Y;
input A;
input B;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor4bb base (
.Y (Y),
.A (A),
.B (B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb_2 (
Y,
A,
B,
C_N,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C_N;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb_2 (
Y,
A,
B,
C_N,
D_N
);
output Y;
input A;
input B;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor4bb base (
.Y (Y),
.A (A),
.B (B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb_4 (
Y,
A,
B,
C_N,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C_N;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4bb_4 (
Y,
A,
B,
C_N,
D_N
);
output Y;
input A;
input B;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor4bb base (
.Y (Y),
.A (A),
.B (B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4b_1 (
Y,
A,
B,
C,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4b_1 (
Y,
A,
B,
C,
D_N
);
output Y;
input A;
input B;
input C;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor4b base (
.Y (Y),
.A (A),
.B (B),
.C (C),
.D_N(D_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4b_2 (
Y,
A,
B,
C,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4b_2 (
Y,
A,
B,
C,
D_N
);
output Y;
input A;
input B;
input C;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor4b base (
.Y (Y),
.A (A),
.B (B),
.C (C),
.D_N(D_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4b_4 (
Y,
A,
B,
C,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
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