code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module sky130_fd_sc_hdll__nor4b_4 (
Y,
A,
B,
C,
D_N
);
output Y;
input A;
input B;
input C;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor4b base (
.Y (Y),
.A (A),
.B (B),
.C (C),
.D_N(D_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4_1 (
Y,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4_2 (
Y,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4_2 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4_4 (
Y,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4_6 (
Y,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4_6 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4_8 (
Y,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__nor4_8 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a (
X,
A1,
A2,
B1,
C1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out;
wire and0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
and and0 (and0_out_X, or0_out, B1, C1);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
and0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a (
X,
A1,
A2,
B1,
C1
);
// Module ports
output X;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X, and0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a (
X,
A1,
A2,
B1,
C1
);
output X;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a (
X,
A1,
A2,
B1,
C1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out;
wire and0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
and and0 (and0_out_X, or0_out, B1, C1);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
and0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a (
X,
A1,
A2,
B1,
C1
);
// Module ports
output X;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire or0_out;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X, and0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a (
X,
A1,
A2,
B1,
C1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai (
Y,
A1,
A2,
B1,
C1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out;
wire nand0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
nand nand0 (nand0_out_Y, C1, or0_out, B1);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nand0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai (
Y,
A1,
A2,
B1,
C1
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire or0_out;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y, nand0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai (
Y,
A1,
A2,
B1,
C1
);
output Y;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai (
Y,
A1,
A2,
B1,
C1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out;
wire nand0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
nand nand0 (nand0_out_Y, C1, or0_out, B1);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nand0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai (
Y,
A1,
A2,
B1,
C1
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire or0_out;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y, nand0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai (
Y,
A1,
A2,
B1,
C1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai_1 (
Y,
A1,
A2,
B1,
C1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai_1 (
Y,
A1,
A2,
B1,
C1
);
output Y;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o211ai base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai_2 (
Y,
A1,
A2,
B1,
C1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai_2 (
Y,
A1,
A2,
B1,
C1
);
output Y;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o211ai base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai_4 (
Y,
A1,
A2,
B1,
C1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211ai_4 (
Y,
A1,
A2,
B1,
C1
);
output Y;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o211ai base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a_1 (
X,
A1,
A2,
B1,
C1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a_1 (
X,
A1,
A2,
B1,
C1
);
output X;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o211a base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a_2 (
X,
A1,
A2,
B1,
C1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a_2 (
X,
A1,
A2,
B1,
C1
);
output X;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o211a base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a_4 (
X,
A1,
A2,
B1,
C1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o211a_4 (
X,
A1,
A2,
B1,
C1
);
output X;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o211a base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out;
wire and0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
and and0 (and0_out_X, or0_out, B1);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
and0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a (
X,
A1,
A2,
B1
);
// Module ports
output X;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
and and0 (and0_out_X, or0_out, B1);
buf buf0 (X, and0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a (
X,
A1,
A2,
B1
);
output X;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out;
wire and0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
and and0 (and0_out_X, or0_out, B1);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
and0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a (
X,
A1,
A2,
B1
);
// Module ports
output X;
input A1;
input A2;
input B1;
// Local signals
wire or0_out;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
and and0 (and0_out_X, or0_out, B1);
buf buf0 (X, and0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out;
wire nand0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
nand nand0 (nand0_out_Y, B1, or0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nand0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai (
Y,
A1,
A2,
B1
);
// Module ports
output Y;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire or0_out;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
nand nand0 (nand0_out_Y, B1, or0_out);
buf buf0 (Y, nand0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai (
Y,
A1,
A2,
B1
);
output Y;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out;
wire nand0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
nand nand0 (nand0_out_Y, B1, or0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nand0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai (
Y,
A1,
A2,
B1
);
// Module ports
output Y;
input A1;
input A2;
input B1;
// Local signals
wire or0_out;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out, A2, A1);
nand nand0 (nand0_out_Y, B1, or0_out);
buf buf0 (Y, nand0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai_1 (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai_1 (
Y,
A1,
A2,
B1
);
output Y;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o21ai base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai_2 (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai_2 (
Y,
A1,
A2,
B1
);
output Y;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o21ai base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai_4 (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ai_4 (
Y,
A1,
A2,
B1
);
output Y;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o21ai base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a_1 (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a_1 (
X,
A1,
A2,
B1
);
output X;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o21a base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a_2 (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a_2 (
X,
A1,
A2,
B1
);
output X;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o21a base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a_4 (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21a_4 (
X,
A1,
A2,
B1
);
output X;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o21a base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba (
X,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nor0_out;
wire nor1_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out, A1, A2);
nor nor1 (nor1_out_X, B1_N, nor0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
nor1_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba (
X,
A1,
A2,
B1_N
);
// Module ports
output X;
input A1;
input A2;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire nor0_out;
wire nor1_out_X;
// Name Output Other arguments
nor nor0 (nor0_out, A1, A2);
nor nor1 (nor1_out_X, B1_N, nor0_out);
buf buf0 (X, nor1_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba (
X,
A1,
A2,
B1_N
);
output X;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba (
X,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nor0_out;
wire nor1_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out, A1, A2);
nor nor1 (nor1_out_X, B1_N, nor0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
nor1_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba (
X,
A1,
A2,
B1_N
);
// Module ports
output X;
input A1;
input A2;
input B1_N;
// Local signals
wire nor0_out;
wire nor1_out_X;
// Name Output Other arguments
nor nor0 (nor0_out, A1, A2);
nor nor1 (nor1_out_X, B1_N, nor0_out);
buf buf0 (X, nor1_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba (
X,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba (
//# {{data|Data Signals}}
input A1,
input A2,
input B1_N,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba (
//# {{data|Data Signals}}
input A1,
input A2,
input B1_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai (
Y,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire b;
wire or0_out;
wire nand0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b, B1_N);
or or0 (or0_out, A2, A1);
nand nand0 (nand0_out_Y, b, or0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nand0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai (
Y,
A1,
A2,
B1_N
);
// Module ports
output Y;
input A1;
input A2;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire b;
wire or0_out;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (b, B1_N);
or or0 (or0_out, A2, A1);
nand nand0 (nand0_out_Y, b, or0_out);
buf buf0 (Y, nand0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai (
Y,
A1,
A2,
B1_N
);
output Y;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai (
Y,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire b;
wire or0_out;
wire nand0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b, B1_N);
or or0 (or0_out, A2, A1);
nand nand0 (nand0_out_Y, b, or0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nand0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai (
Y,
A1,
A2,
B1_N
);
// Module ports
output Y;
input A1;
input A2;
input B1_N;
// Local signals
wire b;
wire or0_out;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (b, B1_N);
or or0 (or0_out, A2, A1);
nand nand0 (nand0_out_Y, b, or0_out);
buf buf0 (Y, nand0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai (
Y,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1_N,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai_1 (
Y,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai_1 (
Y,
A1,
A2,
B1_N
);
output Y;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai_2 (
Y,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai_2 (
Y,
A1,
A2,
B1_N
);
output Y;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai_4 (
Y,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21bai_4 (
Y,
A1,
A2,
B1_N
);
output Y;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba_1 (
X,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba_1 (
X,
A1,
A2,
B1_N
);
output X;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba_2 (
X,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba_2 (
X,
A1,
A2,
B1_N
);
output X;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba_4 (
X,
A1,
A2,
B1_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o21ba_4 (
X,
A1,
A2,
B1_N
);
output X;
input A1;
input A2;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o221a (
X,
A1,
A2,
B1,
B2,
C1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out;
wire or1_out;
wire and0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out, B2, B1);
or or1 (or1_out, A2, A1);
and and0 (and0_out_X, or0_out, or1_out, C1);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
and0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o221a (
X,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out, B2, B1);
or or1 (or1_out, A2, A1);
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X, and0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o221a (
X,
A1,
A2,
B1,
B2,
C1
);
output X;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o221a (
X,
A1,
A2,
B1,
B2,
C1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
input C1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out;
wire or1_out;
wire and0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out, B2, B1);
or or1 (or1_out, A2, A1);
and and0 (and0_out_X, or0_out, or1_out, C1);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
and0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o221a (
X,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire or0_out;
wire or1_out;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out, B2, B1);
or or1 (or1_out, A2, A1);
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X, and0_out_X);
endmodule
| 7.212805 |
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