code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hdll__inv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv_2 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv_4 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv_6 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv_6 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv_8 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc (
X,
SLEEP,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input SLEEP;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out;
wire and0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out, SLEEP);
and and0 (and0_out_X, not0_out, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG$S pwrgood_pp0 (
pwrgood_pp0_out_X,
and0_out_X,
VPWR,
VGND,
SLEEP
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc (
X,
SLEEP,
A
);
// Module ports
output X;
input SLEEP;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire not0_out;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out, SLEEP);
and and0 (and0_out_X, not0_out, A);
buf buf0 (X, and0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc (
X,
SLEEP,
A
);
output X;
input SLEEP;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc (
X,
SLEEP,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input SLEEP;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out;
wire and0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out, SLEEP);
and and0 (and0_out_X, not0_out, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG$S pwrgood_pp0 (
pwrgood_pp0_out_X,
and0_out_X,
VPWR,
VGND,
SLEEP
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc (
X,
SLEEP,
A
);
// Module ports
output X;
input SLEEP;
input A;
// Local signals
wire not0_out;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out, SLEEP);
and and0 (and0_out_X, not0_out, A);
buf buf0 (X, and0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc (
X,
SLEEP,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input SLEEP;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input SLEEP,
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc_1 (
X,
SLEEP,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input SLEEP;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc_1 (
X,
SLEEP,
A
);
output X;
input SLEEP;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc_16 (
X,
SLEEP,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input SLEEP;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc_16 (
X,
SLEEP,
A
);
output X;
input SLEEP;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc_2 (
X,
SLEEP,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input SLEEP;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc_2 (
X,
SLEEP,
A
);
output X;
input SLEEP;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc_4 (
X,
SLEEP,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input SLEEP;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc_4 (
X,
SLEEP,
A
);
output X;
input SLEEP;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc_8 (
X,
SLEEP,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input SLEEP;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__isobufsrc_8 (
X,
SLEEP,
A
);
output X;
input SLEEP;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire mux_2to10_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (
mux_2to10_out_X,
A0,
A1,
S
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
mux_2to10_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2 (
X,
A0,
A1,
S
);
// Module ports
output X;
input A0;
input A1;
input S;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (
mux_2to10_out_X,
A0,
A1,
S
);
buf buf0 (X, mux_2to10_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2 (
X,
A0,
A1,
S
);
output X;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire mux_2to10_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (
mux_2to10_out_X,
A0,
A1,
S
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
mux_2to10_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2 (
X,
A0,
A1,
S
);
// Module ports
output X;
input A0;
input A1;
input S;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (
mux_2to10_out_X,
A0,
A1,
S
);
buf buf0 (X, mux_2to10_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2 (
//# {{data|Data Signals}}
input A0,
input A1,
output X,
//# {{control|Control Signals}}
input S,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2 (
//# {{data|Data Signals}}
input A0,
input A1,
output X,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i (
Y,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire mux_2to1_n0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1_N mux_2to1_n0 (
mux_2to1_n0_out_Y,
A0,
A1,
S
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
mux_2to1_n0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i (
Y,
A0,
A1,
S
);
// Module ports
output Y;
input A0;
input A1;
input S;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire mux_2to1_n0_out_Y;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1_N mux_2to1_n0 (
mux_2to1_n0_out_Y,
A0,
A1,
S
);
buf buf0 (Y, mux_2to1_n0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i (
Y,
A0,
A1,
S
);
output Y;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i (
Y,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire mux_2to1_n0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1_N mux_2to1_n0 (
mux_2to1_n0_out_Y,
A0,
A1,
S
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
mux_2to1_n0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i (
Y,
A0,
A1,
S
);
// Module ports
output Y;
input A0;
input A1;
input S;
// Local signals
wire mux_2to1_n0_out_Y;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1_N mux_2to1_n0 (
mux_2to1_n0_out_Y,
A0,
A1,
S
);
buf buf0 (Y, mux_2to1_n0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i (
Y,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i (
//# {{data|Data Signals}}
input A0,
input A1,
output Y,
//# {{control|Control Signals}}
input S,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i (
//# {{data|Data Signals}}
input A0,
input A1,
output Y,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i_1 (
Y,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i_1 (
Y,
A0,
A1,
S
);
output Y;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__mux2i base (
.Y (Y),
.A0(A0),
.A1(A1),
.S (S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i_2 (
Y,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i_2 (
Y,
A0,
A1,
S
);
output Y;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__mux2i base (
.Y (Y),
.A0(A0),
.A1(A1),
.S (S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i_4 (
Y,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2i_4 (
Y,
A0,
A1,
S
);
output Y;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__mux2i base (
.Y (Y),
.A0(A0),
.A1(A1),
.S (S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2_1 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2_1 (
X,
A0,
A1,
S
);
output X;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__mux2 base (
.X (X),
.A0(A0),
.A1(A1),
.S (S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2_12 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2_12 (
X,
A0,
A1,
S
);
output X;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__mux2 base (
.X (X),
.A0(A0),
.A1(A1),
.S (S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2_16 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2_16 (
X,
A0,
A1,
S
);
output X;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__mux2 base (
.X (X),
.A0(A0),
.A1(A1),
.S (S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2_2 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2_2 (
X,
A0,
A1,
S
);
output X;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__mux2 base (
.X (X),
.A0(A0),
.A1(A1),
.S (S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2_4 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2_4 (
X,
A0,
A1,
S
);
output X;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__mux2 base (
.X (X),
.A0(A0),
.A1(A1),
.S (S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2_8 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__mux2_8 (
X,
A0,
A1,
S
);
output X;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__mux2 base (
.X (X),
.A0(A0),
.A1(A1),
.S (S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb16to1 (
Z,
D,
S
);
// Module ports
output Z;
input [15:0] D;
input [15:0] S;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output Other arguments
bufif1 bufif10 (Z, !D[0], S[0]);
bufif1 bufif11 (Z, !D[1], S[1]);
bufif1 bufif12 (Z, !D[2], S[2]);
bufif1 bufif13 (Z, !D[3], S[3]);
bufif1 bufif14 (Z, !D[4], S[4]);
bufif1 bufif15 (Z, !D[5], S[5]);
bufif1 bufif16 (Z, !D[6], S[6]);
bufif1 bufif17 (Z, !D[7], S[7]);
bufif1 bufif18 (Z, !D[8], S[8]);
bufif1 bufif19 (Z, !D[9], S[9]);
bufif1 bufif110 (Z, !D[10], S[10]);
bufif1 bufif111 (Z, !D[11], S[11]);
bufif1 bufif112 (Z, !D[12], S[12]);
bufif1 bufif113 (Z, !D[13], S[13]);
bufif1 bufif114 (Z, !D[14], S[14]);
bufif1 bufif115 (Z, !D[15], S[15]);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb16to1 (
Z,
D,
S
);
output Z;
input [15:0] D;
input [15:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb16to1 (
Z,
D,
S
);
// Module ports
output Z;
input [15:0] D;
input [15:0] S;
// Name Output Other arguments
bufif1 bufif10 (Z, !D[0], S[0]);
bufif1 bufif11 (Z, !D[1], S[1]);
bufif1 bufif12 (Z, !D[2], S[2]);
bufif1 bufif13 (Z, !D[3], S[3]);
bufif1 bufif14 (Z, !D[4], S[4]);
bufif1 bufif15 (Z, !D[5], S[5]);
bufif1 bufif16 (Z, !D[6], S[6]);
bufif1 bufif17 (Z, !D[7], S[7]);
bufif1 bufif18 (Z, !D[8], S[8]);
bufif1 bufif19 (Z, !D[9], S[9]);
bufif1 bufif110 (Z, !D[10], S[10]);
bufif1 bufif111 (Z, !D[11], S[11]);
bufif1 bufif112 (Z, !D[12], S[12]);
bufif1 bufif113 (Z, !D[13], S[13]);
bufif1 bufif114 (Z, !D[14], S[14]);
bufif1 bufif115 (Z, !D[15], S[15]);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb16to1 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input [15:0] D;
input [15:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb16to1 (
//# {{data|Data Signals}}
input [15:0] D,
output Z,
//# {{control|Control Signals}}
input [15:0] S,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb16to1 (
//# {{data|Data Signals}}
input [15:0] D,
output Z,
//# {{control|Control Signals}}
input [15:0] S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb16to1_1 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input [15:0] D;
input [15:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__muxb16to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb16to1_1 (
Z,
D,
S
);
output Z;
input [15:0] D;
input [15:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__muxb16to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb16to1_2 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input [15:0] D;
input [15:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__muxb16to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb16to1_2 (
Z,
D,
S
);
output Z;
input [15:0] D;
input [15:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__muxb16to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb16to1_4 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input [15:0] D;
input [15:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__muxb16to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb16to1_4 (
Z,
D,
S
);
output Z;
input [15:0] D;
input [15:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__muxb16to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input [3:0] D;
input [3:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_d0;
wire pwrgood_pp1_out_s0;
wire pwrgood_pp2_out_d1;
wire pwrgood_pp3_out_s1;
wire pwrgood_pp4_out_d2;
wire pwrgood_pp5_out_s2;
wire pwrgood_pp6_out_d3;
wire pwrgood_pp7_out_s3;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_d0,
D[0],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_s0,
S[0],
VPWR,
VGND
);
bufif1 bufif10 (Z, !pwrgood_pp0_out_d0, pwrgood_pp1_out_s0);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp2 (
pwrgood_pp2_out_d1,
D[1],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp3 (
pwrgood_pp3_out_s1,
S[1],
VPWR,
VGND
);
bufif1 bufif11 (Z, !pwrgood_pp2_out_d1, pwrgood_pp3_out_s1);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp4 (
pwrgood_pp4_out_d2,
D[2],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp5 (
pwrgood_pp5_out_s2,
S[2],
VPWR,
VGND
);
bufif1 bufif12 (Z, !pwrgood_pp4_out_d2, pwrgood_pp5_out_s2);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp6 (
pwrgood_pp6_out_d3,
D[3],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp7 (
pwrgood_pp7_out_s3,
S[3],
VPWR,
VGND
);
bufif1 bufif13 (Z, !pwrgood_pp6_out_d3, pwrgood_pp7_out_s3);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1 (
Z,
D,
S
);
// Module ports
output Z;
input [3:0] D;
input [3:0] S;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output Other arguments
bufif1 bufif10 (Z, !D[0], S[0]);
bufif1 bufif11 (Z, !D[1], S[1]);
bufif1 bufif12 (Z, !D[2], S[2]);
bufif1 bufif13 (Z, !D[3], S[3]);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1 (
Z,
D,
S
);
output Z;
input [3:0] D;
input [3:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input [3:0] D;
input [3:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_d0;
wire pwrgood_pp1_out_s0;
wire pwrgood_pp2_out_d1;
wire pwrgood_pp3_out_s1;
wire pwrgood_pp4_out_d2;
wire pwrgood_pp5_out_s2;
wire pwrgood_pp6_out_d3;
wire pwrgood_pp7_out_s3;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_d0,
D[0],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_s0,
S[0],
VPWR,
VGND
);
bufif1 bufif10 (Z, !pwrgood_pp0_out_d0, pwrgood_pp1_out_s0);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp2 (
pwrgood_pp2_out_d1,
D[1],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp3 (
pwrgood_pp3_out_s1,
S[1],
VPWR,
VGND
);
bufif1 bufif11 (Z, !pwrgood_pp2_out_d1, pwrgood_pp3_out_s1);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp4 (
pwrgood_pp4_out_d2,
D[2],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp5 (
pwrgood_pp5_out_s2,
S[2],
VPWR,
VGND
);
bufif1 bufif12 (Z, !pwrgood_pp4_out_d2, pwrgood_pp5_out_s2);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp6 (
pwrgood_pp6_out_d3,
D[3],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp7 (
pwrgood_pp7_out_s3,
S[3],
VPWR,
VGND
);
bufif1 bufif13 (Z, !pwrgood_pp6_out_d3, pwrgood_pp7_out_s3);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1 (
Z,
D,
S
);
// Module ports
output Z;
input [3:0] D;
input [3:0] S;
// Name Output Other arguments
bufif1 bufif10 (Z, !D[0], S[0]);
bufif1 bufif11 (Z, !D[1], S[1]);
bufif1 bufif12 (Z, !D[2], S[2]);
bufif1 bufif13 (Z, !D[3], S[3]);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input [3:0] D;
input [3:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1 (
//# {{data|Data Signals}}
input [3:0] D,
output Z,
//# {{control|Control Signals}}
input [3:0] S,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1 (
//# {{data|Data Signals}}
input [3:0] D,
output Z,
//# {{control|Control Signals}}
input [3:0] S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1_1 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input [3:0] D;
input [3:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__muxb4to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1_1 (
Z,
D,
S
);
output Z;
input [3:0] D;
input [3:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__muxb4to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1_2 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input [3:0] D;
input [3:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__muxb4to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1_2 (
Z,
D,
S
);
output Z;
input [3:0] D;
input [3:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__muxb4to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1_4 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input [3:0] D;
input [3:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__muxb4to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb4to1_4 (
Z,
D,
S
);
output Z;
input [3:0] D;
input [3:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__muxb4to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb8to1 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input [7:0] D;
input [7:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_d0;
wire pwrgood_pp1_out_s0;
wire pwrgood_pp2_out_d1;
wire pwrgood_pp3_out_s1;
wire pwrgood_pp4_out_d2;
wire pwrgood_pp5_out_s2;
wire pwrgood_pp6_out_d3;
wire pwrgood_pp7_out_s3;
wire pwrgood_pp8_out_d4;
wire pwrgood_pp9_out_s4;
wire pwrgood_pp10_out_d5;
wire pwrgood_pp11_out_s5;
wire pwrgood_pp12_out_d6;
wire pwrgood_pp13_out_s6;
wire pwrgood_pp14_out_d7;
wire pwrgood_pp15_out_s7;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_d0,
D[0],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_s0,
S[0],
VPWR,
VGND
);
bufif1 bufif10 (Z, !pwrgood_pp0_out_d0, pwrgood_pp1_out_s0);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp2 (
pwrgood_pp2_out_d1,
D[1],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp3 (
pwrgood_pp3_out_s1,
S[1],
VPWR,
VGND
);
bufif1 bufif11 (Z, !pwrgood_pp2_out_d1, pwrgood_pp3_out_s1);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp4 (
pwrgood_pp4_out_d2,
D[2],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp5 (
pwrgood_pp5_out_s2,
S[2],
VPWR,
VGND
);
bufif1 bufif12 (Z, !pwrgood_pp4_out_d2, pwrgood_pp5_out_s2);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp6 (
pwrgood_pp6_out_d3,
D[3],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp7 (
pwrgood_pp7_out_s3,
S[3],
VPWR,
VGND
);
bufif1 bufif13 (Z, !pwrgood_pp6_out_d3, pwrgood_pp7_out_s3);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp8 (
pwrgood_pp8_out_d4,
D[4],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp9 (
pwrgood_pp9_out_s4,
S[4],
VPWR,
VGND
);
bufif1 bufif14 (Z, !pwrgood_pp8_out_d4, pwrgood_pp9_out_s4);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp10 (
pwrgood_pp10_out_d5,
D[5],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp11 (
pwrgood_pp11_out_s5,
S[5],
VPWR,
VGND
);
bufif1 bufif15 (Z, !pwrgood_pp10_out_d5, pwrgood_pp11_out_s5);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp12 (
pwrgood_pp12_out_d6,
D[6],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp13 (
pwrgood_pp13_out_s6,
S[6],
VPWR,
VGND
);
bufif1 bufif16 (Z, !pwrgood_pp12_out_d6, pwrgood_pp13_out_s6);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp14 (
pwrgood_pp14_out_d7,
D[7],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp15 (
pwrgood_pp15_out_s7,
S[7],
VPWR,
VGND
);
bufif1 bufif17 (Z, !pwrgood_pp14_out_d7, pwrgood_pp15_out_s7);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb8to1 (
Z,
D,
S
);
// Module ports
output Z;
input [7:0] D;
input [7:0] S;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output Other arguments
bufif1 bufif10 (Z, !D[0], S[0]);
bufif1 bufif11 (Z, !D[1], S[1]);
bufif1 bufif12 (Z, !D[2], S[2]);
bufif1 bufif13 (Z, !D[3], S[3]);
bufif1 bufif14 (Z, !D[4], S[4]);
bufif1 bufif15 (Z, !D[5], S[5]);
bufif1 bufif16 (Z, !D[6], S[6]);
bufif1 bufif17 (Z, !D[7], S[7]);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb8to1 (
Z,
D,
S
);
output Z;
input [7:0] D;
input [7:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb8to1 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input [7:0] D;
input [7:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_d0;
wire pwrgood_pp1_out_s0;
wire pwrgood_pp2_out_d1;
wire pwrgood_pp3_out_s1;
wire pwrgood_pp4_out_d2;
wire pwrgood_pp5_out_s2;
wire pwrgood_pp6_out_d3;
wire pwrgood_pp7_out_s3;
wire pwrgood_pp8_out_d4;
wire pwrgood_pp9_out_s4;
wire pwrgood_pp10_out_d5;
wire pwrgood_pp11_out_s5;
wire pwrgood_pp12_out_d6;
wire pwrgood_pp13_out_s6;
wire pwrgood_pp14_out_d7;
wire pwrgood_pp15_out_s7;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_d0,
D[0],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_s0,
S[0],
VPWR,
VGND
);
bufif1 bufif10 (Z, !pwrgood_pp0_out_d0, pwrgood_pp1_out_s0);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp2 (
pwrgood_pp2_out_d1,
D[1],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp3 (
pwrgood_pp3_out_s1,
S[1],
VPWR,
VGND
);
bufif1 bufif11 (Z, !pwrgood_pp2_out_d1, pwrgood_pp3_out_s1);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp4 (
pwrgood_pp4_out_d2,
D[2],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp5 (
pwrgood_pp5_out_s2,
S[2],
VPWR,
VGND
);
bufif1 bufif12 (Z, !pwrgood_pp4_out_d2, pwrgood_pp5_out_s2);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp6 (
pwrgood_pp6_out_d3,
D[3],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp7 (
pwrgood_pp7_out_s3,
S[3],
VPWR,
VGND
);
bufif1 bufif13 (Z, !pwrgood_pp6_out_d3, pwrgood_pp7_out_s3);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp8 (
pwrgood_pp8_out_d4,
D[4],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp9 (
pwrgood_pp9_out_s4,
S[4],
VPWR,
VGND
);
bufif1 bufif14 (Z, !pwrgood_pp8_out_d4, pwrgood_pp9_out_s4);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp10 (
pwrgood_pp10_out_d5,
D[5],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp11 (
pwrgood_pp11_out_s5,
S[5],
VPWR,
VGND
);
bufif1 bufif15 (Z, !pwrgood_pp10_out_d5, pwrgood_pp11_out_s5);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp12 (
pwrgood_pp12_out_d6,
D[6],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp13 (
pwrgood_pp13_out_s6,
S[6],
VPWR,
VGND
);
bufif1 bufif16 (Z, !pwrgood_pp12_out_d6, pwrgood_pp13_out_s6);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp14 (
pwrgood_pp14_out_d7,
D[7],
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp15 (
pwrgood_pp15_out_s7,
S[7],
VPWR,
VGND
);
bufif1 bufif17 (Z, !pwrgood_pp14_out_d7, pwrgood_pp15_out_s7);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb8to1 (
Z,
D,
S
);
// Module ports
output Z;
input [7:0] D;
input [7:0] S;
// Name Output Other arguments
bufif1 bufif10 (Z, !D[0], S[0]);
bufif1 bufif11 (Z, !D[1], S[1]);
bufif1 bufif12 (Z, !D[2], S[2]);
bufif1 bufif13 (Z, !D[3], S[3]);
bufif1 bufif14 (Z, !D[4], S[4]);
bufif1 bufif15 (Z, !D[5], S[5]);
bufif1 bufif16 (Z, !D[6], S[6]);
bufif1 bufif17 (Z, !D[7], S[7]);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb8to1 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input [7:0] D;
input [7:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb8to1 (
//# {{data|Data Signals}}
input [7:0] D,
output Z,
//# {{control|Control Signals}}
input [7:0] S,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb8to1 (
//# {{data|Data Signals}}
input [7:0] D,
output Z,
//# {{control|Control Signals}}
input [7:0] S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb8to1_1 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input [7:0] D;
input [7:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__muxb8to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb8to1_1 (
Z,
D,
S
);
output Z;
input [7:0] D;
input [7:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__muxb8to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb8to1_2 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input [7:0] D;
input [7:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__muxb8to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb8to1_2 (
Z,
D,
S
);
output Z;
input [7:0] D;
input [7:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__muxb8to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__muxb8to1_4 (
Z,
D,
S,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input [7:0] D;
input [7:0] S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__muxb8to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.