code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module sky130_fd_sc_hdll__o32ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o32ai_1 (
Y,
A1,
A2,
A3,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input A3;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o32ai_1 (
Y,
A1,
A2,
A3,
B1,
B2
);
output Y;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o32ai base (
.Y (Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o32ai_2 (
Y,
A1,
A2,
A3,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input A3;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o32ai_2 (
Y,
A1,
A2,
A3,
B1,
B2
);
output Y;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o32ai base (
.Y (Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o32ai_4 (
Y,
A1,
A2,
A3,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input A3;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__o32ai_4 (
Y,
A1,
A2,
A3,
B1,
B2
);
output Y;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__o32ai base (
.Y (Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2 (
//# {{data|Data Signals}}
input A,
input B,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b (
X,
A,
B_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out, B_N);
or or0 (or0_out_X, not0_out, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b (
X,
A,
B_N
);
// Module ports
output X;
input A;
input B_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire not0_out;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out, B_N);
or or0 (or0_out_X, not0_out, A);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b (
X,
A,
B_N
);
output X;
input A;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b (
X,
A,
B_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out, B_N);
or or0 (or0_out_X, not0_out, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b (
X,
A,
B_N
);
// Module ports
output X;
input A;
input B_N;
// Local signals
wire not0_out;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out, B_N);
or or0 (or0_out_X, not0_out, A);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b (
X,
A,
B_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b (
//# {{data|Data Signals}}
input A,
input B_N,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b (
//# {{data|Data Signals}}
input A,
input B_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b_1 (
X,
A,
B_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b_1 (
X,
A,
B_N
);
output X;
input A;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or2b base (
.X (X),
.A (A),
.B_N(B_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b_2 (
X,
A,
B_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b_2 (
X,
A,
B_N
);
output X;
input A;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or2b base (
.X (X),
.A (A),
.B_N(B_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b_4 (
X,
A,
B_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2b_4 (
X,
A,
B_N
);
output X;
input A;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or2b base (
.X (X),
.A (A),
.B_N(B_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2_1 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2_2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2_4 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2_6 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2_6 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2_8 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or2_8 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b (
X,
A,
B,
C_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out, C_N);
or or0 (or0_out_X, B, A, not0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b (
X,
A,
B,
C_N
);
// Module ports
output X;
input A;
input B;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire not0_out;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out, C_N);
or or0 (or0_out_X, B, A, not0_out);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b (
X,
A,
B,
C_N
);
output X;
input A;
input B;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b (
X,
A,
B,
C_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out, C_N);
or or0 (or0_out_X, B, A, not0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b (
X,
A,
B,
C_N
);
// Module ports
output X;
input A;
input B;
input C_N;
// Local signals
wire not0_out;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out, C_N);
or or0 (or0_out_X, B, A, not0_out);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b (
X,
A,
B,
C_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b (
//# {{data|Data Signals}}
input A,
input B,
input C_N,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b (
//# {{data|Data Signals}}
input A,
input B,
input C_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b_1 (
X,
A,
B,
C_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b_1 (
X,
A,
B,
C_N
);
output X;
input A;
input B;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or3b base (
.X (X),
.A (A),
.B (B),
.C_N(C_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b_2 (
X,
A,
B,
C_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b_2 (
X,
A,
B,
C_N
);
output X;
input A;
input B;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or3b base (
.X (X),
.A (A),
.B (B),
.C_N(C_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b_4 (
X,
A,
B,
C_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3b_4 (
X,
A,
B,
C_N
);
output X;
input A;
input B;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or3b base (
.X (X),
.A (A),
.B (B),
.C_N(C_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3_1 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3_2 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3_4 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4 (
X,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4 (
X,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4 (
X,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4b (
X,
A,
B,
C,
D_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out, D_N);
or or0 (or0_out_X, not0_out, C, B, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4b (
X,
A,
B,
C,
D_N
);
// Module ports
output X;
input A;
input B;
input C;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire not0_out;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out, D_N);
or or0 (or0_out_X, not0_out, C, B, A);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4b (
X,
A,
B,
C,
D_N
);
output X;
input A;
input B;
input C;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4b (
X,
A,
B,
C,
D_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out, D_N);
or or0 (or0_out_X, not0_out, C, B, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4b (
X,
A,
B,
C,
D_N
);
// Module ports
output X;
input A;
input B;
input C;
input D_N;
// Local signals
wire not0_out;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out, D_N);
or or0 (or0_out_X, not0_out, C, B, A);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4b (
X,
A,
B,
C,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4b (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D_N,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4b (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb (
X,
A,
B,
C_N,
D_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C_N;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nand0_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out, D_N, C_N);
or or0 (or0_out_X, B, A, nand0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb (
X,
A,
B,
C_N,
D_N
);
// Module ports
output X;
input A;
input B;
input C_N;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire nand0_out;
wire or0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out, D_N, C_N);
or or0 (or0_out_X, B, A, nand0_out);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb (
X,
A,
B,
C_N,
D_N
);
output X;
input A;
input B;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb (
X,
A,
B,
C_N,
D_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C_N;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nand0_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out, D_N, C_N);
or or0 (or0_out_X, B, A, nand0_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb (
X,
A,
B,
C_N,
D_N
);
// Module ports
output X;
input A;
input B;
input C_N;
input D_N;
// Local signals
wire nand0_out;
wire or0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out, D_N, C_N);
or or0 (or0_out_X, B, A, nand0_out);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb (
X,
A,
B,
C_N,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C_N;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb (
//# {{data|Data Signals}}
input A,
input B,
input C_N,
input D_N,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb (
//# {{data|Data Signals}}
input A,
input B,
input C_N,
input D_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb_1 (
X,
A,
B,
C_N,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C_N;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb_1 (
X,
A,
B,
C_N,
D_N
);
output X;
input A;
input B;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or4bb base (
.X (X),
.A (A),
.B (B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb_2 (
X,
A,
B,
C_N,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C_N;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb_2 (
X,
A,
B,
C_N,
D_N
);
output X;
input A;
input B;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or4bb base (
.X (X),
.A (A),
.B (B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb_4 (
X,
A,
B,
C_N,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C_N;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4bb_4 (
X,
A,
B,
C_N,
D_N
);
output X;
input A;
input B;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or4bb base (
.X (X),
.A (A),
.B (B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4b_1 (
X,
A,
B,
C,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4b_1 (
X,
A,
B,
C,
D_N
);
output X;
input A;
input B;
input C;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__or4b base (
.X (X),
.A (A),
.B (B),
.C (C),
.D_N(D_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__or4b_2 (
X,
A,
B,
C,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
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