code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module sky130_fd_sc_hdll__sdfstp_4 (
Q,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) && awake);
assign cond2 = ((SCE_delayed === 1'b1) && awake);
assign cond3 = ((D_delayed !== SCD_delayed) && awake);
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) && awake);
assign cond2 = ((SCE_delayed === 1'b1) && awake);
assign cond3 = ((D_delayed !== SCD_delayed) && awake);
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__sdfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxbp_2 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxbp_2 (
Q,
Q_N,
CLK,
D,
SCD,
SCE
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__sdfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) && awake);
assign cond2 = ((SCE_delayed === 1'b1) && awake);
assign cond3 = ((D_delayed !== SCD_delayed) && awake);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp (
Q,
CLK,
D,
SCD,
SCE
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) && awake);
assign cond2 = ((SCE_delayed === 1'b1) && awake);
assign cond3 = ((D_delayed !== SCD_delayed) && awake);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp (
Q,
CLK,
D,
SCD,
SCE
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp_1 (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp_1 (
Q,
CLK,
D,
SCD,
SCE
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__sdfxtp base (
.Q (Q),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp_2 (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp_2 (
Q,
CLK,
D,
SCD,
SCE
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__sdfxtp base (
.Q (Q),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp_4 (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdfxtp_4 (
Q,
CLK,
D,
SCD,
SCE
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__sdfxtp base (
.Q (Q),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire CLK_delayed;
wire SCE_delayed;
wire GATE_delayed;
wire SCE_gate_delayed;
reg notifier;
wire awake;
wire SCE_awake;
wire GATE_awake;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK_delayed);
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed);
sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
SCE_gate_delayed,
clkn,
notifier,
VPWR,
VGND
);
and and0 (GCLK, m0n, CLK_delayed);
assign awake = (VPWR === 1'b1);
assign SCE_awake = (awake & (GATE_delayed === 1'b0));
assign GATE_awake = (awake & (SCE_delayed === 1'b0));
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire CLK_delayed;
wire SCE_delayed;
wire GATE_delayed;
wire SCE_gate_delayed;
reg notifier;
wire awake;
wire SCE_awake;
wire GATE_awake;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK_delayed);
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed);
sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
SCE_gate_delayed,
clkn,
notifier,
VPWR,
VGND
);
and and0 (GCLK, m0n, CLK_delayed);
assign awake = (VPWR === 1'b1);
assign SCE_awake = (awake & (GATE_delayed === 1'b0));
assign GATE_awake = (awake & (SCE_delayed === 1'b0));
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE,
GATE,
CLK
);
output GCLK;
input SCE;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK);
nor nor0 (SCE_GATE, GATE, SCE);
sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
SCE_GATE,
clkn
,,
VPWR,
VGND
);
and and0 (GCLK, m0n, CLK);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK);
nor nor0 (SCE_GATE, GATE, SCE);
sky130_fd_sc_hdll__udp_dlatch$P dlatch0 (
m0,
SCE_GATE,
clkn
);
and and0 (GCLK, m0n, CLK);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE,
//# {{clocks|Clocking}}
input CLK,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE,
//# {{clocks|Clocking}}
input CLK,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp_1 (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp_1 (
GCLK,
SCE,
GATE,
CLK
);
output GCLK;
input SCE;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp_2 (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp_2 (
GCLK,
SCE,
GATE,
CLK
);
output GCLK;
input SCE;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp_4 (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sdlclkp_4 (
GCLK,
SCE,
GATE,
CLK
);
output GCLK;
input SCE;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sedfxbp (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire DE_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out;
wire de_d;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (
mux_out,
de_d,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to11 (
de_d,
buf_Q,
D_delayed,
DE_delayed
);
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = (awake && (SCE_delayed === 1'b0) && (DE_delayed === 1'b1));
assign cond2 = (awake && (SCE_delayed === 1'b1));
assign cond3 = (awake && (DE_delayed === 1'b1) && (D_delayed !== SCD_delayed));
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sedfxbp (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire DE_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out;
wire de_d;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (
mux_out,
de_d,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to11 (
de_d,
buf_Q,
D_delayed,
DE_delayed
);
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = (awake && (SCE_delayed === 1'b0) && (DE_delayed === 1'b1));
assign cond2 = (awake && (SCE_delayed === 1'b1));
assign cond3 = (awake && (DE_delayed === 1'b1) && (D_delayed !== SCD_delayed));
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sedfxbp (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_hdll__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sedfxbp (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sedfxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input DE,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sedfxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input DE,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sedfxbp_1 (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sedfxbp_1 (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__sedfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D),
.DE (DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sedfxbp_2 (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__sedfxbp_2 (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__sedfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D),
.DE (DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tap (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tap (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tap ();
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tap (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tap (
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd ();
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd (
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd2 (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd2 ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd2 (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd2 ();
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd2 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd2 (
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd2_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__tapvgnd2 base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__tapvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__tapvgnd base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvpwrvgnd (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvpwrvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvpwrvgnd (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvpwrvgnd ();
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvpwrvgnd (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvpwrvgnd (
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvpwrvgnd_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__tapvpwrvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tapvpwrvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__tapvpwrvgnd base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tap_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__tap_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__tap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$NSR (
Q,
SET,
RESET,
CLK_N,
D
);
output Q;
input SET;
input RESET;
input CLK_N;
input D;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$NSR (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET,
input SET,
//# {{clocks|Clocking}}
input CLK_N
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$NSR_pp$PG$N (
Q,
SET,
RESET,
CLK_N,
D,
NOTIFIER,
VPWR,
VGND
);
output Q;
input SET;
input RESET;
input CLK_N;
input D;
input NOTIFIER;
input VPWR;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$NSR_pp$PG$N (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET,
input SET,
//# {{clocks|Clocking}}
input CLK_N,
//# {{power|Power}}
input NOTIFIER,
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$P (
Q,
D,
CLK
);
output Q;
input D;
input CLK;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$P (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input CLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$PR (
Q,
D,
CLK,
RESET
);
output Q;
input D;
input CLK;
input RESET;
endmodule
| 7.212805 |
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