code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module sky130_fd_sc_hdll__udp_dff$PR (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N (
Q,
D,
CLK,
RESET,
NOTIFIER,
VPWR,
VGND
);
output Q;
input D;
input CLK;
input RESET;
input NOTIFIER;
input VPWR;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input NOTIFIER,
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$PS (
Q,
D,
CLK,
SET
);
output Q;
input D;
input CLK;
input SET;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$PS (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input SET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N (
Q,
D,
CLK,
SET,
NOTIFIER,
VPWR,
VGND
);
output Q;
input D;
input CLK;
input SET;
input NOTIFIER;
input VPWR;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input SET,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input NOTIFIER,
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$P_pp$PG$N (
Q,
D,
CLK,
NOTIFIER,
VPWR,
VGND
);
output Q;
input D;
input CLK;
input NOTIFIER;
input VPWR;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dff$P_pp$PG$N (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input NOTIFIER,
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dlatch$P (
Q,
D,
GATE
);
output Q;
input D;
input GATE;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dlatch$P (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input GATE
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dlatch$PR (
Q,
D,
GATE,
RESET
);
output Q;
input D;
input GATE;
input RESET;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dlatch$PR (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input GATE
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N (
Q,
D,
GATE,
RESET,
NOTIFIER,
VPWR,
VGND
);
output Q;
input D;
input GATE;
input RESET;
input NOTIFIER;
input VPWR;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input NOTIFIER,
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N (
Q,
D,
GATE,
NOTIFIER,
VPWR,
VGND
);
output Q;
input D;
input GATE;
input NOTIFIER;
input VPWR;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input NOTIFIER,
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_mux_2to1 (
X,
A0,
A1,
S
);
output X;
input A0;
input A1;
input S;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_mux_2to1 (
//# {{data|Data Signals}}
input A0,
input A1,
output X,
//# {{control|Control Signals}}
input S
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_mux_2to1_N (
Y,
A0,
A1,
S
);
output Y;
input A0;
input A1;
input S;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_mux_2to1_N (
//# {{data|Data Signals}}
input A0,
input A1,
output Y,
//# {{control|Control Signals}}
input S
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_mux_4to2 (
X,
A0,
A1,
A2,
A3,
S0,
S1
);
output X;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_mux_4to2 (
//# {{data|Data Signals}}
input A0,
input A1,
input A2,
input A3,
output X,
//# {{control|Control Signals}}
input S0,
input S1
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_pwrgood_pp$G (
UDP_OUT,
UDP_IN,
VGND
);
output UDP_OUT;
input UDP_IN;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_pwrgood_pp$G (
//# {{data|Data Signals}}
input UDP_IN,
output UDP_OUT,
//# {{power|Power}}
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_pwrgood_pp$P (
UDP_OUT,
UDP_IN,
VPWR
);
output UDP_OUT;
input UDP_IN;
input VPWR;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_pwrgood_pp$P (
//# {{data|Data Signals}}
input UDP_IN,
output UDP_OUT,
//# {{power|Power}}
input VPWR
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_pwrgood_pp$PG (
UDP_OUT,
UDP_IN,
VPWR,
VGND
);
output UDP_OUT;
input UDP_IN;
input VPWR;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_pwrgood_pp$PG (
//# {{data|Data Signals}}
input UDP_IN,
output UDP_OUT,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_pwrgood_pp$PG$S (
UDP_OUT,
UDP_IN,
VPWR,
VGND,
SLEEP
);
output UDP_OUT;
input UDP_IN;
input VPWR;
input VGND;
input SLEEP;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__udp_pwrgood_pp$PG$S (
//# {{data|Data Signals}}
input UDP_IN,
output UDP_OUT,
//# {{power|Power}}
input SLEEP,
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xnor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
xnor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
buf buf0 (Y, xnor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xnor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
xnor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
buf buf0 (Y, xnor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2_1 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2_2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2_4 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xnor0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
xnor0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xnor0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C);
buf buf0 (X, xnor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xnor0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
xnor0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xnor0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C);
buf buf0 (X, xnor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3_1 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3_2 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3_4 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xnor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
xor0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
xor0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2 (
//# {{data|Data Signals}}
input A,
input B,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2_1 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2_2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2_4 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
xor0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
xor0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3_1 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3_2 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3_4 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__xor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_1 (
input GATE,
input CLK,
output GCLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_2 (
input GATE,
input CLK,
output GCLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_4 (
input GATE,
input CLK,
output GCLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_mux_2to1 (
output wire X,
input wire A0,
input wire A1,
input wire S
);
assign X = S ? A1 : A0;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_mux_4to2 (
output wire X,
input wire A0,
input wire A1,
input wire A2,
input wire A3,
input wire S0,
input wire S1
);
wire [3:0] all_inputs;
wire [1:0] all_select;
assign all_inputs = {A3, A2, A1, A0};
assign all_select = {S1, S0};
assign X = all_inputs[all_select];
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_mux_2to1_N (
output wire Y,
input wire A0,
input wire A1,
input wire S
);
assign Y = ~(S ? A1 : A0);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N (
output reg Q,
input wire D,
input wire GATE,
input wire NOTIFIER,
input wire VPWR,
input wire VGND
);
always @(*) begin
if (GATE) Q <= D;
end
wire _unused;
assign _unused = &{1'b0, NOTIFIER, VPWR, VGND};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N (
output reg Q,
input wire D,
input wire GATE,
input wire RESET,
input wire NOTIFIER,
input wire VPWR,
input wire VGND
);
always @(*) begin
if (RESET) begin
Q <= 'd0;
end
if (GATE) begin
Q <= D;
end
end
wire _unused;
assign _unused = &{1'b0, NOTIFIER, VPWR, VGND};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N (
output reg Q,
input wire D,
input wire GATE,
input wire NOTIFIER,
input wire VPWR,
input wire VGND
);
always @(*) begin
if (GATE) Q <= D;
end
wire _unused;
assign _unused = &{1'b0, NOTIFIER, VPWR, VGND};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_dff$P_pp$PG$N (
output reg Q,
input wire D,
input wire CLK,
input wire NOTIFIER,
input wire VPWR,
input wire VGND
);
always @(posedge CLK) begin
Q <= D;
end
wire _unused;
assign _unused = &{1'b0, NOTIFIER, VPWR, VGND};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_dff$PS_pp$PG$N (
output reg Q,
input wire D,
input wire CLK,
input wire SET,
input wire NOTIFIER,
input wire VPWR,
input wire VGND
);
always @(posedge CLK, posedge SET) begin
if (SET) begin
Q <= 1'b1;
end else begin
Q <= D;
end
end
wire _unused;
assign _unused = &{1'b0, NOTIFIER, VPWR, VGND};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_dff$PR_pp$PG$N (
output reg Q,
input wire D,
input wire CLK,
input wire RESET,
input wire NOTIFIER,
input wire VPWR,
input wire VGND
);
always @(posedge CLK, posedge RESET) begin
if (RESET) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
wire _unused;
assign _unused = &{1'b0, NOTIFIER, VPWR, VGND};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N (
output reg Q,
input wire SET,
input wire RESET,
input wire CLK_N,
input wire D,
input wire NOTIFIER,
input wire VPWR,
input wire VGND
);
always @(negedge CLK_N, posedge RESET, posedge SET) begin
if (RESET) begin
Q <= 1'b0;
end else if (SET) begin
Q <= 1'b1;
end else begin
Q <= D;
end
end
wire _unused;
assign _unused = &{1'b0, NOTIFIER, VPWR, VGND};
endmodule
| 7.212805 |
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