code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hd__udp_pwrgood_pp$G (
output wire UDP_OUT,
input wire UDP_IN,
input wire VGND
);
assign UDP_OUT = UDP_IN && !VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_pwrgood_pp$P (
output wire UDP_OUT,
input wire UDP_IN,
input wire VPWR
);
assign UDP_OUT = UDP_IN && VPWR;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_pwrgood_pp$PG (
output wire UDP_OUT,
input wire UDP_IN,
input wire VPWR,
input wire VGND
);
assign UDP_OUT = UDP_IN && VPWR && !VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_pwrgood$l_pp$PG (
output wire UDP_OUT,
input wire UDP_IN,
input wire VPWR,
input wire VGND
);
assign UDP_OUT = UDP_IN && VPWR && !VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S (
output wire UDP_OUT,
input wire UDP_IN,
input wire VPWR,
input wire VGND,
input wire SLEEP
);
assign UDP_OUT = UDP_IN && VPWR && !VGND && !SLEEP;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__a211o_1 (
output wire X,
input wire A1,
input wire A2,
input wire B1,
input wire C1,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = ((A1 & A2) | B1 | C1);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__a31o_1 (
output wire X,
input wire A1,
input wire A2,
input wire A3,
input wire B1,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = ((A1 & A2 & A3) | B1);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__and2_1 (
output wire X,
input wire A,
input wire B,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A & B;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__and2_4 (
output wire X,
input wire A,
input wire B,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A & B;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__and2b_1 (
output wire X,
input wire A_N,
input wire B,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = (~A_N) & B;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__and2b_2 (
output wire X,
input wire A_N,
input wire B,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = (~A_N) & B;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__and3b_1 (
output wire X,
input wire A_N,
input wire B,
input wire C,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = (~A_N) & B & C;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__and3b_4 (
output wire X,
input wire A_N,
input wire B,
input wire C,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = (~A_N) & B & C;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__and4_1 (
output wire X,
input wire A,
input wire B,
input wire C,
input wire D,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A & B & C & D;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__and4b_1 (
output wire X,
input wire A_N,
input wire B,
input wire C,
input wire D,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = (~A_N) & B & C & D;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__and4bb_1 (
output wire X,
input wire A_N,
input wire B_N,
input wire C,
input wire D,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = (~A_N) & (~B_N) & C & D;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__buf_1 (
output wire X,
input wire A,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__buf_2 (
output wire X,
input wire A,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__buf_4 (
output wire X,
input wire A,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkbuf_2 (
output wire X,
input wire A,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkbuf_4 (
output wire X,
input wire A,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkbuf_8 (
output wire X,
input wire A,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s25_1 (
output wire X,
input wire A,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s50_1 (
output wire X,
input wire A,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv_1 (
output wire Y,
input wire A,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = ~A;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn_1 (
output reg Q,
input wire CLK_N,
input wire D,
input wire RESET_B,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
wire CLK = ~CLK_N;
wire RESET = ~RESET_B;
always @(posedge CLK, posedge RESET) begin
if (RESET) Q <= 'd0;
else Q <= D;
end
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp_1 (
output reg Q,
input wire CLK,
input wire D,
input wire RESET_B,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
wire RESET = ~RESET_B;
always @(posedge CLK, posedge RESET) begin
if (RESET) Q <= 'd0;
else Q <= D;
end
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfsbp_1 (
output reg Q,
output wire Q_N,
input wire CLK,
input wire D,
input wire SET_B,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
wire SET = ~SET_B;
always @(posedge CLK, posedge SET) begin
if (SET) Q <= 'd1;
else Q <= D;
end
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
assign Q_N = ~Q;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp_1 (
output reg Q,
input wire CLK,
input wire D,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
always @(posedge CLK) begin
Q <= D;
end
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp_4 (
output reg Q,
input wire CLK,
input wire D,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
always @(posedge CLK) begin
Q <= D;
end
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_1 (
output wire GCLK,
input wire GATE,
input wire CLK,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
reg gate_q;
always @(negedge CLK) gate_q <= GATE;
assign GCLK = gate_q & CLK;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn_1 (
output reg Q,
input wire D,
input wire GATE_N,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
always @(GATE_N, D) begin
if (~GATE_N) Q <= D;
end
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn_4 (
output reg Q,
input wire D,
input wire GATE_N,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
always @(GATE_N, D) begin
if (~GATE_N) Q <= D;
end
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtp_1 (
output reg Q,
input wire D,
input wire GATE,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
always @(GATE, D) begin
if (GATE) Q <= D;
end
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn_1 (
output wire Z,
input wire A,
input wire TE_B,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Z = (~TE_B) ? A : 1'dZ;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp_2 (
output wire Z,
input wire A,
input wire TE,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Z = TE ? (~A) : 1'dZ;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa_1 (
output wire COUT,
output wire SUM,
input wire A,
input wire B,
input wire CIN,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign {COUT, SUM} = (A + B + CIN);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa_2 (
output wire COUT,
output wire SUM,
input wire A,
input wire B,
input wire CIN,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign {COUT, SUM} = (A + B + CIN);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__inv_1 (
output wire Y,
input wire A,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = ~A;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__inv_4 (
output wire Y,
input wire A,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = ~A;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__mux2_1 (
output wire X,
input wire A0,
input wire A1,
input wire S,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = S ? A1 : A0;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__mux2i_1 (
output wire Y,
input wire A0,
input wire A1,
input wire S,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = ~(S ? A1 : A0);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__mux4_1 (
output wire X,
input wire A0,
input wire A1,
input wire A2,
input wire A3,
input wire S0,
input wire S1,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
wire [3:0] choices = {A3, A2, A1, A0};
wire [1:0] selects = {S1, S0};
assign X = choices[selects];
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__nand2_1 (
output wire Y,
input wire A,
input wire B,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = ~(A & B);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__nand2_2 (
output wire Y,
input wire A,
input wire B,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = ~(A & B);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__nand3_2 (
output wire Y,
input wire A,
input wire B,
input wire C,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = ~(A & B & C);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__nand4_1 (
output wire Y,
input wire A,
input wire B,
input wire C,
input wire D,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = ~(A & B & C & D);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__nand4b_1 (
output wire Y,
input wire A_N,
input wire B,
input wire C,
input wire D,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = ~((~A_N) & B & C & D);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__nand4bb_1 (
output wire Y,
input wire A_N,
input wire B_N,
input wire C,
input wire D,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = ~((~A_N) & (~B_N) & C & D);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__nor2_1 (
output wire Y,
input wire A,
input wire B,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = ~(A | B);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__nor4_1 (
output wire Y,
input wire A,
input wire B,
input wire C,
input wire D,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = ~(A | B | C | D);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__nor4b_1 (
output wire Y,
input wire A,
input wire B,
input wire C,
input wire D_N,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = ~(A | B | C | (~D_N));
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__o21a_1 (
output wire X,
input wire A1,
input wire A2,
input wire B1,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = ((A1 | A2) & B1);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__or4_1 (
output wire X,
input wire A,
input wire B,
input wire C,
input wire D,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A | B | C | D;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__or4b_1 (
output wire X,
input wire A,
input wire B,
input wire C,
input wire D_N,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A | B | C | (~D_N);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxtp_1 (
output reg Q,
input wire CLK,
input wire D,
input wire SCD,
input wire SCE,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
wire choice;
assign choice = SCE ? SCD : D;
always @(posedge CLK) begin
Q <= choice;
end
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2_1 (
output wire Y,
input wire A,
input wire B,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign Y = !(A ^ B);
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2_1 (
output wire X,
input wire A,
input wire B,
input wire VPWR,
input wire VGND,
input wire VPB,
input wire VNB
);
assign X = A ^ B;
wire _unused;
assign _unused = &{1'b0, VPWR, VGND, VPB, VNB};
endmodule
| 7.212805 |
module \$adffe (
CLK,
ARST,
EN,
D,
Q
);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
parameter ARST_POLARITY = 1'b1;
parameter ARST_VALUE = 0;
input CLK, ARST, EN;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_arst = ARST == ARST_POLARITY;
always @(posedge pos_clk, posedge pos_arst) begin
if (pos_arst) Q <= ARST_VALUE;
else if (EN == EN_POLARITY) Q <= D;
end
endmodule
| 6.899938 |
module \$adffe (ARST, CLK, D, EN, Q);
parameter ARST_POLARITY =1'b1;
parameter ARST_VALUE =1'b0;
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter WIDTH =1;
input ARST, CLK, EN;
input [WIDTH -1 :0] D;
output [WIDTH -1 :0] Q;
wire GCLK;
wire cg_enb;
wire cg_clk;
wire cg_gclk;
// Check the Polarity of Clock Gate Enable
generate
if(EN_POLARITY == 0) begin
assign cg_enb = ~EN;
end else begin
assign cg_enb = EN;
end
endgenerate
// Check the Polarity of Clock
generate
if(CLK_POLARITY == 0) begin
assign cg_clk = ~CLK;
end else begin
assign cg_clk = CLK;
end
endgenerate
// Check the Width the Data
generate
if (WIDTH < 5) begin
sky130_fd_sc_hd__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_hd__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
else begin
sky130_fd_sc_hd__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
endgenerate
// Check the Polarity of Clock
generate
if(CLK_POLARITY == 0) begin
assign cg_gclk = ~GCLK;
end else begin
assign cg_gclk = GCLK;
end
endgenerate
$adff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.ARST_VALUE(ARST_VALUE) ,
.ARST_POLARITY (ARST_POLARITY)
)
flipflop(
.CLK(cg_gclk),
.ARST(ARST),
.D(D),
.Q(Q)
);
endmodule
| 7.72891 |
module \$dffe (
CLK,
EN,
D,
Q
);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
input CLK, EN;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
always @(posedge pos_clk) begin
if (EN == EN_POLARITY) Q <= D;
end
endmodule
| 6.75819 |
module \$dffe ( CLK, D, EN, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
wire cg_enb;
wire cg_clk;
wire cg_gclk;
// Check the Polarity of Clock Gate Enable
generate
if(EN_POLARITY == 0) begin
assign cg_enb = ~EN;
end else begin
assign cg_enb = EN;
end
endgenerate
// Check the Polarity of Clock
generate
if(CLK_POLARITY == 0) begin
assign cg_clk = ~CLK;
end else begin
assign cg_clk = CLK;
end
endgenerate
// Check the Width the Data
generate
if (WIDTH < 5) begin
sky130_fd_sc_hd__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_hd__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
else begin
sky130_fd_sc_hd__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
endgenerate
// Check the Polarity of Clock
generate
if(CLK_POLARITY == 0) begin
assign cg_gclk = ~GCLK;
end else begin
assign cg_gclk = GCLK;
end
endgenerate
$dff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
)
flipflop(
.CLK(cg_gclk),
.D(D),
.Q(Q)
);
endmodule
| 7.215766 |
module \$dffsre (
CLK,
SET,
CLR,
EN,
D,
Q
);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
input CLK, EN;
input [WIDTH-1:0] SET, CLR, D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : bitslices
always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
if (pos_clr[i]) Q[i] <= 0;
else if (pos_set[i]) Q[i] <= 1;
else if (EN == EN_POLARITY) Q[i] <= D[i];
end
endgenerate
endmodule
| 6.848914 |
module \$dffsre ( CLK, EN, CLR, SET, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter CLR_POLARITY =1'b1;
parameter SET_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN, CLR, SET;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
wire cg_enb;
wire cg_clk;
wire cg_gclk;
// Check the Polarity of Clock Gate Enable
generate
if(EN_POLARITY == 0) begin
assign cg_enb = ~EN;
end else begin
assign cg_enb = EN;
end
endgenerate
// Check the Polarity of Clock
generate
if(CLK_POLARITY == 0) begin
assign cg_clk = ~CLK;
end else begin
assign cg_clk = CLK;
end
endgenerate
// Check the Width the Data
generate
if (WIDTH < 5) begin
sky130_fd_sc_hd__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_hd__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
else begin
sky130_fd_sc_hd__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
endgenerate
// Check the Polarity of Clock
generate
if(CLK_POLARITY == 0) begin
assign cg_gclk = ~GCLK;
end else begin
assign cg_gclk = GCLK;
end
endgenerate
$dffsr #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.CLR_POLARITY(CLR_POLARITY),
.SET_POLARITY(SET_POLARITY)
)
flipflop(
.CLK(cg_gclk),
.CLR(CLR),
.SET(SET),
.D(D),
.Q(Q)
);
endmodule
| 7.063232 |
module \$aldffe (
CLK,
ALOAD,
AD,
EN,
D,
Q
);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
parameter ALOAD_POLARITY = 1'b1;
input CLK, ALOAD, EN;
input [WIDTH-1:0] D;
input [WIDTH-1:0] AD;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_aload = ALOAD == ALOAD_POLARITY;
always @(posedge pos_clk, posedge pos_aload) begin
if (pos_aload) Q <= AD;
else if (EN == EN_POLARITY) Q <= D;
end
endmodule
| 6.732977 |
module \$aldffe ( CLK, EN, ALOAD, AD, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter ALOAD_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN, ALOAD;
input [WIDTH -1:0] D;
input [WIDTH-1:0] AD;
output [WIDTH -1:0] Q;
wire GCLK;
wire cg_enb;
wire cg_clk;
wire cg_gclk;
// Check the Polarity of Clock Gate Enable
generate
if(EN_POLARITY == 0) begin
assign cg_enb = ~EN;
end else begin
assign cg_enb = EN;
end
endgenerate
// Check the Polarity of Clock
generate
if(CLK_POLARITY == 0) begin
assign cg_clk = ~CLK;
end else begin
assign cg_clk = CLK;
end
endgenerate
// Check the Width the Data
generate
if (WIDTH < 5) begin
sky130_fd_sc_hd__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_hd__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
else begin
sky130_fd_sc_hd__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
endgenerate
// Check the Polarity of Clock
generate
if(CLK_POLARITY == 0) begin
assign cg_gclk = ~GCLK;
end else begin
assign cg_gclk = GCLK;
end
endgenerate
$aldff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.ALOAD_POLARITY(ALOAD_POLARITY),
)
flipflop(
.CLK(cg_gclk),
.D(D),
.AD(AD),
.Q(Q)
);
endmodule
| 7.710209 |
module \$sdffe ( CLK, EN, SRST, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter SRST_POLARITY =1'b1;
parameter SRST_VALUE =1'b1;
parameter WIDTH =1;
input CLK, EN, SRST;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
wire cg_enb;
wire cg_clk;
wire cg_gclk;
wire cg_rstenb;
// Check the Polarity of Clock Gate Enable
generate
if(SRST_POLARITY == 0) begin
assign cg_rstenb = ~SRST;
end else begin
assign cg_rstenb = SRST;
end
endgenerate
// Check the Polarity of Clock Gate Enable
// We need to enable clock during reset assertion
generate
if(EN_POLARITY == 0) begin
assign cg_enb = (~EN) | cg_rstenb;
end else begin
assign cg_enb = EN | cg_rstenb;
end
endgenerate
// Check the Polarity of Clock
generate
if(CLK_POLARITY == 0) begin
assign cg_clk = ~CLK;
end else begin
assign cg_clk = CLK;
end
endgenerate
// Check the Width the Data
generate
if (WIDTH < 5) begin
sky130_fd_sc_hd__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_hd__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
else begin
sky130_fd_sc_hd__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
endgenerate
// Check the Polarity of Clock
generate
if(CLK_POLARITY == 0) begin
assign cg_gclk = ~GCLK;
end else begin
assign cg_gclk = GCLK;
end
endgenerate
$sdff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.SRST_POLARITY(SRST_POLARITY),
.SRST_VALUE(SRST_VALUE)
)
flipflop(
.CLK(cg_gclk),
.SRST(SRST),
.D(D),
.Q(Q)
);
endmodule
| 7.043312 |
module \$sdffce ( CLK, EN, SRST, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter SRST_POLARITY =1'b1;
parameter SRST_VALUE =1'b1;
parameter WIDTH =1;
input CLK, EN, SRST;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
wire cg_enb;
wire cg_clk;
wire cg_gclk;
// Check the Polarity of Clock Gate Enable
// We need to enable clock during reset assertion
generate
if(EN_POLARITY == 0) begin
assign cg_enb = ~EN ;
end else begin
assign cg_enb = EN ;
end
endgenerate
// Check the Polarity of Clock
generate
if(CLK_POLARITY == 0) begin
assign cg_clk = ~CLK;
end else begin
assign cg_clk = CLK;
end
endgenerate
// Check the Width the Data
generate
if (WIDTH < 5) begin
sky130_fd_sc_hd__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_hd__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
else begin
sky130_fd_sc_hd__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(cg_clk), .GATE(cg_enb) );
end
endgenerate
// Check the Polarity of Clock
generate
if(CLK_POLARITY == 0) begin
assign cg_gclk = ~GCLK;
end else begin
assign cg_gclk = GCLK;
end
endgenerate
$sdff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.SRST_POLARITY(SRST_POLARITY),
.SRST_VALUE(SRST_VALUE)
)
flipflop(
.CLK(cg_gclk),
.SRST(SRST),
.D(D),
.Q(Q)
);
endmodule
| 6.900616 |
module buffer (
Y,
A
);
output Y;
input A;
sky130_fd_sc_hd__buf_1 buffer (
.X(Y),
.A(A)
);
endmodule
| 6.861394 |
module nand2 (
Y,
A,
B
);
output Y;
input A, B;
sky130_fd_sc_hd__nand2_1 nand2 (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 9.113032 |
module nor2 (
Y,
A,
B
);
output Y;
input A, B;
sky130_fd_sc_hd__nor2_1 nor2 (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 8.297456 |
module and2 (
Y,
A,
B
);
output Y;
input A, B;
sky130_fd_sc_hd__and2_1 and2 (
.X(Y),
.A(A),
.B(B)
);
endmodule
| 7.107954 |
module or2 (
Y,
A,
B
);
output Y;
input A, B;
sky130_fd_sc_hd__or2_1 or2 (
.X(Y),
.A(A),
.B(B)
);
endmodule
| 7.637076 |
module nand3 (
Y,
A,
B,
C
);
output Y;
input A, B, C;
sky130_fd_sc_hd__nand3_1 nand3 (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
| 8.175282 |
module nor3 (
Y,
A,
B,
C
);
output Y;
input A, B, C;
sky130_fd_sc_hd__nor3_1 nor3 (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.681855 |
module and3 (
Y,
A,
B,
C
);
output Y;
input A, B, C;
sky130_fd_sc_hd__and3_1 and3 (
.X(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
| 6.818889 |
module or3 (
Y,
A,
B,
C
);
output Y;
input A, B, C;
sky130_fd_sc_hd__or3_1 or3 (
.X(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.391653 |
module nand4 (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
sky130_fd_sc_hd__nand4_1 nand4 (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 8.989501 |
module nor4 (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
sky130_fd_sc_hd__nor4_1 nor4 (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.13519 |
module and4 (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
sky130_fd_sc_hd__and4_1 and4 (
.X(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.001422 |
module or4 (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
sky130_fd_sc_hd__or4_1 or4 (
.X(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.381621 |
module nand2b (
Y,
A,
B
);
output Y;
input A, B;
sky130_fd_sc_hd__nand2b_1 nand2b (
.Y (Y),
.A_N(A),
.B (B)
);
endmodule
| 6.603018 |
module nor2b (
Y,
A,
B
);
output Y;
input A, B;
sky130_fd_sc_hd__nor2b_1 nor2b (
.Y (Y),
.A (B),
.B_N(A)
);
endmodule
| 6.703764 |
module aoi21 (
Y,
A0,
A1,
B0
);
output Y;
input A0, A1, B0;
sky130_fd_sc_hd__a21oi_1 aoi21 (
.Y (Y),
.A1(A0),
.A2(A1),
.B1(B0)
);
endmodule
| 6.591789 |
module oai21 (
Y,
A0,
A1,
B0
);
output Y;
input A0, A1, B0;
sky130_fd_sc_hd__o21ai_1 oai21 (
.X (Y),
.A1(A0),
.A2(A1),
.B1(B0)
);
endmodule
| 6.561625 |
module aoi22 (
Y,
A0,
A1,
B0,
B1
);
output Y;
input A0, A1, B0, B1;
sky130_fd_sc_hd__a22oi_1 aoi22 (
.Y (Y),
.A1(A0),
.A2(A1),
.B1(B0),
.B2(B1)
);
endmodule
| 6.668353 |
module oai22 (
Y,
A0,
A1,
B0,
B1
);
output Y;
input A0, A1, B0, B1;
sky130_fd_sc_hd__o22ai_1 oai22 (
.Y (Y),
.A1(A0),
.A2(A1),
.B1(B0),
.B2(B1)
);
endmodule
| 6.579044 |
module xor2 (
Y,
A,
B
);
output Y;
input A, B;
sky130_fd_sc_hd__xor2_1 xor2 (
.X(Y),
.A(A),
.B(B)
);
endmodule
| 7.788927 |
module xnor2 (
Y,
A,
B
);
output Y;
input A, B;
sky130_fd_sc_hd__xnor2_1 xnor2 (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 6.713225 |
module mux2 (
Y,
S,
A,
B
);
output Y;
input S, A, B;
sky130_fd_sc_hd__mux2_1 mux2 (
.X (Y),
.S (S),
.A0(A),
.A1(B)
);
endmodule
| 6.809767 |
module muxi2 (
Y,
S,
A,
B
);
output Y;
input S, A, B;
sky130_fd_sc_hd__mux2i_1 muxi2 (
.Y (Y),
.S (S),
.A0(A),
.A1(B)
);
endmodule
| 7.147146 |
module BUF_X1 (
A,
Y
);
input A;
output Y;
sky130_fd_sc_hd__buf_1 BUF (
.A(A),
.X(Y)
);
endmodule
| 6.571469 |
module BUF_X2 (
A,
Y
);
input A;
output Y;
sky130_fd_sc_hd__buf_2 BUF (
.A(A),
.X(Y)
);
endmodule
| 7.223756 |
module BUF_X4 (
A,
Y
);
input A;
output Y;
sky130_fd_sc_hd__buf_4 BUF (
.A(A),
.X(Y)
);
endmodule
| 6.611767 |
module BUF_X8 (
A,
Y
);
input A;
output Y;
sky130_fd_sc_hd__buf_8 BUF (
.A(A),
.X(Y)
);
endmodule
| 7.092578 |
module BUFCLK_X1 (
A,
Y
);
input A;
output Y;
sky130_fd_sc_hd__clkbuf_1 BUF (
.A(A),
.X(Y)
);
endmodule
| 6.658653 |
module BUFCLK_X2 (
A,
Y
);
input A;
output Y;
sky130_fd_sc_hd__clkbuf_2 BUF (
.A(A),
.X(Y)
);
endmodule
| 6.817352 |
module BUFCLK_X4 (
A,
Y
);
input A;
output Y;
sky130_fd_sc_hd__clkbuf_4 BUF (
.A(A),
.X(Y)
);
endmodule
| 6.712303 |
module BUFCLK_X8 (
A,
Y
);
input A;
output Y;
sky130_fd_sc_hd__clkbuf_8 BUF (
.A(A),
.X(Y)
);
endmodule
| 6.58655 |
module CARRY_MUX2 (
A0,
A1,
S,
Y
);
input A0, A1, S;
output Y;
sky130_fd_sc_hd__mux2_1 MUX2_X0 (
.A0(A0),
.A1(A1),
.S (S),
.X (Y)
);
endmodule
| 6.816662 |
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