code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hd__dfbbn_1 (
Q,
Q_N,
D,
CLK_N,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input CLK_N;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbn_1 (
Q,
Q_N,
D,
CLK_N,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input CLK_N;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbn_2 (
Q,
Q_N,
D,
CLK_N,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input CLK_N;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbn_2 (
Q,
Q_N,
D,
CLK_N,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input CLK_N;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp (
Q,
Q_N,
D,
CLK,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input D;
input CLK;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
wire SET;
wire buf_Q;
wire CLK_delayed;
wire RESET_B_delayed;
wire SET_B_delayed;
reg notifier;
wire D_delayed;
wire awake;
wire cond0;
wire cond1;
wire condb;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK_delayed,
D_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
buf buf0 (Q, buf_Q);
not not2 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp (
Q,
Q_N,
D,
CLK,
SET_B,
RESET_B
);
// Module ports
output Q;
output Q_N;
input D;
input CLK;
input SET_B;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
wire SET;
wire buf_Q;
wire CLK_delayed;
wire RESET_B_delayed;
wire SET_B_delayed;
reg notifier;
wire D_delayed;
wire awake;
wire cond0;
wire cond1;
wire condb;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK_delayed,
D_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
buf buf0 (Q, buf_Q);
not not2 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp (
Q,
Q_N,
D,
CLK,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input CLK;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire SET ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET;
wire SET ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp (
Q,
Q_N,
D,
CLK,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input CLK;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
input SET_B,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp_1 (
Q,
Q_N,
D,
CLK,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input CLK;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp_1 (
Q,
Q_N,
D,
CLK,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input CLK;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp (
Q,
Q_N,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp (
Q,
Q_N,
CLK,
D,
RESET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp (
Q,
Q_N,
CLK,
D,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp (
Q,
Q_N,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp_1 (
Q,
Q_N,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp_1 (
Q,
Q_N,
CLK,
D,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp_2 (
Q,
Q_N,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp_2 (
Q,
Q_N,
CLK,
D,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn (
Q,
CLK_N,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK_N;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
wire intclk;
reg notifier;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_N_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (intclk, CLK_N_delayed);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
intclk,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn (
Q,
CLK_N,
D,
RESET_B
);
// Module ports
output Q;
input CLK_N;
input D;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
wire intclk;
reg notifier;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_N_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (intclk, CLK_N_delayed);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
intclk,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn (
Q,
CLK_N,
D,
RESET_B
);
output Q;
input CLK_N;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn (
Q,
CLK_N,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK_N;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK_N,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn_1 (
Q,
CLK_N,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK_N;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn_1 (
Q,
CLK_N,
D,
RESET_B
);
output Q;
input CLK_N;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp (
Q,
CLK,
D,
RESET_B
);
// Module ports
output Q;
input CLK;
input D;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp (
Q,
CLK,
D,
RESET_B
);
output Q;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp_1 (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp_1 (
Q,
CLK,
D,
RESET_B
);
output Q;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp_2 (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp_2 (
Q,
CLK,
D,
RESET_B
);
output Q;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp_4 (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtp_4 (
Q,
CLK,
D,
RESET_B
);
output Q;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfsbp (
Q,
Q_N,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
wire D_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (SET_B_delayed === 1'b1);
assign cond1 = (SET_B === 1'b1);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfsbp (
Q,
Q_N,
CLK,
D,
SET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
wire D_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (SET_B_delayed === 1'b1);
assign cond1 = (SET_B === 1'b1);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfsbp (
Q,
Q_N,
CLK,
D,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfsbp (
Q,
Q_N,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfsbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfsbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfsbp_1 (
Q,
Q_N,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfsbp_1 (
Q,
Q_N,
CLK,
D,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfsbp_2 (
Q,
Q_N,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfsbp_2 (
Q,
Q_N,
CLK,
D,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
wire D_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (SET_B_delayed === 1'b1);
assign cond1 = (SET_B === 1'b1);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp (
Q,
CLK,
D,
SET_B
);
// Module ports
output Q;
input CLK;
input D;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
wire D_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (SET_B_delayed === 1'b1);
assign cond1 = (SET_B === 1'b1);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp (
Q,
CLK,
D,
SET_B
);
output Q;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp_1 (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp_1 (
Q,
CLK,
D,
SET_B
);
output Q;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp_2 (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp_2 (
Q,
CLK,
D,
SET_B
);
output Q;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp_4 (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfstp_4 (
Q,
CLK,
D,
SET_B
);
output Q;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxbp (
Q,
Q_N,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire CLK_delayed;
wire awake;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxbp (
Q,
Q_N,
CLK,
D
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire CLK_delayed;
wire awake;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxbp (
Q,
Q_N,
CLK,
D
);
output Q;
output Q_N;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxbp (
Q,
Q_N,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxbp_1 (
Q,
Q_N,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxbp_1 (
Q,
Q_N,
CLK,
D
);
output Q;
output Q_N;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxbp_2 (
Q,
Q_N,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxbp_2 (
Q,
Q_N,
CLK,
D
);
output Q;
output Q_N;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp (
Q,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire CLK_delayed;
wire awake;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp (
Q,
CLK,
D
);
// Module ports
output Q;
input CLK;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire CLK_delayed;
wire awake;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp (
Q,
CLK,
D
);
output Q;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp (
Q,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp_1 (
Q,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp_1 (
Q,
CLK,
D
);
output Q;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfxtp base (
.Q (Q),
.CLK(CLK),
.D (D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp_2 (
Q,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp_2 (
Q,
CLK,
D
);
output Q;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfxtp base (
.Q (Q),
.CLK(CLK),
.D (D)
);
endmodule
| 7.212805 |
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