code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module sky130_fd_sc_hd__dfxtp_4 (
Q,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp_4 (
Q,
CLK,
D
);
output Q;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfxtp base (
.Q (Q),
.CLK(CLK),
.D (D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode (
DIODE
);
// Module ports
input DIODE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode (
DIODE
);
// Module ports
input DIODE;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode (
//# {{power|Power}}
input DIODE,
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode (
//# {{power|Power}}
input DIODE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode_2 (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__diode base (
.DIODE(DIODE),
.VPWR (VPWR),
.VGND (VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode_2 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__diode base (.DIODE(DIODE));
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire m0;
wire clkn;
wire CLK_delayed;
wire GATE_delayed;
reg notifier;
wire awake;
// Name Output Other arguments
not not0 (clkn, CLK_delayed);
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
GATE_delayed,
clkn,
notifier,
VPWR,
VGND
);
and and0 (GCLK, m0, CLK_delayed);
assign awake = (VPWR === 1'b1);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire m0;
wire clkn;
wire CLK_delayed;
wire GATE_delayed;
reg notifier;
wire awake;
// Name Output Other arguments
not not0 (clkn, CLK_delayed);
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
GATE_delayed,
clkn,
notifier,
VPWR,
VGND
);
and and0 (GCLK, m0, CLK_delayed);
assign awake = (VPWR === 1'b1);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire m0;
wire clkn;
// Name Output Other arguments
not not0 (clkn, CLK);
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
GATE,
clkn
,,
VPWR,
VGND
);
and and0 (GCLK, m0, CLK);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK;
// Local signals
wire m0;
wire clkn;
// Name Output Other arguments
not not0 (clkn, CLK);
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (
m0,
GATE,
clkn
);
and and0 (GCLK, m0, CLK);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp (
//# {{clocks|Clocking}}
input CLK,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp (
//# {{clocks|Clocking}}
input CLK,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_1 (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_1 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_2 (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_2 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_4 (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_4 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbn (
Q,
Q_N,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
wire intgate;
reg notifier;
wire D_delayed;
wire GATE_N_delayed;
wire RESET_delayed;
wire RESET_B_delayed;
wire buf_Q;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (intgate, GATE_N_delayed);
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
intgate,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
not not2 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbn (
Q,
Q_N,
RESET_B,
D,
GATE_N
);
// Module ports
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
wire intgate;
reg notifier;
wire D_delayed;
wire GATE_N_delayed;
wire RESET_delayed;
wire RESET_B_delayed;
wire buf_Q;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (intgate, GATE_N_delayed);
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
intgate,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
not not2 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbn (
Q,
Q_N,
RESET_B,
D,
GATE_N
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbn (
Q,
Q_N,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbn (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbn (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbn_1 (
Q,
Q_N,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbn_1 (
Q,
Q_N,
RESET_B,
D,
GATE_N
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbn_2 (
Q,
Q_N,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbn_2 (
Q,
Q_N,
RESET_B,
D,
GATE_N
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbp (
Q,
Q_N,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
reg notifier;
wire D_delayed;
wire GATE_delayed;
wire RESET_delayed;
wire RESET_B_delayed;
wire buf_Q;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbp (
Q,
Q_N,
RESET_B,
D,
GATE
);
// Module ports
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
reg notifier;
wire D_delayed;
wire GATE_delayed;
wire RESET_delayed;
wire RESET_B_delayed;
wire buf_Q;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbp (
Q,
Q_N,
RESET_B,
D,
GATE
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbp (
Q,
Q_N,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbp_1 (
Q,
Q_N,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbp_1 (
Q,
Q_N,
RESET_B,
D,
GATE
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbp_2 (
Q,
Q_N,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbp_2 (
Q,
Q_N,
RESET_B,
D,
GATE
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
wire intgate;
reg notifier;
wire D_delayed;
wire GATE_N_delayed;
wire RESET_delayed;
wire RESET_B_delayed;
wire buf_Q;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (intgate, GATE_N_delayed);
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
intgate,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn (
Q,
RESET_B,
D,
GATE_N
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
wire intgate;
reg notifier;
wire D_delayed;
wire GATE_N_delayed;
wire RESET_delayed;
wire RESET_B_delayed;
wire buf_Q;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (intgate, GATE_N_delayed);
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
intgate,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn (
Q,
RESET_B,
D,
GATE_N
);
output Q;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn_1 (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn_1 (
Q,
RESET_B,
D,
GATE_N
);
output Q;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn_2 (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn_2 (
Q,
RESET_B,
D,
GATE_N
);
output Q;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn_4 (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtn_4 (
Q,
RESET_B,
D,
GATE_N
);
output Q;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
reg notifier;
wire D_delayed;
wire GATE_delayed;
wire RESET_delayed;
wire RESET_B_delayed;
wire buf_Q;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp (
Q,
RESET_B,
D,
GATE
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
reg notifier;
wire D_delayed;
wire GATE_delayed;
wire RESET_delayed;
wire RESET_B_delayed;
wire buf_Q;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp (
Q,
RESET_B,
D,
GATE
);
output Q;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp_1 (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp_1 (
Q,
RESET_B,
D,
GATE
);
output Q;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp_2 (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp_2 (
Q,
RESET_B,
D,
GATE
);
output Q;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp_4 (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrtp_4 (
Q,
RESET_B,
D,
GATE
);
output Q;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbn (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
wire 1 ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
assign awake = ( VPWR === 1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
wire 1 ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
assign awake = ( VPWR === 1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbn (
Q,
Q_N,
D,
GATE_N
);
output Q;
output Q_N;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbn (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire GATE ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Local signals
wire GATE ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_hd__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbn (
Q,
Q_N,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbn (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbn (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbn_1 (
Q,
Q_N,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbn_1 (
Q,
Q_N,
D,
GATE_N
);
output Q;
output Q_N;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbn_2 (
Q,
Q_N,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbn_2 (
Q,
Q_N,
D,
GATE_N
);
output Q;
output Q_N;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbp (
Q,
Q_N,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire GATE_delayed;
wire D_delayed;
reg notifier;
wire awake;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
assign awake = (VPWR === 1'b1);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbp (
Q,
Q_N,
D,
GATE
);
// Module ports
output Q;
output Q_N;
input D;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire GATE_delayed;
wire D_delayed;
reg notifier;
wire awake;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
assign awake = (VPWR === 1'b1);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbp (
Q,
Q_N,
D,
GATE
);
output Q;
output Q_N;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbp (
Q,
Q_N,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbp_1 (
Q,
Q_N,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxbp_1 (
Q,
Q_N,
D,
GATE
);
output Q;
output Q_N;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE)
);
endmodule
| 7.212805 |
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