code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module sky130_fd_sc_hd__dlxtn (
Q,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire GATE;
wire buf_Q;
wire GATE_N_delayed;
wire D_delayed;
reg notifier;
wire awake;
// Name Output Other arguments
not not0 (GATE, GATE_N_delayed);
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE,
notifier,
VPWR,
VGND
);
buf buf0 (Q, buf_Q);
assign awake = (VPWR === 1'b1);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn (
Q,
D,
GATE_N
);
// Module ports
output Q;
input D;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire GATE;
wire buf_Q;
wire GATE_N_delayed;
wire D_delayed;
reg notifier;
wire awake;
// Name Output Other arguments
not not0 (GATE, GATE_N_delayed);
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE,
notifier,
VPWR,
VGND
);
buf buf0 (Q, buf_Q);
assign awake = (VPWR === 1'b1);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn (
Q,
D,
GATE_N
);
output Q;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn (
Q,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire GATE;
wire buf_Q;
// Name Output Other arguments
not not0 (GATE, GATE_N);
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
D,
GATE
,,
VPWR,
VGND
);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn (
Q,
D,
GATE_N
);
// Module ports
output Q;
input D;
input GATE_N;
// Local signals
wire GATE;
wire buf_Q;
// Name Output Other arguments
not not0 (GATE, GATE_N);
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (
buf_Q,
D,
GATE
);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn (
Q,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn_1 (
Q,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn_1 (
Q,
D,
GATE_N
);
output Q;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn_2 (
Q,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn_2 (
Q,
D,
GATE_N
);
output Q;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn_4 (
Q,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtn_4 (
Q,
D,
GATE_N
);
output Q;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtp (
Q,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire GATE_delayed;
wire D_delayed;
reg notifier;
wire awake;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (Q, buf_Q);
assign awake = (VPWR === 1'b1);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtp (
Q,
D,
GATE
);
// Module ports
output Q;
input D;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire GATE_delayed;
wire D_delayed;
reg notifier;
wire awake;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (Q, buf_Q);
assign awake = (VPWR === 1'b1);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtp (
Q,
D,
GATE
);
output Q;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtp (
Q,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
D,
GATE
,,
VPWR,
VGND
);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtp (
Q,
D,
GATE
);
// Module ports
output Q;
input D;
input GATE;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (
buf_Q,
D,
GATE
);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtp (
Q,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtp_1 (
Q,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtp_1 (
Q,
D,
GATE
);
output Q;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd1 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd1 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd1 (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd1 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd1_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlygate4sd1 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd1_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlygate4sd1 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd2 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd2 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd2 (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd2 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd2_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlygate4sd2 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd2_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlygate4sd2 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd3 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd3 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd3 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd3 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd3 (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd3 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd3_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlygate4sd3 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlygate4sd3_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlygate4sd3 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s2s (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s2s (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s2s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s2s (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s2s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s2s (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s2s (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s2s (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s2s_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlymetal6s2s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s2s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlymetal6s2s base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s4s (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s4s (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s4s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s4s (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s4s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s4s (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s4s (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s4s (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s4s_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlymetal6s4s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s4s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlymetal6s4s base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s6s (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s6s (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s6s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s6s (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s6s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s6s (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s6s (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s6s (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s6s_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlymetal6s6s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlymetal6s6s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlymetal6s6s base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_A,
A,
VPWR,
VGND
);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_teb,
TE_B,
VPWR,
VGND
);
bufif0 bufif00 (Z, pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn (
Z,
A,
TE_B
);
// Module ports
output Z;
input A;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output Other arguments
bufif0 bufif00 (Z, A, TE_B);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_A,
A,
VPWR,
VGND
);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_teb,
TE_B,
VPWR,
VGND
);
bufif0 bufif00 (Z, pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn (
Z,
A,
TE_B
);
// Module ports
output Z;
input A;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z, A, TE_B);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn_1 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn_1 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn_2 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn_2 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn_4 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn_4 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn_8 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__ebufn_8 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
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