code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module sky130_fd_sc_hd__edfxbp (
Q,
Q_N,
CLK,
D,
DE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input DE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire DE_delayed;
wire CLK_delayed;
wire mux_out;
wire awake;
wire cond0;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
buf_Q,
D_delayed,
DE_delayed
);
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (DE_delayed === 1'b1));
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxbp (
Q,
Q_N,
CLK,
D,
DE
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input DE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire DE_delayed;
wire CLK_delayed;
wire mux_out;
wire awake;
wire cond0;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
buf_Q,
D_delayed,
DE_delayed
);
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (DE_delayed === 1'b1));
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxbp (
Q,
Q_N,
CLK,
D,
DE
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxbp (
Q ,
Q_N,
CLK,
D ,
DE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxbp (
Q,
Q_N,
CLK,
D,
DE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input DE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input DE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxbp_1 (
Q,
Q_N,
CLK,
D,
DE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__edfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxbp_1 (
Q,
Q_N,
CLK,
D,
DE
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__edfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D),
.DE (DE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxtp (
Q,
CLK,
D,
DE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input DE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire DE_delayed;
wire CLK_delayed;
wire mux_out;
wire awake;
wire cond0;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
buf_Q,
D_delayed,
DE_delayed
);
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (DE_delayed === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxtp (
Q,
CLK,
D,
DE
);
// Module ports
output Q;
input CLK;
input D;
input DE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire DE_delayed;
wire CLK_delayed;
wire mux_out;
wire awake;
wire cond0;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
buf_Q,
D_delayed,
DE_delayed
);
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (DE_delayed === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxtp (
Q,
CLK,
D,
DE
);
output Q;
input CLK;
input D;
input DE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxtp (
Q ,
CLK,
D ,
DE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxtp (
Q,
CLK,
D,
DE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input DE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input DE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input DE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxtp_1 (
Q,
CLK,
D,
DE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input DE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__edfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__edfxtp_1 (
Q,
CLK,
D,
DE
);
output Q;
input CLK;
input D;
input DE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__edfxtp base (
.Q (Q),
.CLK(CLK),
.D (D),
.DE (DE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_A,
A,
VPWR,
VGND
);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_teb,
TE_B,
VPWR,
VGND
);
notif0 notif00 (Z, pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn (
Z,
A,
TE_B
);
// Module ports
output Z;
input A;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output Other arguments
notif0 notif00 (Z, A, TE_B);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_A,
A,
VPWR,
VGND
);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_teb,
TE_B,
VPWR,
VGND
);
notif0 notif00 (Z, pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn (
Z,
A,
TE_B
);
// Module ports
output Z;
input A;
input TE_B;
// Name Output Other arguments
notif0 notif00 (Z, A, TE_B);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn_0 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn_0 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn_1 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn_1 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn_2 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn_2 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn_4 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn_4 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn_8 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvn_8 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_A,
A,
VPWR,
VGND
);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_TE,
TE,
VPWR,
VGND
);
notif1 notif10 (Z, pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp (
Z,
A,
TE
);
// Module ports
output Z;
input A;
input TE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output Other arguments
notif1 notif10 (Z, A, TE);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp (
Z,
A,
TE
);
output Z;
input A;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_A,
A,
VPWR,
VGND
);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_TE,
TE,
VPWR,
VGND
);
notif1 notif10 (Z, pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp (
Z,
A,
TE
);
// Module ports
output Z;
input A;
input TE;
// Name Output Other arguments
notif1 notif10 (Z, A, TE);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp_1 (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp_1 (
Z,
A,
TE
);
output Z;
input A;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__einvp base (
.Z (Z),
.A (A),
.TE(TE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp_2 (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp_2 (
Z,
A,
TE
);
output Z;
input A;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__einvp base (
.Z (Z),
.A (A),
.TE(TE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp_4 (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp_4 (
Z,
A,
TE
);
output Z;
input A;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__einvp base (
.Z (Z),
.A (A),
.TE(TE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp_8 (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__einvp_8 (
Z,
A,
TE
);
output Z;
input A;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__einvp base (
.Z (Z),
.A (A),
.TE(TE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa (
COUT,
SUM,
A,
B,
CIN,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output COUT;
output SUM;
input A;
input B;
input CIN;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out;
wire and0_out;
wire and1_out;
wire and2_out;
wire nor0_out;
wire nor1_out;
wire or1_out_COUT;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM;
wire pwrgood_pp1_out_SUM;
// Name Output Other arguments
or or0 (or0_out, CIN, B);
and and0 (and0_out, or0_out, A);
and and1 (and1_out, B, CIN);
or or1 (or1_out_COUT, and1_out, and0_out);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_COUT,
or1_out_COUT,
VPWR,
VGND
);
buf buf0 (COUT, pwrgood_pp0_out_COUT);
and and2 (and2_out, CIN, A, B);
nor nor0 (nor0_out, A, or0_out);
nor nor1 (nor1_out, nor0_out, COUT);
or or2 (or2_out_SUM, nor1_out, and2_out);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_SUM,
or2_out_SUM,
VPWR,
VGND
);
buf buf1 (SUM, pwrgood_pp1_out_SUM);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa (
COUT,
SUM,
A,
B,
CIN
);
// Module ports
output COUT;
output SUM;
input A;
input B;
input CIN;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire or0_out;
wire and0_out;
wire and1_out;
wire and2_out;
wire nor0_out;
wire nor1_out;
wire or1_out_COUT;
wire or2_out_SUM;
// Name Output Other arguments
or or0 (or0_out, CIN, B);
and and0 (and0_out, or0_out, A);
and and1 (and1_out, B, CIN);
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT, or1_out_COUT);
and and2 (and2_out, CIN, A, B);
nor nor0 (nor0_out, A, or0_out);
nor nor1 (nor1_out, nor0_out, COUT);
or or2 (or2_out_SUM, nor1_out, and2_out);
buf buf1 (SUM, or2_out_SUM);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa (
COUT,
SUM,
A,
B,
CIN
);
output COUT;
output SUM;
input A;
input B;
input CIN;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa (
COUT,
SUM,
A,
B,
CIN,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output COUT;
output SUM;
input A;
input B;
input CIN;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out;
wire and0_out;
wire and1_out;
wire and2_out;
wire nor0_out;
wire nor1_out;
wire or1_out_COUT;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM;
wire pwrgood_pp1_out_SUM;
// Name Output Other arguments
or or0 (or0_out, CIN, B);
and and0 (and0_out, or0_out, A);
and and1 (and1_out, B, CIN);
or or1 (or1_out_COUT, and1_out, and0_out);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_COUT,
or1_out_COUT,
VPWR,
VGND
);
buf buf0 (COUT, pwrgood_pp0_out_COUT);
and and2 (and2_out, CIN, A, B);
nor nor0 (nor0_out, A, or0_out);
nor nor1 (nor1_out, nor0_out, COUT);
or or2 (or2_out_SUM, nor1_out, and2_out);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_SUM,
or2_out_SUM,
VPWR,
VGND
);
buf buf1 (SUM, pwrgood_pp1_out_SUM);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa (
COUT,
SUM,
A,
B,
CIN
);
// Module ports
output COUT;
output SUM;
input A;
input B;
input CIN;
// Local signals
wire or0_out;
wire and0_out;
wire and1_out;
wire and2_out;
wire nor0_out;
wire nor1_out;
wire or1_out_COUT;
wire or2_out_SUM;
// Name Output Other arguments
or or0 (or0_out, CIN, B);
and and0 (and0_out, or0_out, A);
and and1 (and1_out, B, CIN);
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT, or1_out_COUT);
and and2 (and2_out, CIN, A, B);
nor nor0 (nor0_out, A, or0_out);
nor nor1 (nor1_out, nor0_out, COUT);
or or2 (or2_out_SUM, nor1_out, and2_out);
buf buf1 (SUM, or2_out_SUM);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa (
COUT,
SUM,
A,
B,
CIN,
VPWR,
VGND,
VPB,
VNB
);
output COUT;
output SUM;
input A;
input B;
input CIN;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa (
//# {{data|Data Signals}}
input A,
input B,
input CIN,
output COUT,
output SUM,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa (
//# {{data|Data Signals}}
input A,
input B,
input CIN,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fah (
COUT,
SUM,
A,
B,
CI,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output COUT;
output SUM;
input A;
input B;
input CI;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_SUM;
wire pwrgood_pp0_out_SUM;
wire a_b;
wire a_ci;
wire b_ci;
wire or0_out_COUT;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_SUM,
xor0_out_SUM,
VPWR,
VGND
);
buf buf0 (SUM, pwrgood_pp0_out_SUM);
and and0 (a_b, A, B);
and and1 (a_ci, A, CI);
and and2 (b_ci, B, CI);
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_COUT,
or0_out_COUT,
VPWR,
VGND
);
buf buf1 (COUT, pwrgood_pp1_out_COUT);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fah (
COUT,
SUM,
A,
B,
CI
);
// Module ports
output COUT;
output SUM;
input A;
input B;
input CI;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xor0_out_SUM;
wire a_b;
wire a_ci;
wire b_ci;
wire or0_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI);
buf buf0 (SUM, xor0_out_SUM);
and and0 (a_b, A, B);
and and1 (a_ci, A, CI);
and and2 (b_ci, B, CI);
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT, or0_out_COUT);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fah (
COUT,
SUM,
A,
B,
CI
);
output COUT;
output SUM;
input A;
input B;
input CI;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fah (
COUT,
SUM,
A,
B,
CI,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output COUT;
output SUM;
input A;
input B;
input CI;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_SUM;
wire pwrgood_pp0_out_SUM;
wire a_b;
wire a_ci;
wire b_ci;
wire or0_out_COUT;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_SUM,
xor0_out_SUM,
VPWR,
VGND
);
buf buf0 (SUM, pwrgood_pp0_out_SUM);
and and0 (a_b, A, B);
and and1 (a_ci, A, CI);
and and2 (b_ci, B, CI);
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_COUT,
or0_out_COUT,
VPWR,
VGND
);
buf buf1 (COUT, pwrgood_pp1_out_COUT);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fah (
COUT,
SUM,
A,
B,
CI
);
// Module ports
output COUT;
output SUM;
input A;
input B;
input CI;
// Local signals
wire xor0_out_SUM;
wire a_b;
wire a_ci;
wire b_ci;
wire or0_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI);
buf buf0 (SUM, xor0_out_SUM);
and and0 (a_b, A, B);
and and1 (a_ci, A, CI);
and and2 (b_ci, B, CI);
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT, or0_out_COUT);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fah (
COUT,
SUM,
A,
B,
CI,
VPWR,
VGND,
VPB,
VNB
);
output COUT;
output SUM;
input A;
input B;
input CI;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fah (
//# {{data|Data Signals}}
input A,
input B,
input CI,
output COUT,
output SUM,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fah (
//# {{data|Data Signals}}
input A,
input B,
input CI,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcin (
COUT,
SUM,
A,
B,
CIN,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output COUT;
output SUM;
input A;
input B;
input CIN;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire ci;
wire xor0_out_SUM;
wire pwrgood_pp0_out_SUM;
wire a_b;
wire a_ci;
wire b_ci;
wire or0_out_COUT;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
not not0 (ci, CIN);
xor xor0 (xor0_out_SUM, A, B, ci);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_SUM,
xor0_out_SUM,
VPWR,
VGND
);
buf buf0 (SUM, pwrgood_pp0_out_SUM);
and and0 (a_b, A, B);
and and1 (a_ci, A, ci);
and and2 (b_ci, B, ci);
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_COUT,
or0_out_COUT,
VPWR,
VGND
);
buf buf1 (COUT, pwrgood_pp1_out_COUT);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcin (
COUT,
SUM,
A,
B,
CIN
);
// Module ports
output COUT;
output SUM;
input A;
input B;
input CIN;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire ci;
wire xor0_out_SUM;
wire a_b;
wire a_ci;
wire b_ci;
wire or0_out_COUT;
// Name Output Other arguments
not not0 (ci, CIN);
xor xor0 (xor0_out_SUM, A, B, ci);
buf buf0 (SUM, xor0_out_SUM);
and and0 (a_b, A, B);
and and1 (a_ci, A, ci);
and and2 (b_ci, B, ci);
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT, or0_out_COUT);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcin (
COUT,
SUM,
A,
B,
CIN
);
output COUT;
output SUM;
input A;
input B;
input CIN;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcin (
COUT,
SUM,
A,
B,
CIN,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output COUT;
output SUM;
input A;
input B;
input CIN;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire ci;
wire xor0_out_SUM;
wire pwrgood_pp0_out_SUM;
wire a_b;
wire a_ci;
wire b_ci;
wire or0_out_COUT;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
not not0 (ci, CIN);
xor xor0 (xor0_out_SUM, A, B, ci);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_SUM,
xor0_out_SUM,
VPWR,
VGND
);
buf buf0 (SUM, pwrgood_pp0_out_SUM);
and and0 (a_b, A, B);
and and1 (a_ci, A, ci);
and and2 (b_ci, B, ci);
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_COUT,
or0_out_COUT,
VPWR,
VGND
);
buf buf1 (COUT, pwrgood_pp1_out_COUT);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcin (
COUT,
SUM,
A,
B,
CIN
);
// Module ports
output COUT;
output SUM;
input A;
input B;
input CIN;
// Local signals
wire ci;
wire xor0_out_SUM;
wire a_b;
wire a_ci;
wire b_ci;
wire or0_out_COUT;
// Name Output Other arguments
not not0 (ci, CIN);
xor xor0 (xor0_out_SUM, A, B, ci);
buf buf0 (SUM, xor0_out_SUM);
and and0 (a_b, A, B);
and and1 (a_ci, A, ci);
and and2 (b_ci, B, ci);
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT, or0_out_COUT);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcin (
COUT,
SUM,
A,
B,
CIN,
VPWR,
VGND,
VPB,
VNB
);
output COUT;
output SUM;
input A;
input B;
input CIN;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcin (
//# {{data|Data Signals}}
input A,
input B,
input CIN,
output COUT,
output SUM,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcin (
//# {{data|Data Signals}}
input A,
input B,
input CIN,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcin_1 (
COUT,
SUM,
A,
B,
CIN,
VPWR,
VGND,
VPB,
VNB
);
output COUT;
output SUM;
input A;
input B;
input CIN;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__fahcin base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcin_1 (
COUT,
SUM,
A,
B,
CIN
);
output COUT;
output SUM;
input A;
input B;
input CIN;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__fahcin base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM,
A,
B,
CI,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output COUT_N;
output SUM;
input A;
input B;
input CI;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_SUM;
wire pwrgood_pp0_out_SUM;
wire a_b;
wire a_ci;
wire b_ci;
wire or0_out_coutn;
wire pwrgood_pp1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_SUM,
xor0_out_SUM,
VPWR,
VGND
);
buf buf0 (SUM, pwrgood_pp0_out_SUM);
nor nor0 (a_b, A, B);
nor nor1 (a_ci, A, CI);
nor nor2 (b_ci, B, CI);
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_coutn,
or0_out_coutn,
VPWR,
VGND
);
buf buf1 (COUT_N, pwrgood_pp1_out_coutn);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM,
A,
B,
CI
);
// Module ports
output COUT_N;
output SUM;
input A;
input B;
input CI;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xor0_out_SUM;
wire a_b;
wire a_ci;
wire b_ci;
wire or0_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI);
buf buf0 (SUM, xor0_out_SUM);
nor nor0 (a_b, A, B);
nor nor1 (a_ci, A, CI);
nor nor2 (b_ci, B, CI);
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N, or0_out_coutn);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM,
A,
B,
CI
);
output COUT_N;
output SUM;
input A;
input B;
input CI;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM,
A,
B,
CI,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output COUT_N;
output SUM;
input A;
input B;
input CI;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_SUM;
wire pwrgood_pp0_out_SUM;
wire a_b;
wire a_ci;
wire b_ci;
wire or0_out_coutn;
wire pwrgood_pp1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_SUM,
xor0_out_SUM,
VPWR,
VGND
);
buf buf0 (SUM, pwrgood_pp0_out_SUM);
nor nor0 (a_b, A, B);
nor nor1 (a_ci, A, CI);
nor nor2 (b_ci, B, CI);
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_coutn,
or0_out_coutn,
VPWR,
VGND
);
buf buf1 (COUT_N, pwrgood_pp1_out_coutn);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM,
A,
B,
CI
);
// Module ports
output COUT_N;
output SUM;
input A;
input B;
input CI;
// Local signals
wire xor0_out_SUM;
wire a_b;
wire a_ci;
wire b_ci;
wire or0_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI);
buf buf0 (SUM, xor0_out_SUM);
nor nor0 (a_b, A, B);
nor nor1 (a_ci, A, CI);
nor nor2 (b_ci, B, CI);
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N, or0_out_coutn);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM,
A,
B,
CI,
VPWR,
VGND,
VPB,
VNB
);
output COUT_N;
output SUM;
input A;
input B;
input CI;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcon (
//# {{data|Data Signals}}
input A,
input B,
input CI,
output COUT_N,
output SUM,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcon (
//# {{data|Data Signals}}
input A,
input B,
input CI,
output COUT_N,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcon_1 (
COUT_N,
SUM,
A,
B,
CI,
VPWR,
VGND,
VPB,
VNB
);
output COUT_N;
output SUM;
input A;
input B;
input CI;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fahcon_1 (
COUT_N,
SUM,
A,
B,
CI
);
output COUT_N;
output SUM;
input A;
input B;
input CI;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fah_1 (
COUT,
SUM,
A,
B,
CI,
VPWR,
VGND,
VPB,
VNB
);
output COUT;
output SUM;
input A;
input B;
input CI;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fah_1 (
COUT,
SUM,
A,
B,
CI
);
output COUT;
output SUM;
input A;
input B;
input CI;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa_1 (
COUT,
SUM,
A,
B,
CIN,
VPWR,
VGND,
VPB,
VNB
);
output COUT;
output SUM;
input A;
input B;
input CIN;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa_1 (
COUT,
SUM,
A,
B,
CIN
);
output COUT;
output SUM;
input A;
input B;
input CIN;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa_2 (
COUT,
SUM,
A,
B,
CIN,
VPWR,
VGND,
VPB,
VNB
);
output COUT;
output SUM;
input A;
input B;
input CIN;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa_2 (
COUT,
SUM,
A,
B,
CIN
);
output COUT;
output SUM;
input A;
input B;
input CIN;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa_4 (
COUT,
SUM,
A,
B,
CIN,
VPWR,
VGND,
VPB,
VNB
);
output COUT;
output SUM;
input A;
input B;
input CIN;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fa_4 (
COUT,
SUM,
A,
B,
CIN
);
output COUT;
output SUM;
input A;
input B;
input CIN;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fill (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
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