code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module sky130_fd_sc_hd__or4b_4 (
X,
A,
B,
C,
D_N,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input D_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__or4b_4 (
X,
A,
B,
C,
D_N
);
output X;
input A;
input B;
input C;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__or4b base (
.X (X),
.A (A),
.B (B),
.C (C),
.D_N(D_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__or4_1 (
X,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__or4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__or4_2 (
X,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__or4_2 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__or4_4 (
X,
A,
B,
C,
D,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__or4_4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p (
X,
A,
VGND,
VNB,
VPB,
VPWR
);
// Module ports
output X;
input A;
input VGND;
input VNB;
input VPB;
input VPWR;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p (
X,
A
);
output X;
input A;
// Voltage supply signals
supply0 VGND;
supply0 VNB;
supply1 VPB;
supply1 VPWR;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p (
X,
A,
VGND,
VNB,
VPB,
VPWR
);
// Module ports
output X;
input A;
input VGND;
input VNB;
input VPB;
input VPWR;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p (
X,
A,
VGND,
VNB,
VPB,
VPWR
);
output X;
input A;
input VGND;
input VNB;
input VPB;
input VPWR;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply0 VGND;
supply0 VNB;
supply1 VPB;
supply1 VPWR;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p_8 (
X,
A,
VGND,
VNB,
VPB,
VPWR
);
output X;
input A;
input VGND;
input VNB;
input VPB;
input VPWR;
sky130_fd_sc_hd__probec_p base (
.X(X),
.A(A),
.VGND(VGND),
.VNB(VNB),
.VPB(VPB),
.VPWR(VPWR)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply0 VGND;
supply0 VNB;
supply1 VPB;
supply1 VPWR;
sky130_fd_sc_hd__probec_p base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probe_p (
X,
A,
VGND,
VNB,
VPB,
VPWR
);
// Module ports
output X;
input A;
input VGND;
input VNB;
input VPB;
input VPWR;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probe_p (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probe_p (
X,
A
);
output X;
input A;
// Voltage supply signals
supply0 VGND;
supply0 VNB;
supply1 VPB;
supply1 VPWR;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probe_p (
X,
A,
VGND,
VNB,
VPB,
VPWR
);
// Module ports
output X;
input A;
input VGND;
input VNB;
input VPB;
input VPWR;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probe_p (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probe_p (
X,
A,
VGND,
VNB,
VPB,
VPWR
);
output X;
input A;
input VGND;
input VNB;
input VPB;
input VPWR;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probe_p (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probe_p (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply0 VGND;
supply0 VNB;
supply1 VPB;
supply1 VPWR;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probe_p_8 (
X,
A,
VGND,
VNB,
VPB,
VPWR
);
output X;
input A;
input VGND;
input VNB;
input VPB;
input VPWR;
sky130_fd_sc_hd__probe_p base (
.X(X),
.A(A),
.VGND(VGND),
.VNB(VNB),
.VPB(VPB),
.VPWR(VPWR)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probe_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply0 VGND;
supply0 VNB;
supply1 VPB;
supply1 VPWR;
sky130_fd_sc_hd__probe_p base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
wire SET;
wire CLK;
wire buf_Q;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_N_delayed;
wire SET_B_delayed;
wire RESET_B_delayed;
wire mux_out;
wire awake;
wire cond0;
wire cond1;
wire condb;
wire cond_D;
wire cond_SCD;
wire cond_SCE;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
not not2 (CLK, CLK_N_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK,
mux_out,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
assign cond_D = ((SCE_delayed === 1'b0) && condb);
assign cond_SCD = ((SCE_delayed === 1'b1) && condb);
assign cond_SCE = ((D_delayed !== SCD_delayed) && condb);
buf buf0 (Q, buf_Q);
not not3 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B
);
// Module ports
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
wire SET;
wire CLK;
wire buf_Q;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_N_delayed;
wire SET_B_delayed;
wire RESET_B_delayed;
wire mux_out;
wire awake;
wire cond0;
wire cond1;
wire condb;
wire cond_D;
wire cond_SCD;
wire cond_SCE;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
not not2 (CLK, CLK_N_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK,
mux_out,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
assign cond_D = ((SCE_delayed === 1'b0) && condb);
assign cond_SCD = ((SCE_delayed === 1'b1) && condb);
assign cond_SCE = ((D_delayed !== SCD_delayed) && condb);
buf buf0 (Q, buf_Q);
not not3 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK_N,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn_1 (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn_1 (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn_2 (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn_2 (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp (
Q,
Q_N,
D,
SCD,
SCE,
CLK,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
wire SET;
wire buf_Q;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire SET_B_delayed;
wire RESET_B_delayed;
wire mux_out;
wire awake;
wire cond0;
wire cond1;
wire condb;
wire cond_D;
wire cond_SCD;
wire cond_SCE;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK_delayed,
mux_out,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
assign cond_D = ((SCE_delayed === 1'b0) && condb);
assign cond_SCD = ((SCE_delayed === 1'b1) && condb);
assign cond_SCE = ((D_delayed !== SCD_delayed) && condb);
buf buf0 (Q, buf_Q);
not not2 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp (
Q,
Q_N,
D,
SCD,
SCE,
CLK,
SET_B,
RESET_B
);
// Module ports
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK;
input SET_B;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
wire SET;
wire buf_Q;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire SET_B_delayed;
wire RESET_B_delayed;
wire mux_out;
wire awake;
wire cond0;
wire cond1;
wire condb;
wire cond_D;
wire cond_SCD;
wire cond_SCE;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK_delayed,
mux_out,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
assign cond_D = ((SCE_delayed === 1'b0) && condb);
assign cond_SCD = ((SCE_delayed === 1'b1) && condb);
assign cond_SCE = ((D_delayed !== SCD_delayed) && condb);
buf buf0 (Q, buf_Q);
not not2 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp (
Q,
Q_N,
D,
SCD,
SCE,
CLK,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp (
Q,
Q_N,
D,
SCD,
SCE,
CLK,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp_1 (
Q,
Q_N,
D,
SCD,
SCE,
CLK,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp_1 (
Q,
Q_N,
D,
SCD,
SCE,
CLK,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((RESET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((RESET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((RESET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((RESET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp_2 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp_2 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn (
Q,
CLK_N,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK_N;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
wire intclk;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_N_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (intclk, CLK_N_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
intclk,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn (
Q,
CLK_N,
D,
SCD,
SCE,
RESET_B
);
// Module ports
output Q;
input CLK_N;
input D;
input SCD;
input SCE;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
wire intclk;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_N_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (intclk, CLK_N_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
intclk,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn (
Q,
CLK_N,
D,
SCD,
SCE,
RESET_B
);
output Q;
input CLK_N;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn (
Q,
CLK_N,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK_N;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK_N,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn_1 (
Q,
CLK_N,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK_N;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn_1 (
Q,
CLK_N,
D,
SCD,
SCE,
RESET_B
);
output Q;
input CLK_N;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((RESET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((RESET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((RESET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((RESET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp_1 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp_1 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp_2 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp_2 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp_4 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp_4 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((SET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((SET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((SET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((SET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp_2 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp_2 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfstp (
Q,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((SET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((SET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfstp (
Q,
CLK,
D,
SCD,
SCE,
SET_B
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((SET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((SET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
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