code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hvl__probec_p (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probec_p_8 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__probec_p base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
specify
(A + => X) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probec_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__probec_p base (
.X(X),
.A(A)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
specify
(A + => X) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__schmittbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
specify
(A + => X) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__schmittbuf base (
.X(X),
.A(A)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
specify
(A + => X) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire buf0_out_Q;
wire not1_out_qn;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
not not1 (not1_out_qn, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (
Q_N,
not1_out_qn,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, D_delayed,COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(negedge RESET_B => (Q +: RESET_B)) = (0: 0: 0); // delay is tris
(negedge RESET_B => (Q_N -: RESET_B)) = (0: 0: 0); // delay is tris
(posedge CLK => (Q : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
(posedge CLK => (Q_N : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge CLK &&& (RESET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge CLK &&& (RESET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge RESET_B, 0: 0: 0, 0, notifier);
$recrem ( posedge RESET_B , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ;
$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, D_delayed,COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(negedge RESET_B => (Q +: RESET_B)) = (0: 0: 0); // delay is tris
(negedge RESET_B => (Q_N -: RESET_B)) = (0: 0: 0); // delay is tris
(posedge CLK => (Q : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
(posedge CLK => (Q_N : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge CLK &&& (RESET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge CLK &&& (RESET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge RESET_B, 0: 0: 0, 0, notifier);
$recrem ( posedge RESET_B , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ;
$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire buf0_out_Q;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp_1 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, D_delayed,COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(negedge RESET_B => (Q +: RESET_B)) = (0: 0: 0); // delay is tris
(posedge CLK => (Q : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge CLK &&& (RESET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge CLK &&& (RESET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge RESET_B, 0: 0: 0, 0, notifier);
$recrem ( posedge RESET_B , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ;
$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp_1 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, D_delayed,COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(negedge RESET_B => (Q +: RESET_B)) = (0: 0: 0); // delay is tris
(posedge CLK => (Q : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge CLK &&& (RESET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge CLK &&& (RESET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge RESET_B, 0: 0: 0, 0, notifier);
$recrem ( posedge RESET_B , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ;
$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire buf0_out_Q;
wire not1_out_qn;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign cond0 = (SET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
not not1 (not1_out_qn, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (
Q_N,
not1_out_qn,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign cond0 = (SET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, D_delayed,COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(negedge SET_B => (Q -: SET_B)) = (0: 0: 0); // delay is tris
(negedge SET_B => (Q_N +: SET_B)) = (0: 0: 0); // delay is tris
(posedge CLK => (Q : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
(posedge CLK => (Q_N : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge CLK &&& (SET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge CLK &&& (SET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge SET_B, 0: 0: 0, 0, notifier);
$recrem ( posedge SET_B , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ;
$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, D_delayed,COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(negedge SET_B => (Q -: SET_B)) = (0: 0: 0); // delay is tris
(negedge SET_B => (Q_N +: SET_B)) = (0: 0: 0); // delay is tris
(posedge CLK => (Q : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
(posedge CLK => (Q_N : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge CLK &&& (SET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge CLK &&& (SET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge SET_B, 0: 0: 0, 0, notifier);
$recrem ( posedge SET_B , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ;
$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp (
Q,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire buf0_out_Q;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign cond0 = (SET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp (
Q,
CLK,
D,
SCD,
SCE,
SET_B
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign cond0 = (SET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp_1 (
Q,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, D_delayed,COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(negedge SET_B => (Q -: SET_B)) = (0: 0: 0); // delay is tris
(posedge CLK => (Q : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge CLK &&& (SET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge CLK &&& (SET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge SET_B, 0: 0: 0, 0, notifier);
$recrem ( posedge SET_B , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ;
$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp_1 (
Q,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, D_delayed,COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(negedge SET_B => (Q -: SET_B)) = (0: 0: 0); // delay is tris
(posedge CLK => (Q : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge CLK &&& (SET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge CLK &&& (SET_B === 1'b1), 0: 0: 0, 0, notifier);
$width(negedge SET_B, 0: 0: 0, 0, notifier);
$recrem ( posedge SET_B , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ;
$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire buf0_out_Q;
wire not0_out_qn;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign cond1 = (SCE_delayed === 1'b0);
assign cond2 = (SCE_delayed === 1'b1);
assign cond3 = (D_delayed !== SCD_delayed);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
not not0 (not0_out_qn, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (
Q_N,
not0_out_qn,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign cond1 = (SCE_delayed === 1'b0);
assign cond2 = (SCE_delayed === 1'b1);
assign cond3 = (D_delayed !== SCD_delayed);
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, D_delayed,COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(posedge CLK => (Q : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
(posedge CLK => (Q_N : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge CLK, 0: 0: 0, 0, notifier);
$width(negedge CLK, 0: 0: 0, 0, notifier);
$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, D_delayed,COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(posedge CLK => (Q : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
(posedge CLK => (Q_N : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge CLK, 0: 0: 0, 0, notifier);
$width(negedge CLK, 0: 0: 0, 0, notifier);
$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire buf0_out_Q;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign cond1 = (SCE_delayed === 1'b0);
assign cond2 = (SCE_delayed === 1'b1);
assign cond3 = (D_delayed !== SCD_delayed);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp (
Q,
CLK,
D,
SCD,
SCE
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign cond1 = (SCE_delayed === 1'b0);
assign cond2 = (SCE_delayed === 1'b1);
assign cond3 = (D_delayed !== SCD_delayed);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp_1 (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, D_delayed,COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(posedge CLK => (Q : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge CLK, 0: 0: 0, 0, notifier);
$width(negedge CLK, 0: 0: 0, 0, notifier);
$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp_1 (
Q,
CLK,
D,
SCD,
SCE
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdfxtp base (
.Q (Q),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, D_delayed, COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(posedge CLK => (Q : CLK)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge CLK, 0: 0: 0, 0, notifier);
$width(negedge CLK, 0: 0: 0, 0, notifier);
$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire CLK_delayed;
wire SCE_delayed;
wire GATE_delayed;
wire SCE_gate_delayed;
wire GCLK_b;
reg notifier;
wire awake;
wire SCE_awake;
wire GATE_awake;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK_delayed);
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed);
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
SCE_gate_delayed,
clkn,
notifier,
VPWR,
VGND
);
and and0 (GCLK_b, m0n, CLK_delayed);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
GCLK,
GCLK_b,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign SCE_awake = ((GATE_delayed === 1'b0) & awake);
assign GATE_awake = ((SCE_delayed === 1'b0) & awake);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK);
nor nor0 (SCE_GATE, GATE, SCE);
sky130_fd_sc_hvl__udp_dlatch$P dlatch0 (
m0,
SCE_GATE,
clkn
);
and and0 (GCLK, m0n, CLK);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire CLK_delayed;
wire SCE_delayed;
wire GATE_delayed;
wire SCE_gate_delayed;
wire GCLK_b;
reg notifier;
wire awake;
wire SCE_awake;
wire GATE_awake;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK_delayed);
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed);
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
SCE_gate_delayed,
clkn,
notifier,
VPWR,
VGND
);
and and0 (GCLK_b, m0n, CLK_delayed);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
GCLK,
GCLK_b,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign SCE_awake = ((GATE_delayed === 1'b0) & awake);
assign GATE_awake = ((SCE_delayed === 1'b0) & awake);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp_1 (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, GATE_AWAKE, SCE_AWAKE, COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(CLK + => GCLK) = (0: 0: 0, 0: 0: 0); // delays are tris , tfall
$setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , SCE_AWAKE , SCE_AWAKE , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , SCE_AWAKE , SCE_AWAKE , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , posedge GATE , 0:0:0 , 0:0:0 , notifier , GATE_AWAKE , GATE_AWAKE , CLK_delayed , GATE_delayed ) ;
$setuphold ( posedge CLK , negedge GATE , 0:0:0 , 0:0:0 , notifier , GATE_AWAKE , GATE_AWAKE , CLK_delayed , GATE_delayed ) ;
$width(negedge CLK &&& AWAKE, 1.0: 1.0: 1.0, 0, notifier);
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp_1 (
GCLK,
SCE,
GATE,
CLK
);
output GCLK;
input SCE;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, GATE_AWAKE, SCE_AWAKE, COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(CLK + => GCLK) = (0: 0: 0, 0: 0: 0); // delays are tris , tfall
$setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , SCE_AWAKE , SCE_AWAKE , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , SCE_AWAKE , SCE_AWAKE , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , posedge GATE , 0:0:0 , 0:0:0 , notifier , GATE_AWAKE , GATE_AWAKE , CLK_delayed , GATE_delayed ) ;
$setuphold ( posedge CLK , negedge GATE , 0:0:0 , 0:0:0 , notifier , GATE_AWAKE , GATE_AWAKE , CLK_delayed , GATE_delayed ) ;
$width(negedge CLK &&& AWAKE, 1.0: 1.0: 1.0, 0, notifier);
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp (
Q,
D,
SCD,
SCE,
GATE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input D;
input SCD;
input SCE;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire GATE_delayed;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire cond0;
wire cond1;
wire cond2;
reg notifier;
wire mux_out;
wire buf0_out_Q;
// Name Output Other arguments
assign cond0 = (SCE_delayed === 1'b0);
assign cond1 = (SCE_delayed === 1'b1);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
mux_out,
GATE_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp (
Q ,
D ,
SCD ,
SCE ,
GATE
);
// Module ports
output Q ;
input D ;
input SCD ;
input SCE ;
input GATE;
// Local signals
wire mux_out;
wire buf_Q ;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , mux_out, GATE );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp (
Q,
D,
SCD,
SCE,
GATE
);
// Module ports
output Q;
input D;
input SCD;
input SCE;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire GATE_delayed;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire cond0;
wire cond1;
wire cond2;
reg notifier;
wire mux_out;
// Name Output Other arguments
assign cond0 = (SCE_delayed === 1'b0);
assign cond1 = (SCE_delayed === 1'b1);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
mux_out,
GATE_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp_1 (
Q,
D,
SCD,
SCE,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input SCD;
input SCE;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdlxtp base (
.Q(Q),
.D(D),
.SCD(SCD),
.SCE(SCE),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, GATE_AWAKE, D_delayed, SCE_AWAKE, COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(D + => Q) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
(SCD + => Q) = (0: 0: 0, 0: 0: 0); // adding as per CDT 106221
(SCE => Q) = (0: 0: 0, 0: 0: 0); // adding as per CDT 106221
(posedge GATE => (Q +: D)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge GATE, 0: 0: 0, 0, notifier);
$setuphold ( negedge GATE , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ;
$setuphold ( negedge GATE , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ;
$setuphold ( negedge GATE , posedge SCD , 0:0:0, 0:0:0, notifier , , COND1 , GATE_delayed , SCD_delayed ) ;
$setuphold ( negedge GATE , negedge SCD , 0:0:0, 0:0:0, notifier , , COND1 , GATE_delayed , SCD_delayed ) ;
$setuphold ( negedge GATE , posedge SCE , 0:0:0, 0:0:0, notifier , , , GATE_delayed , SCE_delayed ) ;
$setuphold ( negedge GATE , negedge SCE , 0:0:0, 0:0:0, notifier , , , GATE_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp_1 (
Q,
D,
SCD,
SCE,
GATE
);
output Q;
input D;
input SCD;
input SCE;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdlxtp base (
.Q(Q),
.D(D),
.SCD(SCD),
.SCE(SCE),
.GATE(GATE)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
wire SETB_delayed, COND1, COND2, COND3, CLK_delayed, GATE_delayed, GATE_AWAKE, D_delayed, SCE_AWAKE, COND0, SCD_delayed, SCE_delayed, RESETB_delayed, AWAKE;
reg notifier;
specify
(D + => Q) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
(SCD + => Q) = (0: 0: 0, 0: 0: 0); // adding as per CDT 106221
(SCE => Q) = (0: 0: 0, 0: 0: 0); // adding as per CDT 106221
(posedge GATE => (Q +: D)) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
$width(posedge GATE, 0: 0: 0, 0, notifier);
$setuphold ( negedge GATE , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ;
$setuphold ( negedge GATE , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ;
$setuphold ( negedge GATE , posedge SCD , 0:0:0, 0:0:0, notifier , , COND1 , GATE_delayed , SCD_delayed ) ;
$setuphold ( negedge GATE , negedge SCD , 0:0:0, 0:0:0, notifier , , COND1 , GATE_delayed , SCD_delayed ) ;
$setuphold ( negedge GATE , posedge SCE , 0:0:0, 0:0:0, notifier , , , GATE_delayed , SCE_delayed ) ;
$setuphold ( negedge GATE , negedge SCE , 0:0:0, 0:0:0, notifier , , , GATE_delayed , SCE_delayed ) ;
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xnor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
xnor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
buf buf0 (Y, xnor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
buf buf0 (Y, xnor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2_1 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
specify
if ((B)) (A + => Y) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
if ((!B)) (A - => Y) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
if ((A)) (B + => Y) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
if ((!A)) (B - => Y) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
specify
if ((B)) (A + => Y) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
if ((!B)) (A - => Y) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
if ((A)) (B + => Y) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
if ((!A)) (B - => Y) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
xor0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2_1 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
specify
if ((!B)) (A + => X) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
if ((B)) (A - => X) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
if ((!A)) (B + => X) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
if ((A)) (B - => X) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__xor2 base (
.X(X),
.A(A),
.B(B)
);
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
specify
if ((!B)) (A + => X) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
if ((B)) (A - => X) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
if ((!A)) (B + => X) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
if ((A)) (B - => X) = (0: 0: 0, 0: 0: 0); // delays are tris,tfall
endspecify
`endif
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlclkp_1 (
input GATE,
input CLK,
output GCLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlclkp_2 (
// input GATE,
// input CLK,
// output GCLK);
//endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlclkp_4 (
// input GATE,
// input CLK,
// output GCLK);
//endmodule
| 7.212805 |
module \$adffe (ARST, CLK, D, EN, Q);
parameter ARST_POLARITY =1'b1;
parameter ARST_VALUE =1'b0;
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter WIDTH =1;
input ARST, CLK, EN;
input [WIDTH -1 :0] D;
output [WIDTH -1 :0] Q;
wire GCLK;
sky130_fd_sc_hvl__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
$adff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.ARST_VALUE(ARST_VALUE) ,
.ARST_POLARITY (ARST_POLARITY)
)
flipflop(
.CLK(GCLK),
.ARST(ARST),
.D(D),
.Q(Q)
);
endmodule
| 7.72891 |
module \$dffe ( CLK, D, EN, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
sky130_fd_sc_hvl__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
$dff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
)
flipflop(
.CLK(GCLK),
.D(D),
.Q(Q)
);
endmodule
| 7.215766 |
module \$dffsre ( CLK, EN, CLR, SET, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter CLR_POLARITY =1'b1;
parameter SET_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN, CLR, SET;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
sky130_fd_sc_hvl__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
$dffsr #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.CLR_POLARITY(CLR_POLARITY),
.SET_POLARITY(SET_POLARITY)
)
flipflop(
.CLK(GCLK),
.CLR(CLR),
.SET(SET),
.D(D),
.Q(Q)
);
endmodule
| 7.063232 |
module \$aldffe ( CLK, EN, ALOAD, AD, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter ALOAD_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN, ALOAD;
input [WIDTH -1:0] D;
input [WIDTH-1:0] AD;
output [WIDTH -1:0] Q;
wire GCLK;
sky130_fd_sc_hvl__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
$aldff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.ALOAD_POLARITY(ALOAD_POLARITY),
)
flipflop(
.CLK(GCLK),
.D(D),
.AD(AD),
.Q(Q)
);
endmodule
| 7.710209 |
module \$sdffe ( CLK, EN, SRST, D, Q);
// parameter CLK_POLARITY =1'b1;
// parameter EN_POLARITY =1'b1;
// parameter SRST_POLARITY =1'b1;
// parameter SRST_VALUE =1'b1;
// parameter WIDTH =1;
// input CLK, EN, SRST;
// input [WIDTH -1:0] D;
// output [WIDTH -1:0] Q;
// wire GCLK;
//sky130_fd_sc_hvl__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
// $sdff #(
// .WIDTH(WIDTH),
// .CLK_POLARITY(CLK_POLARITY),
// .SRST_POLARITY(SRST_POLARITY),
// .SRST_VALUE(SRST_VALUE)
// )
// flipflop(
// .CLK(GCLK),
// .SRST(SRST),
// .D(D),
// .Q(Q)
// );
//endmodule
| 7.043312 |
module \$sdffce ( CLK, EN, SRST, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter SRST_POLARITY =1'b1;
parameter SRST_VALUE =1'b1;
parameter WIDTH =1;
input CLK, EN, SRST;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
sky130_fd_sc_hvl__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
$sdff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.SRST_POLARITY(SRST_POLARITY),
.SRST_VALUE(SRST_VALUE)
)
flipflop(
.CLK(GCLK),
.SRST(SRST),
.D(D),
.Q(Q)
);
endmodule
| 6.900616 |
module sky130_fd_sc_hvl__a21o (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out, A1, A2);
or or0 (or0_out_X, and0_out, B1);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21o (
X,
A1,
A2,
B1
);
// Module ports
output X;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out, A1, A2);
or or0 (or0_out_X, and0_out, B1);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21o (
X,
A1,
A2,
B1
);
output X;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21o (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out, A1, A2);
or or0 (or0_out_X, and0_out, B1);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21o (
X,
A1,
A2,
B1
);
// Module ports
output X;
input A1;
input A2;
input B1;
// Local signals
wire and0_out;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out, A1, A2);
or or0 (or0_out_X, and0_out, B1);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21o (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21oi (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire nor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out, A1, A2);
nor nor0 (nor0_out_Y, B1, and0_out);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21oi (
Y,
A1,
A2,
B1
);
// Module ports
output Y;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out, A1, A2);
nor nor0 (nor0_out_Y, B1, and0_out);
buf buf0 (Y, nor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21oi (
Y,
A1,
A2,
B1
);
output Y;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21oi (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire nor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out, A1, A2);
nor nor0 (nor0_out_Y, B1, and0_out);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
nor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21oi (
Y,
A1,
A2,
B1
);
// Module ports
output Y;
input A1;
input A2;
input B1;
// Local signals
wire and0_out;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out, A1, A2);
nor nor0 (nor0_out_Y, B1, and0_out);
buf buf0 (Y, nor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21oi (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21oi_1 (
Y,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21oi_1 (
Y,
A1,
A2,
B1
);
output Y;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__a21oi base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21o_1 (
X,
A1,
A2,
B1,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a21o_1 (
X,
A1,
A2,
B1
);
output X;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__a21o base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22o (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire and1_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out, B1, B2);
and and1 (and1_out, A1, A2);
or or0 (or0_out_X, and1_out, and0_out);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22o (
X,
A1,
A2,
B1,
B2
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire and1_out;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out, B1, B2);
and and1 (and1_out, A1, A2);
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22o (
X,
A1,
A2,
B1,
B2
);
output X;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22o (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire and1_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out, B1, B2);
and and1 (and1_out, A1, A2);
or or0 (or0_out_X, and1_out, and0_out);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22o (
X,
A1,
A2,
B1,
B2
);
// Module ports
output X;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire and0_out;
wire and1_out;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out, B1, B2);
and and1 (and1_out, A1, A2);
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22o (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22oi (
Y,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nand0_out;
wire nand1_out;
wire and0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, A2, A1);
nand nand1 (nand1_out, B2, B1);
and and0 (and0_out_Y, nand0_out, nand1_out);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
and0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22oi (
Y,
A1,
A2,
B1,
B2
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire nand0_out;
wire nand1_out;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, A2, A1);
nand nand1 (nand1_out, B2, B1);
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y, and0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22oi (
Y,
A1,
A2,
B1,
B2
);
output Y;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22oi (
Y,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire nand0_out;
wire nand1_out;
wire and0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, A2, A1);
nand nand1 (nand1_out, B2, B1);
and and0 (and0_out_Y, nand0_out, nand1_out);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
and0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22oi (
Y,
A1,
A2,
B1,
B2
);
// Module ports
output Y;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nand0_out;
wire nand1_out;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, A2, A1);
nand nand1 (nand1_out, B2, B1);
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y, and0_out_Y);
endmodule
| 7.212805 |
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