code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hvl__dfstp (
Q,
CLK,
D,
SET_B
);
// Module ports
output Q;
input CLK;
input D;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
wire cond0;
wire D_delayed;
wire SET_B_delayed;
wire CLK_delayed;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign cond0 = (SET_B_delayed === 1'b1);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfstp (
Q,
CLK,
D,
SET_B
);
output Q;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfstp (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfstp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfstp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfstp_1 (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfstp_1 (
Q,
CLK,
D,
SET_B
);
output Q;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxbp (
Q,
Q_N,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire CLK_delayed;
wire buf0_out_Q;
wire not0_out_qn;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
not not0 (not0_out_qn, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (
Q_N,
not0_out_qn,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxbp (
Q,
Q_N,
CLK,
D
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire CLK_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxbp (
Q,
Q_N,
CLK,
D
);
output Q;
output Q_N;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire buf0_out_Q ;
wire not0_out_qn;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND );
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not0 (not0_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not0_out_qn, VPWR, VGND);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxbp (
Q,
Q_N,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxbp_1 (
Q,
Q_N,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxbp_1 (
Q,
Q_N,
CLK,
D
);
output Q;
output Q_N;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__dfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxtp (
Q,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire CLK_delayed;
wire buf0_out_Q;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxtp (
Q,
CLK,
D
);
// Module ports
output Q;
input CLK;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire CLK_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxtp (
Q,
CLK,
D
);
output Q;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxtp (
Q,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxtp_1 (
Q,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfxtp_1 (
Q,
CLK,
D
);
output Q;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__dfxtp base (
.Q (Q),
.CLK(CLK),
.D (D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__diode (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__diode (
DIODE
);
// Module ports
input DIODE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__diode (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__diode (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__diode (
DIODE
);
// Module ports
input DIODE;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__diode (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__diode (
//# {{power|Power}}
input DIODE,
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__diode (
//# {{power|Power}}
input DIODE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__diode_2 (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__diode base (
.DIODE(DIODE),
.VPWR (VPWR),
.VGND (VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__diode_2 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__diode base (.DIODE(DIODE));
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire m0;
wire clkn;
wire CLK_delayed;
wire GATE_delayed;
reg notifier;
wire GCLK_b;
wire awake;
// Name Output Other arguments
not not0 (clkn, CLK_delayed);
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
GATE_delayed,
clkn,
notifier,
VPWR,
VGND
);
and and0 (GCLK_b, m0, CLK_delayed);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
GCLK,
GCLK_b,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire m0;
wire clkn;
wire CLK_delayed;
wire GATE_delayed;
reg notifier;
wire GCLK_b;
wire awake;
// Name Output Other arguments
not not0 (clkn, CLK_delayed);
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
GATE_delayed,
clkn,
notifier,
VPWR,
VGND
);
and and0 (GCLK_b, m0, CLK_delayed);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
GCLK,
GCLK_b,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire m0;
wire clkn;
wire GCLK_b;
// Name Output Other arguments
not not0 (clkn, CLK);
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
GATE,
clkn
,,
VPWR,
VGND
);
and and0 (GCLK_b, m0, CLK);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
GCLK,
GCLK_b,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK;
// Local signals
wire m0;
wire clkn;
// Name Output Other arguments
not not0 (clkn, CLK);
sky130_fd_sc_hvl__udp_dlatch$P dlatch0 (
m0,
GATE,
clkn
);
and and0 (GCLK, m0, CLK);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlclkp (
//# {{clocks|Clocking}}
input CLK,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlclkp (
//# {{clocks|Clocking}}
input CLK,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlclkp_1 (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlclkp_1 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlrtp (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
reg notifier;
wire cond0;
wire D_delayed;
wire GATE_delayed;
wire RESET_delayed;
wire RESET_B_delayed;
wire buf_Q;
wire buf0_out_Q;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlrtp (
Q,
RESET_B,
D,
GATE
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
reg notifier;
wire cond0;
wire D_delayed;
wire GATE_delayed;
wire RESET_delayed;
wire RESET_B_delayed;
wire buf_Q;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlrtp (
Q,
RESET_B,
D,
GATE
);
output Q;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlrtp (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlrtp_1 (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlrtp_1 (
Q,
RESET_B,
D,
GATE
);
output Q;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlxtp (
Q,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
reg notifier;
wire buf_Q;
wire GATE_delayed;
wire D_delayed;
wire buf0_out_Q;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlxtp (
Q,
D,
GATE
);
// Module ports
output Q;
input D;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
reg notifier;
wire buf_Q;
wire GATE_delayed;
wire D_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
D_delayed,
GATE_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlxtp (
Q,
D,
GATE
);
output Q;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlxtp (
Q,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlxtp_1 (
Q,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dlxtp_1 (
Q,
D,
GATE
);
output Q;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_A,
A,
VPWR,
VGND
);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_teb,
TE_B,
VPWR,
VGND
);
notif0 notif00 (Z, pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvn (
Z,
A,
TE_B
);
// Module ports
output Z;
input A;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output Other arguments
notif0 notif00 (Z, A, TE_B);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvn (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_A,
A,
VPWR,
VGND
);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_teb,
TE_B,
VPWR,
VGND
);
notif0 notif00 (Z, pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvn (
Z,
A,
TE_B
);
// Module ports
output Z;
input A;
input TE_B;
// Name Output Other arguments
notif0 notif00 (Z, A, TE_B);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvn (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvn (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvn_1 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvn_1 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvp (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_A,
A,
VPWR,
VGND
);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_TE,
TE,
VPWR,
VGND
);
notif1 notif10 (Z, pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvp (
Z,
A,
TE
);
// Module ports
output Z;
input A;
input TE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output Other arguments
notif1 notif10 (Z, A, TE);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvp (
Z,
A,
TE
);
output Z;
input A;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvp (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_A,
A,
VPWR,
VGND
);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_TE,
TE,
VPWR,
VGND
);
notif1 notif10 (Z, pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvp (
Z,
A,
TE
);
// Module ports
output Z;
input A;
input TE;
// Name Output Other arguments
notif1 notif10 (Z, A, TE);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvp (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvp (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvp (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvp_1 (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__einvp_1 (
Z,
A,
TE
);
output Z;
input A;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__einvp base (
.Z (Z),
.A (A),
.TE(TE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__fill (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__fill (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__fill (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__fill (
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__fill_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__fill_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__fill base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__fill_2 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
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