code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module sky130_fd_sc_hvl__a22oi (
Y,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22oi_1 (
Y,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22oi_1 (
Y,
A1,
A2,
B1,
B2
);
output Y;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__a22oi base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22o_1 (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__a22o_1 (
X,
A1,
A2,
B1,
B2
);
output X;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__a22o base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
and0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B);
buf buf0 (X, and0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
and0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B);
buf buf0 (X, and0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and2 (
//# {{data|Data Signals}}
input A,
input B,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and2_1 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
and0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B);
buf buf0 (X, and0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
and0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B);
buf buf0 (X, and0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and3_1 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__and3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf_16 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf_2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf_32 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf_32 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf_4 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf_8 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__buf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__conb (
HI,
LO,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output HI;
output LO;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pullup0_out_HI;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI);
sky130_fd_sc_hvl__udp_pwrgood_pp$P pwrgood_pp0 (
HI,
pullup0_out_HI,
VPWR
);
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_hvl__udp_pwrgood_pp$G pwrgood_pp1 (
LO,
pulldown0_out_LO,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output
pullup pullup0 (HI);
pulldown pulldown0 (LO);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__conb (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__conb (
HI,
LO,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output HI;
output LO;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pullup0_out_HI;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI);
sky130_fd_sc_hvl__udp_pwrgood_pp$P pwrgood_pp0 (
HI,
pullup0_out_HI,
VPWR
);
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_hvl__udp_pwrgood_pp$G pwrgood_pp1 (
LO,
pulldown0_out_LO,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Name Output
pullup pullup0 (HI);
pulldown pulldown0 (LO);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__conb (
HI,
LO,
VPWR,
VGND,
VPB,
VNB
);
output HI;
output LO;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__conb (
//# {{data|Data Signals}}
output HI,
output LO,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__conb (
//# {{data|Data Signals}}
output HI,
output LO
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__conb_1 (
HI,
LO,
VPWR,
VGND,
VPB,
VNB
);
output HI;
output LO;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__conb base (
.HI (HI),
.LO (LO),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__conb_1 (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__conb base (
.HI(HI),
.LO(LO)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__decap (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__decap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__decap (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__decap ();
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__decap (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__decap (
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__decap_4 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__decap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__decap_8 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__decap_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__decap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrbp (
Q,
Q_N,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire cond0;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire buf0_out_Q;
wire not1_out_qn;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
not not1 (not1_out_qn, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (
Q_N,
not1_out_qn,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrbp (
Q,
Q_N,
CLK,
D,
RESET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire cond0;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrbp (
Q,
Q_N,
CLK,
D,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire buf0_out_Q ;
wire not1_out_qn;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrbp (
Q,
Q_N,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrbp_1 (
Q,
Q_N,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrbp_1 (
Q,
Q_N,
CLK,
D,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrtp (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire cond0;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire buf0_out_Q;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrtp (
Q,
CLK,
D,
RESET_B
);
// Module ports
output Q;
input CLK;
input D;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire cond0;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrtp (
Q,
CLK,
D,
RESET_B
);
output Q;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrtp (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrtp_1 (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfrtp_1 (
Q,
CLK,
D,
RESET_B
);
output Q;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfsbp (
Q,
Q_N,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
wire cond0;
wire D_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire buf0_out_Q;
wire not1_out_qn;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign cond0 = (SET_B_delayed === 1'b1);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
not not1 (not1_out_qn, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (
Q_N,
not1_out_qn,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfsbp (
Q,
Q_N,
CLK,
D,
SET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
wire cond0;
wire D_delayed;
wire SET_B_delayed;
wire CLK_delayed;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign cond0 = (SET_B_delayed === 1'b1);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfsbp (
Q,
Q_N,
CLK,
D,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire buf0_out_Q ;
wire not1_out_qn;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfsbp (
Q,
Q_N,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfsbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfsbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfsbp_1 (
Q,
Q_N,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfsbp_1 (
Q,
Q_N,
CLK,
D,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__dfstp (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
wire cond0;
wire D_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire buf0_out_Q;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign cond0 = (SET_B_delayed === 1'b1);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
endmodule
| 7.212805 |
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