code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hd__probe_p (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probe_p_8 (
X,
A,
VGND,
VNB,
VPB,
VPWR
);
output X;
input A;
input VGND;
input VNB;
input VPB;
input VPWR;
sky130_fd_sc_hd__probe_p base (
.X(X),
.A(A),
.VGND(VGND),
.VNB(VNB),
.VPB(VPB),
.VPWR(VPWR)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probe_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply0 VGND;
supply0 VNB;
supply1 VPB;
supply1 VPWR;
sky130_fd_sc_hd__probe_p base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p (
X,
A,
VGND,
VNB,
VPB,
VPWR
);
// Module ports
output X;
input A;
input VGND;
input VNB;
input VPB;
input VPWR;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p_8 (
X,
A,
VGND,
VNB,
VPB,
VPWR
);
output X;
input A;
input VGND;
input VNB;
input VPB;
input VPWR;
sky130_fd_sc_hd__probec_p base (
.X(X),
.A(A),
.VGND(VGND),
.VNB(VNB),
.VPB(VPB),
.VPWR(VPWR)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__probec_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply0 VGND;
supply0 VNB;
supply1 VPB;
supply1 VPWR;
sky130_fd_sc_hd__probec_p base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
wire SET;
wire CLK;
wire buf_Q;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_N_delayed;
wire SET_B_delayed;
wire RESET_B_delayed;
wire mux_out;
wire awake;
wire cond0;
wire cond1;
wire condb;
wire cond_D;
wire cond_SCD;
wire cond_SCE;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
not not2 (CLK, CLK_N_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK,
mux_out,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
assign cond_D = ((SCE_delayed === 1'b0) && condb);
assign cond_SCD = ((SCE_delayed === 1'b1) && condb);
assign cond_SCE = ((D_delayed !== SCD_delayed) && condb);
buf buf0 (Q, buf_Q);
not not3 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B
);
// Module ports
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
wire SET;
wire CLK;
wire buf_Q;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_N_delayed;
wire SET_B_delayed;
wire RESET_B_delayed;
wire mux_out;
wire awake;
wire cond0;
wire cond1;
wire condb;
wire cond_D;
wire cond_SCD;
wire cond_SCE;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
not not2 (CLK, CLK_N_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK,
mux_out,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
assign cond_D = ((SCE_delayed === 1'b0) && condb);
assign cond_SCD = ((SCE_delayed === 1'b1) && condb);
assign cond_SCE = ((D_delayed !== SCD_delayed) && condb);
buf buf0 (Q, buf_Q);
not not3 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn_1 (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn_1 (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn_2 (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbn_2 (
Q,
Q_N,
D,
SCD,
SCE,
CLK_N,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK_N;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp (
Q,
Q_N,
D,
SCD,
SCE,
CLK,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
wire SET;
wire buf_Q;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire SET_B_delayed;
wire RESET_B_delayed;
wire mux_out;
wire awake;
wire cond0;
wire cond1;
wire condb;
wire cond_D;
wire cond_SCD;
wire cond_SCE;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK_delayed,
mux_out,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
assign cond_D = ((SCE_delayed === 1'b0) && condb);
assign cond_SCD = ((SCE_delayed === 1'b1) && condb);
assign cond_SCE = ((D_delayed !== SCD_delayed) && condb);
buf buf0 (Q, buf_Q);
not not2 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp (
Q,
Q_N,
D,
SCD,
SCE,
CLK,
SET_B,
RESET_B
);
// Module ports
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK;
input SET_B;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
wire SET;
wire buf_Q;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire SET_B_delayed;
wire RESET_B_delayed;
wire mux_out;
wire awake;
wire cond0;
wire cond1;
wire condb;
wire cond_D;
wire cond_SCD;
wire cond_SCE;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK_delayed,
mux_out,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
assign cond_D = ((SCE_delayed === 1'b0) && condb);
assign cond_SCD = ((SCE_delayed === 1'b1) && condb);
assign cond_SCE = ((D_delayed !== SCD_delayed) && condb);
buf buf0 (Q, buf_Q);
not not2 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp_1 (
Q,
Q_N,
D,
SCD,
SCE,
CLK,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfbbp_1 (
Q,
Q_N,
D,
SCD,
SCE,
CLK,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input SCD;
input SCE;
input CLK;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((RESET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((RESET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((RESET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((RESET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp_2 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrbp_2 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn (
Q,
CLK_N,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK_N;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
wire intclk;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_N_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (intclk, CLK_N_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
intclk,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn (
Q,
CLK_N,
D,
SCD,
SCE,
RESET_B
);
// Module ports
output Q;
input CLK_N;
input D;
input SCD;
input SCE;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
wire intclk;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_N_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (intclk, CLK_N_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
intclk,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn_1 (
Q,
CLK_N,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK_N;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtn_1 (
Q,
CLK_N,
D,
SCD,
SCE,
RESET_B
);
output Q;
input CLK_N;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((RESET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((RESET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((RESET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((RESET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp_1 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp_1 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp_2 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp_2 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp_4 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfrtp_4 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((SET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((SET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((SET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((SET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp_2 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfsbp_2 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfstp (
Q,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((SET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((SET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfstp (
Q,
CLK,
D,
SCD,
SCE,
SET_B
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire cond4;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = ((SET_B_delayed === 1'b1) && awake);
assign cond1 = ((SCE_delayed === 1'b0) && cond0);
assign cond2 = ((SCE_delayed === 1'b1) && cond0);
assign cond3 = ((D_delayed !== SCD_delayed) && cond0);
assign cond4 = ((SET_B === 1'b1) && awake);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfstp_1 (
Q,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfstp_1 (
Q,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfstp_2 (
Q,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfstp_2 (
Q,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfstp_4 (
Q,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfstp_4 (
Q,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) && awake);
assign cond2 = ((SCE_delayed === 1'b1) && awake);
assign cond3 = ((D_delayed !== SCD_delayed) && awake);
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) && awake);
assign cond2 = ((SCE_delayed === 1'b1) && awake);
assign cond3 = ((D_delayed !== SCD_delayed) && awake);
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxbp_2 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxbp_2 (
Q,
Q_N,
CLK,
D,
SCD,
SCE
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxtp (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) && awake);
assign cond2 = ((SCE_delayed === 1'b1) && awake);
assign cond3 = ((D_delayed !== SCD_delayed) && awake);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxtp (
Q,
CLK,
D,
SCD,
SCE
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) && awake);
assign cond2 = ((SCE_delayed === 1'b1) && awake);
assign cond3 = ((D_delayed !== SCD_delayed) && awake);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxtp_1 (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxtp_1 (
Q,
CLK,
D,
SCD,
SCE
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfxtp base (
.Q (Q),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxtp_2 (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxtp_2 (
Q,
CLK,
D,
SCD,
SCE
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfxtp base (
.Q (Q),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxtp_4 (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdfxtp_4 (
Q,
CLK,
D,
SCD,
SCE
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdfxtp base (
.Q (Q),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire CLK_delayed;
wire SCE_delayed;
wire GATE_delayed;
wire SCE_gate_delayed;
reg notifier;
wire awake;
wire SCE_awake;
wire GATE_awake;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK_delayed);
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed);
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
SCE_gate_delayed,
clkn,
notifier,
VPWR,
VGND
);
and and0 (GCLK, m0n, CLK_delayed);
assign awake = (VPWR === 1'b1);
assign SCE_awake = (awake & (GATE_delayed === 1'b0));
assign GATE_awake = (awake & (SCE_delayed === 1'b0));
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK);
nor nor0 (SCE_GATE, GATE, SCE);
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (
m0,
SCE_GATE,
clkn
);
and and0 (GCLK, m0n, CLK);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire CLK_delayed;
wire SCE_delayed;
wire GATE_delayed;
wire SCE_gate_delayed;
reg notifier;
wire awake;
wire SCE_awake;
wire GATE_awake;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK_delayed);
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed);
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
SCE_gate_delayed,
clkn,
notifier,
VPWR,
VGND
);
and and0 (GCLK, m0n, CLK_delayed);
assign awake = (VPWR === 1'b1);
assign SCE_awake = (awake & (GATE_delayed === 1'b0));
assign GATE_awake = (awake & (SCE_delayed === 1'b0));
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdlclkp_1 (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdlclkp_1 (
GCLK,
SCE,
GATE,
CLK
);
output GCLK;
input SCE;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdlclkp_2 (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdlclkp_2 (
GCLK,
SCE,
GATE,
CLK
);
output GCLK;
input SCE;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdlclkp_4 (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sdlclkp_4 (
GCLK,
SCE,
GATE,
CLK
);
output GCLK;
input SCE;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxbp (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire DE_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out;
wire de_d;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
de_d,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (
de_d,
buf_Q,
D_delayed,
DE_delayed
);
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = (awake && (SCE_delayed === 1'b0) && (DE_delayed === 1'b1));
assign cond2 = (awake && (SCE_delayed === 1'b1));
assign cond3 = (awake && (DE_delayed === 1'b1) && (D_delayed !== SCD_delayed));
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxbp (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire DE_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out;
wire de_d;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
de_d,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (
de_d,
buf_Q,
D_delayed,
DE_delayed
);
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = (awake && (SCE_delayed === 1'b0) && (DE_delayed === 1'b1));
assign cond2 = (awake && (SCE_delayed === 1'b1));
assign cond3 = (awake && (DE_delayed === 1'b1) && (D_delayed !== SCD_delayed));
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxbp_1 (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxbp_1 (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sedfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D),
.DE (DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxbp_2 (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxbp_2 (
Q,
Q_N,
CLK,
D,
DE,
SCD,
SCE
);
output Q;
output Q_N;
input CLK;
input D;
input DE;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sedfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D),
.DE (DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxtp (
Q,
CLK,
D,
DE,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input DE;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire DE_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out;
wire de_d;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
de_d,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (
de_d,
buf_Q,
D_delayed,
DE_delayed
);
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = (awake && (SCE_delayed === 1'b0) && (DE_delayed === 1'b1));
assign cond2 = (awake && (SCE_delayed === 1'b1));
assign cond3 = (awake && (DE_delayed === 1'b1) && (D_delayed !== SCD_delayed));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxtp (
Q,
CLK,
D,
DE,
SCD,
SCE
);
// Module ports
output Q;
input CLK;
input D;
input DE;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire DE_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out;
wire de_d;
wire awake;
wire cond1;
wire cond2;
wire cond3;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (
mux_out,
de_d,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (
de_d,
buf_Q,
D_delayed,
DE_delayed
);
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond1 = (awake && (SCE_delayed === 1'b0) && (DE_delayed === 1'b1));
assign cond2 = (awake && (SCE_delayed === 1'b1));
assign cond3 = (awake && (DE_delayed === 1'b1) && (D_delayed !== SCD_delayed));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxtp_1 (
Q,
CLK,
D,
DE,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input DE;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxtp_1 (
Q,
CLK,
D,
DE,
SCD,
SCE
);
output Q;
input CLK;
input D;
input DE;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sedfxtp base (
.Q (Q),
.CLK(CLK),
.D (D),
.DE (DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxtp_2 (
Q,
CLK,
D,
DE,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input DE;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxtp_2 (
Q,
CLK,
D,
DE,
SCD,
SCE
);
output Q;
input CLK;
input D;
input DE;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sedfxtp base (
.Q (Q),
.CLK(CLK),
.D (D),
.DE (DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxtp_4 (
Q,
CLK,
D,
DE,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input DE;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__sedfxtp_4 (
Q,
CLK,
D,
DE,
SCD,
SCE
);
output Q;
input CLK;
input D;
input DE;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__sedfxtp base (
.Q (Q),
.CLK(CLK),
.D (D),
.DE (DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tap (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tap ();
// No contents.
endmodule
| 7.212805 |
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