code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hd__tap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tap_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tap_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__tap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tap_2 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tap_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__tap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd2 (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd2 ();
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd2 ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd2_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__tapvgnd2 base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd ();
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__tapvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__tapvgnd base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvpwrvgnd (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvpwrvgnd ();
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvpwrvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvpwrvgnd_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__tapvpwrvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvpwrvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__tapvpwrvgnd base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xnor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
xnor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
buf buf0 (Y, xnor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
buf buf0 (Y, xnor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2_1 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2_2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2_4 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xnor0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
xnor0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xnor0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C);
buf buf0 (X, xnor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xnor0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C);
buf buf0 (X, xnor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor3_1 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor3_2 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor3_4 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
xor0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2_1 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2_2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2_4 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
xor0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor3_1 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor3_2 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor3_4 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_1 (
input GATE,
input CLK,
output GCLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_2 (
input GATE,
input CLK,
output GCLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_4 (
input GATE,
input CLK,
output GCLK
);
endmodule
| 7.212805 |
module \$adffe (ARST, CLK, D, EN, Q);
parameter ARST_POLARITY =1'b1;
parameter ARST_VALUE =1'b0;
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter WIDTH =1;
input ARST, CLK, EN;
input [WIDTH -1 :0] D;
output [WIDTH -1 :0] Q;
wire GCLK;
generate
if (WIDTH < 5) begin
sky130_fd_sc_hd__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_hd__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else begin
sky130_fd_sc_hd__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
endgenerate
$adff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.ARST_VALUE(ARST_VALUE) ,
.ARST_POLARITY (ARST_POLARITY)
)
flipflop(
.CLK(GCLK),
.ARST(ARST),
.D(D),
.Q(Q)
);
endmodule
| 7.72891 |
module \$dffe ( CLK, D, EN, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
generate
if (WIDTH < 5) begin
sky130_fd_sc_hd__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_hd__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else begin
sky130_fd_sc_hd__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
endgenerate
$dff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
)
flipflop(
.CLK(GCLK),
.D(D),
.Q(Q)
);
endmodule
| 7.215766 |
module \$dffsre ( CLK, EN, CLR, SET, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter CLR_POLARITY =1'b1;
parameter SET_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN, CLR, SET;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
generate
if (WIDTH < 5) begin
sky130_fd_sc_hd__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_hd__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else begin
sky130_fd_sc_hd__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
endgenerate
$dffsr #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.CLR_POLARITY(CLR_POLARITY),
.SET_POLARITY(SET_POLARITY)
)
flipflop(
.CLK(GCLK),
.CLR(CLR),
.SET(SET),
.D(D),
.Q(Q)
);
endmodule
| 7.063232 |
module \$aldffe ( CLK, EN, ALOAD, AD, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter ALOAD_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN, ALOAD;
input [WIDTH -1:0] D;
input [WIDTH-1:0] AD;
output [WIDTH -1:0] Q;
wire GCLK;
generate
if (WIDTH < 5) begin
sky130_fd_sc_hd__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_hd__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else begin
sky130_fd_sc_hd__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
endgenerate
$aldff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.ALOAD_POLARITY(ALOAD_POLARITY),
)
flipflop(
.CLK(GCLK),
.D(D),
.AD(AD),
.Q(Q)
);
endmodule
| 7.710209 |
module \$sdffce ( CLK, EN, SRST, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter SRST_POLARITY =1'b1;
parameter SRST_VALUE =1'b1;
parameter WIDTH =1;
input CLK, EN, SRST;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
generate
if (WIDTH < 5) begin
sky130_fd_sc_hd__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_hd__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else begin
sky130_fd_sc_hd__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
endgenerate
$sdff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.SRST_POLARITY(SRST_POLARITY),
.SRST_VALUE(SRST_VALUE)
)
flipflop(
.CLK(GCLK),
.SRST(SRST),
.D(D),
.Q(Q)
);
endmodule
| 6.900616 |
module sky130_nor2 (
out,
inp1,
inp2
);
input inp1;
input inp2;
output out;
sky130_fd_sc_hs__nor2_1 nor2 (
.A(inp1),
.B(inp2),
.Y(out)
);
endmodule
| 6.897109 |
module sky130_rom_1kbyte_8x1024_tapeout (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: R
clk,
cs,
addr,
dout
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 10;
parameter ROM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk; // clock
input wire cs; // active high chip select
input wire [ADDR_WIDTH-1:0] addr;
output reg [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] mem[0:ROM_DEPTH-1];
initial begin
$readmemh(
"/home/hadirkhan/chipignite/openram_testchip2/verilog/rtl/sky130_rom_1kbyte_8x1024.hex",
mem, 0, ROM_DEPTH - 1);
end
// reg cs_reg;
// reg [ADDR_WIDTH-1:0] addr_reg;
//wire [DATA_WIDTH-1:0] dout;
always @(negedge clk) begin : MEM_READ0
#(T_HOLD) dout <= 8'bx;
if (cs && VERBOSE) $display($time, " Reading %m addr=%b dout=%b", addr, mem[addr]);
if (cs) #(T_HOLD) dout <= #(DELAY) mem[addr];
end
endmodule
| 7.299843 |
module sky130_sram_1kbytes_1rw1r_8x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg csb0_reg;
reg web0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
addr0_reg = addr0;
din0_reg = din0;
#(T_HOLD) dout0 = 8'bx;
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b", addr0_reg, din0_reg);
end
reg csb1_reg;
reg [ADDR_WIDTH-1:0] addr1_reg;
reg [DATA_WIDTH-1:0] dout1;
// All inputs are registers
always @(posedge clk1) begin
csb1_reg = csb1;
addr1_reg = addr1;
if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
$display(
$time, " WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!", addr0, addr1
);
#(T_HOLD) dout1 = 8'bx;
if (!csb1_reg && VERBOSE)
$display($time, " Reading %m addr1=%b dout1=%b", addr1_reg, mem[addr1_reg]);
end
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
mem[addr0_reg][7:0] = din0_reg[7:0];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
// Memory Read Block Port 1
// Read Operation : When web1 = 1, csb1 = 0
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 7.095527 |
module sky130_sram_1kbyte_1r1w_8x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: W
clk0,
csb0,
addr0,
din0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg csb0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
addr0_reg = addr0;
din0_reg = din0;
if (!csb0_reg && VERBOSE) $display($time, " Writing %m addr0=%b din0=%b", addr0_reg, din0_reg);
end
reg csb1_reg;
reg [ADDR_WIDTH-1:0] addr1_reg;
reg [DATA_WIDTH-1:0] dout1;
// All inputs are registers
always @(posedge clk1) begin
csb1_reg = csb1;
addr1_reg = addr1;
if (!csb0 && !csb1 && (addr0 == addr1))
$display(
$time, " WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!", addr0, addr1
);
#(T_HOLD) dout1 = 8'bx;
if (!csb1_reg && VERBOSE)
$display($time, " Reading %m addr1=%b dout1=%b", addr1_reg, mem[addr1_reg]);
end
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg) begin
mem[addr0_reg][7:0] = din0_reg[7:0];
end
end
// Memory Read Block Port 1
// Read Operation : When web1 = 1, csb1 = 0
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 7.095527 |
module sky130_sram_1kbyte_1rw1r_32x256_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
endmodule
| 7.095527 |
module sky130_sram_1kbyte_1rw1r_32x256_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS-1:0] wmask0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
addr0_reg = addr0;
din0_reg = din0;
`ifndef FORMAL_COMPAT
#(T_HOLD) dout0 = 32'bx;
`endif
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b wmask0=%b", addr0_reg, din0_reg, wmask0_reg);
end
reg csb1_reg;
reg [ADDR_WIDTH-1:0] addr1_reg;
reg [DATA_WIDTH-1:0] dout1;
// All inputs are registers
always @(posedge clk1) begin
csb1_reg = csb1;
addr1_reg = addr1;
if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
$display(
$time, " WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!", addr0, addr1
);
`ifndef FORMAL_COMPAT
#(T_HOLD) dout1 = 32'bx;
`endif
if (!csb1_reg && VERBOSE)
$display($time, " Reading %m addr1=%b dout1=%b", addr1_reg, mem[addr1_reg]);
end
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] = din0_reg[7:0];
if (wmask0_reg[1]) mem[addr0_reg][15:8] = din0_reg[15:8];
if (wmask0_reg[2]) mem[addr0_reg][23:16] = din0_reg[23:16];
if (wmask0_reg[3]) mem[addr0_reg][31:24] = din0_reg[31:24];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
// Memory Read Block Port 1
// Read Operation : When web1 = 1, csb1 = 0
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 7.095527 |
module sky130_sram_1kbyte_1rw1r_8x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 1;
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
endmodule
| 7.095527 |
module sky130_sram_1kbyte_1rw1r_8x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 1;
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS-1:0] wmask0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
addr0_reg = addr0;
din0_reg = din0;
#(T_HOLD) dout0 = 8'bx;
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b wmask0=%b", addr0_reg, din0_reg, wmask0_reg);
end
reg csb1_reg;
reg [ADDR_WIDTH-1:0] addr1_reg;
reg [DATA_WIDTH-1:0] dout1;
// All inputs are registers
always @(posedge clk1) begin
csb1_reg = csb1;
addr1_reg = addr1;
if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
$display(
$time, " WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!", addr0, addr1
);
#(T_HOLD) dout1 = 8'bx;
if (!csb1_reg && VERBOSE)
$display($time, " Reading %m addr1=%b dout1=%b", addr1_reg, mem[addr1_reg]);
end
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] = din0_reg[7:0];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
// Memory Read Block Port 1
// Read Operation : When web1 = 1, csb1 = 0
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 7.095527 |
module sky130_sram_1kbyte_1rw1r_8x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 1;
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
endmodule
| 7.095527 |
module sky130_sram_1kbyte_1rw1r_8x1024_8_norbl (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg csb0_reg;
reg web0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
addr0_reg = addr0;
din0_reg = din0;
#(T_HOLD) dout0 = 8'bx;
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b", addr0_reg, din0_reg);
end
reg csb1_reg;
reg [ADDR_WIDTH-1:0] addr1_reg;
reg [DATA_WIDTH-1:0] dout1;
// All inputs are registers
always @(posedge clk1) begin
csb1_reg = csb1;
addr1_reg = addr1;
if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
$display(
$time, " WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!", addr0, addr1
);
#(T_HOLD) dout1 = 8'bx;
if (!csb1_reg && VERBOSE)
$display($time, " Reading %m addr1=%b dout1=%b", addr1_reg, mem[addr1_reg]);
end
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
mem[addr0_reg][7:0] = din0_reg[7:0];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
// Memory Read Block Port 1
// Read Operation : When web1 = 1, csb1 = 0
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 7.095527 |
module sky130_sram_1kbyte_1rw_32x256_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 33;
parameter ADDR_WIDTH = 9;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input spare_wen0; // spare mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS-1:0] wmask0_reg;
reg spare_wen0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
spare_wen0_reg = spare_wen0;
addr0_reg = addr0;
din0_reg = din0;
#(T_HOLD) dout0 = 32'bx;
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b wmask0=%b", addr0_reg, din0_reg, wmask0_reg);
end
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] = din0_reg[7:0];
if (wmask0_reg[1]) mem[addr0_reg][15:8] = din0_reg[15:8];
if (wmask0_reg[2]) mem[addr0_reg][23:16] = din0_reg[23:16];
if (wmask0_reg[3]) mem[addr0_reg][31:24] = din0_reg[31:24];
if (spare_wen0_reg) mem[addr0_reg][32] = din0_reg[32];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
endmodule
| 7.095527 |
module sky130_sram_1kbyte_1rw1r_32x256_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 0;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 0; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS-1:0] wmask0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
addr0_reg = addr0;
din0_reg = din0;
//#(T_HOLD) dout0 = 32'bx;
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b wmask0=%b", addr0_reg, din0_reg, wmask0_reg);
end
reg csb1_reg;
reg [ADDR_WIDTH-1:0] addr1_reg;
reg [DATA_WIDTH-1:0] dout1;
// All inputs are registers
always @(posedge clk1) begin
csb1_reg = csb1;
addr1_reg = addr1;
if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
$display(
$time, " WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!", addr0, addr1
);
// #(T_HOLD) dout1 = 32'bx;
if (!csb1_reg && VERBOSE)
$display($time, " Reading %m addr1=%b dout1=%b", addr1_reg, mem[addr1_reg]);
end
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] = din0_reg[7:0];
if (wmask0_reg[1]) mem[addr0_reg][15:8] = din0_reg[15:8];
if (wmask0_reg[2]) mem[addr0_reg][23:16] = din0_reg[23:16];
if (wmask0_reg[3]) mem[addr0_reg][31:24] = din0_reg[31:24];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
// Memory Read Block Port 1
// Read Operation : When web1 = 1, csb1 = 0
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 7.095527 |
module sky130_sram_1rw1r_64x256_8 (
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 8;
parameter DATA_WIDTH = 64;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS-1:0] wmask0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// All inputs are registers
always @(posedge clk0) begin
csb0_reg <= csb0;
web0_reg <= web0;
wmask0_reg <= wmask0;
addr0_reg <= addr0;
din0_reg <= din0;
/*verilator lint_off STMTDLY*/
//#(T_HOLD) dout0 <= 64'bx;
// if ( !csb0_reg && web0_reg )
// $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
// if ( !csb0_reg && !web0_reg )
// $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
/*verilator lint_on STMTDLY*/
end
reg csb1_reg;
reg [ADDR_WIDTH-1:0] addr1_reg;
reg [DATA_WIDTH-1:0] dout1;
// All inputs are registers
always @(posedge clk1) begin
csb1_reg <= csb1;
addr1_reg <= addr1;
// if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
// $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
// dout1 <= 64'bx;
// if ( !csb1_reg )
// $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
end
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] <= din0_reg[7:0];
if (wmask0_reg[1]) mem[addr0_reg][15:8] <= din0_reg[15:8];
if (wmask0_reg[2]) mem[addr0_reg][23:16] <= din0_reg[23:16];
if (wmask0_reg[3]) mem[addr0_reg][31:24] <= din0_reg[31:24];
if (wmask0_reg[4]) mem[addr0_reg][39:32] <= din0_reg[39:32];
if (wmask0_reg[5]) mem[addr0_reg][47:40] <= din0_reg[47:40];
if (wmask0_reg[6]) mem[addr0_reg][55:48] <= din0_reg[55:48];
if (wmask0_reg[7]) mem[addr0_reg][63:56] <= din0_reg[63:56];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg)
/*verilator lint_off ASSIGNDLY*/
dout0 <= #(DELAY) mem[addr0_reg];
end
// Memory Read Block Port 1
// Read Operation : When web1 = 1, csb1 = 0
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 7.095527 |
module sky130_sram_2kbyte_1rw1r_32x512 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 9;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
endmodule
| 7.203597 |
module sky130_sram_2kbyte_1rw1r_32x512_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
//for test-bench
parameter DEPTH = 1 << ADDR_WIDTH;
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 9;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS-1:0] wmask0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
//always @(posedge clk0)
always @(*) begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
addr0_reg = addr0;
din0_reg = din0;
//#(T_HOLD) dout0 = 32'bx;
//if ( !csb0_reg && web0_reg && VERBOSE )
// $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
//if ( !csb0_reg && !web0_reg && VERBOSE )
// $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
end
reg csb1_reg;
reg [ADDR_WIDTH-1:0] addr1_reg;
reg [DATA_WIDTH-1:0] dout1;
// All inputs are registers
//always @(posedge clk1)
always @(*) begin
csb1_reg = csb1;
addr1_reg = addr1;
//if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
// $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
//#(T_HOLD) dout1 = 32'bx;
//if ( !csb1_reg && VERBOSE )
// $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
end
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] = din0_reg[7:0];
if (wmask0_reg[1]) mem[addr0_reg][15:8] = din0_reg[15:8];
if (wmask0_reg[2]) mem[addr0_reg][23:16] = din0_reg[23:16];
if (wmask0_reg[3]) mem[addr0_reg][31:24] = din0_reg[31:24];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
// Memory Read Block Port 1
// Read Operation : When web1 = 1, csb1 = 0
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 7.203597 |
module sky130_sram_2kbyte_1rw1r_32x512_8_wrapper (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
clk0,
cs0,
web0,
wmask0,
addr0,
din0,
dout0,
clk1,
cs1,
addr1,
dout1
);
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:156.24-156.28" *)
wire _0_;
(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:157.24-157.28" *)
wire _1_;
(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:144.27-144.32" *)
input [8:0] addr0;
wire [8:0] addr0;
(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:149.27-149.32" *)
input [8:0] addr1;
wire [8:0] addr1;
(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:140.10-140.14" *)
input clk0;
wire clk0;
(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:147.10-147.14" *)
input clk1;
wire clk1;
(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:141.11-141.14" *)
input cs0;
wire cs0;
(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:148.11-148.14" *)
input cs1;
wire cs1;
(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:145.27-145.31" *)
input [31:0] din0;
wire [31:0] din0;
(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:146.27-146.32" *)
output [31:0] dout0;
wire [31:0] dout0;
(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:150.27-150.32" *)
output [31:0] dout1;
wire [31:0] dout1;
(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:142.10-142.14" *)
input web0;
wire web0;
(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:143.28-143.34" *)
input [3:0] wmask0;
wire [3:0] wmask0;
assign _0_ = !(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:156.24-156.28" *) cs0;
assign _1_ = !(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:157.24-157.28" *) cs1;
(* module_not_derived = 32'd1 *)
(* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:151.37-158.4" *)
sky130_sram_2kbyte_1rw1r_32x512_8 inner (
`ifdef USE_POWER_PINS
.vccd1 (vccd1),
.vssd1 (vssd1),
`endif
.addr0 (addr0),
.addr1 (addr1),
.clk0 (clk0),
.clk1 (clk1),
.csb0 (_0_),
.csb1 (_1_),
.din0 (din0),
.dout0 (dout0),
.dout1 (dout1),
.web0 (web0),
.wmask0(wmask0)
);
endmodule
| 7.203597 |
module sky130_sram_2kbyte_1rw_32x512_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 33;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input spare_wen0; // spare mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS-1:0] wmask0_reg;
reg spare_wen0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
spare_wen0_reg = spare_wen0;
addr0_reg = addr0;
din0_reg = din0;
#(T_HOLD) dout0 = 32'bx;
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b wmask0=%b", addr0_reg, din0_reg, wmask0_reg);
end
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] = din0_reg[7:0];
if (wmask0_reg[1]) mem[addr0_reg][15:8] = din0_reg[15:8];
if (wmask0_reg[2]) mem[addr0_reg][23:16] = din0_reg[23:16];
if (wmask0_reg[3]) mem[addr0_reg][31:24] = din0_reg[31:24];
if (spare_wen0_reg) mem[addr0_reg][32] = din0_reg[32];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
endmodule
| 7.203597 |
module sky130_sram_4kbyte_1rw1r_32x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS-1:0] wmask0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
addr0_reg = addr0;
din0_reg = din0;
#(T_HOLD) dout0 = 32'bx;
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b wmask0=%b", addr0_reg, din0_reg, wmask0_reg);
end
reg csb1_reg;
reg [ADDR_WIDTH-1:0] addr1_reg;
reg [DATA_WIDTH-1:0] dout1;
// All inputs are registers
always @(posedge clk1) begin
csb1_reg = csb1;
addr1_reg = addr1;
if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
$display(
$time, " WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!", addr0, addr1
);
#(T_HOLD) dout1 = 32'bx;
if (!csb1_reg && VERBOSE)
$display($time, " Reading %m addr1=%b dout1=%b", addr1_reg, mem[addr1_reg]);
end
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] = din0_reg[7:0];
if (wmask0_reg[1]) mem[addr0_reg][15:8] = din0_reg[15:8];
if (wmask0_reg[2]) mem[addr0_reg][23:16] = din0_reg[23:16];
if (wmask0_reg[3]) mem[addr0_reg][31:24] = din0_reg[31:24];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
// Memory Read Block Port 1
// Read Operation : When web1 = 1, csb1 = 0
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 7.295928 |
module sky130_sram_4kbyte_1rw_32x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 33;
parameter ADDR_WIDTH = 11;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input spare_wen0; // spare mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS-1:0] wmask0_reg;
reg spare_wen0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
spare_wen0_reg = spare_wen0;
addr0_reg = addr0;
din0_reg = din0;
#(T_HOLD) dout0 = 32'bx;
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b wmask0=%b", addr0_reg, din0_reg, wmask0_reg);
end
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] = din0_reg[7:0];
if (wmask0_reg[1]) mem[addr0_reg][15:8] = din0_reg[15:8];
if (wmask0_reg[2]) mem[addr0_reg][23:16] = din0_reg[23:16];
if (wmask0_reg[3]) mem[addr0_reg][31:24] = din0_reg[31:24];
if (spare_wen0_reg) mem[addr0_reg][32] = din0_reg[32];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
endmodule
| 7.295928 |
module sky130_sram_4kbyte_1rw_64x512_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 8;
parameter DATA_WIDTH = 65;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input spare_wen0; // spare mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS-1:0] wmask0_reg;
reg spare_wen0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
spare_wen0_reg = spare_wen0;
addr0_reg = addr0;
din0_reg = din0;
#(T_HOLD) dout0 = 64'bx;
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b wmask0=%b", addr0_reg, din0_reg, wmask0_reg);
end
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] = din0_reg[7:0];
if (wmask0_reg[1]) mem[addr0_reg][15:8] = din0_reg[15:8];
if (wmask0_reg[2]) mem[addr0_reg][23:16] = din0_reg[23:16];
if (wmask0_reg[3]) mem[addr0_reg][31:24] = din0_reg[31:24];
if (wmask0_reg[4]) mem[addr0_reg][39:32] = din0_reg[39:32];
if (wmask0_reg[5]) mem[addr0_reg][47:40] = din0_reg[47:40];
if (wmask0_reg[6]) mem[addr0_reg][55:48] = din0_reg[55:48];
if (wmask0_reg[7]) mem[addr0_reg][63:56] = din0_reg[63:56];
if (spare_wen0_reg) mem[addr0_reg][64] = din0_reg[64];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
endmodule
| 7.295928 |
module sky130_sram_8kbyte_1rw1r_32x2048_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 11;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS-1:0] wmask0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
addr0_reg = addr0;
din0_reg = din0;
#(T_HOLD) dout0 = 32'bx;
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b wmask0=%b", addr0_reg, din0_reg, wmask0_reg);
end
reg csb1_reg;
reg [ADDR_WIDTH-1:0] addr1_reg;
reg [DATA_WIDTH-1:0] dout1;
// All inputs are registers
always @(posedge clk1) begin
csb1_reg = csb1;
addr1_reg = addr1;
if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
$display(
$time, " WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!", addr0, addr1
);
#(T_HOLD) dout1 = 32'bx;
if (!csb1_reg && VERBOSE)
$display($time, " Reading %m addr1=%b dout1=%b", addr1_reg, mem[addr1_reg]);
end
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] = din0_reg[7:0];
if (wmask0_reg[1]) mem[addr0_reg][15:8] = din0_reg[15:8];
if (wmask0_reg[2]) mem[addr0_reg][23:16] = din0_reg[23:16];
if (wmask0_reg[3]) mem[addr0_reg][31:24] = din0_reg[31:24];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
// Memory Read Block Port 1
// Read Operation : When web1 = 1, csb1 = 0
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 7.18435 |
module sky130_sram_8kbyte_1rw_64x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 8;
parameter DATA_WIDTH = 65;
parameter ADDR_WIDTH = 11;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input spare_wen0; // spare mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS-1:0] wmask0_reg;
reg spare_wen0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
spare_wen0_reg = spare_wen0;
addr0_reg = addr0;
din0_reg = din0;
#(T_HOLD) dout0 = 64'bx;
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b wmask0=%b", addr0_reg, din0_reg, wmask0_reg);
end
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] = din0_reg[7:0];
if (wmask0_reg[1]) mem[addr0_reg][15:8] = din0_reg[15:8];
if (wmask0_reg[2]) mem[addr0_reg][23:16] = din0_reg[23:16];
if (wmask0_reg[3]) mem[addr0_reg][31:24] = din0_reg[31:24];
if (wmask0_reg[4]) mem[addr0_reg][39:32] = din0_reg[39:32];
if (wmask0_reg[5]) mem[addr0_reg][47:40] = din0_reg[47:40];
if (wmask0_reg[6]) mem[addr0_reg][55:48] = din0_reg[55:48];
if (wmask0_reg[7]) mem[addr0_reg][63:56] = din0_reg[63:56];
if (spare_wen0_reg) mem[addr0_reg][64] = din0_reg[64];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
endmodule
| 7.18435 |
module sl16 (
input [15:0] in,
output [31:0] out
);
assign out = {in, {16{1'b0}}};
endmodule
| 7.393703 |
module SlakeCol (
input wire [1:0] state,
input wire [3:0] AN,
output reg [3:0] ANout
);
parameter INITIAL = 0;
always @(state, AN) begin
if (state == INITIAL) ANout = 4'b1111;
else ANout = AN;
end
endmodule
| 6.690232 |
module foreground_layer (
input master_clk,
input pixel_clk,
input [7:0] VPIX,
input [11:0] HPIX,
input SCREEN_FLIP,
input ATRRAM,
input CHARAM,
input Z80_WR,
input Z80_RD,
input CPU_RAM_SYNC,
input [15:0] CPU_ADDR,
input [7:0] CPU_DIN,
input [24:0] dn_addr,
input [7:0] dn_data,
input ep3_cs_i,
input ep4_cs_i,
input dn_wr,
output [8:0] HPIX_LT_out,
output [7:0] FG_HI_out,
output [7:0] FG_LO_out,
output [7:0] pixel_output,
output FG_WAIT
);
reg [ 8:0] HPIX_LT;
reg [ 7:0] FG_PX_D;
wire [15:0] FG_RAMD;
always @(posedge pixel_clk) begin
HPIX_LT <= HPIX[8:0]; //this is a 'de-scrambled' version of HPIX_PT - U2D
end
assign HPIX_LT_out = HPIX_LT;
wire FG_CLK = (SCREEN_FLIP ^ !HPIX_LT[2]); //U3C_A
wire FG_SYNC = !(FG_CLK & (SCREEN_FLIP ^ !HPIX_LT[0]) & (SCREEN_FLIP ^ HPIX_LT[1])); //U4C_B
wire colour_copy = FG_SYNC | pixel_clk; //U4B_C
// wire FG_RAM_nOE = (FG_CLK) ? 1'b0 : Z80_RD; //U4D (LS157) - output enable
wire FG_SELECT = (CPU_RAM_SYNC | FG_SYNC);
wire FG_S0 = !(SCREEN_FLIP & FG_SELECT);
wire FG_S1 = !(!SCREEN_FLIP & FG_SELECT);
//foreground RAM - dual port RAM for ease of use
//graphics eproms use port A, CPU uses port B
dpram_dc #(
.widthad_a(11)
) FG_U4G (
.clock_a (master_clk),
.address_a({VPIX[7:3], HPIX_LT[8:3]}),
.data_a (CPU_DIN), //Z80A_databus_out
.wren_a (1'b0),
.q_a (FG_RAMD[15:8]),
.clock_b(master_clk),
.address_b(CPU_ADDR[10:0]),
.data_b(CPU_DIN),
.wren_b(!ATRRAM & !Z80_WR),
.q_b(FG_HI_out)
);
dpram_dc #(
.widthad_a(11)
) FG_U4F (
.clock_a(master_clk),
.address_a({VPIX[7:3], HPIX_LT[8:3]}),
.data_a(CPU_DIN),
.wren_a(1'b0),
.q_a(FG_RAMD[7:0]),
.clock_b(master_clk),
.address_b(CPU_ADDR[10:0]),
.data_b(CPU_DIN),
.wren_b(!CHARAM & !Z80_WR),
.q_b(FG_LO_out)
);
//ROM for foreground graphics
wire [7:0] U6G_FG_A77_03_out, U6F_FG_A77_04_out;
eprom_3 U6G_FG_A77_03 (
.ADDR({FG_RAMD,VPIX[2:0]}), //ROM Address
.CLK(master_clk), //clkm_36MHZ
.DATA(U6G_FG_A77_03_out), //Data output
.ADDR_DL(dn_addr), //Download ROM Address
.CLK_DL (master_clk), //
.DATA_IN(dn_data), //Download Data
.CS_DL (ep3_cs_i), //Select ROM for download
.WR (dn_wr) //Download to ROM
);
eprom_4 U6G_FG_A77_04 (
.ADDR({FG_RAMD,VPIX[2:0]}), //ROM Address
.CLK(master_clk), //clkm_36MHZ
.DATA(U6F_FG_A77_04_out), //Data output
.ADDR_DL(dn_addr), //Download ROM Address
.CLK_DL (master_clk), //
.DATA_IN(dn_data), //Download Data
.CS_DL (ep4_cs_i), //Select ROM for download
.WR (dn_wr) //Download to ROM
);
wire U7F_QA, U7F_QH;
wire U7G_QA, U7G_QH;
//render each pixel to the screen by
//shifting each pixel out of ROM
ls299 U7F (
.clk(pixel_clk),
.pin(U6F_FG_A77_04_out),
.S0 (FG_S0),
.S1 (FG_S1),
.QA (U7F_QA),
.QH (U7F_QH)
);
ls299 U7G (
.clk(pixel_clk),
.pin(U6G_FG_A77_03_out),
.S0 (FG_S0),
.S1 (FG_S1),
.QA (U7G_QA),
.QH (U7G_QH)
);
always @(*) begin //posedge pixel_clk
FG_PX_D[0] <= (SCREEN_FLIP) ? U7G_QA : U7G_QH;
FG_PX_D[1] <= (SCREEN_FLIP) ? U7F_QA : U7F_QH;
end
always @(posedge colour_copy) FG_PX_D[7:2] <= FG_RAMD[15:10];
assign pixel_output = FG_PX_D;
//wait state
wire U2A_SF_B_Q, U1A_SF_B_nQ;
reg U1A_SF_B_Q;
reg U2A_SF_B_Qx;
wire FG_CHIP_SEL = (ATRRAM & CHARAM);
//wire nFG_CHIP_SEL=!FG_CHIP_SEL;
wire nFG_CLK = !FG_CLK;
reg [7:0] count_wait;
//end
reg FG_CS_OLD;
always @(posedge nFG_CLK) begin
count_wait = (!FG_CHIP_SEL & FG_CS_OLD) ? 8'b11000000 : count_wait << 1;
U1A_SF_B_Q = count_wait[7];
FG_CS_OLD = FG_CHIP_SEL;
end
assign FG_WAIT = FG_CHIP_SEL | U1A_SF_B_Q; //FG_CHIP_SEL|
endmodule
| 6.644058 |
module
module m6116_ram(
input[7:0] data,
input clk,
input cen,
input[10:0] addr,
input nWE,
output reg [7:0] q
);
reg[7:0] ram[2047:0];
reg[10:0] addr_reg;
always @ (posedge clk)
begin
if (!nWE && cen) ram[addr] <= data;
if (cen) q <=ram[addr];
end
endmodule
| 6.803339 |
module
module m2016_ram(
input[7:0] data,
input clk,
input nOE,
input nCS,
input[10:0] addr,
input nWE,
output reg [7:0] q
);
reg[7:0] ram[2047:0];
reg[10:0] addr_reg;
always @ (posedge clk)
begin
if (!nWE) ram[addr] <= data; // && !nCS
q <= (!nOE) ? ram[addr] : 8'b00000000; //if (!nOE && !nCS)
end
endmodule
| 6.778266 |
module m6116_ramDP (
input [7:0] data,
input [7:0] data_b,
input clk,
input cen,
input [10:0] addr,
input [10:0] addr_b,
input nWE,
nWE_b,
output reg [7:0] q,
q_b
);
reg [7:0] ram[2047:0];
reg [10:0] addr_reg;
always @(posedge clk) begin
if (!nWE && cen) ram[addr] <= data;
if (cen) q <= ram[addr];
end
always @(posedge clk) begin
if (!nWE_b && cen) ram[addr_b] <= data_b;
if (cen) q_b <= ram[addr_b];
end
endmodule
| 7.08048 |
module m2114_ram (
input [7:0] data,
input clk,
input [6:0] addr,
input nWE,
output reg [7:0] q
);
reg [7:0] ram[127:0];
reg [6:0] addr_reg;
always @(posedge clk) begin
if (!nWE) ram[addr] <= data;
q <= ram[addr];
end
endmodule
| 7.31464 |
module m2511_ram_4 (
input [3:0] data,
input clk,
input [8:0] addr,
input nWE,
output reg [3:0] q
);
reg [3:0] ram[511:0];
reg [8:0] addr_reg;
always @(posedge clk) begin
if (!nWE) ram[addr] <= data;
if (nWE) q <= ram[addr];
end
endmodule
| 7.139377 |
module m6148x2 (
input [7:0] data,
input clk,
input [8:0] addr,
input nWE,
input nCS,
output reg [7:0] q
);
reg [7:0] ram[511:0];
reg [8:0] addr_reg;
always @(posedge clk) begin
if (!nWE) ram[addr] <= data;
if (nWE) q <= ram[addr];
end
endmodule
| 7.267512 |
module m6148_7 (
input [3:0] data,
input clk,
input [7:0] addr,
input nWE,
output reg [7:0] q
);
reg [3:0] ram[255:0];
reg [7:0] addr_reg;
always @(posedge clk) begin
if (!nWE) ram[addr] <= data;
if (nWE) q <= ram[addr];
end
endmodule
| 7.140978 |
module prom6301_L8 (
input [7:0] addr,
input clk,
n_cs,
output reg [3:0] q
);
reg [3:0] rom[255:0];
initial begin
$readmemh("roms/promL8.txt", rom);
end
always @(posedge clk) begin
if (!n_cs) begin
q <= rom[addr];
end
end
endmodule
| 6.888658 |
module prom6331_E1 (
input [4:0] addr,
input clk,
n_cs,
output reg [7:0] q
);
reg [7:0] rom[31:0];
initial begin
$readmemh("roms/promE1.txt", rom);
end
always @(posedge clk) begin
if (!n_cs) begin
q <= rom[addr];
end
end
endmodule
| 6.590665 |
module prom6301_3L (
input [7:0] addr,
input clk,
n_cs,
output reg [3:0] q
);
reg [3:0] rom[255:0];
initial begin
$readmemh("roms/prom3L.txt", rom);
end
always @(posedge clk) begin
if (!n_cs) begin
q <= rom[addr];
end
end
endmodule
| 6.859485 |
module prom6301_4KJ (
input [7:0] addr,
input clk,
n_cs,
output reg [3:0] q
);
reg [3:0] rom[255:0];
initial begin
$readmemh("roms/prom4KJ.txt", rom);
end
always @(posedge clk) begin
if (!n_cs) begin
q <= rom[addr];
end
end
endmodule
| 6.623277 |
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