code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hd__tap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tap_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tap_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__tap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tap_2 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tap_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__tap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd2 (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd2 ();
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd2 ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd2_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__tapvgnd2 base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd ();
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__tapvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__tapvgnd base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvpwrvgnd (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvpwrvgnd ();
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvpwrvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvpwrvgnd_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__tapvpwrvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__tapvpwrvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__tapvpwrvgnd base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xnor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Out... | 7.212805 |
module sky130_fd_sc_hd__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
buf buf0 (Y, xnor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
buf buf0... | 7.212805 |
module sky130_fd_sc_hd__xnor2_1 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB... | 7.212805 |
module sky130_fd_sc_hd__xnor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2_2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB... | 7.212805 |
module sky130_fd_sc_hd__xnor2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor2_4 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB... | 7.212805 |
module sky130_fd_sc_hd__xnor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xnor0_out_X;
wire pwrgood_pp0_out_X;
// ... | 7.212805 |
module sky130_fd_sc_hd__xnor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xnor0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C);
buf buf0 (X, xnor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xnor0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X,... | 7.212805 |
module sky130_fd_sc_hd__xnor3_1 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGN... | 7.212805 |
module sky130_fd_sc_hd__xnor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor3_2 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGN... | 7.212805 |
module sky130_fd_sc_hd__xnor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xnor3_4 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGN... | 7.212805 |
module sky130_fd_sc_hd__xnor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_X;
wire pwrgood_pp0_out_X;
// Name Outpu... | 7.212805 |
module sky130_fd_sc_hd__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
buf buf0 (X, xor... | 7.212805 |
module sky130_fd_sc_hd__xor2_1 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(V... | 7.212805 |
module sky130_fd_sc_hd__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2_2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(V... | 7.212805 |
module sky130_fd_sc_hd__xor2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor2_4 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(V... | 7.212805 |
module sky130_fd_sc_hd__xor2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_X;
wire pwrgood_pp0_out_X;
// ... | 7.212805 |
module sky130_fd_sc_hd__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C... | 7.212805 |
module sky130_fd_sc_hd__xor3_1 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)... | 7.212805 |
module sky130_fd_sc_hd__xor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor3_2 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)... | 7.212805 |
module sky130_fd_sc_hd__xor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__xor3_4 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)... | 7.212805 |
module sky130_fd_sc_hd__xor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_1 (
input GATE,
input CLK,
output GCLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_2 (
input GATE,
input CLK,
output GCLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_4 (
input GATE,
input CLK,
output GCLK
);
endmodule
| 7.212805 |
module \$adffe (ARST, CLK, D, EN, Q);
parameter ARST_POLARITY =1'b1;
parameter ARST_VALUE =1'b0;
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter WIDTH =1;
input ARST, CLK, EN;
input [WIDTH -1 :0] D;
output [WIDTH -1 :0] Q;
wire GCLK;
generate
if ... | 7.72891 |
module \$dffe ( CLK, D, EN, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
generate
if (WIDTH < 5) begin
sky130_fd_sc_hd__dlclkp_1 clk_gate ( .GCLK(GCL... | 7.215766 |
module \$dffsre ( CLK, EN, CLR, SET, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter CLR_POLARITY =1'b1;
parameter SET_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN, CLR, SET;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
generate
... | 7.063232 |
module \$aldffe ( CLK, EN, ALOAD, AD, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter ALOAD_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN, ALOAD;
input [WIDTH -1:0] D;
input [WIDTH-1:0] AD;
output [WIDTH -1:0] Q;
wire GCLK;
generate
if... | 7.710209 |
module \$sdffce ( CLK, EN, SRST, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter SRST_POLARITY =1'b1;
parameter SRST_VALUE =1'b1;
parameter WIDTH =1;
input CLK, EN, SRST;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
generate
if ... | 6.900616 |
module sky130_nor2 (
out,
inp1,
inp2
);
input inp1;
input inp2;
output out;
sky130_fd_sc_hs__nor2_1 nor2 (
.A(inp1),
.B(inp2),
.Y(out)
);
endmodule
| 6.897109 |
module sky130_rom_1kbyte_8x1024_tapeout (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: R
clk,
cs,
addr,
dout
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 10;
parameter ROM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter ... | 7.299843 |
module sky130_sram_1kbytes_1rw1r_8x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = 1 ... | 7.095527 |
module sky130_sram_1kbyte_1r1w_8x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: W
clk0,
csb0,
addr0,
din0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXM... | 7.095527 |
module sky130_sram_1kbyte_1rw1r_32x256_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADD... | 7.095527 |
module sky130_sram_1kbyte_1rw1r_32x256_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADD... | 7.095527 |
module sky130_sram_1kbyte_1rw1r_8x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 1;
parameter DATA_WIDTH = 8;
parameter ADDR... | 7.095527 |
module sky130_sram_1kbyte_1rw1r_8x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 1;
parameter DATA_WIDTH = 8;
parameter ADDR... | 7.095527 |
module sky130_sram_1kbyte_1rw1r_8x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 1;
parameter DATA_WIDTH = 8;
parameter ADDR... | 7.095527 |
module sky130_sram_1kbyte_1rw1r_8x1024_8_norbl (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH... | 7.095527 |
module sky130_sram_1kbyte_1rw_32x256_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 33;
parameter ADDR_WIDTH = 9;
parameter RAM_DEPTH = 1 << ADD... | 7.095527 |
module sky130_sram_1kbyte_1rw1r_32x256_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADD... | 7.095527 |
module sky130_sram_1rw1r_64x256_8 (
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 8;
parameter DATA_WIDTH = 64;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//... | 7.095527 |
module sky130_sram_2kbyte_1rw1r_32x512 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_... | 7.203597 |
module sky130_sram_2kbyte_1rw1r_32x512_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
//for test-bench
parameter DEPTH = 1 << ADDR_WIDTH;
parameter NUM... | 7.203597 |
module sky130_sram_2kbyte_1rw1r_32x512_8_wrapper (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
clk0,
cs0,
web0,
wmask0,
addr0,
din0,
dout0,
clk1,
cs1,
addr1,
dout1
);
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif (* src = "boards/qf100/sky130_sram_2kbyte_... | 7.203597 |
module sky130_sram_2kbyte_1rw_32x512_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 33;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = 1 << AD... | 7.203597 |
module sky130_sram_4kbyte_1rw1r_32x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter AD... | 7.295928 |
module sky130_sram_4kbyte_1rw_32x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 33;
parameter ADDR_WIDTH = 11;
parameter RAM_DEPTH = 1 << A... | 7.295928 |
module sky130_sram_4kbyte_1rw_64x512_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 8;
parameter DATA_WIDTH = 65;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = 1 << AD... | 7.295928 |
module sky130_sram_8kbyte_1rw1r_32x2048_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter AD... | 7.18435 |
module sky130_sram_8kbyte_1rw_64x1024_8 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 8;
parameter DATA_WIDTH = 65;
parameter ADDR_WIDTH = 11;
parameter RAM_DEPTH = 1 << A... | 7.18435 |
module sl16 (
input [15:0] in,
output [31:0] out
);
assign out = {in, {16{1'b0}}};
endmodule
| 7.393703 |
module SlakeCol (
input wire [1:0] state,
input wire [3:0] AN,
output reg [3:0] ANout
);
parameter INITIAL = 0;
always @(state, AN) begin
if (state == INITIAL) ANout = 4'b1111;
else ANout = AN;
end
endmodule
| 6.690232 |
module foreground_layer (
input master_clk,
input pixel_clk,
input [7:0] VPIX,
input [11:0] HPIX,
input SCREEN_FLIP,
input ATRRAM,
input CHARAM,
input Z80_WR,
input Z80_RD,
input CPU_RAM_SYNC,
input [15:0] CPU_ADDR,
input [7:0] CPU_DIN,
input [24:0] dn_addr,
inpu... | 6.644058 |
module
module m6116_ram(
input[7:0] data,
input clk,
input cen,
input[10:0] addr,
input nWE,
output reg [7:0] q
);
reg[7:0] ram[2047:0];
reg[10:0] addr_reg;
always @ (posedge clk)
begin
if (!nWE && cen) ram[addr] <= data;
if (cen) q <=ram[addr];
end
endmodule
| 6.803339 |
module
module m2016_ram(
input[7:0] data,
input clk,
input nOE,
input nCS,
input[10:0] addr,
input nWE,
output reg [7:0] q
);
reg[7:0] ram[2047:0];
reg[10:0] addr_reg;
always @ (posedge clk)
begin
if (!nWE) ram[addr] <= data; // && !nCS
q <= (!nOE) ? ram[addr] : 8'b00000000; //if (!nOE && !nCS)
en... | 6.778266 |
module m6116_ramDP (
input [7:0] data,
input [7:0] data_b,
input clk,
input cen,
input [10:0] addr,
input [10:0] addr_b,
input nWE,
nWE_b,
output reg [7:0] q,
q_b
);
reg [7:0] ram[2047:0];
reg [10:0] addr_reg;
always @(posedge clk) begin
if (!nWE && cen) ram[addr] <= d... | 7.08048 |
module m2114_ram (
input [7:0] data,
input clk,
input [6:0] addr,
input nWE,
output reg [7:0] q
);
reg [7:0] ram[127:0];
reg [6:0] addr_reg;
always @(posedge clk) begin
if (!nWE) ram[addr] <= data;
q <= ram[addr];
end
endmodule
| 7.31464 |
module m2511_ram_4 (
input [3:0] data,
input clk,
input [8:0] addr,
input nWE,
output reg [3:0] q
);
reg [3:0] ram[511:0];
reg [8:0] addr_reg;
always @(posedge clk) begin
if (!nWE) ram[addr] <= data;
if (nWE) q <= ram[addr];
end
endmodule
| 7.139377 |
module m6148x2 (
input [7:0] data,
input clk,
input [8:0] addr,
input nWE,
input nCS,
output reg [7:0] q
);
reg [7:0] ram[511:0];
reg [8:0] addr_reg;
always @(posedge clk) begin
if (!nWE) ram[addr] <= data;
if (nWE) q <= ram[addr];
end
endmodule
| 7.267512 |
module m6148_7 (
input [3:0] data,
input clk,
input [7:0] addr,
input nWE,
output reg [7:0] q
);
reg [3:0] ram[255:0];
reg [7:0] addr_reg;
always @(posedge clk) begin
if (!nWE) ram[addr] <= data;
if (nWE) q <= ram[addr];
end
endmodule
| 7.140978 |
module prom6301_L8 (
input [7:0] addr,
input clk,
n_cs,
output reg [3:0] q
);
reg [3:0] rom[255:0];
initial begin
$readmemh("roms/promL8.txt", rom);
end
always @(posedge clk) begin
if (!n_cs) begin
q <= rom[addr];
end
end
endmodule
| 6.888658 |
module prom6331_E1 (
input [4:0] addr,
input clk,
n_cs,
output reg [7:0] q
);
reg [7:0] rom[31:0];
initial begin
$readmemh("roms/promE1.txt", rom);
end
always @(posedge clk) begin
if (!n_cs) begin
q <= rom[addr];
end
end
endmodule
| 6.590665 |
module prom6301_3L (
input [7:0] addr,
input clk,
n_cs,
output reg [3:0] q
);
reg [3:0] rom[255:0];
initial begin
$readmemh("roms/prom3L.txt", rom);
end
always @(posedge clk) begin
if (!n_cs) begin
q <= rom[addr];
end
end
endmodule
| 6.859485 |
module prom6301_4KJ (
input [7:0] addr,
input clk,
n_cs,
output reg [3:0] q
);
reg [3:0] rom[255:0];
initial begin
$readmemh("roms/prom4KJ.txt", rom);
end
always @(posedge clk) begin
if (!n_cs) begin
q <= rom[addr];
end
end
endmodule
| 6.623277 |
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