code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Slave_AXI4Lite #(
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 4
) (
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
//
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input wire [2 : 0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
//
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
//
output wire [1 : 0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
//
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
input wire [2 : 0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
//
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
output wire [1 : 0] S_AXI_RRESP,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
//
output wire [C_S_AXI_DATA_WIDTH-1:0] rdata_out
);
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// AWREADY
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
axi_awready <= 1'b0;
end else begin
if (S_AXI_AWADDR < 16 && S_AXI_AWADDR > 0 && S_AXI_AWVALID) begin
axi_awready <= 1'b1;
end else begin
axi_awready <= 1'b0;
end
end
end
// AWADDR
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
axi_awaddr <= 0;
end else begin
axi_awaddr <= S_AXI_AWADDR;
end
end
// WREADY
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
axi_wready <= 1'b0;
end else begin
if (S_AXI_WVALID && ~S_AXI_AWVALID) begin
axi_wready <= 1'b1;
end else begin
axi_wready <= 1'b0;
end
end
end
// BVALID BRESP
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
axi_bvalid <= 0;
axi_bresp <= 2'bZ;
end else begin
if (S_AXI_BRESP == 2'b0) begin
axi_bvalid <= 1'b1;
end else axi_bvalid <= 1'b0;
end
end
// ARREADY
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
axi_arready <= 1'b0;
end else begin
if (S_AXI_ARADDR < 16 && S_AXI_ARADDR > 0) begin
axi_arready <= 1'b1;
end else begin
axi_arready <= 1'b0;
end
end
end
// RVALID RRESP
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
axi_rvalid <= 0;
axi_rresp <= 2'bZ;
end else begin
if (S_AXI_RDATA) begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0;
end else if (~S_AXI_RDATA) begin
axi_rvalid <= 1'b0;
axi_rresp <= 2'bZ;
end
end
end
// RDATA
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
axi_rdata <= 0;
end else begin
if (~S_AXI_ARREADY) axi_rdata <= rdata_out;
else axi_rdata <= 0;
end
end
endmodule
| 7.948503 |
module MetadataArray (
input clk,
input reset,
output io_read_ready,
input io_read_valid,
input [5:0] io_read_bits_idx,
output io_write_ready,
input io_write_valid,
input [5:0] io_write_bits_idx,
input io_write_bits_way_en,
input [19:0] io_write_bits_data_tag,
input [1:0] io_write_bits_data_coh_state,
output [19:0] io_resp_0_tag,
output [1:0] io_resp_0_coh_state
);
wire [1:0] T0;
wire [21:0] T1;
wire [21:0] T2;
reg [21:0] tag_arr[63:0];
wire [21:0] T3;
wire [21:0] T4;
wire [21:0] T5;
wire [21:0] T6;
wire [21:0] T7;
wire [21:0] T8;
wire [21:0] T9;
wire T10;
wire wmask;
wire T11;
reg [6:0] rst_cnt;
wire [6:0] T12;
wire [6:0] T13;
wire [6:0] T14;
wire [21:0] T15;
wire [5:0] T16;
wire [6:0] waddr;
wire [6:0] T17;
wire [21:0] T18;
wire [21:0] wdata;
wire [21:0] T19;
wire [1:0] T20;
wire [21:0] T21;
wire [21:0] T22;
wire [21:0] T23;
wire [1:0] rstVal_coh_state;
wire [1:0] T24;
wire [19:0] rstVal_tag;
wire [19:0] T25;
wire T26;
wire [5:0] T27;
reg [5:0] R28;
wire [5:0] T29;
wire [19:0] T30;
wire T31;
wire T32;
wire T33;
wire T34;
`ifndef SYNTHESIS
integer initvar;
initial begin
#0.002;
for (initvar = 0; initvar < 64; initvar = initvar + 1) tag_arr[initvar] = {1{$random}};
rst_cnt = {1{$random}};
R28 = {1{$random}};
end
`endif
assign io_resp_0_coh_state = T0;
assign T0 = T1[1'h1:1'h0];
assign T1 = T2[5'h15:1'h0];
assign T2 = tag_arr[R28];
always @(posedge clk) if (T26) tag_arr[T27] <= T4;
assign T4 = T18 | T5;
assign T5 = T15 & T6;
assign T6 = ~T7;
assign T7 = T8;
assign T8 = 22'h0 - T9;
assign T9 = {21'h0, T10};
assign T10 = wmask;
assign wmask = T11 ? 1'h1 : io_write_bits_way_en;
assign T11 = rst_cnt < 7'h40;
assign T12 = reset ? 7'h0 : T13;
assign T13 = T11 ? T14 : rst_cnt;
assign T14 = rst_cnt + 7'h1;
assign T15 = tag_arr[T16];
assign T16 = waddr[3'h5:1'h0];
assign waddr = T11 ? rst_cnt : T17;
assign T17 = {1'h0, io_write_bits_idx};
assign T18 = wdata & T7;
assign wdata = T19;
assign T19 = {T25, T20};
assign T20 = T21[1'h1:1'h0];
assign T21 = T11 ? T23 : T22;
assign T22 = {io_write_bits_data_tag, io_write_bits_data_coh_state};
assign T23 = {rstVal_tag, rstVal_coh_state};
assign rstVal_coh_state = T24;
assign T24 = 2'h0;
assign rstVal_tag = 20'h0;
assign T25 = T21[5'h15:2'h2];
assign T26 = T11 | io_write_valid;
assign T27 = waddr[3'h5:1'h0];
assign T29 = io_read_valid ? io_read_bits_idx : R28;
assign io_resp_0_tag = T30;
assign T30 = T1[5'h15:2'h2];
assign io_write_ready = T31;
assign T31 = T11 ^ 1'h1;
assign io_read_ready = T32;
assign T32 = T34 & T33;
assign T33 = io_write_valid ^ 1'h1;
assign T34 = T11 ^ 1'h1;
always @(posedge clk) begin
if (reset) begin
rst_cnt <= 7'h0;
end else if (T11) begin
rst_cnt <= T14;
end
if (io_read_valid) begin
R28 <= io_read_bits_idx;
end
end
endmodule
| 6.901681 |
module RRArbiter_0 (
input clk,
input reset,
output io_in_1_ready,
input io_in_1_valid,
input [29:0] io_in_1_bits,
output io_in_0_ready,
input io_in_0_valid,
input [29:0] io_in_0_bits,
input io_out_ready,
output io_out_valid,
output [29:0] io_out_bits,
output io_chosen
);
wire T0;
wire T1;
wire T2;
wire T3;
wire T4;
reg R5;
wire T6;
wire T7;
wire T8;
wire [29:0] T9;
wire T10;
wire T11;
wire T12;
wire T13;
wire T14;
wire T15;
wire T16;
wire T17;
wire T18;
wire T19;
wire T20;
wire T21;
wire T22;
wire T23;
wire T24;
wire T25;
wire T26;
wire T27;
wire T28;
wire T29;
wire T30;
`ifndef SYNTHESIS
integer initvar;
initial begin
#0.002;
R5 = {1{$random}};
end
`endif
assign io_chosen = T0;
assign T0 = T1;
assign T1 = T3 ? 1'h1 : T2;
assign T2 = io_in_0_valid == 1'h0;
assign T3 = io_in_1_valid & T4;
assign T4 = R5 < 1'h1;
assign T6 = reset ? 1'h0 : T7;
assign T7 = T8 ? T0 : R5;
assign T8 = io_out_ready & io_out_valid;
assign io_out_bits = T9;
assign T9 = T10 ? io_in_1_bits : io_in_0_bits;
assign T10 = T0;
assign io_out_valid = T11;
assign T11 = T10 ? io_in_1_valid : io_in_0_valid;
assign io_in_0_ready = T12;
assign T12 = T13 & io_out_ready;
assign T13 = T14;
assign T14 = T21 | T15;
assign T15 = T16 ^ 1'h1;
assign T16 = T19 | T17;
assign T17 = io_in_1_valid & T18;
assign T18 = R5 < 1'h1;
assign T19 = io_in_0_valid & T20;
assign T20 = R5 < 1'h0;
assign T21 = R5 < 1'h0;
assign io_in_1_ready = T22;
assign T22 = T23 & io_out_ready;
assign T23 = T24;
assign T24 = T28 | T25;
assign T25 = T26 ^ 1'h1;
assign T26 = T27 | io_in_0_valid;
assign T27 = T19 | T17;
assign T28 = T30 & T29;
assign T29 = R5 < 1'h1;
assign T30 = T19 ^ 1'h1;
always @(posedge clk) begin
if (reset) begin
R5 <= 1'h0;
end else if (T8) begin
R5 <= T0;
end
end
endmodule
| 6.876771 |
module Queue_3 (
input clk,
input reset,
output io_enq_ready,
input io_enq_valid,
input [25:0] io_enq_bits_addr,
input [4:0] io_enq_bits_tag,
input io_enq_bits_rw,
input io_deq_ready,
output io_deq_valid,
output [25:0] io_deq_bits_addr,
output [4:0] io_deq_bits_tag,
output io_deq_bits_rw,
output [1:0] io_count
);
wire [1:0] T0;
wire ptr_diff;
reg deq_ptr;
wire T1;
wire T2;
wire T3;
wire do_deq;
wire T4;
wire do_flow;
wire T5;
reg enq_ptr;
wire T6;
wire T7;
wire T8;
wire do_enq;
wire T9;
wire T10;
wire T11;
wire ptr_match;
reg maybe_full;
wire T12;
wire T13;
wire T14;
wire T15;
wire [31:0] T16;
wire [5:0] T17;
wire T18;
wire [31:0] T19;
reg [31:0] ram[1:0];
wire [31:0] T20;
wire [31:0] T21;
wire [31:0] T22;
wire [5:0] T23;
wire [4:0] T24;
wire [25:0] T25;
wire [4:0] T26;
wire [25:0] T27;
wire T28;
wire empty;
wire T29;
wire T30;
wire full;
`ifndef SYNTHESIS
integer initvar;
initial begin
#0.002;
deq_ptr = {1{$random}};
enq_ptr = {1{$random}};
maybe_full = {1{$random}};
for (initvar = 0; initvar < 2; initvar = initvar + 1) ram[initvar] = {1{$random}};
end
`endif
assign io_count = T0;
assign T0 = {T11, ptr_diff};
assign ptr_diff = enq_ptr - deq_ptr;
assign T1 = reset ? 1'h0 : T2;
assign T2 = do_deq ? T3 : deq_ptr;
assign T3 = deq_ptr + 1'h1;
assign do_deq = T5 & T4;
assign T4 = do_flow ^ 1'h1;
assign do_flow = 1'h0;
assign T5 = io_deq_ready & io_deq_valid;
assign T6 = reset ? 1'h0 : T7;
assign T7 = do_enq ? T8 : enq_ptr;
assign T8 = enq_ptr + 1'h1;
assign do_enq = T10 & T9;
assign T9 = do_flow ^ 1'h1;
assign T10 = io_enq_ready & io_enq_valid;
assign T11 = maybe_full & ptr_match;
assign ptr_match = enq_ptr == deq_ptr;
assign T12 = reset ? 1'h0 : T13;
assign T13 = T14 ? do_enq : maybe_full;
assign T14 = do_enq != do_deq;
assign io_deq_bits_rw = T15;
assign T15 = T16[1'h0:1'h0];
assign T16 = {T25, T17};
assign T17 = {T24, T18};
assign T18 = T19[1'h0:1'h0];
assign T19 = ram[deq_ptr];
always @(posedge clk) if (do_enq) ram[enq_ptr] <= T21;
assign T21 = T22;
assign T22 = {io_enq_bits_addr, T23};
assign T23 = {io_enq_bits_tag, io_enq_bits_rw};
assign T24 = T19[3'h5:1'h1];
assign T25 = T19[5'h1f:3'h6];
assign io_deq_bits_tag = T26;
assign T26 = T16[3'h5:1'h1];
assign io_deq_bits_addr = T27;
assign T27 = T16[5'h1f:3'h6];
assign io_deq_valid = T28;
assign T28 = empty ^ 1'h1;
assign empty = ptr_match & T29;
assign T29 = maybe_full ^ 1'h1;
assign io_enq_ready = T30;
assign T30 = full ^ 1'h1;
assign full = ptr_match & maybe_full;
always @(posedge clk) begin
if (reset) begin
deq_ptr <= 1'h0;
end else if (do_deq) begin
deq_ptr <= T3;
end
if (reset) begin
enq_ptr <= 1'h0;
end else if (do_enq) begin
enq_ptr <= T8;
end
if (reset) begin
maybe_full <= 1'h0;
end else if (T14) begin
maybe_full <= do_enq;
end
end
endmodule
| 6.517764 |
module slave (
input [1:0] MODE,
input reg [7:0] data_in,
input reset,
input clk,
input MOSI,
output reg MISO,
input CS,
output reg [7:0] data_out
);
reg entered = 0;
reg [7:0] R_data;
reg [7:0] T_data;
reg done; //
integer count = 0;
reg is_read = 0;
//wire sclk;
//assign sclk= (MODE==2'b00||MODE==2'b11)?~clk:clk;
always @(posedge clk) begin
//if(MODE==2'b00||MODE==2'b11)
//begin
if ((reset || !is_read)) begin
T_data = data_in;
count = 0;
entered = 0;
done = 0;
end
//end
if (!CS) begin
//if(MODE==2'b00||MODE==2'b11)
// begin
if (entered) begin
R_data = {MOSI, R_data[7:1]};
count = count + 1;
if (count == 8) begin
count = 0;
entered = 0;
data_out = R_data;
is_read = 0;
done = 1;
end
end
// end
/*else if(MODE==2'b10||MODE==2'b01)
if(!done)
begin
MISO=T_data[7];
T_data={T_data[6:0],1'bx};
entered=1;
is_read=1;
end*/
end
end
always @(negedge clk) begin
/*if(MODE==2'b01||MODE==2'b10)
begin*/
if ((reset || !is_read)) begin
T_data = data_in;
count = 0;
entered = 0;
done = 0;
end
//end
if (!CS) begin
/*if(MODE==2'b01||MODE==2'b10)
begin
if(entered)
begin
R_data={MOSI,R_data[7:1]};
count=count+1;
if(count==8)
begin
count=0;
entered=0;
data_out=R_data;
is_read=0;
done=1;
end
end
end
else if(MODE==2'b00||MODE==2'b11)*/
if (!done) begin
MISO = T_data[7];
T_data = {T_data[6:0], 1'bx};
entered = 1;
is_read = 1;
end
end
end
endmodule
| 7.264319 |
module slaveFIFO2b_streamIN (
input reset_,
input clk_100,
input stream_in_mode_selected,
input flaga_d,
input flagb_d,
output slwr_streamIN_,
output [31:0] data_out_stream_in
);
reg [ 2:0] current_stream_in_state;
reg [ 2:0] next_stream_in_state;
reg [31:0] data_gen_stream_in;
//parameters for StreamIN mode state machine
parameter [2:0] stream_in_idle = 3'd0;
parameter [2:0] stream_in_wait_flagb = 3'd1;
parameter [2:0] stream_in_write = 3'd2;
parameter [2:0] stream_in_write_wr_delay = 3'd3;
assign slwr_streamIN_ = ((current_stream_in_state == stream_in_write) | (current_stream_in_state == stream_in_write_wr_delay)) ? 1'b0 : 1'b1;
//streamIN mode state machine
always @(posedge clk_100, negedge reset_) begin
if (!reset_) begin
current_stream_in_state <= stream_in_idle;
end else begin
current_stream_in_state <= next_stream_in_state;
end
end
//StreamIN mode state machine combo
always @(*) begin
next_stream_in_state = current_stream_in_state;
case (current_stream_in_state)
stream_in_idle: begin
if ((stream_in_mode_selected) & (flaga_d == 1'b1)) begin
next_stream_in_state = stream_in_wait_flagb;
end else begin
next_stream_in_state = stream_in_idle;
end
end
stream_in_wait_flagb: begin
if (flagb_d == 1'b1) begin
next_stream_in_state = stream_in_write;
end else begin
next_stream_in_state = stream_in_wait_flagb;
end
end
stream_in_write: begin
if (flagb_d == 1'b0) begin
next_stream_in_state = stream_in_write_wr_delay;
end else begin
next_stream_in_state = stream_in_write;
end
end
stream_in_write_wr_delay: begin
next_stream_in_state = stream_in_idle;
end
endcase
end
//data generator counter for Partial, ZLP, StreamIN modes
always @(posedge clk_100, negedge reset_) begin
if (!reset_) begin
data_gen_stream_in <= 32'd0;
end else if ((slwr_streamIN_ == 1'b0) & (stream_in_mode_selected)) begin
data_gen_stream_in <= data_gen_stream_in + 1;
end else if (!stream_in_mode_selected) begin
data_gen_stream_in <= 32'd0;
end
end
assign data_out_stream_in = data_gen_stream_in;
endmodule
| 6.613765 |
module slaveFIFO2b_streamIN_only #(
parameter DW = 32
) (
input wire reset_, //input reset active low
input wire clk, //input clk
output wire wfifo_rd,
input wire fifo_aempty,
output wire clk_out, //output clk 100 Mhz (max) and 180 phase shift
output wire [1:0] faddr, //output fifo address
output wire slrd_, //output read select 1'b1
output wire slwr_, //output write select
input wire flaga, //full flag
input wire flagb, //partial full flag
//input wire flagc, //empty flag
//input wire flagd, //empty partial flag
output wire sloe_, //output enable select
output wire slcs_, //output chip select
output wire pktend_ //output pkt end
);
reg [ 2:0] current_stream_in_state;
reg [ 2:0] next_stream_in_state;
reg [DW-1:0] data_gen_stream_in;
// parameters for StreamIN mode state machine
localparam [2:0] stream_in_idle = 3'd0;
localparam [2:0] stream_in_wait_flagb = 3'd1;
localparam [2:0] stream_in_write = 3'd2;
localparam [2:0] stream_in_write_wr_delay = 3'd3;
reg flaga_d;
reg flagb_d;
//reg flagc_d;
//reg flagd_d;
reg slwr_streamIN_d1_;
wire slwr_streamIN_;
//output signal assignment
assign slcs_ = 1'b0;
assign pktend_ = 1'b1;
assign slrd_ = 1'b1;
assign faddr = 2'd0;
assign sloe_ = 1'b1;
//assign PMODE = 2'b11;
//assign RESET = 1'b1;
//assign fdata = (slwr_streamIN_d1_) ? {DW{1'bz}}'dz : data_gen_stream_in;
assign slwr_ = slwr_streamIN_d1_;
assign clk_out = ~clk;
//wire clk;
//wire lock;
///flopping the INPUTs flags
always @(posedge clk, negedge reset_) begin
if (!reset_) begin
flaga_d <= 1'd0;
flagb_d <= 1'd0;
//flagc_d <= 1'd0;
//flagd_d <= 1'd0;
end else begin
flaga_d <= flaga;
flagb_d <= flagb;
//flagc_d <= flagc;
//flagd_d <= flagd;
end
end
assign slwr_streamIN_ = ( (!fifo_aempty) & (current_stream_in_state == stream_in_write)) ? 1'b0 : 1'b1;
assign wfifo_rd = ~slwr_streamIN_;
always @(posedge clk, negedge reset_) begin
if (!reset_) begin
slwr_streamIN_d1_ <= 1'b1;
end else begin
slwr_streamIN_d1_ <= slwr_streamIN_;
end
end
//streamIN mode state machine
always @(posedge clk, negedge reset_) begin
if (!reset_) begin
current_stream_in_state <= stream_in_idle;
end else begin
current_stream_in_state <= next_stream_in_state;
end
end
//StreamIN mode state machine combo
always @(*) begin
next_stream_in_state = current_stream_in_state;
case (current_stream_in_state)
stream_in_idle: begin
if (flaga_d == 1'b1) begin
next_stream_in_state = stream_in_wait_flagb;
end else begin
next_stream_in_state = stream_in_idle;
end
end
stream_in_wait_flagb: begin
if (flagb_d == 1'b1) begin
next_stream_in_state = stream_in_write;
end else begin
next_stream_in_state = stream_in_wait_flagb;
end
end
stream_in_write: begin
if (flagb_d == 1'b0) begin
next_stream_in_state = stream_in_write_wr_delay;
end else begin
next_stream_in_state = stream_in_write;
end
end
stream_in_write_wr_delay: begin
next_stream_in_state = stream_in_idle;
end
endcase
end
endmodule
| 6.613765 |
module slaveFIFO2b_streamOUT (
input reset_,
input clk_100,
input stream_out_mode_selected,
input flagc_d,
input flagd_d,
input [31:0] stream_out_data_from_fx3,
output slrd_streamOUT_,
output sloe_streamOUT_
);
reg [2:0] current_stream_out_state;
reg [2:0] next_stream_out_state;
//parameters for StreamOUT mode state machine
parameter [2:0] stream_out_idle = 3'd0;
parameter [2:0] stream_out_flagc_rcvd = 3'd1;
parameter [2:0] stream_out_wait_flagd = 3'd2;
parameter [2:0] stream_out_read = 3'd3;
parameter [2:0] stream_out_read_rd_and_oe_delay = 3'd4;
parameter [2:0] stream_out_read_oe_delay = 3'd5;
reg [1:0] oe_delay_cnt;
reg rd_oe_delay_cnt;
assign slrd_streamOUT_ = ((current_stream_out_state == stream_out_read) | (current_stream_out_state == stream_out_read_rd_and_oe_delay)) ? 1'b0 : 1'b1;
assign sloe_streamOUT_ = ((current_stream_out_state == stream_out_read) | (current_stream_out_state == stream_out_read_rd_and_oe_delay) | (current_stream_out_state == stream_out_read_oe_delay)) ? 1'b0 : 1'b1;
//counter to delay the read and output enable signal
always @(posedge clk_100, negedge reset_) begin
if (!reset_) begin
rd_oe_delay_cnt <= 1'b0;
end else if (current_stream_out_state == stream_out_read) begin
rd_oe_delay_cnt <= 1'b1;
end else if((current_stream_out_state == stream_out_read_rd_and_oe_delay) & (rd_oe_delay_cnt > 1'b0))begin
rd_oe_delay_cnt <= rd_oe_delay_cnt - 1'b1;
end else begin
rd_oe_delay_cnt <= rd_oe_delay_cnt;
end
end
//Counter to delay the OUTPUT Enable(oe) signal
always @(posedge clk_100, negedge reset_) begin
if (!reset_) begin
oe_delay_cnt <= 2'd0;
end else if (current_stream_out_state == stream_out_read_rd_and_oe_delay) begin
oe_delay_cnt <= 2'd2;
end else if((current_stream_out_state == stream_out_read_oe_delay) & (oe_delay_cnt > 1'b0))begin
oe_delay_cnt <= oe_delay_cnt - 1'b1;
end else begin
oe_delay_cnt <= oe_delay_cnt;
end
end
//streamOUT mode state machine
always @(posedge clk_100, negedge reset_) begin
if (!reset_) begin
current_stream_out_state <= stream_out_idle;
end else begin
current_stream_out_state <= next_stream_out_state;
end
end
//steamOUT mode state machine combo
always @(*) begin
next_stream_out_state = current_stream_out_state;
case (current_stream_out_state)
stream_out_idle: begin
if ((stream_out_mode_selected) & (flagc_d == 1'b1)) begin
next_stream_out_state = stream_out_flagc_rcvd;
end else begin
next_stream_out_state = stream_out_idle;
end
end
stream_out_flagc_rcvd: begin
next_stream_out_state = stream_out_wait_flagd;
end
stream_out_wait_flagd: begin
if (flagd_d == 1'b1) begin
next_stream_out_state = stream_out_read;
end else begin
next_stream_out_state = stream_out_wait_flagd;
end
end
stream_out_read: begin
if (flagd_d == 1'b0) begin
next_stream_out_state = stream_out_read_rd_and_oe_delay;
end else begin
next_stream_out_state = stream_out_read;
end
end
stream_out_read_rd_and_oe_delay: begin
if (rd_oe_delay_cnt == 0) begin
next_stream_out_state = stream_out_read_oe_delay;
end else begin
next_stream_out_state = stream_out_read_rd_and_oe_delay;
end
end
stream_out_read_oe_delay: begin
if (oe_delay_cnt == 0) begin
next_stream_out_state = stream_out_idle;
end else begin
next_stream_out_state = stream_out_read_oe_delay;
end
end
endcase
end
endmodule
| 6.613765 |
module slaveFIFO2b_ZLP (
input reset_,
input clk_100,
input zlp_mode_selected,
input flaga_d,
input flagb_d,
output slwr_zlp_,
output pktend_zlp_,
output [31:0] data_out_zlp
);
reg [2:0] current_zlp_state;
reg [2:0] next_zlp_state;
//parameters for ZLP mode state machine
parameter [2:0] zlp_idle = 3'd0;
parameter [2:0] zlp_wait_flagb = 3'd1;
parameter [2:0] zlp_write = 3'd2;
parameter [2:0] zlp_write_wr_delay = 3'd3;
parameter [2:0] zlp_wait = 3'd4;
reg [ 3:0] strob_cnt;
reg strob;
reg [31:0] data_gen_zlp;
reg pktend_;
assign slwr_zlp_ = ((current_zlp_state == zlp_write) | (current_zlp_state == zlp_write_wr_delay)) ? 1'b0 : 1'b1;
//counter to generate the strob for ZLP data pkts
always @(posedge clk_100, negedge reset_) begin
if (!reset_) begin
strob_cnt <= 4'd0;
end else if (current_zlp_state == zlp_idle) begin
strob_cnt <= 4'd0;
end else if (current_zlp_state == zlp_wait) begin
strob_cnt <= strob_cnt + 1'b1;
end
end
//Strob logic
always @(posedge clk_100, negedge reset_) begin
if (!reset_) begin
strob <= 1'b0;
end else if ((current_zlp_state == zlp_wait) && (strob_cnt == 4'b0111)) begin
strob <= !strob;
end
end
always @(*) begin
if (zlp_mode_selected & (strob_cnt == 4'b0011) & (strob == 1'b1)) begin
pktend_ = 1'b0;
end else begin
pktend_ = 1'b1;
end
end
assign pktend_zlp_ = pktend_;
//ZLP mode state machine
always @(posedge clk_100, negedge reset_) begin
if (!reset_) begin
current_zlp_state <= zlp_idle;
end else begin
current_zlp_state <= next_zlp_state;
end
end
//ZLP mode state machine combo
always @(*) begin
next_zlp_state = current_zlp_state;
case (current_zlp_state)
zlp_idle: begin
if ((zlp_mode_selected) & (flaga_d == 1'b1)) begin
next_zlp_state = zlp_wait_flagb;
end else begin
next_zlp_state = zlp_idle;
end
end
zlp_wait_flagb: begin
if ((strob == 1'b1) & (flagb_d == 1'b1)) begin
next_zlp_state = zlp_wait;
end else if (flagb_d == 1'b1) begin
next_zlp_state = zlp_write;
end else begin
next_zlp_state = zlp_wait_flagb;
end
end
zlp_write: begin
if (flagb_d == 1'b0) begin
next_zlp_state = zlp_write_wr_delay;
end else begin
next_zlp_state = zlp_write;
end
end
zlp_write_wr_delay: begin
next_zlp_state = zlp_wait;
end
zlp_wait: begin
if (strob_cnt == 4'b0111) begin
next_zlp_state = zlp_idle;
end else begin
next_zlp_state = zlp_wait;
end
end
endcase
end
//data generator counter for zlp mode
always @(posedge clk_100, negedge reset_) begin
if (!reset_) begin
data_gen_zlp <= 32'd0;
end else if ((slwr_zlp_ == 1'b0) & (zlp_mode_selected)) begin
data_gen_zlp <= data_gen_zlp + 1;
end else if (!zlp_mode_selected) begin
data_gen_zlp <= 32'd0;
end
end
assign data_out_zlp = data_gen_zlp;
endmodule
| 7.341839 |
module SlaveMaster (
input reset,
input ss1,
input ss2,
input ss3,
input ss4,
input sck,
input cpol,
input cpoh,
input MOSI,
//input [7:0] Address,
output MISO
);
slave1 s1 (
reset,
ss1,
sck,
cpol,
cpoh,
MOSI,
MISO
);
slave2 s2 (
reset,
ss2,
sck,
cpol,
cpoh,
MOSI,
MISO
);
slave3 s3 (
reset,
ss3,
sck,
cpol,
cpoh,
MOSI,
MISO
);
slave4 s4 (
reset,
ss4,
sck,
cpol,
cpoh,
MOSI,
MISO
);
endmodule
| 6.767317 |
module SlaveModule #(
parameter DATA_WIDTH_SLAVE = 32,
parameter STROBE_WIDTH_SLAVE = DATA_WIDTH_SLAVE / 8,
parameter ADDRESS_WIDTH_SLAVE = 8
) (
//Global signals
input aclk,
input aresetn,
//Write address channel
input [ADDRESS_WIDTH_SLAVE-1:0] awaddr,
input awvalid,
output reg awready,
//Write data channel
input [ DATA_WIDTH_SLAVE-1:0] wdata,
input [ STROBE_WIDTH_SLAVE-1:0] wstrb,
input wvalid,
output reg wready,
//Write response channel
output reg bvalid,
input bready,
//Read address channel
input [ADDRESS_WIDTH_SLAVE-1:0] araddr,
input [ 2:0] arprot,
input arvalid,
output reg arready,
//Read data channel
output reg [ DATA_WIDTH_SLAVE-1:0] rdata,
output reg rvalid,
input rready
);
reg [2:0] ss, ss_next;
localparam S0=3'b000, READ=3'b001, DATAREAD=3'b010, WRITE=3'b011, DATAWRITE=3'b100,RESPONSE=3'b101, READINIT=3'b110, WRITEINIT=3'b111;
reg [DATA_WIDTH_SLAVE-1:0] memory[0:1023];
reg [2:0] prot;
localparam path = "C:\ProgettoES1\progettoAXI4\data.hex";
integer outfile;
integer i;
reg [DATA_WIDTH_SLAVE-1:0] temp_memory;
always @(posedge aclk)
if (aresetn) ss <= S0;
else ss <= ss_next;
always @(ss, awaddr, awvalid, wdata, wstrb, wvalid, bready, araddr, arprot, arvalid, rready) begin
ss_next = ss;
$readmemh("data.hex", memory);
begin
case (ss)
S0: begin
awready = 0;
wready = 0;
bvalid = 0;
awready = 0;
arready = 0;
rvalid = 0;
rdata = 0;
if (awvalid == 1) ss_next = WRITEINIT;
if (arvalid == 1) ss_next = READINIT;
end
READINIT: begin
arready = 1;
prot = arprot;
ss_next = READ;
end
WRITEINIT: begin
awready = 1;
ss_next = WRITE;
end
READ:
if (rready == 1) begin
rvalid = 1;
ss_next = DATAREAD;
arready = 0;
end
DATAREAD: begin
rdata = memory[araddr];
ss_next = S0;
end
WRITE:
if (wvalid == 1) begin
wready = 1;
ss_next = DATAWRITE;
awready = 0;
end
DATAWRITE: begin
temp_memory = memory[awaddr];
for (i = 0; i < 32; i = i + 1) begin
if (wstrb[i/8] == 1) begin
temp_memory[i] = wdata[i];
end
end
memory[awaddr] = temp_memory;
outfile = $fopen("data.hex", "w");
for (i = 0; i < 1024; i = i + 1) begin
$fdisplay(outfile, "%h", memory[i]); //write as hexadecimal
end
$fclose(outfile);
ss_next = RESPONSE;
end
RESPONSE: begin
if (bready == 1) begin
bvalid = 1;
ss_next = S0;
end
end
endcase
end
end
endmodule
| 7.113216 |
module slaveRxStatusMonitor (
connectStateIn,
connectStateOut,
resumeDetectedIn,
resetEventOut,
resumeIntOut,
clk,
rst
);
input [1:0] connectStateIn;
input resumeDetectedIn;
input clk;
input rst;
output resetEventOut;
output [1:0] connectStateOut;
output resumeIntOut;
wire [1:0] connectStateIn;
wire resumeDetectedIn;
reg resetEventOut;
reg [1:0] connectStateOut;
reg resumeIntOut;
wire clk;
wire rst;
reg [1:0] oldConnectState;
reg oldResumeDetected;
always @(connectStateIn) begin
connectStateOut <= connectStateIn;
end
always @(posedge clk) begin
if (rst == 1'b1) begin
oldConnectState <= connectStateIn;
oldResumeDetected <= resumeDetectedIn;
end else begin
oldConnectState <= connectStateIn;
oldResumeDetected <= resumeDetectedIn;
if (oldConnectState != connectStateIn) resetEventOut <= 1'b1;
else resetEventOut <= 1'b0;
if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0) resumeIntOut <= 1'b1;
else resumeIntOut <= 1'b0;
end
end
endmodule
| 6.544278 |
module slaveRxStatusMonitor_simlib (
connectStateIn,
connectStateOut,
resumeDetectedIn,
resetEventOut,
resumeIntOut,
clk,
rst
);
input [1:0] connectStateIn;
input resumeDetectedIn;
input clk;
input rst;
output resetEventOut;
output [1:0] connectStateOut;
output resumeIntOut;
wire [1:0] connectStateIn;
wire resumeDetectedIn;
reg resetEventOut;
reg [1:0] connectStateOut;
reg resumeIntOut;
wire clk;
wire rst;
reg [1:0] oldConnectState;
reg oldResumeDetected;
always @(connectStateIn) begin
connectStateOut <= connectStateIn;
end
always @(posedge clk) begin
if (rst == 1'b1) begin
oldConnectState <= connectStateIn;
oldResumeDetected <= resumeDetectedIn;
end else begin
oldConnectState <= connectStateIn;
oldResumeDetected <= resumeDetectedIn;
if (oldConnectState != connectStateIn) resetEventOut <= 1'b1;
else resetEventOut <= 1'b0;
if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0) resumeIntOut <= 1'b1;
else resumeIntOut <= 1'b0;
end
end
endmodule
| 6.544278 |
module involving the switching of the slave select line
// during transmission and idle states.
//
// Inputs:
// rst User input Reset
// transmit signal from SPImaster causing ss line to go low
// ( enable )
// done signal from SPIinterface causing ss line to go
// high ( disable )
//
// Outputs:
// ss ss output to ACL
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added comments and modified code (Josh Sackos)
////////////////////////////////////////////////////////////////////////////////////
// ===================================================================================
// Define Module, Inputs and Outputs
// ===================================================================================
module slaveSelect(
rst,
clk,
transmit,
done,
ss
);
// ====================================================================================
// Port Declarations
// ====================================================================================
input rst;
input clk;
input transmit;
input done;
output ss;
reg ss = 1'b1;
// ===================================================================================
// Implementation
// ===================================================================================
//-----------------------------------------------
// Generates Slave Select Signal
//-----------------------------------------------
always @(posedge clk)
begin: ssprocess
begin
//reset state, ss goes high ( disabled )
if (rst == 1'b1)
ss <= 1'b1;
//if transmitting, then ss goes low ( enabled )
else if (transmit == 1'b1)
ss <= 1'b0;
//if done, then ss goes high ( disabled )
else if (done == 1'b1)
ss <= 1'b1;
end
end
endmodule
| 8.691693 |
module slave_0 (
clk,
rst,
sel,
s_data_in_0,
ack,
s_data_out_0
);
//---Input & output Port---//
input [31:0] s_data_in_0;
input sel, clk, rst;
output [31:0] s_data_out_0;
output ack;
//---- Your design code---//
reg [31:0] s_data_out_0;
reg ack = 0;
reg [7:0] mac_dataA = 8'd0, mac_dataB = 8'd0;
reg [31:0] reg_product = 32'd0, reg_compute = 32'd0;
reg data_in = 0, mac_product = 0, mac_compute = 0;
reg [3:0] counter = 4'b0000;
always @(posedge clk or posedge rst) begin
if (rst) begin
s_data_out_0 <= 31'd0;
ack <= 0;
end
if (sel) begin
if (counter == 4'd8) begin
s_data_out_0 <= reg_compute;
ack <= 1;
end else ack <= 0;
end
end
always @(posedge clk or posedge rst) begin
if (rst) counter <= 4'd0;
else if (sel) begin
if (counter == 4'd12) counter <= 4'd0;
else counter <= counter + 1;
end
end
always @(posedge clk) begin
if (sel) begin
mac_dataA <= s_data_in_0[15:8];
mac_dataB <= s_data_in_0[7:0];
end
end
always @(*) begin
reg_product = mac_dataA * mac_dataB;
end
always @(*) begin
if (counter == 4'd0) begin
reg_compute = reg_product;
end
else if (counter == 4'd1 || counter == 4'd2 || counter == 4'd3 || counter == 4'd4 || counter == 4'd5 || counter == 4'd6 || counter == 4'd7 || counter ==4'd8)
begin
reg_compute = reg_compute + reg_product;
end
end
endmodule
| 6.721307 |
module butterfly0 (
ar,
ai,
br,
bi,
xr,
xi,
yr,
yi,
w0r,
w0i
);
input signed [15:0] xr, yr, xi, yi;
input signed [31:0] w0r, w0i;
output signed [15:0] ar, ai, br, bi;
assign ar = xr + yr;
assign ai = xi;
assign br = xr - yr;
assign bi = xi;
endmodule
| 8.051328 |
module butterfly1 (
ar,
ai,
br,
bi,
xr,
xi,
yr,
yi,
w0r,
w0i
);
input signed [15:0] xr, xi, yr, yi;
input signed [31:0] w0r, w0i;
output signed [15:0] ar, ai, br, bi;
wire signed [47:0] dick_re1, dick_im1, dick_re2, dick_im2;
wire signed [47:0] far, fai, fbr, fbi;
assign dick_re1 = yr * w0r;
assign dick_re2 = yi * w0i;
assign dick_im1 = yr * w0i;
assign dick_im2 = yi * w0r;
assign far = (xr << 16) + dick_re1 - dick_re2;
assign fai = (xi << 16) + dick_im1 + dick_im2;
assign fbr = (xr << 16) - dick_re1 + dick_re2;
assign fbi = (xi << 16) - dick_im1 - dick_im2;
assign ar = far[31:16];
assign ai = fai[31:16];
assign br = fbr[31:16];
assign bi = fbi[31:16];
endmodule
| 7.109482 |
module slave_1_tb ();
reg clk, rst_n, slave_en;
wire slave_done;
wire [3:0] slave_out;
slave_1 obey (
clk,
rst_n,
slave_en,
slave_done,
slave_out
);
initial begin
$dumpfile("slave_1_tb.vcd");
$dumpvars(0, slave_1_tb);
rst_n = 0;
slave_en = 0;
#10;
rst_n = 1;
slave_en = 1;
#40;
slave_en = 0;
#200;
$finish;
end
always begin
clk = 1'b1;
#5;
clk = 1'b0;
#5;
end
endmodule
| 7.651523 |
module Slave_4K (
SEL,
HADDR,
HWDATA,
HRDATA,
HRESP,
CLK,
HREADY,
RST,
MLOCK,
AB
);
input [15:0] HADDR;
input [31:0] HWDATA;
input SEL;
input RST, CLK;
input MLOCK;
//input HWRITE;
output reg [31:0] HRDATA;
output reg [1:0] HRESP;
output reg HREADY;
output reg AB;
// Slave States
parameter IDLE = 3'd0;
parameter ACTIVE = 3'd1;
parameter WRITE = 3'd2;
parameter READ = 3'd3;
parameter MSB_ADDR = 11; // MSB for 2K Address
reg [2:0] state;
reg [10:0] S_ADDR;
reg HWRITE;
reg TRANS;
// 4K Memory Addresses
reg [31:0] S_REG[4095:0]; //4K, 32-bit registers
initial begin
AB = 1'bz;
HREADY <= 1'bz;
end
always @(posedge CLK or posedge RST) begin
if (RST == 1) begin
HRDATA <= 32'bx;
HRESP <= `OKAY;
HREADY <= 1'bz;
S_ADDR <= 11'bx;
HWRITE <= 1'bx;
TRANS <= 1'bx;
state <= IDLE;
end else begin
state <= IDLE;
case (state)
IDLE: begin
HRESP <= `OKAY;
HREADY <= 1'bz;
state <= (SEL == 1) ? ACTIVE : IDLE;
end
ACTIVE: begin
HRESP <= `OKAY;
HREADY <= 1'b1;
S_ADDR <= HADDR[MSB_ADDR:0];
HWRITE <= HADDR[12];
TRANS <= HADDR[15];
if (TRANS == 1'b1) begin
HREADY <= 1'b1; // toggles the HREADY line only if selected as active device
HRESP <= `OKAY;
state <= (HWRITE == 1) ? WRITE : READ;
end else begin
HRESP <= `ERROR;
state <= (SEL == 1) ? ACTIVE : IDLE;
end
end
WRITE: begin
S_ADDR <= HADDR[MSB_ADDR:0];
HWRITE <= HADDR[12];
TRANS <= HADDR[15];
if (TRANS == `START) begin
S_REG[S_ADDR] <= HWDATA;
if (HWDATA == S_REG[S_ADDR]) begin
HRESP <= `OKAY;
HREADY <= 1'b1;
state <= ACTIVE;
end else if (HWDATA !== S_REG[S_ADDR] && MLOCK == 1) begin
HRESP <= `RETRY;
HREADY <= 1'b0;
state <= WRITE;
end else begin
HRESP <= `ERROR;
HREADY <= 1'b0;
state <= ACTIVE;
end
end else begin
HRESP <= `RETRY;
state <= ACTIVE;
end
end
READ: begin
S_ADDR <= HADDR[MSB_ADDR:0];
HWRITE <= HADDR[12];
TRANS <= HADDR[15];
if (TRANS == `START) begin
HRDATA <= S_REG[S_ADDR];
end else begin
HRESP <= `RETRY;
state <= ACTIVE;
end
if (HRDATA == S_REG[S_ADDR]) begin
HRESP <= `OKAY;
HREADY <= 1'b1;
state <= ACTIVE;
end else if (HRDATA != S_REG[S_ADDR] && MLOCK == 1) begin
HRESP <= `RETRY;
HREADY <= 1'b0;
state <= READ;
end else begin
HRESP <= `ERROR;
HREADY <= 1'b0;
state <= ACTIVE;
end
end
endcase
end
end
endmodule
| 6.849796 |
module slave_apb (
output reg [7 : 0] prdata, //dataout from slave
input penable, // to enable read or write
input pwrite, // control signal
input psel, // select signal
input pclk, // posedge clk
input presetn, // negedge reset
input [7 : 0] paddr, // 8-bit address
input [7 : 0] pwdata // 8-bit write data
);
parameter IDLE = 2'b00; // states
parameter SETUP = 2'b01;
parameter ACCESS = 2'b10;
reg [1 : 0] pres_state; // to store state changes
reg [1 : 0] next_state;
reg [7 : 0] slave [0 : 255]; // slaveory-256 bytes
reg [7 : 0] prdata1;
always @(posedge pclk or negedge presetn) begin // : fsm_slave
if (!presetn) pres_state = IDLE;
else pres_state = next_state;
end // : fsm_slave
always @(*) begin
prdata1 = 8'b0;
next_state = 2'b0;
case (pres_state)
IDLE: begin //: idle_state
if (!penable) begin
if (psel == 0) begin
next_state = IDLE;
prdata1 = 8'b0;
end else if ((psel == 1) && (penable == 0)) next_state = SETUP;
end
end //: idle_state
SETUP: begin //: setup_state
if ((psel == 1) && (penable == 1)) next_state = ACCESS;
end //: setup_state
ACCESS: begin //: access_state
if ((psel == 1) && (penable == 0)) next_state = SETUP;
else begin //: no_transfer
next_state = IDLE;
end //: no_transfer
if (!pwrite) prdata1 = slave[paddr];
if ((psel == 0) && (penable == 0)) next_state = IDLE;
end //: enable_state
default: next_state = IDLE;
endcase
end //: state_change
always @( /*posedge pclk or negedge presetn*/ *) begin
if (!presetn) begin
prdata = 8'b0;
end else if ((pres_state == ACCESS) && (pwrite == 0)) prdata = prdata1;
end
always @( /*posedge pclk or negedge presetn*/ *) begin
if ((pres_state == ACCESS) && (pwrite == 1)) begin
slave[paddr] = pwdata;
end
end
endmodule
| 9.552011 |
module slave_axi_v3_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add ports here
input wire [C_S00_AXI_DATA_WIDTH-1:0] user_reg2,
input wire [C_S00_AXI_DATA_WIDTH-1:0] user_reg3,
output wire [C_S00_AXI_DATA_WIDTH-1:0] user_reg1,
output wire [C_S00_AXI_DATA_WIDTH-1:0] user_reg0,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
slave_axi_v3_v1_0_S00_AXI #(
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) slave_axi_v3_v1_0_S00_AXI_inst (
.user_reg0(user_reg0),
.user_reg1(user_reg1),
.user_reg2(user_reg2),
.user_reg3(user_reg3),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
| 6.806688 |
module slave_bus_ifc (
rst_n,
cc_psel,
cc_penable,
cc_pwrite,
cc_paddr,
cc_pwdata,
cc_prdata,
rng_cpu_prdata,
cpu_rng_psel,
cpu_rng_pwrite,
cpu_rng_paddr,
cpu_rng_pwdata
);
parameter CRY_ENGINE_UPPER_IDX = 4'ha;
`include "cc_params.inc"
parameter CLK_STATUS_ADDR = 12'h824;
input rst_n;
input cc_psel;
input cc_penable;
input cc_pwrite;
input [11:0] cc_paddr;
input [31:0] cc_pwdata;
input [31:0] rng_cpu_prdata;
output [31:0] cc_prdata;
output cpu_rng_psel;
output cpu_rng_pwrite;
output [11:0] cpu_rng_paddr;
output [31:0] cpu_rng_pwdata;
wire [31:0] prdata;
wire cpu_cry_ctl_sel;
wire cpu_cry_ctl_write;
wire [11:0] cpu_cry_ctl_addr;
wire [31:0] cpu_cry_ctl_wdata;
assign cpu_cry_ctl_sel = cc_psel & (cc_paddr[11:8] == 4'h8);
assign cpu_rng_psel = cc_psel & (cc_paddr[11:8] == 4'h1);
assign cpu_cry_ctl_write = cc_pwrite & cc_penable;
assign cpu_rng_pwrite = cc_pwrite & cc_penable;
assign cpu_cry_ctl_addr = cpu_cry_ctl_sel ? cc_paddr[11:0] : 12'b0;
assign cpu_rng_paddr = cpu_rng_psel ? cc_paddr[11:0] : 12'b0;
assign cpu_cry_ctl_wdata = cc_pwdata & {32{cpu_cry_ctl_sel}};
assign cpu_rng_pwdata = cc_pwdata & {32{cpu_rng_psel}};
assign cc_prdata = cpu_rng_psel ? rng_cpu_prdata : {32{1'b0}};
endmodule
| 7.473276 |
module when rst_n == 0.
// request :request signal sent by the master.
// ack :ack output to master.
// data_in :data input from master.
// notice :signal indicating the receive of data or request from master, will be asserted for 1 sec.
// data :data output to the seven segment module, in order to display the data from master.
// valid :signal from master indicating the current data_in is valid and is ready to be sampled.
//////////////////////////////////////////////////////////////////////////////////
module slave_control(clk, rst_n, request, ack, data_in, notice, valid, data);
input clk;
input rst_n;
input request;
input [3-1:0] data_in;
input valid;
output reg ack;
output reg notice;
output reg [3-1:0] data;
parameter state_wait_rqst = 2'b00;
parameter state_wait_to_send_ack = 2'b01;
parameter state_send_ack = 2'b10;
parameter state_wait_data = 2'b11;
reg [2-1:0] state, next_state;
reg start, next_start;
reg next_ack;
reg next_notice;
reg [3-1:0] next_data;
wire done;
counter cnt_0(.clk(clk), .rst_n(rst_n), .start(start), .done(done));
always@(posedge clk) begin
if (rst_n == 0) begin
state <= state_wait_rqst;
notice <= 0;
ack <= 0;
data <= 0;
start <= 0;
end
else begin
state <= next_state;
notice <= next_notice;
ack <= next_ack;
data <= next_data;
start <= next_start;
end
end
always@(*) begin
next_state = state;
next_notice = notice;
next_ack = ack;
next_data = data;
next_start = start;
case(state)
state_wait_rqst: begin
next_state = (request == 1)? state_wait_to_send_ack : state_wait_rqst;
next_notice = 1'b0;
next_ack = 1'b0;
next_data = data;
next_start = (request == 1)? 1'b1 : 1'b0;
end
state_wait_to_send_ack: begin
next_state = (done == 1)? state_wait_data : state_wait_to_send_ack;
next_notice = 1'b1;
next_ack = 1'b0;
next_data = data;
next_start = 1'b1;
end
state_wait_data: begin
next_state = (valid == 1)? state_wait_rqst : state_wait_data;
next_notice = 1'b0;
next_ack = 1'b1;
next_data = (valid == 1)? data_in : data;
next_start = 1'b0;
end
default: begin
next_state = state_wait_rqst;
next_notice = 1'b0;
next_ack = 1'b0;
next_data = 3'b0;
next_start = 1'b0;
end
endcase
end
endmodule
| 7.974228 |
module slave_controller (
input clk,
input reset,
input chipselect,
input write,
input [3:0] addr,
input [31:0] writedata,
output [23:0] GPIO_out
);
reg [11:0] in = 12'd0;
reg [6*`PERIOD_LENGTH-1:0] duty_cycle = 0;
reg [15:0] period = 16'd0;
always @(posedge clk)
if (chipselect & write)
casex (addr)
4'b0000: in[1:0] <= writedata[1:0];
4'b0001: in[3:2] <= writedata[1:0];
4'b0010: in[5:4] <= writedata[1:0];
4'b0011: in[7:6] <= writedata[1:0];
4'b0100: in[9:8] <= writedata[1:0];
4'b0101: in[11:10] <= writedata[1:0];
4'b1000: duty_cycle[`PERIOD_LENGTH-1:0] <= writedata[`PERIOD_LENGTH-1:0];
4'b1001: duty_cycle[2*`PERIOD_LENGTH-1:`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4'b1010: duty_cycle[3*`PERIOD_LENGTH-1:2*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4'b1011: duty_cycle[4*`PERIOD_LENGTH-1:3*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4'b1100: duty_cycle[5*`PERIOD_LENGTH-1:4*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH:0];
4'b1101: duty_cycle[6*`PERIOD_LENGTH-1:5*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH:0];
4'b1110: period <= writedata[15:0];
default: ; // do nothing
endcase
generate
genvar i;
for (i = 0; i < 6; i = i + 1) begin : motor_control_loop
motor_controller mc (
clk,
in[i*2+1],
in[i*2],
period,
duty_cycle[(i+1)*`PERIOD_LENGTH-1:i*`PERIOD_LENGTH],
GPIO_out[i*4+3:i*4]
);
end
endgenerate
endmodule
| 7.868824 |
module slave_det(
output reg sequence,
output out,
input clk,
input resetn,
input [4:0]in
);
seq_detector sd(.sequence(sequence),.clk(clk),.resetn(resetn),.out(out));
always @(posedge clk)
begin
if(~resetn)
sequence = in[0];
else
sequence = {1'b0,in[4:1]};
end
endmodule
| 8.072941 |
module slave_FIFO #(
parameter DATA_DEPTH = 'd64 //FIFO深度
) (
input clk_i, //时钟
rstn_i, //复位
chx_valid_i, //外部信号有效信号
a2sx_ack_i, //仲裁器允许读数据包
slvx_en_i, //通道使能(来自寄存器)
input wire [31:0] chx_data_i,
input wire [ 2:0] slvx_pkglen_i, //本通道数据包长度
output wire chx_ready_o, //允许接收外部信号(如果FIFO比较满就不接收)
output wire [ 5:0] margin_o, //本通道FIFO余量
output wire [31:0] slvx_data_o, //发送给仲裁器的数据
output reg slvx_val_o, //发送给仲裁器的数据有效
output wire slvx_req_o,
output reg slvx_end_o //增加的
);
/*************************<中间信号>*********************/
wire [5:0] pkglen;
integer i;
wire wr_en, rd_en, val_i, //i不为0时该信号为1，用于生成rd_en的中间信号
rst_n;
assign wr_en = chx_valid_i & chx_ready_o;
assign chx_ready_o = (margin_o >= 'd32); //这里比较充裕，可以(margin_o<slvx_pkglen_i)
assign rst_n = rstn_i & slvx_en_i;
assign pkglen = 2 ** (slvx_pkglen_i + 'd2); //因为slvx_pkglen_i时[2:0]所以+2不会溢出
/*************************<实例化SCFIFO>*********************/
SCFIFO FIFO1 (
.clk(clk_i),
.rst_n(rst_n),
.data_in(chx_data_i),
.rd_en(rd_en),
.wr_en(wr_en),
.data_out(slvx_data_o),
.empty(), //保留
.full(), //保留
.FIFO_margin_o(margin_o)
);
/*************************<时序电路>*********************/
always @(posedge clk_i or negedge rst_n) begin //产生输出长度i计数信号
if (~rst_n) i <= 0;
else if (a2sx_ack_i == 1) i <= 1;
else if (i > 0 && i < pkglen - 1) //^^C语言连续不等式是错误的
i <= i + 1;
else i <= 0;
end
always @(posedge clk_i or negedge rst_n) begin
if (~rst_n) slvx_val_o <= 0;
else slvx_val_o <= rd_en;
end
always @(posedge clk_i or negedge rst_n) begin
if (~rst_n) slvx_end_o <= 0;
else if (i == pkglen - 1) slvx_end_o <= 1;
else slvx_end_o <= 0;
end
/*************************<组合电路>*********************/
assign val_i = (i == 0) ? 0 : 1;
assign rd_en = val_i | a2sx_ack_i;
assign slvx_req_o=(margin_o<=DATA_DEPTH-pkglen)?1:0;//如果FIFO使用量大于一个pkglen，则请求发送
endmodule
| 8.435445 |
module slave_file #(
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 4
) (
input wire s_aclk,
input wire s_aresetn,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] s_awaddr,
input wire [2 : 0] s_awprot,
input wire s_awvalid,
output wire s_awready,
input wire [C_S_AXI_DATA_WIDTH-1 : 0] s_wdata,
input wire s_wvalid,
output wire s_wready,
output wire [1 : 0] s_bresp,
output wire s_bvalid,
input wire s_bready,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] s_araddr,
input wire [2 : 0] s_arprot,
input wire s_arvalid,
output wire s_arready,
output wire [C_S_AXI_DATA_WIDTH-1 : 0] s_rdata,
output wire [1 : 0] s_rresp,
output wire s_rvalid,
input wire s_rready,
output wire [C_S_AXI_DATA_WIDTH-1:0] rdata_out,
output wire [C_S_AXI_DATA_WIDTH-1:0] data
);
Slave_AXI4Lite #(
.C_S_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH)
) Slave_AXI4Lite_file (
.S_AXI_ACLK(s_aclk),
.S_AXI_ARESETN(s_aresetn),
.S_AXI_AWADDR(s_awaddr),
.S_AXI_AWPROT(s_awprot),
.S_AXI_AWVALID(s_awvalid),
.S_AXI_AWREADY(s_awready),
.S_AXI_WDATA(s_wdata),
.S_AXI_WVALID(s_wvalid),
.S_AXI_WREADY(s_wready),
.S_AXI_BRESP(s_bresp),
.S_AXI_BVALID(s_bvalid),
.S_AXI_BREADY(s_bready),
.S_AXI_ARADDR(s_araddr),
.S_AXI_ARPROT(s_arprot),
.S_AXI_ARVALID(s_arvalid),
.S_AXI_ARREADY(s_arready),
.S_AXI_RDATA(s_rdata),
.S_AXI_RRESP(s_rresp),
.S_AXI_RVALID(s_rvalid),
.S_AXI_RREADY(s_rready),
.rdata_out(rdata_out)
);
// Slave
//
reg [C_S_AXI_ADDR_WIDTH-1 : 0] reg_waddr_in;
//
reg [C_S_AXI_ADDR_WIDTH-1 : 0] reg_raddr_in;
// Master
reg [C_S_AXI_DATA_WIDTH-1 : 0] slave_reg[16 : 1];
//
initial begin : d
integer i;
for (i = 1; i < 17; i = i + 1) slave_reg[i] = i;
end
//
always @(posedge s_awready) begin
reg_waddr_in <= s_awaddr;
end
// Master
always @(posedge s_wready) begin
slave_reg[reg_waddr_in] <= s_wdata;
end
//
always @(posedge s_arready) begin
reg_raddr_in <= s_araddr;
end
//
assign data = slave_reg[reg_raddr_in];
endmodule
| 8.24519 |
module slave_mux #(
parameter ADDR_WD = 32,
parameter DATA_WD = 32,
parameter STRB_WD = 4,
parameter PROT_WD = 3
) (
input b_pclk,
input b_prst_n,
input b_psel,
input b_penable,
input b_pwrite,
input [ADDR_WD-1 : 0] b_paddr,
input [DATA_WD-1 : 0] b_pwdata,
input [PROT_WD-1 : 0] b_pprot,
input [STRB_WD-1 : 0] b_pstrb,
output [DATA_WD-1 : 0] b_prdata,
output b_pready
);
wire [DATA_WD-1 : 0] prdata0, prdata1, prdata2, prdata3;
wire psel0, psel1, psel2, psel3;
wire pready0, pready1, pready2, pready3;
wire [1 : 0] addrx;
wire [3 : 0] selx;
reg [DATA_WD-1 : 0] b_prdata_r;
assign b_prdata = b_prdata_r;
assign addrx = b_paddr[ADDR_WD-1 : ADDR_WD-2];
assign selx = {addrx == 2'd3, addrx == 2'd2, addrx == 2'd1, addrx == 2'd0};
assign psel0 = b_psel && selx[0];
assign psel1 = b_psel && selx[1];
assign psel2 = b_psel && selx[2];
assign psel3 = b_psel && selx[3];
assign b_pready = pready0 && selx[0] || pready1 && selx[1] || pready2 && selx[2] || pready2 && selx[3];
always @(*) begin
case (selx)
4'b0001: b_prdata_r = prdata0;
4'b0010: b_prdata_r = prdata1;
4'b0100: b_prdata_r = prdata2;
4'b1000: b_prdata_r = prdata3;
default: b_prdata_r = prdata0;
endcase
end
slave #(
.ADDR_WD(ADDR_WD),
.DATA_WD(DATA_WD),
.STRB_WD(STRB_WD),
.PROT_WD(PROT_WD)
) slave0 (
.b_pclk(b_pclk),
.b_prst_n(b_prst_n),
.b_psel(psel0),
.b_penable(b_penable),
.b_pwrite(b_pwrite),
.b_paddr(b_paddr),
.b_pwdata(b_pwdata),
.b_pprot(b_pprot),
.b_pstrb(b_pstrb),
.b_prdata(prdata0),
.b_pready(pready0)
);
slave #(
.ADDR_WD(ADDR_WD),
.DATA_WD(DATA_WD),
.STRB_WD(STRB_WD),
.PROT_WD(PROT_WD)
) slave1 (
.b_pclk(b_pclk),
.b_prst_n(b_prst_n),
.b_psel(psel1),
.b_penable(b_penable),
.b_pwrite(b_pwrite),
.b_paddr(b_paddr),
.b_pwdata(b_pwdata),
.b_pprot(b_pprot),
.b_pstrb(b_pstrb),
.b_prdata(prdata1),
.b_pready(pready1)
);
slave #(
.ADDR_WD(ADDR_WD),
.DATA_WD(DATA_WD),
.STRB_WD(STRB_WD),
.PROT_WD(PROT_WD)
) slave2 (
.b_pclk(b_pclk),
.b_prst_n(b_prst_n),
.b_psel(psel2),
.b_penable(b_penable),
.b_pwrite(b_pwrite),
.b_paddr(b_paddr),
.b_pwdata(b_pwdata),
.b_pprot(b_pprot),
.b_pstrb(b_pstrb),
.b_prdata(prdata2),
.b_pready(pready2)
);
slave #(
.ADDR_WD(ADDR_WD),
.DATA_WD(DATA_WD),
.STRB_WD(STRB_WD),
.PROT_WD(PROT_WD)
) slave3 (
.b_pclk(b_pclk),
.b_prst_n(b_prst_n),
.b_psel(psel3),
.b_penable(b_penable),
.b_pwrite(b_pwrite),
.b_paddr(b_paddr),
.b_pwdata(b_pwdata),
.b_pprot(b_pprot),
.b_pstrb(b_pstrb),
.b_prdata(prdata3),
.b_pready(pready3)
);
endmodule
| 7.174126 |
module
//
// This module interfaces with an APB master and selects
// and routes data from connected slave devices
//
// select - bits to select the peripheral
// PRDATA - APB data from the current peripheral
// PSELs - Peripheral select - Only one bit in this vector
// will ever be set at the same time
// PRDATAs - Data from each of the peripherals
// PSEL - Peripheral select enable
module slave_mux_apb2_slave #(
parameter SELECTOR_BITS = 4,
parameter DATA_BITS = 8,
parameter SLAVES = 2**SELECTOR_BITS
)
(
input wire [SELECTOR_BITS - 1:0] select,
input wire [SLAVES * DATA_BITS - 1:0] PRDATAs,
input wire PSEL,
output wire [DATA_BITS - 1:0] PRDATA,
output wire [SLAVES - 1:0] PSELs
);
assign PSELs = 0 + PSEL << select;
assign PRDATA = (select < SLAVES) ? PRDATAs[select * DATA_BITS+:DATA_BITS] : 0;
endmodule
| 8.000328 |
module slave_mux_apb2_slave_tb;
localparam SELECTOR_BITS = 5;
localparam DATA_BITS = 9;
localparam PERIPHERALS = 1 << SELECTOR_BITS;
reg [SELECTOR_BITS - 1:0] select;
reg [PERIPHERALS * DATA_BITS - 1:0] PRDATAs;
reg PSEL;
wire [DATA_BITS - 1:0] PRDATA;
wire [PERIPHERALS - 1:0] PSELs;
slave_mux_apb2_slave #(
.SELECTOR_BITS(SELECTOR_BITS),
.DATA_BITS(DATA_BITS)
) slave_mux_apb2_slave (
.select(select),
.PRDATAs(PRDATAs),
.PSEL(PSEL),
.PRDATA(PRDATA),
.PSELs(PSELs)
);
initial begin
$dumpfile("top.vcd");
$dumpvars;
end
initial begin
select = 0;
PRDATAs = 'hx;
PSEL = 0;
end
event terminate_sim;
initial begin
@terminate_sim;
#200 $finish;
end
task normal_operation_testcase;
integer i;
reg [DATA_BITS - 1:0] expected;
begin
for (i = 0; i < PERIPHERALS; i = i + 1) begin
expected = $random;
select = i;
PSEL = 0;
PRDATAs = 'hx;
PRDATAs[i*DATA_BITS+:DATA_BITS] = expected;
#1;
`util_assert_equal(expected, PRDATA);
`util_assert_equal(0, PSELs);
PSEL = 1;
#1 `util_assert_equal(expected, PRDATA);
`util_assert_equal(1 << select, PSELs);
end
end
endtask
initial begin
normal_operation_testcase();
->terminate_sim;
end
endmodule
| 6.55923 |
module slave_passthru #(
parameter S_WB_ADR_WIDTH = 32,
parameter S_WB_DAT_WIDTH = 32
) (
// wishbone slave signals
input [S_WB_ADR_WIDTH-1:0] S_ADR_I,
input [S_WB_DAT_WIDTH-1:0] S_DAT_I,
input S_WE_I,
input [S_WB_DAT_WIDTH/8-1:0] S_SEL_I,
input S_STB_I,
input S_CYC_I,
input S_LOCK_I,
input [2:0] S_CTI_I,
input [1:0] S_BTE_I,
output [S_WB_DAT_WIDTH-1:0] S_DAT_O,
output S_ACK_O,
output S_ERR_O,
output S_RTY_O,
// external signals
output clk,
output rst,
output [S_WB_ADR_WIDTH-1:0] slv_adr,
output [S_WB_DAT_WIDTH-1:0] slv_master_data,
input [S_WB_DAT_WIDTH-1:0] slv_slave_data,
output slv_strb,
output slv_cyc,
input slv_ack,
input slv_err,
input slv_rty,
output [S_WB_DAT_WIDTH/8-1:0] slv_sel,
output slv_we,
output [1:0] slv_bte,
output [2:0] slv_cti,
output slv_lock,
input intr_active_high,
input CLK_I,
input RST_I,
output INTR_O
);
// Instantiate the open cores module
passthru instantiate_passthru (
// Connect Wishbone slave
.S_ADR_I (S_ADR_I),
.S_DAT_I (S_DAT_I),
.S_WE_I (S_WE_I),
.S_SEL_I (S_SEL_I),
.S_STB_I (S_STB_I),
.S_CYC_I (S_CYC_I),
.S_LOCK_I(S_LOCK_I),
.S_CTI_I (S_CTI_I),
.S_BTE_I (S_BTE_I),
.S_DAT_O (S_DAT_O),
.S_ACK_O (S_ACK_O),
.S_ERR_O (S_ERR_O),
.S_RTY_O (S_RTY_O),
// Connect External signals
.clk(clk),
.rst(rst),
.slv_adr(slv_adr),
.slv_master_data(slv_master_data),
.slv_slave_data(slv_slave_data),
.slv_strb(slv_strb),
.slv_cyc(slv_cyc),
.slv_ack(slv_ack),
.slv_err(slv_err),
.slv_rty(slv_rty),
.slv_sel(slv_sel),
.slv_we(slv_we),
.slv_bte(slv_bte),
.slv_cti(slv_cti),
.slv_lock(slv_lock),
.intr_active_high(intr_active_high),
.CLK_I(CLK_I),
.RST_I(RST_I),
.intr_high(INTR_O)
);
endmodule
| 8.625748 |
module slave_select (
input clk,
input [ 7:0] adr_1,
input [15:0] adr_first_reg_tx_1,
input [ 7:0] num_reg_tx_1,
input [15:0] adr_first_reg_rx_1,
input [ 7:0] num_reg_rx_1,
input [15:0] data_in_1,
input [ 7:0] adr_2,
input [15:0] adr_first_reg_tx_2,
input [ 7:0] num_reg_tx_2,
input [15:0] adr_first_reg_rx_2,
input [ 7:0] num_reg_rx_2,
input [15:0] data_in_2,
input transfer_done,
input reset,
output reg [ 7:0] adr,
output reg [15:0] adr_first_reg_tx,
output reg [ 7:0] num_reg_tx,
output reg [15:0] adr_first_reg_rx,
output reg [ 7:0] num_reg_rx,
output reg [15:0] data_out
);
parameter [7:0] number_of_slaves = 2;
reg [7:0] selector = 8'h01;
reg previous_strb = 1'b0;
initial begin
adr = 8'h00;
adr_first_reg_rx = 16'h0000;
adr_first_reg_tx = 16'h0000;
num_reg_rx = 8'h00;
num_reg_tx = 8'h00;
data_out = 16'h0000;
end
always @(posedge clk) begin
if (reset) begin
selector <= 8'h01;
end else begin
previous_strb <= transfer_done;
if (transfer_done && !previous_strb) begin
if (selector == number_of_slaves) selector <= 8'h01;
else selector <= selector + 8'h01;
end else begin
end
case (selector)
1: begin
adr <= adr_1;
adr_first_reg_rx <= adr_first_reg_rx_1;
adr_first_reg_tx <= adr_first_reg_tx_1;
num_reg_rx <= num_reg_rx_1;
num_reg_tx <= num_reg_tx_1;
data_out <= data_in_1;
end
2: begin
adr <= adr_2;
adr_first_reg_rx <= adr_first_reg_rx_2;
adr_first_reg_tx <= adr_first_reg_tx_2;
num_reg_rx <= num_reg_rx_2;
num_reg_tx <= num_reg_tx_2;
data_out <= data_in_2;
end
default: begin
end
endcase
end
end
endmodule
| 7.087801 |
module main (
input clk,
input serdes_in,
output serdes_out,
output serdes_en
);
wire clk;
wire resetn_out;
wire linkerror;
wire linkready;
wire mode_recv;
wire mode_send;
wire [7:0] gpio_i = 0;
wire [7:0] gpio_o;
wire [4:0] in_tdata = 0;
wire [3:0] in_tuser = 0;
wire in_tvalid = 1;
wire in_tlast = 0;
wire in_tready;
wire [4:0] out_tdata;
wire [3:0] out_tuser;
wire out_tvalid;
wire out_tlast;
wire out_tready = 1;
wire serdes_in;
wire serdes_out;
wire serdes_en;
ponylink_slave #(
.SERDES_REG_IN(1),
.SERDES_REG_OUT(1),
.M2S_TDATA_WIDTH(8),
.M2S_TUSER_WIDTH(4),
.S2M_TDATA_WIDTH(8),
.S2M_TUSER_WIDTH(4),
.MASTER_RECV_DELAY(8),
.SLAVE_RECV_DELAY(8),
.MASTER_SEND_DELAY(32),
.SLAVE_SEND_DELAY(32),
.MASTER_PARBITS(1),
.SLAVE_PARBITS(1),
.MASTER_PKTLEN(8),
.SLAVE_PKTLEN(8),
.MASTER_TIMINGS(80'h2e241a100618130e0904),
.SLAVE_TIMINGS(80'h05040302010907050301)
) uut (
.clk (clk),
.resetn_out(resetn_out),
.linkerror (linkerror),
.linkready (linkready),
.mode_recv (mode_recv),
.mode_send (mode_send),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.in_tdata (in_tdata),
.in_tuser (in_tuser),
.in_tvalid (in_tvalid),
.in_tlast (in_tlast),
.in_tready (in_tready),
.out_tdata (out_tdata),
.out_tuser (out_tuser),
.out_tvalid(out_tvalid),
.out_tlast (out_tlast),
.out_tready(out_tready),
.serdes_in (serdes_in),
.serdes_out(serdes_out),
.serdes_en (serdes_en)
);
endmodule
| 7.081372 |
module Slave_spi_v1(clk, SCK, MOSI, SS, DATAIN, start,
Enable, dataout11, dataout22, dataout33, dataout44,);
input clk;
input SCK;
input MOSI;
input SS;
input start;
input [15:0] DATAIN;
output reg Enable = 0;
output reg [15:0] dataout11;
output reg [15:0] dataout22;
output reg [15:0] dataout33;
output reg [15:0] dataout44;
reg [7:0] countbit = 16;
reg [16:0] data = 0;
reg [5:0] countdata = 0;
reg [15:0] datain [3:0];
reg unsigned [9:0] data1 = 0;
reg [5:0] flag_accepted = 0;
reg EnableOut = 0;
reg flag = 0;
reg flagSS = 0;
//always @(posedge clk) begin
// if(SS==1) begin
//end
always @(negedge SCK) begin
if(EnableOut == 1) EnableOut = 0;
if((SS == 0)&(flag == 1)) begin
flag = 0;
countbit = 0;
flagSS = 1;
end
if(SS==1) begin
flag = 1;
end
if(flagSS == 1) begin
if(countbit < 16)begin
// Enable = 0;
data[15-countbit] = MOSI;
end
end
if(countbit == 15)begin
flagSS = 0;
datain[countdata] = data;
// data1 = data1+1;
// if(data1 == 280) data1 = 0;
countdata = countdata + 1;
if(countdata == 4) begin
countdata = 0;
EnableOut = 1;
end
end
if(countbit < 40) countbit = countbit + 1;
if(countbit == 40) begin countdata = 0; end
end
always @(posedge clk) begin
if(start == 1) Enable = 0;
// if(Enable == 1) Enable = 0;
if(EnableOut == 0) flag_accepted = 0;
if((EnableOut == 1)&(flag_accepted < 3)) begin
if(flag_accepted == 1) Enable = 1;
// data1 = data1+1;
// if(data1 == 251) data1 = 0;
dataout11 = datain[0];
dataout22 = datain[1];
dataout33 = datain[2];
dataout44 = datain[3];
// dataout11 = data1;
// dataout22 = data1;
// dataout33 = data1;
// dataout44 = data1;
flag_accepted = flag_accepted + 1;
end
end
endmodule
| 6.515813 |
module Slave_TB ();
reg reset;
reg [7:0] slaveDataToSend; //input
wire [7:0] slaveDataReceived; //output
reg SCLK;
reg CS;
reg MOSI;
wire MISO;
wire [7:0] testcase_slaveData[1: /*TESTCASECOUNT*/4];
wire [7:0] testcase_masterData[1: /*TESTCASECOUNT*/4];
integer i, j;
reg [7:0] masterDataReceived;
localparam PERIOD = 10;
Slave UUT_S (
reset,
slaveDataToSend,
slaveDataReceived,
SCLK,
CS,
MOSI,
MISO
);
assign testcase_slaveData[1] = 8'b00000000; //data send from slave and received in master
assign testcase_slaveData[2] = 8'b11111111;
assign testcase_slaveData[3] = 8'b10000011;
assign testcase_slaveData[4] = 8'b10011010;
assign testcase_masterData[1] = 8'b00000000; //data send from master and received in slave
assign testcase_masterData[2] = 8'b11111111;
assign testcase_masterData[3] = 8'b00100000;
assign testcase_masterData[4] = 8'b01111111;
always #(PERIOD / 2) SCLK = ~SCLK;
initial begin
SCLK = 1;
reset = 1;
#PERIOD reset = 0;
i = 0;
j = 0;
CS = 0;
for (i = 1; i <= 4; i = i + 1) begin
$display("Running test set %d", i);
slaveDataToSend = testcase_slaveData[i];
for (j = 0; j < 8; j = j + 1) begin
#(PERIOD / 2) MOSI = testcase_masterData[i][j];
#(PERIOD / 2) masterDataReceived[j] = MISO;
end
if (slaveDataReceived == testcase_masterData[i]) $display("From Master to Slave : Success");
else begin
$display("From Master to Slave : Failure (Expected: %b, Received: %b)",
testcase_masterData[i], slaveDataReceived);
end
if (masterDataReceived == testcase_slaveData[i]) $display("From Slave to Master : Success");
else begin
$display("From Slave to Master : Failure (Expected: %b, Received: %b)",
testcase_slaveData[i], masterDataReceived);
end
end
$finish;
end
endmodule
| 6.75127 |
module to simplify having a register of variable width and containing independent byte lanes
module register_with_bytelanes (
clk,
reset,
data_in,
write,
byte_enables,
data_out
);
parameter DATA_WIDTH = 32;
input clk;
input reset;
input [DATA_WIDTH-1:0] data_in;
input write;
input [(DATA_WIDTH/8)-1:0] byte_enables;
output reg [DATA_WIDTH-1:0] data_out;
// generating write logic for each group of 8 bits for 'data_out'
generate
genvar LANE;
for(LANE = 0; LANE < (DATA_WIDTH/8); LANE = LANE+1)
begin: register_bytelane_generation
always @ (posedge clk or posedge reset)
begin
if(reset == 1)
begin
data_out[(LANE*8)+7:(LANE*8)] <= 0;
end
else
begin
if((byte_enables[LANE] == 1) & (write == 1))
begin
data_out[(LANE*8)+7:(LANE*8)] <= data_in[(LANE*8)+7:(LANE*8)]; // write to each byte lane with write = 1 and the lane byteenable = 1
end
end
end
end
endgenerate
endmodule
| 8.882302 |
module slbi (
A,
B,
Out
);
input [15:0] A, B;
output wire [15:0] Out;
assign Out = (A << 8) | B;
endmodule
| 6.759902 |
module sld_virtual_jtag (
ir_out,
tdo,
ir_in,
tck,
tdi,
virtual_state_cdr,
virtual_state_cir,
virtual_state_e1dr,
virtual_state_e2dr,
virtual_state_pdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir
);
parameter sld_auto_instance_index = "YES";
parameter sld_instance_index = 0;
parameter sld_ir_width = 1;
input [sld_ir_width-1:0] ir_out;
input tdo;
output [sld_ir_width-1:0] ir_in;
output tck;
output tdi;
output virtual_state_cdr;
output virtual_state_cir;
output virtual_state_e1dr;
output virtual_state_e2dr;
output virtual_state_pdr;
output virtual_state_sdr;
output virtual_state_udr;
output virtual_state_uir;
endmodule
| 6.971215 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
.CI(CIN),
.CO(inst1_CO)
);
assign O = inst0_O;
assign COUT = inst1_CO;
endmodule
| 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1]),
.I1(I1[1]),
.CIN(inst0_COUT),
.O(inst1_O),
.COUT(inst1_COUT)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.821676 |
module SLE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0071)
) inst1 (
.I0(inst0_O[1]),
.I1(I1[1]),
.I2(I0[1]),
.I3(1'b0),
.O (inst1_O)
);
assign O = inst1_O;
endmodule
| 7.129266 |
module main (
input [3:0] J1,
output J3
);
wire inst0_O;
SLE2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module SLE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2_cin1 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h71)
) inst1 (
.I0(inst0_O[1]),
.I1(I1[1]),
.I2(I0[1]),
.O (inst1_O)
);
assign O = inst1_O;
endmodule
| 7.129266 |
module SLE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2_cin1 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h71)
) inst1 (
.I0(inst0_O[1]),
.I1(I1[1]),
.I2(I0[1]),
.O (inst1_O)
);
assign O = inst1_O;
endmodule
| 7.129266 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
.CI(CIN),
.CO(inst1_CO)
);
assign O = inst0_O;
assign COUT = inst1_CO;
endmodule
| 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1]),
.I1(I1[1]),
.CIN(inst0_COUT),
.O(inst1_O),
.COUT(inst1_COUT)
);
FullAdder inst2 (
.I0(I0[2]),
.I1(I1[2]),
.CIN(inst1_COUT),
.O(inst2_O),
.COUT(inst2_COUT)
);
FullAdder inst3 (
.I0(I0[3]),
.I1(I1[3]),
.CIN(inst2_COUT),
.O(inst3_O),
.COUT(inst3_COUT)
);
assign O = {inst3_O, inst2_O, inst1_O, inst0_O};
endmodule
| 7.507677 |
module SLE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0071)
) inst1 (
.I0(inst0_O[3]),
.I1(I1[3]),
.I2(I0[3]),
.I3(1'b0),
.O (inst1_O)
);
assign O = inst1_O;
endmodule
| 7.225341 |
module main (
input [7:0] J1,
output J3
);
wire inst0_O;
SLE4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module SLE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4_cin1 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h71)
) inst1 (
.I0(inst0_O[3]),
.I1(I1[3]),
.I2(I0[3]),
.O (inst1_O)
);
assign O = inst1_O;
endmodule
| 7.225341 |
module main (
input [7:0] SWITCH,
output LED
);
wire inst0_O;
SLE4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module SLE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4_cin1 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h71)
) inst1 (
.I0(inst0_O[3]),
.I1(I1[3]),
.I2(I0[3]),
.O (inst1_O)
);
assign O = inst1_O;
endmodule
| 7.225341 |
module sled (
input wire clock,
output wire [7:0] segs,
output wire [3:0] digs
);
// Variavel com os dados a serem exibidos no display de 7 segmentos
reg [ 3:0] disp_dat;
reg [ 7:0] segs_dsp;
// Contador:
reg [36:0] count;
// Ligar os 4 digitos do display
assign digs = 4'b0000;
// --> Bloco always executado nas bordas de subida do clock:
always @(posedge clock) begin
// Incrementar 'count'
count = count + 1'b1;
end
// --> Bloco always executado quand o 25o bit de 'count' for 1
always @(count[24]) begin
disp_dat = {count[28:25]};
end
// --> Bloco 'always' executado a cada mudanca em 'disp_dat'
always @(disp_dat) begin
case (disp_dat)
4'h0: segs_dsp = 8'b11000000;
4'h1: segs_dsp = 8'b11111001;
4'h2: segs_dsp = 8'b10100100;
4'h3: segs_dsp = 8'b10110000;
4'h4: segs_dsp = 8'b10011001;
4'h5: segs_dsp = 8'b10010010;
4'h6: segs_dsp = 8'b10000010;
4'h7: segs_dsp = 8'b11111000;
4'h8: segs_dsp = 8'b10000000;
4'h9: segs_dsp = 8'b10010000;
4'ha: segs_dsp = 8'b10001000;
4'hb: segs_dsp = 8'b10000011;
4'hc: segs_dsp = 8'b11000110;
4'hd: segs_dsp = 8'b10100001;
4'he: segs_dsp = 8'b10000110;
4'hf: segs_dsp = 8'b10001110;
endcase
end
// --> Atribuicao aos segmentos do display
assign segs = segs_dsp;
endmodule
| 6.521856 |
module sleep_or_not (
clk,
ps_data,
tosleep
);
input clk, ps_data;
output reg tosleep;
parameter [31:0] lim = 100000000; // default 10000000
integer cnt;
initial begin
cnt = 0;
tosleep = 0;
end
always @(posedge clk) begin
if (ps_data == 0) begin
cnt <= 0;
tosleep <= 0;
end else begin
if (tosleep == 1 || cnt == lim) begin
cnt <= lim;
tosleep <= 1;
end else begin
cnt <= cnt + 1;
tosleep <= 0;
end
end
end
endmodule
| 6.736378 |
module sleep_unit #(
parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
) (
HCLK,
HRESETn,
PADDR,
PWDATA,
PWRITE,
PSEL,
PENABLE,
PRDATA,
PREADY,
PSLVERR,
irq_i,
event_i,
core_busy_i,
fetch_en_o,
clk_gate_core_o
);
//parameter APB_ADDR_WIDTH = 12;
input wire HCLK;
input wire HRESETn;
input wire [APB_ADDR_WIDTH - 1:0] PADDR;
input wire [31:0] PWDATA;
input wire PWRITE;
input wire PSEL;
input wire PENABLE;
output reg [31:0] PRDATA;
output wire PREADY;
output wire PSLVERR;
input wire irq_i;
input wire event_i;
input wire core_busy_i;
output reg fetch_en_o;
output reg clk_gate_core_o;
reg [1:0] SLEEP_STATE_N;
reg [1:0] SLEEP_STATE_Q;
reg [63:0] regs_q;
reg [63:0] regs_n;
reg core_sleeping_int;
always @(*) begin
SLEEP_STATE_N = SLEEP_STATE_Q;
case (SLEEP_STATE_Q)
2'd0: if (regs_q[32]) if (~event_i) SLEEP_STATE_N = 2'd1;
2'd1:
if (event_i) SLEEP_STATE_N = 2'd0;
else if (~core_busy_i && ~irq_i) SLEEP_STATE_N = 2'd2;
2'd2:
if (event_i) SLEEP_STATE_N = 2'd0;
else if (irq_i) SLEEP_STATE_N = 2'd1;
default: SLEEP_STATE_N = 2'd0;
endcase
end
always @(*) begin
fetch_en_o = 1'b1;
clk_gate_core_o = 1'b1;
core_sleeping_int = 1'b0;
case (SLEEP_STATE_Q)
2'd0: if (regs_q[32] && ~event_i) fetch_en_o = 1'b0;
else fetch_en_o = 1'b1;
2'd1: fetch_en_o = 1'b0;
2'd2: begin
clk_gate_core_o = (event_i ? 1'b1 : 1'b0);
core_sleeping_int = 1'b1;
fetch_en_o = 1'b0;
end
default: begin
fetch_en_o = 1'b1;
clk_gate_core_o = 1'b1;
core_sleeping_int = 1'b0;
end
endcase
end
wire [0:0] register_adr;
assign register_adr = PADDR[3:2];
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
always @(*) begin
regs_n = regs_q;
regs_n[1'b0] = core_sleeping_int;
if (core_sleeping_int || event_i) regs_n[32] = 1'b0;
if ((PSEL && PENABLE) && PWRITE)
case (register_adr)
2'b00: regs_n[32+:32] = PWDATA;
endcase
end
always @(*) begin
PRDATA = 'b0;
if ((PSEL && PENABLE) && !PWRITE)
case (register_adr)
2'b00: PRDATA = regs_q[32+:32];
2'b01: PRDATA = regs_q[0+:32];
default: PRDATA = 'b0;
endcase
end
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
SLEEP_STATE_Q <= 2'd0;
regs_q <= {2{32'b00000000000000000000000000000000}};
end else begin
SLEEP_STATE_Q <= SLEEP_STATE_N;
regs_q <= regs_n;
end
endmodule
| 7.876149 |
module sleft (
input [25:0] shiftleft,
output reg [25:0] shifted
);
wire [25:0] shiftl = shiftleft << 2;
always @(*) begin
shifted = shiftl;
end
endmodule
| 7.024926 |
module slew (
clk,
in_set,
enable,
wrap,
tick,
out_val,
motion
);
parameter dw = 16;
input clk;
input [dw-1:0] in_set;
input enable; // when zero, in_set propagates directly to out_val
input wrap; // set to allow wrapping, as when value represents phase
input tick; // step out_val towards in_set
output [dw-1:0] out_val;
output motion; // output is slewing towards set point
reg [dw-1:0] current = 0;
reg [ dw:0] diff = 0;
reg match = 0, dir = 0;
wire [dw-1:0] next = match ? current : dir ? current - 1 : current + 1;
always @(posedge clk) begin
diff <= in_set - current;
match <= diff == 0;
dir <= wrap ? diff[dw-1] : diff[dw];
if (tick) current <= enable ? next : in_set;
end
assign out_val = current;
assign motion = ~match;
endmodule
| 7.154021 |
module slew_array (
clk,
h_write,
h_addr,
h_data,
enable,
wrap,
trig,
outv
);
parameter dw = 18;
parameter aw = 3;
input clk; // timespec 7.8 ns
input h_write;
input [aw-1:0] h_addr;
input signed [dw-1:0] h_data;
input enable; // when zero, values propagate directly to output
input wrap; // set to allow wrapping, as when value represents phase
input trig; // start the flow of 2^aw results
output signed [dw-1:0] outv;
reg [aw-1:0] count = 0, count1 = 0, count2 = 0, count3 = 0;
reg run = 0, run1 = 0, run2 = 0, run3 = 0;
always @(posedge clk) begin
count <= count + (trig | run);
count1 <= count;
count2 <= count1;
count3 <= count2;
run <= trig | (run & ~(&count));
run1 <= run | trig;
run2 <= run1;
run3 <= run2;
end
wire signed [dw-1:0] goal, oldv, nextv;
dpram #(
.dw(dw),
.aw(aw)
) hbuf (
.clka (clk),
.clkb (clk),
.addra(h_addr),
.dina (h_data),
.wena (h_write),
.addrb(count),
.doutb(goal)
);
dpram #(
.dw(dw),
.aw(aw)
) state (
.clka (clk),
.clkb (clk),
.addra(count3),
.dina (nextv),
.wena (run3),
.addrb(count),
.doutb(oldv)
);
reg signed [dw-1:0] goal1 = 0, goal2 = 0, oldv1 = 0, oldv2 = 0;
reg signed [dw:0] diff = 0;
reg match = 0, dir = 0;
assign nextv = enable ? (match ? oldv2 : dir ? oldv2 - 1 : oldv2 + 1) : goal2;
always @(posedge clk) begin
// stage 1
diff <= goal - oldv;
goal1 <= goal;
oldv1 <= oldv;
// stage 2
match <= diff == 0;
dir <= wrap ? diff[dw-1] : diff[dw];
oldv2 <= oldv1;
goal2 <= goal1;
end
assign outv = oldv;
endmodule
| 7.402725 |
module slew_xarray #(
parameter dw = 18
) (
input clk,
input enable, // when zero, just passes through
input signed [dw-1:0] setmp, // from localbus
output signed [dw-1:0] setmp_l, // to application, slew-rate-limited
input setmp_addr,
input step, // can wire to 1 for full-speed slew
output [1:0] motion
);
// Note that mp_proc does
// assign setmp_addr = {1'b0, ~state[0]};
// We "know" that, and only take in the lsb.
reg [dw-1:0] current = 0, prev = 0;
reg [dw:0] diff = 0;
reg match = 1, enable1 = 0;
reg motionm = 0, motionp = 0;
wire wrap = setmp_addr; // verified in simulation
wire dir = wrap ? diff[dw-1] : diff[dw];
wire step1 = enable & step & ~match;
always @(posedge clk) begin
diff <= setmp - current;
match <= setmp == current;
// following line should synthesize to a single bank of addsub
current <= dir ? prev - step1 : prev + step1;
prev <= enable ? current : setmp;
enable1 <= enable;
if (~setmp_addr) motionm <= ~match;
if (setmp_addr) motionp <= ~match;
end
assign setmp_l = current;
assign motion = {motionm, motionp};
endmodule
| 8.89578 |
module slew_xarray_tb;
reg clk, fail = 0;
integer cc;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("slew_xarray.vcd");
$dumpvars(5, slew_xarray_tb);
end
for (cc = 0; cc < 400; cc = cc + 1) begin
clk = 0;
#5;
clk = 1;
#5;
end
if (fail) begin
$display("FAIL"); // tell Makefile that we broke
$stop(0);
end else begin
$display("PASS");
$finish(0);
end
end
// Configure for 5-bit values, range 0 to 31.
// Speeds up the simulation by a factor of 8192.
reg [4:0] setm = 0, setp = 0;
reg enable = 0;
reg [1:0] state = 0;
always @(posedge clk) state <= state + 1;
wire setmp_addr = state[0]; // will be provided by mp_proc
wire step = state[1]; // half-speed
// Test stimulus
always @(posedge clk) begin
if (cc == 3) setm <= 15;
if (cc == 8) enable <= 1;
if (cc == 14) setm <= 10;
if (cc == 45) setm <= 30; // increase because no wrap
if (cc == 140) setm <= 10;
if (cc == 180) setp <= 10;
if (cc == 240) setp <= 30; // decrease because wrap
if (cc == 300) setp <= 20;
if (cc == 350) setp <= 10;
end
wire [4:0] setmp = setmp_addr ? setm : setp;
wire [4:0] setmp_l;
wire [1:0] motion;
slew_xarray #(
.dw(5)
) dut (
.clk(clk),
.enable(enable),
.setmp(setmp),
.setmp_addr(setmp_addr),
.step(step),
.setmp_l(setmp_l),
.motion(motion)
);
// These signals definitely help to make sense of the timing diagram
reg [4:0] setm_l = 0, setp_l = 0;
always @(posedge clk) begin
if (setmp_addr) setm_l <= setmp_l;
if (~setmp_addr) setp_l <= setmp_l;
end
// Simple check that the output never moves more than a single step at a time
wire signed [5:0] setm_d = setmp_l - setm_l;
wire signed [4:0] setp_d = setmp_l - setp_l;
reg setm_f = 0, setp_f = 0; // faults
always @(posedge clk) begin
if (setmp_addr) setm_f <= enable && (setm_d > 1 || setm_d < -1);
if (~setmp_addr) setp_f <= enable && (setp_d > 1 || setp_d < -1);
if (setm_f | setp_f) fail = 1;
end
endmodule
| 8.241514 |
module slicer (
input wire signed [17:0] reference_level,
input wire signed [17:0] decision_variable,
output reg [1:0] symbol
);
always @*
if (decision_variable > reference_level) symbol = 2'b10;
else if (decision_variable > 0) symbol = 2'b11;
else if (decision_variable > -reference_level) symbol = 2'b01;
else symbol = 2'b00;
endmodule
| 8.375179 |
module slice_fixed (
input clk,
input GSR,
input CE,
input SR,
input [6:1] A_61,
input [6:1] B_61,
input [6:1] C_61,
input [6:1] D_61,
input AX,
input BX,
input CX,
input DX,
output reg A,
output reg B,
output reg C,
output reg D,
output reg AQ,
output reg BQ,
output reg CQ,
output reg DQ,
output reg AMUX,
output reg BMUX,
output reg CMUX,
output reg DMUX,
input CIN,
output reg COUT,
input config_clk,
input config_in,
input config_en,
output config_out
);
////////////////////////////
// parameters
////////////////////////////
parameter param_mode_QSlice_A = 2'b00;
parameter param_mode_QSlice_B = 2'b00;
parameter param_mode_QSlice_C = 2'b00;
parameter param_mode_QSlice_D = 2'b00;
parameter param_mux_optimizer = 1'b0;
// wires and regs
reg [6:1] A_61_reg;
reg [6:1] B_61_reg;
reg [6:1] C_61_reg;
reg [6:1] D_61_reg;
reg AX_reg;
reg BX_reg;
reg CX_reg;
reg DX_reg;
wire A_temp;
wire B_temp;
wire C_temp;
wire D_temp;
wire AQ_temp;
wire BQ_temp;
wire CQ_temp;
wire DQ_temp;
wire AMUX_temp;
wire BMUX_temp;
wire CMUX_temp;
wire DMUX_temp;
reg CIN_reg;
wire COUT_temp;
always @(posedge clk) begin
A_61_reg <= A_61;
B_61_reg <= B_61;
C_61_reg <= C_61;
D_61_reg <= D_61;
AX_reg <= AX;
BX_reg <= BX;
CX_reg <= CX;
DX_reg <= DX;
A <= A_temp;
B <= B_temp;
C <= C_temp;
D <= D_temp;
AQ <= AQ_temp;
BQ <= BQ_temp;
CQ <= CQ_temp;
DQ <= DQ_temp;
AMUX <= AMUX_temp;
BMUX <= BMUX_temp;
CMUX <= CMUX_temp;
DMUX <= DMUX_temp;
CIN_reg <= CIN;
COUT <= COUT_temp;
end
defparam slice_inst.param_mode_QSlice_A = param_mode_QSlice_A;
defparam slice_inst.param_mode_QSlice_B = param_mode_QSlice_B;
defparam slice_inst.param_mode_QSlice_C = param_mode_QSlice_C;
defparam slice_inst.param_mode_QSlice_D = param_mode_QSlice_D;
defparam slice_inst.param_mux_optimizer = param_mux_optimizer;
slice slice_inst (
.clk(clk),
.GSR(GSR),
.CE (CE),
.SR (SR),
.A_61(A_61_reg),
.B_61(B_61_reg),
.C_61(C_61_reg),
.D_61(D_61_reg),
.AX(AX_reg),
.BX(BX_reg),
.CX(CX_reg),
.DX(DX_reg),
.A(A_temp),
.B(B_temp),
.C(C_temp),
.D(D_temp),
.AQ(AQ_temp),
.BQ(BQ_temp),
.CQ(CQ_temp),
.DQ(DQ_temp),
.AMUX(AMUX_temp),
.BMUX(BMUX_temp),
.CMUX(CMUX_temp),
.DMUX(DMUX_temp),
.CIN (CIN_reg),
.COUT(COUT_temp),
.config_clk(config_clk),
.config_in (config_in),
.config_en (config_en),
.config_out(config_out)
);
endmodule
| 6.681078 |
module dsp_slice_fp32 (
clk,
enable,
clr,
funct,
chainin,
accumulate,
ax,
ay,
az,
chainout,
resulta_flopped
);
input clk;
input enable;
input clr;
input [3:0] funct;
input [31:0] chainin;
input accumulate;
input [31:0] ax;
input [31:0] ay;
input [31:0] az;
output [31:0] chainout;
output [31:0] resulta_flopped;
reg [31:0] ax_flopped;
reg [31:0] ay_flopped;
reg [31:0] az_flopped;
reg accumulate_flopped_1;
reg [3:0] funct_flopped;
always @(posedge clk) begin
if (clr) begin
ax_flopped <= 0;
ay_flopped <= 0;
az_flopped <= 0;
accumulate_flopped_1 <= 0;
funct_flopped <= 0;
end else begin
ax_flopped <= ax;
ay_flopped <= ay;
az_flopped <= az;
accumulate_flopped_1 <= accumulate;
funct_flopped <= funct;
end
end
wire mux1_select;
wire [1:0] mux2_select;
wire mux3_select;
wire mux5_select;
assign mux1_select = (funct_flopped[1] & funct_flopped[0] ) | (funct_flopped[3] & ~funct_flopped[1]) | (funct_flopped[2] & ~funct_flopped[0] );
assign mux2_select[1] = ( ~funct_flopped[3] & ~funct_flopped[2] & ~funct_flopped[1]) | ( ~funct_flopped[3] & ~funct_flopped[2] & ~funct_flopped[0]) | ( funct_flopped[3] & funct_flopped[1] & funct_flopped[0]);
assign mux2_select[0] = funct_flopped[2] | ( funct_flopped[3] & ~funct_flopped[1]) | (funct_flopped[1] & funct_flopped [0]);
assign mux3_select = (funct_flopped[3] & ~funct_flopped[1]) + (funct_flopped[2] & funct_flopped[1] & funct_flopped[0]);
assign mux5_select = funct_flopped[3] | (~funct_flopped[2] & funct_flopped[0]) | (funct_flopped[2] & ~funct_flopped[0]) | (funct_flopped[2] & ~funct_flopped[1]) ;
wire [31:0] mult_ip_a;
wire [31:0] mult_ip_b;
wire [31:0] mult_out;
reg [31:0] mult_out_flopped_1;
reg [31:0] mult_out_flopped_2;
wire [ 4:0] mult_flags;
assign mult_ip_a = ay_flopped;
assign mult_ip_b = az_flopped;
FPMult_single Multiplier (
clk,
clr,
mult_ip_a,
mult_ip_b,
mult_out,
mult_flags
);
//Two flop stages after the output of the multiplier
always @(posedge clk) begin
if (clr) begin
mult_out_flopped_1 <= 0;
mult_out_flopped_2 <= 0;
end else begin
mult_out_flopped_1 <= mult_out;
mult_out_flopped_2 <= mult_out_flopped_1;
end
end
wire [31:0] adder_ip_a;
wire [31:0] adder_ip_b;
wire [31:0] mux1_out;
reg [31:0] mux1_out_flopped_1;
reg [31:0] mux1_out_flopped_2;
reg [31:0] mux1_out_flopped_3;
wire [31:0] mux2_out;
wire [31:0] mux4_out;
wire [31:0] adder_out;
wire [4:0] adder_flags;
wire operation;
assign operation = ( ~funct_flopped[3] & ~funct_flopped[2] & ~funct_flopped[0]) | ( ~funct_flopped[3] & ~funct_flopped[1] & ~funct_flopped[0]) | ( funct_flopped[3] & ~funct_flopped[1] & funct_flopped[0]);
assign mux1_out = mux1_select ? chainin : ax_flopped;
//Three flop stages at the input of the adder
always @(posedge clk) begin
if (clr) begin
mux1_out_flopped_1 <= 0;
mux1_out_flopped_2 <= 0;
mux1_out_flopped_3 <= 0;
end else begin
mux1_out_flopped_1 <= mux1_out;
mux1_out_flopped_2 <= mux1_out_flopped_1;
mux1_out_flopped_3 <= mux1_out_flopped_2;
end
end
assign mux4_out = accumulate ? resulta_flopped : mux1_out_flopped_3;
assign mux2_out= mux2_select[1] ? ( mux2_select[0] ? ax_flopped : ay_flopped) : ( mux2_select[0] ? mult_out_flopped_2 : 32'd0);
assign adder_ip_a = mux4_out;
assign adder_ip_b = mux2_out;
FPAddSub_single Adder (
clk,
clr,
adder_ip_a,
adder_ip_b,
operation,
adder_out,
adder_flags
);
wire [31:0] mux3_out;
assign mux3_out = mux3_select ? ax_flopped : resulta_flopped;
assign chainout = mux3_out;
wire [31:0] resulta;
wire [31:0] mux5_out;
assign mux5_out = mux5_select ? adder_out : mult_out_flopped_2;
assign resulta = mux5_out;
reg [31:0] resulta_flopped_1;
always @(posedge clk) begin
if (clr) begin
resulta_flopped_1 <= 0;
end else begin
resulta_flopped_1 <= resulta;
end
end
assign resulta_flopped = resulta_flopped_1;
endmodule
| 6.706938 |
module //
// Date: Nov 2011 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: This only tests the basic functionality of the module, more //
// comprehensive testing is done in the python test file //
// //
//============================================================================//
module slice_tb;
//===================
// local parameters
//==================
localparam LOCAL_DATA_WIDTH = `ifdef DATA_WIDTH `DATA_WIDTH `else 8 `endif;
//=============
// local regs
//=============
reg clk;
reg[LOCAL_DATA_WIDTH-1:0] data_in;
//==============
// local wires
//==============
wire [5-1:0] data_out;
//=====================================
// instance, "(d)esign (u)nder (t)est"
//=====================================
slice # (
.INPUT_DATA_WIDTH (`ifdef INPUT_DATA_WIDTH `INPUT_DATA_WIDTH `else 8 `endif),
.OFFSET_REL_TO_MSB (`ifdef OFFSET_REL_TO_MSB `OFFSET_REL_TO_MSB `else 1 `endif),
.OFFSET_1 (`ifdef OFFSET_1 `OFFSET_1 `else 1 `endif),
.OFFSET_2 (`ifdef OFFSET_2 `OFFSET_2 `else 5 `endif)
) dut (
.clk(clk),
.data_in(data_in),
.data_out(data_out)
);
//=============
// initialize
//=============
initial begin
clk = 0;
data_in = 8'b00001111;
end
//====================
// simulate the clock
//====================
always #1 begin
clk = ~clk;
end
//===============
// print output
//===============
always @(posedge clk) $display(data_out);
//===================
// finish condition
//===================
initial #5 $finish;
endmodule
| 8.238592 |
module SLICE_WO #(
parameter win = 64,
parameter uout = 31,
parameter lout = 18
) (
input clk_i,
input [ win-1:0] sig_i,
output [uout-lout:0] sig_o
);
reg [uout-lout:0] sig;
always @(posedge clk_i) begin
if ({sig_i[win-1], |sig_i[win-3:uout]} == 2'b01) //positive overflow
sig <= 14'h1FFF;
else if ({sig_i[win-1], &sig_i[win-2:uout]} == 2'b10) //negative overflow
sig <= 14'h2000;
else sig <= sig_i[uout:lout];
end
assign sig_o = sig;
endmodule
| 7.835776 |
module SLICE_WO_32 #(
parameter win = 64,
parameter uout = 31,
parameter lout = 0
) (
input clk_i,
input [ win-1:0] sig_i,
output [uout-lout:0] sig_o
);
reg [uout-lout:0] sig;
always @(posedge clk_i) begin
if ({sig_i[win-1], |sig_i[win-3:uout]} == 2'b01) //positive overflow
sig <= 32'h7FFFFFFF;
else if ({sig_i[win-1], &sig_i[win-2:uout]} == 2'b10) //negative overflow
sig <= 32'h80000000;
else sig <= sig_i[uout:lout];
end
assign sig_o = sig;
endmodule
| 8.172968 |
module slider (
addrP,
lastPixelF,
trig,
M,
N,
clk,
rst
);
// Parameters
parameter ADDR_WIDTH = 8, WINDOW_N = 2;
// Outputs
output reg [ADDR_WIDTH - 1 : 0] addrP;
output reg lastPixelF;
// Inputs
input wire trig, clk, rst;
input wire [15 : 0] M, N;
// Registers
reg [15 : 0] i, j;
reg lastPixel;
always @(posedge rst) begin
i <= WINDOW_N;
j <= WINDOW_N;
lastPixelF <= 0;
lastPixel <= 0;
end // always @(posedge rst)
always @(posedge trig) begin
#5 addrP <= i * N + j;
if (lastPixel) lastPixelF = 1;
j <= j + 1;
if (j == N - WINDOW_N - 1) begin
j <= WINDOW_N;
i <= i + 1;
if (i == M - WINDOW_N - 1) lastPixel <= 1;
end // f(j == N)
end // always @(posedge trig)
endmodule
| 7.928406 |
module SlideSwitches (
input CLK_50, //Defining the clock as an input (The onboard clock of the Kiwi is 50MHz)
input [3:0] SW, //Defining the 4 built in slide switches on the Kiwi.
output [7:0] LED //Defining the 8 built in LEDs on the Kiwi.
//Note: these definitions were made using the μLab Kiwi Project Generator.
);
assign LED[7:4] = 4'b1111; //Turn off the unused LEDs (1 means that the led is OFF)
assign LED[3:0] = SW[3:0]; //Assign the LEDs in position 0-3 (4 in total) to the 4 slide switches.
endmodule
| 7.776276 |
module divfreq (
input CLk,
output reg CLk_div
);
reg [24:0] number;
always @(posedge CLk) begin
if (number > 50000) begin
number <= 25'b0;
CLk_div <= ~CLk_div;
end else number <= number + 1'b1;
end
endmodule
| 6.846501 |
module divfreq2 (
input CLk,
output reg CLk_div2
);
reg [24:0] number2;
always @(posedge CLk) begin
if (number2 > 3000000) begin
number2 <= 25'b0;
CLk_div2 <= ~CLk_div2;
end else number2 <= number2 + 1'b1;
end
endmodule
| 6.675631 |
module divfreq3 (
input CLk,
output reg CLk_div3
);
reg [50:0] number3;
always @(posedge CLk) begin
if (number3 > 5000000) begin
number3 <= 25'b0;
CLk_div3 <= ~CLk_div3;
end else number3 <= number3 + 1'b1;
end
endmodule
| 6.801986 |
module divfreq4 (
input CLk,
output reg CLk_div4
);
reg [50:0] number4;
always @(posedge CLk) begin
if (number4 > 75000000) begin
number4 <= 25'b0;
CLk_div4 <= ~CLk_div4;
end else number4 <= number4 + 1'b1;
end
endmodule
| 6.77823 |
module slide_window_conv #(
parameter In_d_W = 8,
In_Add_W = 4,
R_N = 5,
C_N = 5,
R_F = 3,
C_F = 3,
P = 0,
S = 1,
Timeperiod = 10
) (
input clk,
clk_en,
rst,
clr,
en_wr,
en_rd,
wr,
en_MAC,
en_MAC_out, //wr=1 (Write), wr=0 (Read)
input [(C_N*R_N*In_d_W)-1:0] N, // [199:0] N
input [(C_F*R_F*In_d_W)-1:0] F, // [71:0] F
output [(((2*In_d_W)+2)*(((R_N+(2*P)-R_F)/S)+1)*(((C_N+(2*P)-C_F)/S)+1))-1:0] Y // [161:0] Y
);
parameter R_O = (((R_N + (2 * P) - R_F) / S) + 1); //3
parameter C_O = (((C_N + (2 * P) - C_F) / S) + 1); //3
parameter Out_d_W = ((2 * In_d_W) + 2); //18
//wire [(In_d_W*R_N)-1:0] X [0:(C_N-1)]; // [39:0] X [0:4]
wire [(In_d_W*R_O)-1:0] Z[0:((R_O*C_N)-1)]; // [23:0] Z [0:14]
wire [(In_d_W*R_F*C_F)-1:0] A[0:(R_O*C_O)-1]; // [71:0] A [0:8]
wire [Out_d_W-1:0] W[0:(R_O*C_O)-1]; // [17:0] W [0:8]
generate
genvar i, j;
for (
i = 0; i < C_N; i = i + 1
) //i<5
begin
for (
j = (R_O * i); j < (R_O + (R_O * i)); j = j + 1
) // j=3*i; j<3+3i; j=j+1
begin
assign Z[j] = N[((R_O*In_d_W)+(In_d_W*(j+(i*(R_F-1))))-1):(In_d_W*(j+(i*(R_F-1))))]; // N[(3*8)+(8*(j+(i*2)))-1 : 8*(j+(i*2))]
end
end
endgenerate
generate
genvar n, p;
for (
n = 0; n < (R_O * C_O); n = n + 1
) // n<9
begin
for (
p = 0; p < (R_F * C_F * In_d_W); p = p + (R_F * In_d_W)
) // p<72; p=p+24
begin
assign A[n][(p+(R_F*In_d_W)-1):p]=Z[n+(R_O*p/(R_F*In_d_W))]; // A[n][p+24-1:p]=Z[n+(3*p/24)]
end
end
endgenerate
generate
genvar t;
for (
t = 0; t < (R_O * C_O); t = t + 1
) //t<9
begin
assign Y[(Out_d_W+(t*Out_d_W))-1 : (t*Out_d_W)] = W[t]; // Y[18+(t*18)-1:(t*18)]=W[t]
end
endgenerate
generate
genvar r;
for (
r = 0; r < (R_O * C_O); r = r + 1
) // r<9
begin
conv #(In_d_W, R_F, C_F, In_Add_W, Timeperiod) CV (
.clk(clk),
.clk_en(clk_en),
.rst(rst),
.clr(clr),
.en_wr(en_wr),
.en_rd(en_rd),
.wr(wr),
.en_MAC(en_MAC),
.en_MAC_out(en_MAC_out),
.A(A[r]),
.B(F),
.Y(W[r])
);
end
endgenerate
endmodule
| 6.964635 |
module implements a sliding average logic.
* With every trigger cycle the average of the previous output value
* and the sampled value is calculated:
* new_output <= (previous_output + sample_value)/2
*/
module average_sliding
#(
parameter bitwidth_sample = 12,
parameter initial_accumulator_value = 0
)
(
// With every trigger cycle a new averaged value is calculated
input trigger,
// With the rising edge, the accumulator is set to it's initial value
input reset,
input[bitwidth_sample-1:0] sample_value,
output[bitwidth_sample-1:0] averaged_value
);
reg[bitwidth_sample:0] accumulator = initial_accumulator_value;
assign averaged_value[bitwidth_sample-1:0] = accumulator[bitwidth_sample-1:0];
// Add
wire[bitwidth_sample:0] sum;
assign sum = accumulator[bitwidth_sample:0] + sample_value;
always @(posedge trigger or posedge reset)
begin
if (reset == 1)
begin
// Reset accumulator
accumulator[bitwidth_sample:0] <= initial_accumulator_value;
end
else begin
// Divide by two
accumulator[bitwidth_sample-1:0] <= sum[bitwidth_sample:1];
end
end
endmodule
| 6.904081 |
module concatenates a preconfigured number of
* sliding average modules in an attempt to achieve a more noise-free signal.
*/
module average_sliding_iterative
#(
parameter bitwidth_sample = 12,
parameter initial_accumulator_value = 0,
parameter iteration_count = 3
)
(
// With every trigger cycle a new averaged value is calculated
input trigger,
// With the rising edge, the accumulator is set to it's initial value
input reset,
input [bitwidth_sample-1:0] sample_value,
output [bitwidth_sample-1:0] averaged_value
);
// Define all the wires connecting the sliding average modules.
wire[bitwidth_sample-1:0] intermediate_value[0:iteration_count+1];
// The input bus of the first sliding average module is this module's input.
assign intermediate_value[0][bitwidth_sample-1:0] = sample_value[bitwidth_sample-1:0];
// The last bus is the output value.
assign averaged_value = intermediate_value[iteration_count][bitwidth_sample-1:0];
genvar i;
generate
for (i=0; i<iteration_count; i=i+1)
begin
average_sliding #(
.bitwidth_sample(bitwidth_sample),
.initial_accumulator_value(initial_accumulator_value)
) average (
.reset (reset),
.trigger (trigger),
.sample_value (intermediate_value[i] [bitwidth_sample-1:0]),
.averaged_value (intermediate_value[i+1] [bitwidth_sample-1:0])
);
end
endgenerate
endmodule
| 7.734569 |
module sliding_window (
input wire clk,
input wire enable,
input wire enable_process,
input wire [15:0] wav_input,
input wire [31:0] idx,
output reg [(2**16)-1:0] window
);
parameter sample_size = 2 ** 12;
parameter width = 16;
parameter file_size = 4365900;
reg [file_size*width-1:0] wav_file = 0;
integer count = 0;
always @(posedge clk) begin
if (enable == 1'b1) begin
wav_file[idx*width+:width] = wav_input;
end
if (enable_process == 1'b1) begin
window = wav_file[count*width+:sample_size*width];
count = count + 1;
end
end
endmodule
| 8.418455 |
module slink_apb_driver #(
parameter ADDR_WIDTH = 8,
parameter CLK_PER_NS = 10
) (
input wire apb_clk,
input wire apb_reset,
output reg [ADDR_WIDTH-1:0] apb_paddr,
output reg apb_pwrite,
output reg apb_psel,
output reg apb_penable,
output reg [ 31:0] apb_pwdata,
input wire [ 31:0] apb_prdata,
input wire apb_pready,
input wire apb_pslverr
);
`include "slink_msg.v"
always @(posedge apb_reset) begin
apb_paddr <= 0;
apb_pwrite <= 0;
apb_psel <= 0;
apb_penable <= 0;
apb_pwdata <= 0;
end
task write;
input [ADDR_WIDTH-1:0] addr;
input [31:0] wdata;
begin
@(posedge apb_clk);
apb_paddr <= addr;
apb_pwdata <= wdata;
apb_pwrite <= 1;
apb_psel <= 1;
@(posedge apb_clk);
apb_penable <= 1;
@(posedge apb_clk);
apb_psel <= 0;
apb_penable <= 0;
apb_pwrite <= 0;
//$display("REG_WRITE: 32'h%8h to %4h", wdata, addr);
//`sim_info($display("apb_write: 32'h%8h to %4h", wdata, addr))
end
endtask
task read(input bit [ADDR_WIDTH-1:0] addr, output bit [31:0] rdata);
@(posedge apb_clk);
apb_paddr <= addr;
apb_psel <= 1;
@(posedge apb_clk);
apb_penable <= 1;
@(posedge apb_clk);
apb_psel <= 0;
apb_penable <= 0;
rdata = apb_prdata; //ensure non-blocking
//`sim_info($display("apb_read: 32'h%8h from %4h", rdata, addr))
endtask
endmodule
| 6.987987 |
module slink_app_monitor #(
parameter APP_DATA_WIDTH = 32
) (
input wire link_clk,
input wire link_reset,
input wire rx_sop,
input wire [ 7:0] rx_data_id,
input wire [ 15:0] rx_word_count,
input wire [APP_DATA_WIDTH-1:0] rx_app_data,
input wire rx_valid,
input wire rx_crc_corrupted
);
`include "slink_msg.v"
bit disable_monitor = 0;
bit [7:0] pkt[$];
bit [7:0] pkt_array[$];
task addByte(bit [7:0] b);
`sim_debug($display("Pushing back byte %2h", b))
pkt_array.push_back(b);
endtask
task printBytes;
foreach (pkt_array[i]) begin
`sim_debug($display("%0d: %2h", i, pkt_array[i]))
end
endtask
initial begin
//Monitor Fork
fork
monitorIntf;
join_none
end
task monitorIntf;
bit [ 7:0] b;
bit [15:0] wc;
int remaining_bytes;
forever begin
@(posedge link_clk);
if (~disable_monitor) begin
if (rx_sop && rx_valid) begin
//SOP
if (rx_data_id <= 'h2f) begin
//Short Packet
`sim_info($display("Short packet Received ID: %2h WC: %4h", rx_data_id, rx_word_count))
checkByte(rx_data_id);
checkByte(rx_word_count[7:0]);
checkByte(rx_word_count[15:8]);
end else begin
//Long Packet
checkByte(rx_data_id);
checkByte(rx_word_count[7:0]);
checkByte(rx_word_count[15:8]);
`sim_info($display("Long packet Received ID: %2h WC: %4h", rx_data_id, rx_word_count))
wc = rx_word_count;
remaining_bytes = wc;
for (int i = 0; i < APP_DATA_WIDTH / 8; i++) begin
if (remaining_bytes) begin
checkByte(rx_app_data[i*8+:8]);
remaining_bytes--;
end
end
end
end else if (~rx_sop && rx_valid) begin
//Rest of long data
for (int i = 0; i < APP_DATA_WIDTH / 8; i++) begin
if (remaining_bytes) begin
checkByte(rx_app_data[i*8+:8]);
remaining_bytes--;
end
end
if (rx_crc_corrupted) begin
`sim_error($display("CRC Corruption Seen!"))
if (remaining_bytes != 0) begin
`sim_error($display("CRC Corruption Error seen when not on final cycle!"))
end
end
end else if (rx_sop && ~rx_valid) begin
`sim_error($display("RX_SOP seen but RX_VALID not asserted!"))
end
end
end
endtask
task checkByte(bit [7:0] b);
bit [7:0] pkt_b;
if (pkt_array.size() == 0) begin
`sim_error($display("Went to check byte 0x%2h but pkt_array is empty!", b))
end else begin
pkt_b = pkt_array.pop_front();
if (b != pkt_b) begin
`sim_error($display("byte mismatch! Received 0x%2h but expecting 0x%2h", b, pkt_b))
end else begin
`sim_debug($display("byte match! Received 0x%2h and expecting 0x%2h", b, pkt_b))
end
end
endtask
task finalCheck;
if (pkt_array.size()) begin
`sim_error($display("Packet Array is not empty! Still contains %0d packets",
pkt_array.size()))
`sim_debug($display("Here are all the bytes still in the array"))
foreach (pkt_array[i]) begin
`sim_debug($display("%8d : 0x%2h", i, pkt_array[i]))
end
end
if (sim_errors) begin
`sim_error($display("%0d errors seen", sim_errors))
end
endtask
endmodule
| 6.941233 |
module slink_attribute_base #(
parameter ADDR = 16'h0,
parameter WIDTH = 1,
parameter RESET_VAL = {WIDTH{1'b0}},
parameter NAME = "unNamed",
parameter IS_RO = 0
) (
input wire clk,
input wire reset,
input wire hard_reset_cond,
input wire [15:0] link_attr_addr,
input wire [15:0] link_attr_data,
input wire link_shadow_update, //Asserts to take the addr/data check
input wire [15:0] app_attr_addr,
input wire [15:0] app_attr_data,
input wire app_shadow_update,
input wire [15:0] sw_attr_addr,
input wire [15:0] sw_attr_data,
input wire sw_shadow_update,
input wire effective_update, //Asserts to update effective to shadow value
output reg [WIDTH-1:0] shadow_reg,
output reg [WIDTH-1:0] effective_reg
);
generate
if (IS_RO == 1) begin
//"_int" variables just to keep iverilog warnings about no sensitivity list items
wire [WIDTH-1:0] shadow_reg_int;
wire [WIDTH-1:0] effective_reg_int;
assign shadow_reg_int = RESET_VAL;
assign effective_reg_int = RESET_VAL;
always @(*) begin
shadow_reg = shadow_reg_int;
effective_reg = effective_reg_int;
end
end else begin
wire link_attr_update;
wire app_attr_update;
wire sw_attr_update;
assign link_attr_update = link_shadow_update && (link_attr_addr == ADDR);
assign app_attr_update = app_shadow_update && (app_attr_addr == ADDR);
assign sw_attr_update = sw_shadow_update && (sw_attr_addr == ADDR);
always @(posedge clk or posedge reset) begin
if (reset) begin
effective_reg <= RESET_VAL;
shadow_reg <= RESET_VAL;
end else begin
effective_reg <= hard_reset_cond ? RESET_VAL :
effective_update ? shadow_reg : effective_reg;
shadow_reg <= hard_reset_cond ? RESET_VAL :
link_attr_update ? link_attr_data :
app_attr_update ? app_attr_data :
sw_attr_update ? sw_attr_data : shadow_reg;
`ifdef SIMULATION
if (link_attr_update) begin
$display("SLink Attribute Shadow Update (link): %s -> %4h", NAME, link_attr_data);
end else if (app_attr_update) begin
$display("SLink Attribute Shadow Update (app): %s -> %4h", NAME, app_attr_data);
end else if (sw_attr_update) begin
$display("SLink Attribute Shadow Update (sw): %s -> %4h", NAME, sw_attr_data);
end
`endif
end
end
end
endgenerate
endmodule
| 7.475466 |
module slink_clk_control #(
parameter NUM_RX_LANES = 4
) (
input wire core_scan_mode,
input wire core_scan_clk,
input wire core_scan_asyncrst_ctrl,
input wire apb_clk,
input wire apb_reset,
output wire apb_clk_scan,
output wire apb_reset_scan,
input wire refclk,
input wire phy_clk,
input wire main_reset,
input wire use_phy_clk,
output wire refclk_scan,
output wire refclk_scan_reset,
input wire [NUM_RX_LANES-1:0] rxclk_in,
output wire [NUM_RX_LANES-1:0] rxclk_out,
output wire [NUM_RX_LANES-1:0] rxclk_reset_out,
output wire link_clk,
output wire link_clk_reset
);
slink_clock_mux u_slink_clock_mux_apb_clk (
.clk0 (apb_clk),
.clk1 (core_scan_clk),
.sel (core_scan_mode),
.clk_out(apb_clk_scan)
);
slink_reset_sync u_slink_reset_sync_apb_reset (
.clk (apb_clk_scan),
.scan_ctrl(core_scan_asyncrst_ctrl),
.reset_in (apb_reset),
.reset_out(apb_reset_scan)
);
//wire refclk_scan;
slink_clock_mux u_slink_clock_mux_ref_clk (
.clk0 (refclk),
.clk1 (core_scan_clk),
.sel (core_scan_mode),
.clk_out(refclk_scan)
);
//wire main_reset_ref_clk_scan;
slink_reset_sync u_slink_reset_sync_main_reset_ref_clk (
.clk (refclk_scan),
.scan_ctrl(core_scan_asyncrst_ctrl),
.reset_in (main_reset),
.reset_out(refclk_scan_reset)
);
wire phy_clk_scan;
slink_clock_mux u_slink_clock_mux_phy_clk (
.clk0 (phy_clk),
.clk1 (core_scan_clk),
.sel (core_scan_mode),
.clk_out(phy_clk_scan)
);
wire main_reset_phy_clk_scan;
slink_reset_sync u_slink_reset_sync_main_reset_phy_clk (
.clk (phy_clk_scan),
.scan_ctrl(core_scan_asyncrst_ctrl),
.reset_in (main_reset),
.reset_out(main_reset_phy_clk_scan)
);
genvar laneindex;
generate
for (
laneindex = 0; laneindex < NUM_RX_LANES; laneindex = laneindex + 1
) begin : gen_rx_clock_muxes
slink_clock_mux u_slink_clock_mux_rxclk (
.clk0 (rxclk_in[laneindex]),
.clk1 (core_scan_clk),
.sel (core_scan_mode),
.clk_out(rxclk_out[laneindex])
);
slink_reset_sync u_slink_reset_sync_rxclk_reset (
.clk (rxclk_out[laneindex]),
.scan_ctrl(core_scan_asyncrst_ctrl),
.reset_in (main_reset),
.reset_out(rxclk_reset_out[laneindex])
);
end
endgenerate
wire link_clk_pre_scan;
slink_clock_mux_sync u_slink_clock_mux_sync (
.reset0 (refclk_scan_reset),
.reset1 (main_reset_phy_clk_scan),
.sel (use_phy_clk),
.clk0 (refclk_scan),
.clk1 (phy_clk_scan),
.clk_out(link_clk_pre_scan)
);
slink_clock_mux u_slink_clock_mux_link_clk (
.clk0 (link_clk_pre_scan),
.clk1 (core_scan_clk),
.sel (core_scan_mode),
.clk_out(link_clk)
);
slink_reset_sync u_slink_reset_sync_link_clk_reset (
.clk (link_clk),
.scan_ctrl(core_scan_asyncrst_ctrl),
.reset_in (main_reset),
.reset_out(link_clk_reset)
);
endmodule
| 7.229424 |
module slink_crc_8_16bit_compute (
input wire clk,
input wire reset,
input wire [ 7:0] data_in,
input wire valid,
input wire init,
input wire [15:0] crc_prev,
output wire [15:0] crc_next,
output reg [15:0] crc
);
wire [15:0] crc_in16;
wire [15:0] crc_in8;
reg [15:0] crc_in8_xfix;
always @(posedge clk or posedge reset) begin
if (reset) begin
crc <= 16'hffff;
end else begin
crc <= init ? 16'hffff : valid ? crc_in8_xfix : crc;
end
end
assign crc_next = valid ? crc_in8_xfix : 16'hffff;
//Can this be more optimzed?
assign crc_in8[15] = data_in[7] ^ data_in[3] ^ crc_prev[3] ^ crc_prev[7];
assign crc_in8[14] = data_in[6] ^ data_in[2] ^ crc_prev[2] ^ crc_prev[6];
assign crc_in8[13] = data_in[5] ^ data_in[1] ^ crc_prev[1] ^ crc_prev[5];
assign crc_in8[12] = data_in[4] ^ data_in[0] ^ crc_prev[0] ^ crc_prev[4];
assign crc_in8[11] = data_in[3] ^ crc_prev[3];
assign crc_in8[10] = data_in[7] ^ data_in[3] ^ crc_prev[3] ^ crc_prev[7] ^ data_in[2] ^ crc_prev[2];
assign crc_in8[ 9] = data_in[6] ^ data_in[2] ^ crc_prev[2] ^ crc_prev[6] ^ data_in[1] ^ crc_prev[1];
assign crc_in8[ 8] = data_in[5] ^ data_in[1] ^ crc_prev[1] ^ crc_prev[5] ^ data_in[0] ^ crc_prev[0];
assign crc_in8[7] = data_in[4] ^ data_in[0] ^ crc_prev[0] ^ crc_prev[4] ^ crc_prev[15];
assign crc_in8[6] = data_in[3] ^ crc_prev[3] ^ crc_prev[14];
assign crc_in8[5] = data_in[2] ^ crc_prev[2] ^ crc_prev[13];
assign crc_in8[4] = data_in[1] ^ crc_prev[1] ^ crc_prev[12];
assign crc_in8[ 3] = data_in[7] ^ data_in[3] ^ crc_prev[3] ^ crc_prev[7] ^ data_in[0] ^ crc_prev[0] ^ crc_prev[11];
assign crc_in8[2] = data_in[6] ^ data_in[2] ^ crc_prev[2] ^ crc_prev[6] ^ crc_prev[10];
assign crc_in8[1] = data_in[5] ^ data_in[1] ^ crc_prev[1] ^ crc_prev[5] ^ crc_prev[9];
assign crc_in8[0] = data_in[4] ^ data_in[0] ^ crc_prev[0] ^ crc_prev[4] ^ crc_prev[8];
always @(*) begin
crc_in8_xfix = crc_in8;
`ifndef SYNTHESIS
for (int jj = 0; jj < 16; jj++) begin
if (crc_in8[jj] === 1'bx) begin
crc_in8_xfix[jj] = 1'b0;
end
end
`endif
end
endmodule
| 7.263547 |
module slink_fc_replay_addr_sync #(
parameter ADDR_WIDTH = 4
) (
input wire wclk,
input wire wreset,
input wire [ADDR_WIDTH-1:0] waddr,
input wire rclk,
input wire rreset,
output wire [ADDR_WIDTH-1:0] raddr
);
wire wready;
wire rready;
wire [ADDR_WIDTH-1:0] raddr_fifo;
reg [ADDR_WIDTH-1:0] raddr_reg;
always @(posedge rclk or posedge rreset) begin
if (rreset) begin
raddr_reg <= {ADDR_WIDTH{1'b0}};
end else begin
raddr_reg <= rready ? raddr_fifo : raddr_reg;
end
end
assign raddr = rready ? raddr_fifo : raddr_reg;
slink_multibit_sync #(
.DATA_SIZE(ADDR_WIDTH)
) u_slink_multibit_sync (
.wclk (wclk),
.wreset(wreset),
.winc (1'b1),
.wready(),
.wdata (waddr),
.rclk (rclk),
.rreset(rreset),
.rinc (1'b1),
.rready(rready),
.rdata (raddr_fifo)
);
endmodule
| 7.281095 |
module slink_generic_pstate_ctrl (
input wire refclk,
input wire refclk_reset,
input wire enable,
input wire link_clk,
input wire link_clk_reset,
input wire link_active,
input wire in_px_state,
input wire [7:0] swi_1us_tick_count,
input wire [7:0] swi_inactivity_count,
input wire [2:0] swi_pstate_req,
output reg p1_req,
output reg p2_req,
output reg p3_req
);
wire enable_ff2;
wire in_px_state_ff2;
reg in_px_state_ff3;
wire px_state_exit;
reg [7:0] count_1us;
wire [7:0] count_1us_in;
wire count_1us_tick;
reg [7:0] inactivity_count;
wire [7:0] inactivity_count_in;
wire inactivity_time_reached;
wire p1_req_in;
wire p2_req_in;
wire p3_req_in;
slink_demet_reset u_slink_demet_reset (
.clk (refclk),
.reset (refclk_reset),
.sig_in (enable),
.sig_out(enable_ff2)
);
slink_demet_reset u_slink_demet_reset_in_px_state (
.clk (refclk),
.reset (refclk_reset),
.sig_in (in_px_state),
.sig_out(in_px_state_ff2)
);
wire link_acitve_sync;
wire link_acitve_valid;
wire link_acitve_refclk;
slink_multibit_sync #(
.DATA_SIZE(1)
) u_slink_multibit_sync (
.wclk (link_clk),
.wreset(link_clk_reset),
.winc (link_active),
.wready(),
.wdata (link_active),
.rclk (refclk),
.rreset(refclk_reset),
.rinc (1'b1),
.rready(link_acitve_valid),
.rdata (link_acitve_sync)
);
assign link_acitve_refclk = (link_acitve_valid && link_acitve_sync) || px_state_exit;
always @(posedge refclk or posedge refclk_reset) begin
if (refclk_reset) begin
count_1us <= 8'd0;
inactivity_count <= 8'd0;
p1_req <= 1'b0;
p2_req <= 1'b0;
p3_req <= 1'b0;
in_px_state_ff3 <= 1'b0;
end else begin
count_1us <= count_1us_in;
inactivity_count <= inactivity_count_in;
p1_req <= p1_req_in;
p2_req <= p2_req_in;
p3_req <= p3_req_in;
in_px_state_ff3 <= in_px_state_ff2;
end
end
assign px_state_exit = ~in_px_state_ff2 & in_px_state_ff3;
assign count_1us_tick = count_1us == swi_1us_tick_count;
assign count_1us_in = ~enable_ff2 ? 8'd0 : count_1us_tick ? 8'd0 : count_1us + 8'd1;
assign inactivity_time_reached = (inactivity_count == swi_inactivity_count);
assign inactivity_count_in = ~enable_ff2 || link_acitve_refclk ? 8'd0 : count_1us_tick ? (inactivity_time_reached ? inactivity_count : inactivity_count + 8'd1) : inactivity_count;
assign p3_req_in = inactivity_time_reached && swi_pstate_req[2];
assign p2_req_in = inactivity_time_reached && swi_pstate_req[1] && ~p3_req_in;
assign p1_req_in = inactivity_time_reached && swi_pstate_req[0] && ~p2_req_in;
endmodule
| 6.719737 |
module slink_generic_rx_router #(
parameter NUM_CHANNELS = 8,
parameter RX_APP_DATA_WIDTH = 64
) (
input wire clk,
input wire reset,
input wire rx_sop,
input wire [ 7:0] rx_data_id,
input wire [ 15:0] rx_word_count,
input wire [RX_APP_DATA_WIDTH-1:0] rx_app_data,
input wire rx_valid,
input wire rx_crc_corrupted,
input wire [(NUM_CHANNELS*8)-1:0] swi_ch_sp_min,
input wire [(NUM_CHANNELS*8)-1:0] swi_ch_sp_max,
input wire [(NUM_CHANNELS*8)-1:0] swi_ch_lp_min,
input wire [(NUM_CHANNELS*8)-1:0] swi_ch_lp_max,
output wire [ NUM_CHANNELS-1:0] rx_sop_ch,
output wire [ (NUM_CHANNELS*8)-1:0] rx_data_id_ch,
output wire [ (NUM_CHANNELS*16)-1:0] rx_word_count_ch,
output wire [(NUM_CHANNELS*
RX_APP_DATA_WIDTH)-1:0] rx_app_data_ch,
output wire [ NUM_CHANNELS-1:0] rx_valid_ch,
output wire [ NUM_CHANNELS-1:0] rx_crc_corrupted_ch
);
localparam NUM_CHANNELS_CLOG2 = $clog2(NUM_CHANNELS);
reg [NUM_CHANNELS-1:0] ch_sel;
wire [NUM_CHANNELS-1:0] ch_sel_in;
wire ch_update;
wire enable_ff2;
always @(posedge clk or posedge reset) begin
if (reset) begin
ch_sel <= {NUM_CHANNELS_CLOG2{1'b0}};
end else begin
ch_sel <= ch_sel_in;
end
end
assign ch_update = rx_sop && rx_valid;
genvar index;
generate
for (index = 0; index < NUM_CHANNELS; index = index + 1) begin : gen_indexes
assign ch_sel_in[index] = ch_update ? ((rx_data_id >= swi_ch_sp_min[((index+1)*8)-1:(index*8)]) &&
(rx_data_id <= swi_ch_sp_max[((index+1)*8)-1:(index*8)])) ||
((rx_data_id >= swi_ch_lp_min[((index+1)*8)-1:(index*8)]) &&
(rx_data_id <= swi_ch_lp_max[((index+1)*8)-1:(index*8)])) : ch_sel[index];
assign rx_sop_ch[index] = rx_sop && ch_sel_in[index];
assign rx_valid_ch[index] = rx_valid && ch_sel_in[index];
assign rx_crc_corrupted_ch[index] = rx_crc_corrupted && ch_sel_in[index];
assign rx_data_id_ch[((index+1)*8)-1:(index*8)] = rx_data_id;
assign rx_word_count_ch[((index+1)*16)-1:(index*16)] = rx_word_count;
assign rx_app_data_ch[((index+1)*RX_APP_DATA_WIDTH)-1:(index*RX_APP_DATA_WIDTH)] = rx_app_data;
end
endgenerate
endmodule
| 6.719737 |
module slink_generic_tx_router #(
parameter NUM_CHANNELS = 8,
parameter TX_APP_DATA_WIDTH = 64
) (
input wire clk,
input wire reset,
input wire enable,
input wire [ NUM_CHANNELS-1:0] tx_sop_ch,
input wire [ (NUM_CHANNELS*8)-1:0] tx_data_id_ch,
input wire [ (NUM_CHANNELS*16)-1:0] tx_word_count_ch,
input wire [(NUM_CHANNELS*
TX_APP_DATA_WIDTH)-1:0] tx_app_data_ch,
output wire [ NUM_CHANNELS-1:0] tx_advance_ch,
output wire tx_sop,
output wire [ 7:0] tx_data_id,
output wire [ 15:0] tx_word_count,
output wire [TX_APP_DATA_WIDTH-1:0] tx_app_data,
input wire tx_advance
);
localparam NUM_CHANNELS_CLOG2 = $clog2(NUM_CHANNELS);
reg [NUM_CHANNELS_CLOG2-1:0] curr_ch;
reg [NUM_CHANNELS_CLOG2-1:0] curr_ch_reg;
reg [NUM_CHANNELS_CLOG2-1:0] curr_ch_reg_in;
wire [NUM_CHANNELS_CLOG2-1:0] curr_ch_next;
wire enable_ff2;
wire [ NUM_CHANNELS-1:0] higher_index_sel;
reg [NUM_CHANNELS_CLOG2-1:0] higher_index_pri;
wire [ NUM_CHANNELS-1:0] lower_index_sel;
reg [NUM_CHANNELS_CLOG2-1:0] lower_index_pri;
wire tx_sop_sel [NUM_CHANNELS-1:0];
wire [ 7:0] tx_data_id_sel [NUM_CHANNELS-1:0];
wire [ 15:0] tx_word_count_sel[NUM_CHANNELS-1:0];
wire [ TX_APP_DATA_WIDTH-1:0] tx_app_data_sel [NUM_CHANNELS-1:0];
slink_demet_reset u_slink_demet_reset_enable (
.clk (clk),
.reset (reset),
.sig_in (enable),
.sig_out(enable_ff2)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_ch_reg <= {NUM_CHANNELS_CLOG2{1'b0}};
end else begin
curr_ch_reg <= enable_ff2 ? curr_ch_reg_in : {NUM_CHANNELS_CLOG2{1'b0}};
end
end
genvar index;
generate
for (index = 0; index < NUM_CHANNELS; index = index + 1) begin : gen_indexes
assign higher_index_sel[index] = (index > curr_ch_reg) && tx_sop_ch[index];
assign lower_index_sel[index] = (index <= curr_ch_reg) && tx_sop_ch[index];
assign tx_advance_ch[index] = tx_advance && (curr_ch == index);
assign tx_sop_sel[index] = tx_sop_ch[index];
assign tx_data_id_sel[index] = tx_data_id_ch[((index+1)*8)-1:(index*8)];
assign tx_word_count_sel[index] = tx_word_count_ch[((index+1)*16)-1:(index*16)];
assign tx_app_data_sel[index] = tx_app_data_ch[((index+1)*TX_APP_DATA_WIDTH)-1:(index*TX_APP_DATA_WIDTH)];
end
endgenerate
integer i;
always @(*) begin
higher_index_pri = {NUM_CHANNELS_CLOG2{1'b0}};
for (i = (NUM_CHANNELS - 1); i >= 0; i = i - 1) begin
if ((i > curr_ch_reg) && tx_sop_ch[i]) begin
higher_index_pri = i;
end
end
end
integer j;
always @(*) begin
lower_index_pri = {NUM_CHANNELS_CLOG2{1'b0}};
for (j = (NUM_CHANNELS - 1); j >= 0; j = j - 1) begin
//if((j <= curr_ch_reg) && tx_sop_ch[j]) begin
if ((j < curr_ch_reg) && tx_sop_ch[j]) begin
lower_index_pri = j;
end
end
end
always @(*) begin
curr_ch_reg_in = curr_ch_reg;
curr_ch = curr_ch_reg;
if ((curr_ch_reg != higher_index_pri) && ~(|lower_index_sel)) begin
curr_ch_reg_in = higher_index_pri;
curr_ch = higher_index_pri;
end else begin
if (tx_advance) begin
curr_ch_reg_in = |higher_index_sel ? higher_index_pri :
|lower_index_sel ? lower_index_pri : {NUM_CHANNELS_CLOG2{1'b0}};
end
end
end
assign tx_sop = tx_sop_sel[curr_ch];
assign tx_data_id = tx_data_id_sel[curr_ch];
assign tx_word_count = tx_word_count_sel[curr_ch];
assign tx_app_data = tx_app_data_sel[curr_ch];
endmodule
| 6.719737 |
module slink_gpio_model (
input wire oen,
output wire sig_in,
inout wire pad
);
assign pad = oen ? 1'b0 : 1'bz;
pullup (weak1) pad_pu (pad);
assign sig_in = pad === 1'bz ? 1'b1 : pad;
endmodule
| 8.227232 |
module slink_ll_rx_pkt_filt (
input wire clk,
input wire reset,
input wire sop,
input wire [ 7:0] data_id,
input wire [15:0] word_count,
input wire valid,
output wire sop_app,
output wire valid_app
);
`include "slink_includes.vh"
wire pkt_is_internal;
wire attr_addr_pkt;
wire attr_data_pkt;
wire attr_req_pkt;
assign pkt_is_internal = (data_id == NOP_DATAID) || (data_id == IDL_SYM);
assign sop_app = ~pkt_is_internal && sop;
assign valid_app = ~pkt_is_internal && valid;
endmodule
| 7.34087 |
module slink_simple_io_phy_model #(
parameter IS_MASTER = 1,
parameter CLK_PER_NS = 2,
parameter DATA_WIDTH = 8,
parameter NUM_TX_LANES = 4,
parameter NUM_RX_LANES = 4
) (
input wire clk_enable,
input wire clk_idle,
output wire clk_ready,
inout wire clk_byteclk,
output wire parclk,
input wire [ NUM_TX_LANES-1:0] tx_enable,
input wire [(NUM_TX_LANES*DATA_WIDTH)-1:0] tx_data,
input wire tx_data_ctrl,
input wire [ NUM_TX_LANES-1:0] tx_reset,
output wire [ NUM_TX_LANES-1:0] tx_dirdy,
output wire [ NUM_TX_LANES-1:0] tx_ready,
input wire [ NUM_RX_LANES-1:0] rx_enable,
output reg [(NUM_RX_LANES*DATA_WIDTH)-1:0] rx_data,
output reg rx_data_ctrl,
input wire [ NUM_RX_LANES-1:0] rx_reset,
output wire [ NUM_RX_LANES-1:0] rx_dordy,
output wire [ NUM_RX_LANES-1:0] rx_ready,
output reg [(NUM_TX_LANES*DATA_WIDTH)-1:0] tx,
output reg tx_ctrl,
input wire [(NUM_RX_LANES*DATA_WIDTH)-1:0] rx,
input wire rx_ctrl
);
wire bitclk;
serdes_clk_model #(
//parameters
.IS_MASTER (IS_MASTER),
.CLK_PER_NS(CLK_PER_NS)
) u_serdes_clk_model (
.enable(clk_enable),
.idle (clk_idle),
.ready (clk_ready),
.bitclk(bitclk)
); //really a byteclk here
assign clk_byteclk = IS_MASTER ? bitclk : 1'bz;
assign parclk = clk_byteclk;
// TODO CLEAN UP THESE RESETS!
always @(negedge clk_byteclk or posedge tx_reset) begin
if (tx_reset) begin
tx <= {NUM_TX_LANES * DATA_WIDTH{1'b0}};
tx_ctrl <= 1'b0;
end else begin
tx <= tx_data;
tx_ctrl <= tx_data_ctrl;
end
end
always @(posedge clk_byteclk or posedge rx_reset) begin
if (rx_reset) begin
rx_data <= {NUM_RX_LANES * DATA_WIDTH{1'b0}};
rx_data_ctrl <= 1'b0;
end else begin
rx_data <= rx;
rx_data_ctrl <= rx_ctrl;
end
end
//temp
assign tx_ready = {NUM_TX_LANES{1'b1}};
assign rx_ready = {NUM_TX_LANES{1'b1}};
endmodule
| 6.860006 |
module slink_sync_pulse (
input wire clk_in,
input wire clk_in_reset,
input wire data_in,
input wire clk_out,
input wire clk_out_reset,
output wire data_out
);
reg clk_in_pulse;
always @(posedge clk_in or posedge clk_in_reset) begin
if (clk_in_reset) begin
clk_in_pulse <= 1'b0;
end else begin
clk_in_pulse <= data_in ? ~clk_in_pulse : clk_in_pulse;
end
end
wire pulse_demeted;
reg pulse_demeted_ff3;
slink_demet_reset u_slink_demet_reset (
.clk (clk_out),
.reset (clk_out_reset),
.sig_in (clk_in_pulse),
.sig_out(pulse_demeted)
);
always @(posedge clk_out or posedge clk_out_reset) begin
if (clk_out_reset) begin
pulse_demeted_ff3 <= 1'b0;
end else begin
pulse_demeted_ff3 <= pulse_demeted;
end
end
assign data_out = pulse_demeted ^ pulse_demeted_ff3;
endmodule
| 6.571673 |
module slink_demet_reset (
input wire clk,
input wire reset,
input wire sig_in,
output wire sig_out
);
reg [1:0] demet_flops;
assign sig_out = demet_flops[0];
always @(posedge clk or posedge reset) begin
if (reset) begin
demet_flops <= 2'b00;
end else begin
demet_flops <= {sig_in, demet_flops[1]};
end
end
endmodule
| 6.881975 |
module slink_demet_set (
input wire clk,
input wire set,
input wire sig_in,
output wire sig_out
);
reg [1:0] demet_flops;
assign sig_out = demet_flops[0];
always @(posedge clk or posedge set) begin
if (set) begin
demet_flops <= 2'b11;
end else begin
demet_flops <= {sig_in, demet_flops[1]};
end
end
endmodule
| 6.922732 |
module slink_reset_sync (
input wire clk,
input wire scan_ctrl,
input wire reset_in,
output wire reset_out
);
wire reset_in_ff2;
wire reset_in_int;
assign reset_in_int = ~scan_ctrl & reset_in;
slink_demet_set u_demet_set (
.clk (clk),
.set (reset_in_int),
.sig_in (1'b0),
.sig_out(reset_in_ff2)
);
//assign reset_out = ~scan_ctrl & (reset_in | reset_in_ff2);
assign reset_out = ~scan_ctrl & reset_in_ff2;
endmodule
| 8.500962 |
module slink_clock_mux (
input wire clk0,
input wire clk1,
input wire sel,
output wire clk_out
);
assign clk_out = sel ? clk1 : clk0;
endmodule
| 6.904644 |
module slink_clock_inv (
input wire clk_in,
output wire clk_out
);
assign clk_out = ~clk_in;
endmodule
| 7.662846 |
module slink_clock_buf (
input wire clk_in,
output wire clk_out
);
assign clk_out = clk_in;
endmodule
| 7.271512 |
module slink_clock_gate (
input wire clk_in,
input wire reset,
input wire core_scan_mode,
input wire enable,
input wire disable_clkgate,
output wire clk_out
);
wire clk_en;
wire enable_ff2;
slink_demet_reset u_slink_demet_reset (
.clk (clk_in),
.reset (reset),
.sig_in (enable || disable_clkgate),
.sig_out(enable_ff2)
);
assign clk_en = enable_ff2 | core_scan_mode;
assign clk_out = clk_en & clk_in;
endmodule
| 8.17648 |
module slink_clock_or (
input wire clk0,
input wire clk1,
output wire clk_out
);
assign clk_out = clk0 | clk1;
endmodule
| 8.145422 |
module slink_clock_mux_sync (
input wire reset0,
input wire reset1,
input wire sel,
input wire clk0,
input wire clk1,
output wire clk_out
);
wire clk0_inv;
wire clk1_inv;
wire sel_inv;
wire sel0_in;
wire sel1_in;
wire clk0_out;
wire clk1_out;
wire clk_out_pre;
reg sel0_ff1, sel0_ff2;
reg sel1_ff1, sel1_ff2;
wire sel_buf;
//Google glichless clock mux and look for EETimes article
slink_clock_inv u_clk0_inv (
.clk_in (clk0),
.clk_out(clk0_inv)
);
slink_clock_inv u_clk1_inv (
.clk_in (clk1),
.clk_out(clk1_inv)
);
//for case_analysis settings
slink_clock_buf u_sel_buf (
.clk_in (sel),
.clk_out(sel_buf)
);
slink_clock_inv u_sel_inv (
.clk_in (sel_buf),
.clk_out(sel_inv)
);
//assign sel_inv = ~sel;
assign sel0_in = ~sel1_ff2 & sel_inv;
assign sel1_in = ~sel0_ff2 & sel;
assign clk0_out = sel0_ff2 & clk0;
assign clk1_out = sel1_ff2 & clk1;
always @(posedge clk0 or posedge reset0) begin
if (reset0) sel0_ff1 <= 1'b0;
else sel0_ff1 <= sel0_in;
end
always @(posedge clk0_inv or posedge reset0) begin
if (reset0) sel0_ff2 <= 1'b0;
else sel0_ff2 <= sel0_ff1;
end
always @(posedge clk1 or posedge reset1) begin
if (reset1) sel1_ff1 <= 1'b0;
else sel1_ff1 <= sel1_in;
end
always @(posedge clk1_inv or posedge reset1) begin
if (reset1) sel1_ff2 <= 1'b0;
else sel1_ff2 <= sel1_ff1;
end
//assign clk_out_pre = clk0_out | clk1_out;
slink_clock_or u_clk_or (
.clk0(clk0_out),
.clk1(clk1_out),
.clk_out(clk_out_pre)
);
//Final buffer (declare clock here)
slink_clock_buf u_slink_clock_buf (
.clk_in (clk_out_pre),
.clk_out(clk_out)
);
endmodule
| 6.904644 |
module slink_fifo_top #(
parameter DATA_SIZE = 40,
parameter ADDR_SIZE = 4
) (
input wire wclk,
input wire wreset,
input wire winc,
input wire rclk,
input wire rreset,
input wire rinc,
input wire [DATA_SIZE-1:0] wdata,
output wire [DATA_SIZE-1:0] rdata,
output wire wfull,
output wire rempty,
output wire [ ADDR_SIZE:0] rbin_ptr,
output wire [ADDR_SIZE+1:0] rdiff,
output wire [ ADDR_SIZE:0] wbin_ptr,
output wire [ADDR_SIZE+1:0] wdiff,
input wire [ADDR_SIZE-1:0] swi_almost_empty,
input wire [ADDR_SIZE-1:0] swi_almost_full,
output wire half_full,
output wire almost_empty,
output wire almost_full
);
wire [ADDR_SIZE-1:0] waddr;
wire [ADDR_SIZE-1:0] raddr;
wire [ADDR_SIZE:0] wptr, sync_wptr;
wire [ADDR_SIZE:0] rptr, sync_rptr;
//demets for ptr sync
slink_demet_reset u_rptr_to_wlogic_demet[ADDR_SIZE:0] (
.clk (wclk),
.reset (wreset),
.sig_in (rptr),
.sig_out(sync_rptr)
);
slink_demet_reset u_wptr_to_rlogic_demet[ADDR_SIZE:0] (
.clk (rclk),
.reset (rreset),
.sig_in (wptr),
.sig_out(sync_wptr)
);
//write logic
slink_fifo_ptr_logic #(
.ADDR_SIZE (ADDR_SIZE),
.IS_WRITE_PTR(1)
) u_write_ptr_logic (
.inc (winc),
.clk (wclk),
.reset (wreset),
.swi_almost_val(swi_almost_full),
.sync_ptr (sync_rptr),
.ptr (wptr),
.bin_ptr (wbin_ptr),
.diff (wdiff),
.addr (waddr),
.flag (wfull),
.almost_fe (almost_full),
.half_full (half_full)
);
//read logic
slink_fifo_ptr_logic #(
.ADDR_SIZE (ADDR_SIZE),
.IS_WRITE_PTR(0)
) u_read_ptr_logic (
.inc (rinc),
.clk (rclk),
.reset (rreset),
.swi_almost_val(swi_almost_empty),
.sync_ptr (sync_wptr),
.ptr (rptr),
.bin_ptr (rbin_ptr),
.diff (rdiff),
.addr (raddr),
.flag (rempty),
.almost_fe (almost_empty),
.half_full ()
);
//mem
slink_fifomem #(
.DATA_SIZE(DATA_SIZE),
.ADDR_SIZE(ADDR_SIZE)
) u_mem (
.wclk (wclk),
.rclk (rclk),
.wclken (winc),
.read_en(~rempty),
.wreset (wreset),
.wfull (wfull),
.waddr (waddr),
.raddr (raddr),
.wdata (wdata),
.rdata (rdata)
);
endmodule
| 6.849978 |
module slink_fifomem #(
parameter DATA_SIZE = 40,
parameter ADDR_SIZE = 4
) (
input wire wclk,
input wire rclk,
input wire wclken,
input wire read_en,
input wire wreset,
input wire wfull,
input wire [ADDR_SIZE-1:0] waddr,
input wire [ADDR_SIZE-1:0] raddr,
input wire [DATA_SIZE-1:0] wdata,
output wire [DATA_SIZE-1:0] rdata
);
localparam DEPTH = 1 << ADDR_SIZE;
wire web;
wire reb;
reg [DATA_SIZE-1:0] mem[0:DEPTH-1];
assign rdata = mem[raddr];
integer i;
always @(posedge wclk or posedge wreset) begin
if (wreset) begin
for (i = 0; i < (1 << ADDR_SIZE); i = i + 1) begin
mem[i] <= {DATA_SIZE{1'b0}};
end
end else begin
if (wclken & ~wfull) begin
mem[waddr] <= wdata;
end
end
end
endmodule
| 6.915958 |
module slink_multibit_sync #(
parameter DATA_SIZE = 8
) (
input wire wclk,
input wire wreset,
input wire winc,
output wire wready,
input wire [DATA_SIZE-1:0] wdata,
input wire rclk,
input wire rreset,
input wire rinc,
output wire rready,
output wire [DATA_SIZE-1:0] rdata
);
//reg [DATA_SIZE-1:0] mem [2];
reg [DATA_SIZE-1:0] mem [1:0];
reg wptr;
wire wptr_in;
wire we;
wire rptr_wclk;
reg rptr;
wire rptr_in;
wire wptr_rclk;
always @(posedge wclk or posedge wreset) begin
if (wreset) begin
wptr <= 1'b0;
mem[0] <= {DATA_SIZE{1'b0}};
mem[1] <= {DATA_SIZE{1'b0}};
end else begin
wptr <= wptr_in;
if (we) begin
mem[wptr] <= wdata;
end
end
end
slink_demet_reset u_slink_demet_rptr_wclk (
.clk (wclk),
.reset (wreset),
.sig_in (rptr),
.sig_out(rptr_wclk)
);
assign wptr_in = we ^ wptr;
assign wready = ~(rptr_wclk ^ wptr);
assign we = winc & wready;
always @(posedge rclk or posedge rreset) begin
if (rreset) begin
rptr <= 1'b0;
end else begin
rptr <= rptr_in;
end
end
slink_demet_reset u_slink_demet_wptr_rclk (
.clk (rclk),
.reset (rreset),
.sig_in (wptr),
.sig_out(wptr_rclk)
);
assign rready = rptr ^ wptr_rclk;
assign rptr_in = rptr ^ (rinc & rready);
assign rdata = mem[rptr];
endmodule
| 7.787808 |
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