code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Slave_AXI4Lite #(
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 4
) (
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
//
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input wire [2 : 0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
outp... | 7.948503 |
module MetadataArray (
input clk,
input reset,
output io_read_ready,
input io_read_valid,
input [5:0] io_read_bits_idx,
output io_write_ready,
input io_write_valid,
input [5:0] io_write_bits_idx,
input io_write_bits_way_en,
input [19:0] io_write_bits_data_tag,
input [1:0] io_... | 6.901681 |
module RRArbiter_0 (
input clk,
input reset,
output io_in_1_ready,
input io_in_1_valid,
input [29:0] io_in_1_bits,
output io_in_0_ready,
input io_in_0_valid,
input [29:0] io_in_0_bits,
input io_out_ready,
output io_out_valid,
output [29:0] io_out_bits,
output io_chosen
);... | 6.876771 |
module Queue_3 (
input clk,
input reset,
output io_enq_ready,
input io_enq_valid,
input [25:0] io_enq_bits_addr,
input [4:0] io_enq_bits_tag,
input io_enq_bits_rw,
input io_deq_ready,
output io_deq_valid,
output [25:0] io_deq_bits_addr,
output [4:0] io_deq_bits_tag,
outpu... | 6.517764 |
module slave (
input [1:0] MODE,
input reg [7:0] data_in,
input reset,
input clk,
input MOSI,
output reg MISO,
input CS,
output reg [7:0] data_out
);
reg entered = 0;
reg [7:0] R_data;
reg [7:0] T_data;
reg done; //
integer count = 0;
reg is_read = 0;
//wire sclk;
//ass... | 7.264319 |
module slaveFIFO2b_streamIN (
input reset_,
input clk_100,
input stream_in_mode_selected,
input flaga_d,
input flagb_d,
output slwr_streamIN_,
output [31:0] data_out_stream_in
);
reg [ 2:0] current_stream_in_state;
reg [ 2:0] next_stream_in_state;
reg [31:0] data_gen_stream_in;
//p... | 6.613765 |
module slaveFIFO2b_streamIN_only #(
parameter DW = 32
) (
input wire reset_, //input reset active low
input wire clk, //input clk
output wire wfifo_rd,
input wire fifo_aempty,
output wire clk_out, //output clk 100 Mhz (max) and 180 phase shift
output wire [1:0] faddr, //ou... | 6.613765 |
module slaveFIFO2b_streamOUT (
input reset_,
input clk_100,
input stream_out_mode_selected,
input flagc_d,
input flagd_d,
input [31:0] stream_out_data_from_fx3,
output slrd_streamOUT_,
output sloe_streamOUT_
);
reg [2:0] current_stream_out_state;
reg [2:0] next_stream_out_state;
... | 6.613765 |
module slaveFIFO2b_ZLP (
input reset_,
input clk_100,
input zlp_mode_selected,
input flaga_d,
input flagb_d,
output slwr_zlp_,
output pktend_zlp_,
output [31:0] data_out_zlp
);
reg [2:0] current_zlp_state;
reg [2:0] next_zlp_state;
//parameters for ZLP mode state machine
parame... | 7.341839 |
module SlaveMaster (
input reset,
input ss1,
input ss2,
input ss3,
input ss4,
input sck,
input cpol,
input cpoh,
input MOSI,
//input [7:0] Address,
output MISO
);
slave1 s1 (
reset,
ss1,
sck,
cpol,
cpoh,
MOSI,
MISO
);
... | 6.767317 |
module SlaveModule #(
parameter DATA_WIDTH_SLAVE = 32,
parameter STROBE_WIDTH_SLAVE = DATA_WIDTH_SLAVE / 8,
parameter ADDRESS_WIDTH_SLAVE = 8
) (
//Global signals
input aclk,
input aresetn,
//Write address channel
input ... | 7.113216 |
module slaveRxStatusMonitor (
connectStateIn,
connectStateOut,
resumeDetectedIn,
resetEventOut,
resumeIntOut,
clk,
rst
);
input [1:0] connectStateIn;
input resumeDetectedIn;
input clk;
input rst;
output resetEventOut;
output [1:0] connectStateOut;
output resumeIntOut;
wire ... | 6.544278 |
module slaveRxStatusMonitor_simlib (
connectStateIn,
connectStateOut,
resumeDetectedIn,
resetEventOut,
resumeIntOut,
clk,
rst
);
input [1:0] connectStateIn;
input resumeDetectedIn;
input clk;
input rst;
output resetEventOut;
output [1:0] connectStateOut;
output resumeIntOut;
... | 6.544278 |
module involving the switching of the slave select line
// during transmission and idle states.
//
// Inputs:
// rst User input Reset
// transmit signal from SPImaster causing ss line to go low
// ( enable )
// done signal from SPIinterface causing ss line to go
// high ( disable )... | 8.691693 |
module slave_0 (
clk,
rst,
sel,
s_data_in_0,
ack,
s_data_out_0
);
//---Input & output Port---//
input [31:0] s_data_in_0;
input sel, clk, rst;
output [31:0] s_data_out_0;
output ack;
//---- Your design code---//
reg [31:0] s_data_out_0;
reg ack = 0;
reg [7:0] mac_dataA =... | 6.721307 |
module butterfly0 (
ar,
ai,
br,
bi,
xr,
xi,
yr,
yi,
w0r,
w0i
);
input signed [15:0] xr, yr, xi, yi;
input signed [31:0] w0r, w0i;
output signed [15:0] ar, ai, br, bi;
assign ar = xr + yr;
assign ai = xi;
assign br = xr - yr;
assign bi = xi;
endmodule
| 8.051328 |
module butterfly1 (
ar,
ai,
br,
bi,
xr,
xi,
yr,
yi,
w0r,
w0i
);
input signed [15:0] xr, xi, yr, yi;
input signed [31:0] w0r, w0i;
output signed [15:0] ar, ai, br, bi;
wire signed [47:0] dick_re1, dick_im1, dick_re2, dick_im2;
wire signed [47:0] far, fai, fbr, fbi;
a... | 7.109482 |
module slave_1_tb ();
reg clk, rst_n, slave_en;
wire slave_done;
wire [3:0] slave_out;
slave_1 obey (
clk,
rst_n,
slave_en,
slave_done,
slave_out
);
initial begin
$dumpfile("slave_1_tb.vcd");
$dumpvars(0, slave_1_tb);
rst_n = 0;
slave_en = 0;
#10;
rs... | 7.651523 |
module Slave_4K (
SEL,
HADDR,
HWDATA,
HRDATA,
HRESP,
CLK,
HREADY,
RST,
MLOCK,
AB
);
input [15:0] HADDR;
input [31:0] HWDATA;
input SEL;
input RST, CLK;
input MLOCK;
//input HWRITE;
output reg [31:0] HRDATA;
output reg [1:0] HRESP;
output reg HREADY;
output ... | 6.849796 |
module slave_apb (
output reg [7 : 0] prdata, //dataout from slave
input penable, // to enable read or write
input pwrite, // control signal
input psel, // select signal
input pclk, // posedge clk
input presetn, // ... | 9.552011 |
module slave_axi_v3_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add... | 6.806688 |
module slave_bus_ifc (
rst_n,
cc_psel,
cc_penable,
cc_pwrite,
cc_paddr,
cc_pwdata,
cc_prdata,
rng_cpu_prdata,
cpu_rng_psel,
cpu_rng_pwrite,
cpu_rng_paddr,
cpu_rng_pwdata
);
parameter CRY_ENGINE_UPPER_IDX = 4'ha;
`include "cc_params.inc"
parameter CLK_STATUS_ADDR = 1... | 7.473276 |
module when rst_n == 0.
// request :request signal sent by the master.
// ack :ack output to master.
// data_in :data input from master.
// notice :signal indicating the receive of data or request from master, will be asserted for 1 sec.
// data :data output to the seven segment mo... | 7.974228 |
module slave_controller (
input clk,
input reset,
input chipselect,
input write,
input [3:0] addr,
input [31:0] writedata,
output [23:0] GPIO_out
);
reg [11:0] in = 12'd0;
reg [6*`PERIOD_LENGTH-1:0] duty_cycle = 0;
reg [15:0] period = 16'd0;
always @(posedge clk)
if (chipselect ... | 7.868824 |
module slave_det(
output reg sequence,
output out,
input clk,
input resetn,
input [4:0]in
);
seq_detector sd(.sequence(sequence),.clk(clk),.resetn(resetn),.out(out));
always @(posedge clk)
begin
if(~resetn)
sequence = in[0];
else
sequence = {1'b0,in[4:1]};
end
endmodule
| 8.072941 |
module slave_FIFO #(
parameter DATA_DEPTH = 'd64 //FIFO深度
) (
input clk_i, //时钟
rstn_i, //复位
chx_valid_i, //外部信号有效信号
a2sx_ack_i, //仲裁器允许读数据包
slvx_en_i, //通道使能(来自寄存器)
input wire [31:0] chx_data_i,
input wire [ 2:0] slvx_pkglen_i, //本通道数据包长度
output wire ... | 8.435445 |
module slave_file #(
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 4
) (
input wire s_aclk,
input wire s_aresetn,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] s_awaddr,
input wire [2 : 0] s_awprot,
input wire s_awvalid,
output wire s_awready,
input wire [... | 8.24519 |
module slave_mux #(
parameter ADDR_WD = 32,
parameter DATA_WD = 32,
parameter STRB_WD = 4,
parameter PROT_WD = 3
) (
input b_pclk,
input b_prst_n,
input b_psel,
input b_penable,
input b_pwrite,
input [ADDR_WD-1 : 0] b_paddr,
... | 7.174126 |
module
//
// This module interfaces with an APB master and selects
// and routes data from connected slave devices
//
// select - bits to select the peripheral
// PRDATA - APB data from the current peripheral
// PSELs - Peripheral select - Only one bit in this vector
// will ever be set at the same time
// PRDA... | 8.000328 |
module slave_mux_apb2_slave_tb;
localparam SELECTOR_BITS = 5;
localparam DATA_BITS = 9;
localparam PERIPHERALS = 1 << SELECTOR_BITS;
reg [SELECTOR_BITS - 1:0] select;
reg [PERIPHERALS * DATA_BITS - 1:0] PRDATAs;
reg PSEL;
wire [DATA_BITS - 1:0] PRDATA;
wire [PERIPHERALS - 1:0] PSELs;
slave_mux_apb2_s... | 6.55923 |
module slave_passthru #(
parameter S_WB_ADR_WIDTH = 32,
parameter S_WB_DAT_WIDTH = 32
) (
// wishbone slave signals
input [S_WB_ADR_WIDTH-1:0] S_ADR_I,
input [S_WB_DAT_WIDTH-1:0] S_DAT_I,
input S_WE_I,
input [S_WB_DAT_WIDTH/8-1:0] S_SEL_I,
input S_STB_I,
input S_CYC_I,
input S_LO... | 8.625748 |
module slave_select (
input clk,
input [ 7:0] adr_1,
input [15:0] adr_first_reg_tx_1,
input [ 7:0] num_reg_tx_1,
input [15:0] adr_first_reg_rx_1,
input [ 7:0] num_reg_rx_1,
input [15:0] data_in_1,
input [ 7:0] adr_2,
input [15:0] adr_first_reg_tx_2,
input [ 7:0] num_reg_tx_2,
... | 7.087801 |
module main (
input clk,
input serdes_in,
output serdes_out,
output serdes_en
);
wire clk;
wire resetn_out;
wire linkerror;
wire linkready;
wire mode_recv;
wire mode_send;
wire [7:0] gpio_i = 0;
wire [7:0] gpio_o;
wire [4:0] in_tdata = 0;
wire [3:0] in_tuser = 0;
wire in_tvalid =... | 7.081372 |
module Slave_spi_v1(clk, SCK, MOSI, SS, DATAIN, start,
Enable, dataout11, dataout22, dataout33, dataout44,);
input clk;
input SCK;
input MOSI;
input SS;
input start;
input [15:0] DATAIN;
output reg Enable = 0;
output reg [15:0] dataout11;
output reg [15:0] dataout22;
output reg [15:0] dataout33;
output reg [15... | 6.515813 |
module Slave_TB ();
reg reset;
reg [7:0] slaveDataToSend; //input
wire [7:0] slaveDataReceived; //output
reg SCLK;
reg CS;
reg MOSI;
wire MISO;
wire [7:0] testcase_slaveData[1: /*TESTCASECOUNT*/4];
wire [7:0] testcase_masterData[1: /*TESTCASECOUNT*/4];
integer i, j;
reg [7:0] masterDataRecei... | 6.75127 |
module to simplify having a register of variable width and containing independent byte lanes
module register_with_bytelanes (
clk,
reset,
data_in,
write,
byte_enables,
data_out
);
parameter DATA_WIDTH = 32;
input clk;
input reset;
input [DATA_WIDTH-1:0] data_in;
input write;
input [(DATA_WIDTH/8)-1:0... | 8.882302 |
module slbi (
A,
B,
Out
);
input [15:0] A, B;
output wire [15:0] Out;
assign Out = (A << 8) | B;
endmodule
| 6.759902 |
module sld_virtual_jtag (
ir_out,
tdo,
ir_in,
tck,
tdi,
virtual_state_cdr,
virtual_state_cir,
virtual_state_e1dr,
virtual_state_e2dr,
virtual_state_pdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir
);
parameter sld_auto_instance_index = "YES";
paramete... | 6.971215 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1... | 6.821676 |
module SLE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0071)
) inst1 (
.I0(inst0_O[1]),
.I1(I1[1]),
.I2(I0[1]),
.I3(1'b0),
... | 7.129266 |
module main (
input [3:0] J1,
output J3
);
wire inst0_O;
SLE2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module SLE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2_cin1 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h71)
) inst1 (
.I0(inst0_O[1]),
.I1(I1[1]),
.I2(I0[1]),
.O (inst1_O)
);
... | 7.129266 |
module SLE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2_cin1 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h71)
) inst1 (
.I0(inst0_O[1]),
.I1(I1[1]),
.I2(I0[1]),
.O (inst1_O)
);
... | 7.129266 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(ins... | 7.507677 |
module SLE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0071)
) inst1 (
.I0(inst0_O[3]),
.I1(I1[3]),
.I2(I0[3]),
.I3(1'b0),
... | 7.225341 |
module main (
input [7:0] J1,
output J3
);
wire inst0_O;
SLE4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module SLE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4_cin1 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h71)
) inst1 (
.I0(inst0_O[3]),
.I1(I1[3]),
.I2(I0[3]),
.O (inst1_O)
);
... | 7.225341 |
module main (
input [7:0] SWITCH,
output LED
);
wire inst0_O;
SLE4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module SLE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4_cin1 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h71)
) inst1 (
.I0(inst0_O[3]),
.I1(I1[3]),
.I2(I0[3]),
.O (inst1_O)
);
... | 7.225341 |
module sled (
input wire clock,
output wire [7:0] segs,
output wire [3:0] digs
);
// Variavel com os dados a serem exibidos no display de 7 segmentos
reg [ 3:0] disp_dat;
reg [ 7:0] segs_dsp;
// Contador:
reg [36:0] count;
// Ligar os 4 digitos do display
assign digs = 4'b0000;
// --> Bloc... | 6.521856 |
module sleep_or_not (
clk,
ps_data,
tosleep
);
input clk, ps_data;
output reg tosleep;
parameter [31:0] lim = 100000000; // default 10000000
integer cnt;
initial begin
cnt = 0;
tosleep = 0;
end
always @(posedge clk) begin
if (ps_data == 0) begin
cnt <= 0;
tosleep <=... | 6.736378 |
module sleep_unit #(
parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
) (
HCLK,
HRESETn,
PADDR,
PWDATA,
PWRITE,
PSEL,
PENABLE,
PRDATA,
PREADY,
PSLVERR,
irq_i,
event_i,
core_busy_i,
fetch_en_o,
clk_gate_core_o
);
//parameter APB_ADDR_WIDTH =... | 7.876149 |
module sleft (
input [25:0] shiftleft,
output reg [25:0] shifted
);
wire [25:0] shiftl = shiftleft << 2;
always @(*) begin
shifted = shiftl;
end
endmodule
| 7.024926 |
module slew (
clk,
in_set,
enable,
wrap,
tick,
out_val,
motion
);
parameter dw = 16;
input clk;
input [dw-1:0] in_set;
input enable; // when zero, in_set propagates directly to out_val
input wrap; // set to allow wrapping, as when value represents phase
input tick; // step out... | 7.154021 |
module slew_array (
clk,
h_write,
h_addr,
h_data,
enable,
wrap,
trig,
outv
);
parameter dw = 18;
parameter aw = 3;
input clk; // timespec 7.8 ns
input h_write;
input [aw-1:0] h_addr;
input signed [dw-1:0] h_data;
input enable; // when zero, values propagate directly to o... | 7.402725 |
module slew_xarray #(
parameter dw = 18
) (
input clk,
input enable, // when zero, just passes through
input signed [dw-1:0] setmp, // from localbus
output signed [dw-1:0] setmp_l, // to application, slew-rate-limited
input setmp_addr,
input step, // can wire to 1 for full-speed slew
... | 8.89578 |
module slew_xarray_tb;
reg clk, fail = 0;
integer cc;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("slew_xarray.vcd");
$dumpvars(5, slew_xarray_tb);
end
for (cc = 0; cc < 400; cc = cc + 1) begin
clk = 0;
#5;
clk = 1;
#5;
end
if (fail) begin
... | 8.241514 |
module slicer (
input wire signed [17:0] reference_level,
input wire signed [17:0] decision_variable,
output reg [1:0] symbol
);
always @*
if (decision_variable > reference_level) symbol = 2'b10;
else if (decision_variable > 0) symbol = 2'b11;
else if (decision_variable > -reference_level) sy... | 8.375179 |
module slice_fixed (
input clk,
input GSR,
input CE,
input SR,
input [6:1] A_61,
input [6:1] B_61,
input [6:1] C_61,
input [6:1] D_61,
input AX,
input BX,
input CX,
input DX,
output reg A,
output reg B,
output reg C,
output reg D,
output reg AQ,
... | 6.681078 |
module dsp_slice_fp32 (
clk,
enable,
clr,
funct,
chainin,
accumulate,
ax,
ay,
az,
chainout,
resulta_flopped
);
input clk;
input enable;
input clr;
input [3:0] funct;
input [31:0] chainin;
input accumulate;
input [31:0] ax;
input [31:0] ay;
input [31:0] az;
... | 6.706938 |
module //
// Date: Nov 2011 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: This only tests the ... | 8.238592 |
module SLICE_WO #(
parameter win = 64,
parameter uout = 31,
parameter lout = 18
) (
input clk_i,
input [ win-1:0] sig_i,
output [uout-lout:0] sig_o
);
reg [uout-lout:0] sig;
always @(posedge clk_i) begin
if ({sig_i[win-1], |sig_i[win-3:uout]} == 2'b01) //positive... | 7.835776 |
module SLICE_WO_32 #(
parameter win = 64,
parameter uout = 31,
parameter lout = 0
) (
input clk_i,
input [ win-1:0] sig_i,
output [uout-lout:0] sig_o
);
reg [uout-lout:0] sig;
always @(posedge clk_i) begin
if ({sig_i[win-1], |sig_i[win-3:uout]} == 2'b01) //positi... | 8.172968 |
module slider (
addrP,
lastPixelF,
trig,
M,
N,
clk,
rst
);
// Parameters
parameter ADDR_WIDTH = 8, WINDOW_N = 2;
// Outputs
output reg [ADDR_WIDTH - 1 : 0] addrP;
output reg lastPixelF;
// Inputs
input wire trig, clk, rst;
input wire [15 : 0] M, N;
// Registers
reg [15... | 7.928406 |
module SlideSwitches (
input CLK_50, //Defining the clock as an input (The onboard clock of the Kiwi is 50MHz)
input [3:0] SW, //Defining the 4 built in slide switches on the Kiwi.
output [7:0] LED //Defining the 8 built in LEDs on the Kiwi.
//Note: these definitions were made using the μLab Kiwi Pr... | 7.776276 |
module divfreq (
input CLk,
output reg CLk_div
);
reg [24:0] number;
always @(posedge CLk) begin
if (number > 50000) begin
number <= 25'b0;
CLk_div <= ~CLk_div;
end else number <= number + 1'b1;
end
endmodule
| 6.846501 |
module divfreq2 (
input CLk,
output reg CLk_div2
);
reg [24:0] number2;
always @(posedge CLk) begin
if (number2 > 3000000) begin
number2 <= 25'b0;
CLk_div2 <= ~CLk_div2;
end else number2 <= number2 + 1'b1;
end
endmodule
| 6.675631 |
module divfreq3 (
input CLk,
output reg CLk_div3
);
reg [50:0] number3;
always @(posedge CLk) begin
if (number3 > 5000000) begin
number3 <= 25'b0;
CLk_div3 <= ~CLk_div3;
end else number3 <= number3 + 1'b1;
end
endmodule
| 6.801986 |
module divfreq4 (
input CLk,
output reg CLk_div4
);
reg [50:0] number4;
always @(posedge CLk) begin
if (number4 > 75000000) begin
number4 <= 25'b0;
CLk_div4 <= ~CLk_div4;
end else number4 <= number4 + 1'b1;
end
endmodule
| 6.77823 |
module slide_window_conv #(
parameter In_d_W = 8,
In_Add_W = 4,
R_N = 5,
C_N = 5,
R_F = 3,
C_F = 3,
P = 0,
S = 1,
Timeperiod = 10
) (
input clk,
clk_en,
rst,
clr,
en_wr,
en_rd,
wr,
en_MAC,
en_MAC_out, //wr=1 (Write), wr=0 (Read)
input [(C_N*R_... | 6.964635 |
module implements a sliding average logic.
* With every trigger cycle the average of the previous output value
* and the sampled value is calculated:
* new_output <= (previous_output + sample_value)/2
*/
module average_sliding
#(
parameter bitwidth_sample = 12,
parameter initial_accumulator_v... | 6.904081 |
module concatenates a preconfigured number of
* sliding average modules in an attempt to achieve a more noise-free signal.
*/
module average_sliding_iterative
#(
parameter bitwidth_sample = 12,
parameter initial_accumulator_value = 0,
parameter iteration_count = 3
)
(
... | 7.734569 |
module sliding_window (
input wire clk,
input wire enable,
input wire enable_process,
input wire [15:0] wav_input,
input wire [31:0] idx,
output reg [(2**16)-1:0] window
);
parameter sample_size = 2 ** 12;
parameter width = 16;
parameter file_size = 4365900;
reg [file_size*width-1:0] w... | 8.418455 |
module slink_apb_driver #(
parameter ADDR_WIDTH = 8,
parameter CLK_PER_NS = 10
) (
input wire apb_clk,
input wire apb_reset,
output reg [ADDR_WIDTH-1:0] apb_paddr,
output reg apb_pwrite,
output reg apb_psel,
output ... | 6.987987 |
module slink_app_monitor #(
parameter APP_DATA_WIDTH = 32
) (
input wire link_clk,
input wire link_reset,
input wire rx_sop,
input wire [ 7:0] rx_data_id,
input wire [ 15:0] rx_word_count,
input wire [APP_DATA_WIDTH-1:0] rx_app_data,
input... | 6.941233 |
module slink_attribute_base #(
parameter ADDR = 16'h0,
parameter WIDTH = 1,
parameter RESET_VAL = {WIDTH{1'b0}},
parameter NAME = "unNamed",
parameter IS_RO = 0
) (
input wire clk,
input wire reset,
input wire hard_reset_cond,
input wire [15:0] link_attr_addr,
... | 7.475466 |
module slink_clk_control #(
parameter NUM_RX_LANES = 4
) (
input wire core_scan_mode,
input wire core_scan_clk,
input wire core_scan_asyncrst_ctrl,
input wire apb_clk,
input wire apb_reset,
output wire apb_clk_scan,
output wire apb_reset_scan,
input wire refclk,
input wire phy... | 7.229424 |
module slink_crc_8_16bit_compute (
input wire clk,
input wire reset,
input wire [ 7:0] data_in,
input wire valid,
input wire init,
input wire [15:0] crc_prev,
output wire [15:0] crc_next,
output reg [15:0] crc
);
wire [15:0] crc_in16;
wire [15:0] ... | 7.263547 |
module slink_fc_replay_addr_sync #(
parameter ADDR_WIDTH = 4
) (
input wire wclk,
input wire wreset,
input wire [ADDR_WIDTH-1:0] waddr,
input wire rclk,
input wire rreset,
output wire [ADDR_WIDTH-1:0] raddr
);
wire ... | 7.281095 |
module slink_generic_pstate_ctrl (
input wire refclk,
input wire refclk_reset,
input wire enable,
input wire link_clk,
input wire link_clk_reset,
input wire link_active,
input wire in_px_state,
input wire [7:0] swi_1us_tick_count,
input wire [7:0] swi_inactivity_count,
input wi... | 6.719737 |
module slink_generic_rx_router #(
parameter NUM_CHANNELS = 8,
parameter RX_APP_DATA_WIDTH = 64
) (
input wire clk,
input wire reset,
input wire rx_sop,
input wire [ 7:0] rx_data_id,
input wire [ 15:0] rx_word_count,
input wir... | 6.719737 |
module slink_generic_tx_router #(
parameter NUM_CHANNELS = 8,
parameter TX_APP_DATA_WIDTH = 64
) (
input wire clk,
input wire reset,
input wire enable,
input wire [ NUM_CHANNELS-1:0] tx_sop_ch,
input wire [ (NUM_CHAN... | 6.719737 |
module slink_gpio_model (
input wire oen,
output wire sig_in,
inout wire pad
);
assign pad = oen ? 1'b0 : 1'bz;
pullup (weak1) pad_pu (pad);
assign sig_in = pad === 1'bz ? 1'b1 : pad;
endmodule
| 8.227232 |
module slink_ll_rx_pkt_filt (
input wire clk,
input wire reset,
input wire sop,
input wire [ 7:0] data_id,
input wire [15:0] word_count,
input wire valid,
output wire sop_app,
output wire valid_app
);
`include "slink_includes.vh"
wire pkt_is_internal;
wire attr_... | 7.34087 |
module slink_simple_io_phy_model #(
parameter IS_MASTER = 1,
parameter CLK_PER_NS = 2,
parameter DATA_WIDTH = 8,
parameter NUM_TX_LANES = 4,
parameter NUM_RX_LANES = 4
) (
input wire clk_enable,
input wire clk_idle,
output wire clk_ready,
inout wire clk_byteclk,
output... | 6.860006 |
module slink_sync_pulse (
input wire clk_in,
input wire clk_in_reset,
input wire data_in,
input wire clk_out,
input wire clk_out_reset,
output wire data_out
);
reg clk_in_pulse;
always @(posedge clk_in or posedge clk_in_reset) begin
if (clk_in_reset) begin
clk_in_pulse <= 1'b0... | 6.571673 |
module slink_demet_reset (
input wire clk,
input wire reset,
input wire sig_in,
output wire sig_out
);
reg [1:0] demet_flops;
assign sig_out = demet_flops[0];
always @(posedge clk or posedge reset) begin
if (reset) begin
demet_flops <= 2'b00;
end else begin
demet_flops <=... | 6.881975 |
module slink_demet_set (
input wire clk,
input wire set,
input wire sig_in,
output wire sig_out
);
reg [1:0] demet_flops;
assign sig_out = demet_flops[0];
always @(posedge clk or posedge set) begin
if (set) begin
demet_flops <= 2'b11;
end else begin
demet_flops <= {sig_in... | 6.922732 |
module slink_reset_sync (
input wire clk,
input wire scan_ctrl,
input wire reset_in,
output wire reset_out
);
wire reset_in_ff2;
wire reset_in_int;
assign reset_in_int = ~scan_ctrl & reset_in;
slink_demet_set u_demet_set (
.clk (clk),
.set (reset_in_int),
.sig_in (1... | 8.500962 |
module slink_clock_mux (
input wire clk0,
input wire clk1,
input wire sel,
output wire clk_out
);
assign clk_out = sel ? clk1 : clk0;
endmodule
| 6.904644 |
module slink_clock_inv (
input wire clk_in,
output wire clk_out
);
assign clk_out = ~clk_in;
endmodule
| 7.662846 |
module slink_clock_buf (
input wire clk_in,
output wire clk_out
);
assign clk_out = clk_in;
endmodule
| 7.271512 |
module slink_clock_gate (
input wire clk_in,
input wire reset,
input wire core_scan_mode,
input wire enable,
input wire disable_clkgate,
output wire clk_out
);
wire clk_en;
wire enable_ff2;
slink_demet_reset u_slink_demet_reset (
.clk (clk_in),
.reset (reset),
... | 8.17648 |
module slink_clock_or (
input wire clk0,
input wire clk1,
output wire clk_out
);
assign clk_out = clk0 | clk1;
endmodule
| 8.145422 |
module slink_clock_mux_sync (
input wire reset0,
input wire reset1,
input wire sel,
input wire clk0,
input wire clk1,
output wire clk_out
);
wire clk0_inv;
wire clk1_inv;
wire sel_inv;
wire sel0_in;
wire sel1_in;
wire clk0_out;
wire clk1_out;
wire clk_out_pre;
reg sel0_f... | 6.904644 |
module slink_fifo_top #(
parameter DATA_SIZE = 40,
parameter ADDR_SIZE = 4
) (
input wire wclk,
input wire wreset,
input wire winc,
input wire rclk,
input wire rreset,
input wire rinc,
... | 6.849978 |
module slink_fifomem #(
parameter DATA_SIZE = 40,
parameter ADDR_SIZE = 4
) (
input wire wclk,
input wire rclk,
input wire wclken,
input wire read_en,
input wire wreset,
input wire wfull... | 6.915958 |
module slink_multibit_sync #(
parameter DATA_SIZE = 8
) (
input wire wclk,
input wire wreset,
input wire winc,
output wire wready,
input wire [DATA_SIZE-1:0] wdata,
input wire rclk,
input wire ... | 7.787808 |
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