code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module stage_30 (
rst_n,
clk,
valid_in,
x_in,
x_out,
valid_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input clk;
input rst_n;
input [DATA_WIDTH-1:0] x_in;
input valid_in;
output [DATA_WIDTH-1:0] x_out;
output valid... | 7.371967 |
module stage_31 (
rst_n,
clk,
valid_in,
x_in,
x_out,
valid_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input clk;
input rst_n;
input [DATA_WIDTH-1:0] x_in;
input valid_in;
output [DATA_WIDTH-1:0] x_out;
output valid... | 7.028499 |
module Stage_9_block (
clk,
reset,
enb,
dataIn,
validIn,
dataOut,
validOut
);
input clk;
input reset;
input enb;
input dataIn; // ufix1
input validIn;
output dataOut; // ufix1
output validOut;
wire Stage_9_out1; // ufix1
wire Stage_9_out2;
Stage_9 u_Stage_9 (
... | 6.86657 |
module stage_A (
input clk,
input reset,
output DOR,
input DIR,
input ack_from_next,
output ack_prev,
input [7:0] data_in,
output [7:0] data_out
);
parameter IDLE = 1'd0;
parameter WAITING_ACK = 1'd1;
reg state = IDLE;
reg [7:0] data_out_reg = 8'd0;
reg DOR_reg = 0;
reg ack... | 7.928488 |
module stage_B (
input clk,
input reset,
output DOR,
input DIR,
input ack_from_next,
output ack_prev,
input [7:0] data_in,
output [7:0] data_out
);
parameter IDLE = 1'd0;
parameter WAITING_ACK = 1'd1;
reg state = IDLE;
reg [7:0] data_out_reg = 8'd0;
reg DOR_reg = 0;
reg ack... | 7.786472 |
module stage_C (
input clk,
input reset,
output DOR,
input DIR,
input ack_from_next,
output ack_prev,
input [7:0] data_in,
output [7:0] data_out
);
parameter IDLE = 1'd0;
parameter WAITING_ACK = 1'd1;
reg state = IDLE;
reg [7:0] data_out_reg = 8'd0;
reg DOR_reg = 0;
reg ack... | 7.931829 |
module stage_control ();
// stage control
always @(posedge clock) begin
if (reset) stage <= 2'b00;
else if (load_stage) stage <= next_stage;
end
always @(*) begin
if (iSW[1:0] == 2'b11) next_stage = iSW[3:2];
else if (state == ST_INIT) next_stage = 2'b00;
else next_stage = (stage + 1) % 4;
... | 7.530452 |
module clz32 (
output reg [31:0] result,
input [31:0] value
);
reg [15:0] val16;
reg [ 7:0] val8;
reg [ 3:0] val4;
always @* begin
result[31:6] = 0;
if (value == 32'b0) begin
result[5:0] = 32;
end else begin
result[5] = 0;
result[4] = value[31:16] == 16'b0;
val16... | 6.838726 |
module stage_EXEMEM (
clk,
nrst,
ALUResult,
ALUResult_out,
rd_data2,
rd_data2_out,
MemWrite,
Branch,
MemRead,
RegWrite,
MemToReg,
ALUOp,
ALUSrc,
Jump,
sd,
ld,
bne,
wmask,
MemWrite_o,
Branch_o,
MemRead_o,
RegWrite_o,
MemToReg_o,
... | 7.090998 |
module stage_EXMEM_tb ();
reg clk, rst, en;
reg [31:0] pc4;
reg [31:0] opcode1, opcode2;
reg [31:0] instruction;
reg [4:0] rs2, rd;
reg [3:0] alu_sel;
reg [2:0] wb_sel;
initial begin
$dumpfile("exmem_dump.vcd");
$dumpvars();
$display("test for EXMEM stage, are the correct values latching")... | 6.971327 |
module stage_fetch #(
parameter ADDR_MIN = 'h3000,
parameter ADDR_MAX = 'h5000,
parameter ADDR_HANDLER = 'h4180
) (
input wire clk,
input wire reset,
input wire [31:0] next_pc,
output reg [31:0] pc,
output wire [31:0] instr,
output wire [`EXC_CODE_LEN - 1:0] exc
);
localparam WORD_... | 9.02626 |
module stage_IDEXE (
clk,
nrst,
inst_IDEXE,
rd_data1,
rd_data2,
jal_imm_in,
jalr_imm_in,
branch_imm_in,
sd_imm_in,
addi_imm_in,
jal_imm_out,
jalr_imm_out,
branch_imm_out,
sd_imm_out,
addi_imm_out,
inst_IDEXE_out,
rd_data1_out,
rd_data2_out,
Mem... | 7.220464 |
module stage_IDEX ();
reg clk, rst, en;
reg [31:0] instruction, pc, pc4, nop;
initial begin
$dumpfile("idex_dump.vcd");
$dumpvars();
$display("test for IDEX stage, are the correct values latching");
$monitor("PC+4:[%h] PC:[%h] INST:[%h] op1:[%h] op2:[%h] RD:[%b] wb_sel:[%b]",
stage... | 7.221435 |
module stage_if (
input wire rst,
input wire [`MemAddrBus] pc_i,
input wire [ `RegBus] mem_data_i,
input wire mem_busy,
input wire mem_done,
input wire br,
input wire right_one,
output reg mem_... | 7.09664 |
module stage_IFID (
clk,
nrst,
pc,
out_pc,
inst_IFID,
out_inst
);
input clk, nrst;
input [31:0] pc;
input [31:0] inst_IFID;
output reg [31:0] out_pc, out_inst;
always @(posedge clk) begin
if (!nrst) out_pc <= 32'd0;
else begin
out_pc <= pc;
out_inst <= inst_IFID... | 7.528671 |
module stage_IFID_tb ();
reg clk, rst, en;
reg [2:0] pc_sel_in;
initial begin
$dumpfile("ifid_dump.vcd");
$dumpvars();
$display("test for IFID stage, are the correct values latching");
$monitor("PC:[%h] PC+4:[%h] INST:[%h]", stageIFID.pc_out, stageIFID.pc4_out,
stageIFID.instructio... | 6.631196 |
module stage_MEMWB (
clk,
nrst,
rdata,
ALUResult,
ALUResult_out,
rdata_out,
MemWrite,
Branch,
MemRead,
RegWrite,
MemToReg,
ALUOp,
ALUSrc,
Jump,
sd,
ld,
bne,
wmask,
MemWrite_o,
Branch_o,
MemRead_o,
RegWrite_o,
MemToReg_o,
ALU... | 7.201803 |
module stage_MEMWB_tb ();
reg clk, rst, en;
initial begin
$dumpfile("memwb_dump.vcd");
$dumpvars();
$display("test for MEMEX stage, are the correct values latching");
// this one should show before and after MEMWB
//$monitor("", );
clk <= 1'b1;
rst <= 1;
en <= 1;
#100 $finis... | 6.770492 |
module stage_mem_bias (
input bias_int_32_3 bias_int,
input [31:0] bias_int_wr_data,
input clk,
input reset,
output [31:0] bias_int_rd_data
);
// Parameters
// Wires
wire [31:0] read_0; // <32,0>
wire [3... | 7.778361 |
module stage_mem_data (
input clk,
input data_int_32_6 data_int,
input [31:0] data_int_wr_data,
input reset,
output [31:0] data_int_rd_data
);
// Parameters
// Wires
wire [31:0] read_0; // <32,0>
wire [3... | 6.766413 |
module STAGE_REG_FD (
input reset_n,
input clk,
input wren,
input [31:0] in_ins,
input [31:0] in_next_pc,
output reg [31:0] ins,
output reg [31:0] next_pc
);
always @(posedge clk) begin
if (!reset_n) begin
ins <= 0;
next_pc <= 0;
end else if (wren) begin
ins <= i... | 8.513962 |
module STAGE_REG_DE (
input reset_n,
input clk,
input wren,
input [31:0] in_next_pc,
input [31:0] in_data0,
input [31:0] in_data1,
input [4:0] in_dst_reg,
input [31:0] in_ins,
input in_dec_alu_src,
input in_dec_mem_to_reg,
input in_dec_reg_write,
input in_dec_mem_read,
... | 7.538748 |
module STAGE_REG_EM (
input reset_n,
input clk,
input wren,
input [31:0] in_next_pc,
input [31:0] in_branch_pc,
input [31:0] in_alu_result,
input [31:0] in_mem_write_data,
input [4:0] in_dst_reg,
input [31:0] in_ins,
input in_dec_mem_to_reg,
input in_dec_reg_write,
input ... | 7.326317 |
module STAGE_REG_MW (
input reset_n,
input clk,
input wren,
input [31:0] in_mem_data,
input [31:0] in_alu_result,
input [4:0] in_dst_reg,
input [31:0] in_return_pc,
input in_dec_mem_to_reg,
input in_dec_reg_write,
input in_dec_pc_to_ra,
output reg [31:0] mem_data,
output ... | 7.992598 |
module PC (
input reset_n,
input clk,
input wren,
input [31:0] jmp_to,
output [31:0] pc_data
);
reg [31:0] _pc_data;
assign pc_data = _pc_data;
always @(posedge clk) begin
if (!reset_n) begin
_pc_data <= 0;
end else if (wren) begin
_pc_data <= jmp_to;
end
end
end... | 7.578567 |
module to check execution
module exec_tb();
//Control Unit Signals
reg clk = 0;
reg ALU_Src=1'b1; //Use immediate value for addition
reg regWrite_receive = 1;
reg Mem_Write_receive=1'b0;
reg [1:0] ALU_Op_receive = 2'b10; //Add
reg Mem_to_Reg_receive=1'b0;
reg Mem_Read_receive=1'b1;
reg Branch_recei... | 7.727827 |
module stage_URAM #(
parameter INDEX_WIDTH = 12
) (
input k,
input [INDEX_WIDTH-1:0] q,
input [INDEX_WIDTH-1:0] pre,
output [INDEX_WIDTH-1:0] out
);
//------------------output of and ------------------------------------//
wire [INDEX_WIDTH-1:0] out_and;
//------------------u_module-------... | 7.512729 |
module STALL
(
input i_clk ,
input i_rst_n ,
input i_signal ,
input i_clr ,
output o_stall
);
reg r_stall;
assign o_stall = r_stall;
always@(posedge i_clk or negedge... | 6.968212 |
module: StallControllBlock
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module StallControllBlock_TB;
// Inputs
reg reset;
reg clk;
reg [23:0] ins;
// Outputs
wire Stall_pm;
wir... | 6.981038 |
module stallctrl (
//from if
input wire stall_from_if,
//from id
input wire stall_from_id,
//from mem
input wire stall_from_mem,
//to pc id_id id_ex ex_mem mem_wb
output reg [5:0] stall //stall[0] stand for pc stop 1stand for stop
);
always @(*) begin
stall = 0;
if (stall_fro... | 6.556049 |
module Staller (
input clk,
input rst,
input alu_full,
input bra_full,
input lsm_full,
input rob_full,
input icache_enable,
// with Decoder
input [`Opcode_Width-1 : 0] op,
// with PC
input pc_locked,
output reg pc_stall,
// with icache
output reg icache_stall,
... | 6.729616 |
module stalling_unit (
input EX_MemRead,
input [4:0] EX_rd,
input [4:0] ID_rs1,
input [4:0] ID_rs2,
output MemStall
);
assign MemStall = EX_MemRead & (EX_rd == ID_rs1 | EX_rd == ID_rs2);
endmodule
| 6.994513 |
module produces a "ready" signal;
// if "ready" is not asserted, the read
// or write did not take place.
//
// Reads happen combinationally with zero delay in cycles that ready is high.
// Writes occur on rising clock edge in cycles that ready is high.
// Concurrent read and write not allowed.
//
// On reset, memory l... | 6.523855 |
module produces a "ready" signal;
// if "ready" is not asserted, the read
// or write did not take place.
//
// Reads happen combinationally with zero delay in cycles that ready is high.
// Writes occur on rising clock edge in cycles that ready is high.
// Concurrent read and write not allowed.
//
// On reset, memory l... | 6.523855 |
module stallmux (
wb,
m,
ex,
MemToReg,
RegWrite,
MemRead,
MemWrite,
RegDst,
AluOp,
AluSrc,
AluMux,
HiLoEnable,
HazardMuxSelect
);
output [1:0] wb;
output [1:0] m;
output [6:0] ex;
reg [ 1:0] wb;
reg [ 1:0] m;
reg [13:0] ex;
input MemToReg, RegWrite, Me... | 6.622616 |
module stall_controller (
input [4:0] IDA1,
input [1:0] Tuse1,
input [4:0] IDA2,
input [1:0] Tuse2,
input [4:0] DEA3,
input DERegWE,
input [1:0] DETnew,
input [4:0] EMA3,
input EMRegWE,
input [1:0] EMTnew,
input [4:0] MWA3,
input MWRegWE,
input [1:0] MWTnew,
//Bus... | 7.056201 |
module stall_control_block (
stall,
stall_pm,
op,
clk,
reset
);
input [5:0] op;
input clk, reset;
output stall, stall_pm;
//Output of AND Gates will be stored here
wire HLT, LD_op, JUMP;
// Assigning appropriate values
assign HLT = (op[0] && ~op[1] && ~op[2] && ~op[3] && op[4] && ~op... | 7.056201 |
module
module d_flip_flop(Q,D,clk,reset);
output reg Q;
input D, clk, reset;
always@(posedge clk)
begin
if(reset)
Q <= D;
else
Q <= 1'b0;
end
endmodule
| 7.744862 |
module: stall_control_block
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module stall_control_block_tb;
// Inputs
reg [5:0] op;
reg clk;
reg reset;
// Outputs
wire stall;
wire s... | 7.151925 |
module stall_control_module (
stall,
stall_pm,
ins_pm,
clk,
reset
);
output stall, stall_pm; //declaring output
input clk, reset; //declaring input
input [19:0] ins_pm; //declaring input of 20 bits
wire [4:0] temp; //declaring wire of 5 bits
wire Jump, LD, HLT, d1, d2, d3; //declar... | 7.056201 |
module of our microprocessor.
///////////////////////////////////////////////////////////////////
module stall_control_tb;
// Inputs
reg [19:0] ins_pm;
reg clk;
reg reset;
// Outputs
wire stall;
wire stall_pm;
// Instantiate the Unit Under Test (UUT)
stall_control_module uut (
.stall(stall),
.stall_p... | 7.266313 |
module Stall_Detection_Unit (
input [31:0] InstrD,
input [31:0] InstrE,
input [31:0] InstrM,
input IntReq,
output stall
);
Instruction_Decoder ID_D (
.Instr(InstrD),
.cal_r(cal_r_D),
.cal_s(cal_s_D),
.cal_il(cal_il_D),
.cal_ia(cal_ia_D),
.load(load_D),
.s... | 6.686589 |
module stall_solve (
input nop,
input regwrite,
input [2:0] aluc,
input alusrc,
input regdst,
input memtoreg,
input memwrite,
input [1:0] extop,
input branch,
input memread,
output regwriteD,
output [2:0] alucD,
output alusrcD,
output regdstD,
output memtoregD... | 6.674315 |
module stall_unit (
//from mdu
input busy_from_mdu,
input finish_from_mdu,
input [`ZCRV_REG_SIZE-1:0] rd_from_mdu,
//from other clk id/ex stage
input [`ZCRV_REG_SIZE-1:0] rs1_from_id,
input [`ZCRV_REG_SIZE-1:0] rs2_from_id,
input [`ZCRV_REG_S... | 6.713718 |
module
*
* Copyright notice:
* Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford
* Junior University
*
* Licence:
* This file is part of the NetFPGA 10G development base package.
*
* This file is free code: you can redistribute it and/o... | 6.70034 |
module standardizer #(
parameter EXP_SIZE = `EXP_SIZE,
parameter MANTIS_SIZE = `MANTIS_SIZE
) (
exp_in,
mantis_in,
operator_in,
loss,
exp_out,
mantis_out
);
// Inputs
input [EXP_SIZE -1:0] exp_in; // input exponent
input [(MANTIS_SIZE+3)-1:0] mantis_in; // input mantissa... | 6.604843 |
module standard_deviation_filter #(
parameter WIDTH = 14,
parameter WINDOW_WIDTH = 7
) (
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out,
input wire reset,
input wire clk
);
wire [WIDTH*2-1:0] variance_out;
variance #(
.WIDTH(WIDTH),
.WINDOW_WIDTH(WINDOW_WID... | 8.302781 |
module stand_1bit (
input clk,
input enable,
input din,
output reg dout
);
/**
* Always checking for positive edge of clock to make the changes
* on output , based on the input and register enable status.
*
*/
always @(posedge clk) begin
if (enable) dout <= din;
end
endmodule
| 7.198945 |
module cordic_sin_cos (
input clock,
input reset,
input [63:0] io_theta,
output [63:0] io_sin,
output [63:0] io_cos
);
wire cordic_unit_clock; // @[Cordic_CR.scala 145:45]
wire cordic_unit_reset; // @[Cordic_CR.scala 145:45]
wire [63:0] cordic_unit_io_x; // @[Cordic_CR.scal... | 7.055288 |
module ComplexMul (
input [63:0] io_op1_re,
input [63:0] io_op1_im,
input [63:0] io_op2_re,
input [63:0] io_op2_im,
output [63:0] io_res_re,
output [63:0] io_res_im
);
wire [63:0] _k1_T_2 = $signed(io_op1_re) + $signed(io_op1_im); // @[Complex_Operater.scala 38:35]
wire [127:0] k1 = $si... | 7.643712 |
module kronecker_v1 (
input [63:0] io_matrixA_1_re,
input [63:0] io_matrixA_1_im,
input [63:0] io_matrixB_1_re,
input [63:0] io_matrixB_1_im,
output [63:0] io_matrixOut_0_re,
output [63:0] io_matrixOut_0_im,
output [63:0] io_matrixOut_1_re,
output [63:0] io_matrixOut_1_im,
output... | 6.557244 |
module ComplexAdd (
input [63:0] io_op1_re,
input [63:0] io_op1_im,
input [63:0] io_op2_re,
input [63:0] io_op2_im,
output [63:0] io_res_re,
output [63:0] io_res_im
);
assign io_res_re = $signed(io_op1_re) + $signed(io_op2_re); // @[Complex_Operater.scala 7:26]
assign io_res_im = $signe... | 8.602364 |
module cordic_cv (
input clock,
input reset,
input [63:0] io_x,
input [63:0] io_y,
output [63:0] io_theta,
output [63:0] io_r
);
wire cordic_cv_unit_clock; // @[Cordic_CV.scala 104:30]
wire cordic_cv_unit_reset; // @[Cordic_CV.scala 104:30]
wire [63:0] cordic_cv_unit_io... | 7.286598 |
module ComplexSub (
input [63:0] io_op1_re,
input [63:0] io_op1_im,
input [63:0] io_op2_re,
input [63:0] io_op2_im,
output [63:0] io_res_re,
output [63:0] io_res_im
);
assign io_res_re = $signed(io_op1_re) - $signed(io_op2_re); // @[Complex_Operater.scala 22:26]
assign io_res_im = $sign... | 8.653321 |
module starfield_top (
input wire [0 : 0] clk, // clock
input wire [0 : 0] reset, // reset
output wire [0 : 0] hsync, // horizontal sync
output wire [0 : 0] vsync, // vertical sync
output wire [2 : 0] rgb // RGB VGA
);
/*******************************************************
* ... | 6.655319 |
module StartButton (
input wire clk,
input wire rst_n,
input wire [3:0] key_val,
input wire key_flag,
input wire [1:0] state,
output reg start = 0
);
parameter INITIAL = 2'b00;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) start <= 0;
else if (state != INITIAL) start <= 0;
... | 8.192184 |
module StartCounter #(
////////////////////////////////////////////////////
// Parameters
parameter width = 4
) (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
CountEn,
Start,
output reg [width-1:0] Count,
output reg End,
Busy
);
wire... | 7.055272 |
module StartDelay (
clock,
reset,
trigger,
timeOut
);
input clock; // NbN
input reset; // Zbg
input trigger; // NM
output timeOut; // ^CAEgM
reg [2:0] StartDelayCount; // 3rbg̃JE^
always @(posedge clock or negedge reset) begin
if (!reset) begin
StartDelayCount <= 0; // Zbg
... | 7.07327 |
module starter3e (
input CLK_50MHZ,
input [3:0] SW,
input BTN_EAST,
input BTN_NORTH,
input BTN_SOUTH,
input BTN_WEST,
output [7:0] LED
);
wire [9:0] outputs;
assign LED = outputs[7:0];
top top (
.clock (CLK_50MHZ),
.reset_n(BTN_NORTH),... | 7.120118 |
module startscreen_rom (
input clk,
input [7:0] x,
input [6:0] y,
output reg [2:0] dout
);
parameter IMAGE_FILE = "startscreen.mem";
wire [14:0] addr = 160 * y + x;
reg [2:0] mem[0:19199];
initial $readmemh(IMAGE_FILE, mem);
always @(posedge clk) dout <= mem[addr];
en... | 7.426057 |
module startStopConfig (
clk,
rst_n,
start,
stop,
clr,
din,
sin,
dout,
sout
);
input clk;
input rst_n;
input start;
input stop;
input clr;
input [7:0] din;
input sin;
output [7:0] dout;
output sout;
reg enable; //1:ok 2:nonono
always @(posedge clk or neg... | 7.190821 |
module startStopLapReset_LCD ( CLK_50M,
SW,
PUSH_BTN_SS, PUSH_BTN_LR,
LED,
LCD_DB,
LCD_E, LCD_RS, LCD_RW);
input CLK_50M;
input SW;
input PUSH_BTN_SS;
input PUSH_BTN_LR;
output [7:0] LED;
output [7:0] LCD_DB;
output LCD_E;
output LCD_RS;
output LCD_RW;
wire [15:0] wb_counter;
wire [... | 6.955501 |
module StartStopSequencer (
clock,
reset,
start,
run,
stop,
running
);
input clock; // NbN
input reset; // Zbg
input start; // Q[Jn
input run; // NE
input stop; // Xgbv
output running; // ꂪ8iJE^ւenableMɂrunԂ\M
wire clock, reset;
wire start, run, stop; // X^[gXCb`̐Mstartr... | 6.731442 |
module startsync ( /*AUTOARG*/
// Outputs
startsync_sampler_start_r_sync,
// Inputs
clk_sampler,
rst_sampler_n_sync,
samplertop_startsync_start_sync
);
`include "sync_params.v"
//-------------Input Ports--------------------
input clk_sampler;
input rst_sampler_n_sync;
input samplertop... | 7.058302 |
module startup #(
parameter RESET_TIMEOUT = 32'h0000FFFF
) (
input clk,
output reg startup_rst = 1
);
//Local Parameters
//Registers/Wires
reg [31:0] startup_count;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @(posedge clk) begin
if (startup_count < RESET_TIMEOUT) be... | 7.419674 |
module startup_wrapper #(
) (
// Flash Interface Pins
output wire [3:0] flash_DQ_I,
input wire [3:0] flash_DQ_O,
input wire [3:0] flash_DQ_tri_ctrl,
input wire flash_CS_N,
input wire flash_CS_N_tri_ctrl,
input wire flash_clk,
output wire startup_eos
);
// ... | 7.588911 |
module start_bgm (
input mp3_clk,
input rst,
input DREQ,
output RSET,
output CS,
output DCS,
output MOSI,
output SCLK
);
parameter MUSIC_SIZE = 21698;
wire [20:0] mp3_addr;
wire [31:0] mp3_data;
wire music_over;
mp3_driver #(
.MUSIC_SIZE(MUSIC_SIZE)
) display_musi... | 6.998339 |
module start_bit_det (
input clk,
input n_Rst,
input data_in,
output wire start_detected
);
reg Q_1, Q_2, Q_3;
always @(posedge clk, negedge n_Rst) begin
if (n_Rst == 1'b0) begin
Q_1 <= 1'b1;
Q_2 <= 1'b1;
Q_3 <= 1'b1;
end else begin
Q_3 <= Q_2;
Q_2 <= Q_1;
... | 6.610416 |
module start_for_And_3_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:D... | 6.904696 |
module start_for_And_3_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset... | 6.904696 |
module start_for_app_aes_end_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd13;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL... | 6.739074 |
module start_for_app_aes_end_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd13;
input clk;
inp... | 6.739074 |
module start_for_app_aes_process_0_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0... | 6.739074 |
module start_for_app_aes_process_0_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
... | 6.739074 |
module start_for_app_aes_process_1_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0... | 6.739074 |
module start_for_app_aes_process_1_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
... | 6.739074 |
module start_for_app_aes_process_2_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd6;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0... | 6.739074 |
module start_for_app_aes_process_2_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd6;
input clk;
... | 6.739074 |
module start_for_app_aes_process_3_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0... | 6.739074 |
module start_for_app_aes_process_3_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd7;
input clk;
... | 6.739074 |
module start_for_app_aes_process_4_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0... | 6.739074 |
module start_for_app_aes_process_4_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd8;
input clk;
... | 6.739074 |
module start_for_app_aes_process_5_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0... | 6.739074 |
module start_for_app_aes_process_5_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd9;
input clk;
... | 6.739074 |
module start_for_app_aes_process_6_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd10;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:... | 6.739074 |
module start_for_app_aes_process_6_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd10;
input clk;... | 6.739074 |
module start_for_app_aes_process_7_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd11;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:... | 6.739074 |
module start_for_app_aes_process_7_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd11;
input clk;... | 6.739074 |
module start_for_app_aes_process_8_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd12;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:... | 6.739074 |
module start_for_app_aes_process_8_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd12;
input clk;... | 6.739074 |
module start_for_app_aes_start_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SR... | 6.739074 |
module start_for_app_aes_start_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
in... | 6.739074 |
module start_for_app_conv_combine_l0_0_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH... | 6.739074 |
module start_for_app_conv_combine_l0_0_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd9;
input c... | 6.739074 |
module start_for_app_conv_combine_l0_1_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd13;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDT... | 6.739074 |
module start_for_app_conv_combine_l0_1_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd13;
input ... | 6.739074 |
module start_for_app_conv_combine_l0_2_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd5;
parameter DEPTH = 32'd17;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDT... | 6.739074 |
module start_for_app_conv_combine_l0_2_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd5;
parameter DEPTH = 32'd17;
input ... | 6.739074 |
module start_for_app_conv_combine_l0_3_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd5;
parameter DEPTH = 32'd21;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDT... | 6.739074 |
module start_for_app_conv_combine_l0_3_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd5;
parameter DEPTH = 32'd21;
input ... | 6.739074 |
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