code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module stage_30 (
rst_n,
clk,
valid_in,
x_in,
x_out,
valid_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input clk;
input rst_n;
input [DATA_WIDTH-1:0] x_in;
input valid_in;
output [DATA_WIDTH-1:0] x_out;
output valid_out;
reg valid;
reg [DATA_WIDTH-1:0] x;
assign valid_out = valid;
assign x_out = x;
always @(posedge clk) begin
if (!rst_n) begin
valid <= 1'b0;
x <= {DATA_WIDTH{1'b0}};
end else begin
if (valid_in) begin
x <= x_in;
valid <= valid_in;
end else begin
x <= {DATA_WIDTH{1'b0}};
valid <= 1'b0;
end
end
end
endmodule
| 7.371967 |
module stage_31 (
rst_n,
clk,
valid_in,
x_in,
x_out,
valid_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input clk;
input rst_n;
input [DATA_WIDTH-1:0] x_in;
input valid_in;
output [DATA_WIDTH-1:0] x_out;
output valid_out;
reg valid;
reg [DATA_WIDTH-1:0] x;
assign valid_out = valid;
assign x_out = x;
always @(posedge clk) begin
if (!rst_n) begin
valid <= 1'b0;
x <= {DATA_WIDTH{1'b0}};
end else begin
if (valid_in) begin
x <= x_in;
valid <= valid_in;
end else begin
x <= {DATA_WIDTH{1'b0}};
valid <= 1'b0;
end
end
end
endmodule
| 7.028499 |
module Stage_9_block (
clk,
reset,
enb,
dataIn,
validIn,
dataOut,
validOut
);
input clk;
input reset;
input enb;
input dataIn; // ufix1
input validIn;
output dataOut; // ufix1
output validOut;
wire Stage_9_out1; // ufix1
wire Stage_9_out2;
Stage_9 u_Stage_9 (
.clk(clk),
.reset(reset),
.enb(enb),
.dataIn(dataIn), // ufix1
.validIn(validIn),
.dataOut(Stage_9_out1), // ufix1
.validOut(Stage_9_out2)
);
assign dataOut = Stage_9_out1;
assign validOut = Stage_9_out2;
endmodule
| 6.86657 |
module stage_A (
input clk,
input reset,
output DOR,
input DIR,
input ack_from_next,
output ack_prev,
input [7:0] data_in,
output [7:0] data_out
);
parameter IDLE = 1'd0;
parameter WAITING_ACK = 1'd1;
reg state = IDLE;
reg [7:0] data_out_reg = 8'd0;
reg DOR_reg = 0;
reg ack_prev_reg = 0;
reg [7:0] data_in_buffer;
assign data_out = data_out_reg;
assign DOR = DOR_reg;
assign ack_prev = ack_prev_reg;
always @(posedge clk) begin
if (reset) begin
state <= IDLE;
data_out_reg <= 0;
DOR_reg <= 0;
ack_prev_reg <= 0;
end else begin
case (state)
IDLE: begin
if (DIR) begin
$display("stage_A receives input_data %d", data_in);
state <= WAITING_ACK;
ack_prev_reg <= 1;
DOR_reg <= 1;
end
data_in_buffer <= data_in;
data_out_reg <= data_in + 1;
end
WAITING_ACK: begin
if (ack_from_next) begin
$display("stage_A got ACK form stage_B");
DOR_reg <= 0;
state <= IDLE;
end else begin
$display("stage_A waits for ACK from stage_B");
state <= WAITING_ACK;
DOR_reg <= 1;
end
data_out_reg <= data_in + 1;
ack_prev_reg <= 0;
end
endcase
end
end
endmodule
| 7.928488 |
module stage_B (
input clk,
input reset,
output DOR,
input DIR,
input ack_from_next,
output ack_prev,
input [7:0] data_in,
output [7:0] data_out
);
parameter IDLE = 1'd0;
parameter WAITING_ACK = 1'd1;
reg state = IDLE;
reg [7:0] data_out_reg = 8'd0;
reg DOR_reg = 0;
reg ack_prev_reg = 0;
reg [7:0] data_in_buffer;
assign data_out = data_out_reg;
assign DOR = DOR_reg;
assign ack_prev = ack_prev_reg;
always @(posedge clk) begin
if (reset) begin
state <= IDLE;
data_out_reg <= 0;
DOR_reg <= 0;
ack_prev_reg <= 0;
end else begin
case (state)
IDLE: begin
if (DIR) begin
$display("stage_B receives input_data %d", data_in);
state <= WAITING_ACK;
ack_prev_reg <= 1;
DOR_reg <= 1;
end
data_in_buffer <= data_in;
data_out_reg <= data_in + 1;
end
WAITING_ACK: begin
if (ack_from_next) begin
$display("stage_B got ACK form stage_C");
DOR_reg <= 0;
state <= IDLE;
end else begin
$display("stage_B waits for ACK from stage_C");
state <= WAITING_ACK;
DOR_reg <= 1;
end
data_out_reg <= data_in + 1;
ack_prev_reg <= 0;
end
endcase
end
end
endmodule
| 7.786472 |
module stage_C (
input clk,
input reset,
output DOR,
input DIR,
input ack_from_next,
output ack_prev,
input [7:0] data_in,
output [7:0] data_out
);
parameter IDLE = 1'd0;
parameter WAITING_ACK = 1'd1;
reg state = IDLE;
reg [7:0] data_out_reg = 8'd0;
reg DOR_reg = 0;
reg ack_prev_reg = 0;
reg [7:0] data_in_buffer;
assign data_out = data_out_reg;
assign DOR = DOR_reg;
assign ack_prev = ack_prev_reg;
always @(posedge clk) begin
if (reset) begin
state <= IDLE;
data_out_reg <= 0;
DOR_reg <= 0;
ack_prev_reg <= 0;
end else begin
case (state)
IDLE: begin
if (DIR) begin
$display("stage_C receives input_data %d", data_in);
state <= WAITING_ACK;
ack_prev_reg <= 1;
DOR_reg <= 1;
end
data_in_buffer <= data_in;
data_out_reg <= data_in + 1;
end
WAITING_ACK: begin
if (ack_from_next) begin
$display("stage_C got ACK form stage_B");
DOR_reg <= 0;
state <= IDLE;
end else begin
$display("stage_C waits for ACK from stage_B");
state <= WAITING_ACK;
DOR_reg <= 1;
end
data_out_reg <= data_in + 1;
ack_prev_reg <= 0;
end
endcase
end
end
endmodule
| 7.931829 |
module stage_control ();
// stage control
always @(posedge clock) begin
if (reset) stage <= 2'b00;
else if (load_stage) stage <= next_stage;
end
always @(*) begin
if (iSW[1:0] == 2'b11) next_stage = iSW[3:2];
else if (state == ST_INIT) next_stage = 2'b00;
else next_stage = (stage + 1) % 4;
end
endmodule
| 7.530452 |
module clz32 (
output reg [31:0] result,
input [31:0] value
);
reg [15:0] val16;
reg [ 7:0] val8;
reg [ 3:0] val4;
always @* begin
result[31:6] = 0;
if (value == 32'b0) begin
result[5:0] = 32;
end else begin
result[5] = 0;
result[4] = value[31:16] == 16'b0;
val16 = result[4] ? value[15:0] : value[31:16];
result[3] = val16[15:8] == 8'b0;
val8 = result[3] ? val16[7:0] : val16[15:8];
result[2] = val8[7:4] == 4'b0;
val4 = result[2] ? val8[3:0] : val8[7:4];
result[1] = val4[3:2] == 2'b0;
result[0] = result[1] ? ~val4[1] : ~val4[3];
end
end
endmodule
| 6.838726 |
module stage_EXEMEM (
clk,
nrst,
ALUResult,
ALUResult_out,
rd_data2,
rd_data2_out,
MemWrite,
Branch,
MemRead,
RegWrite,
MemToReg,
ALUOp,
ALUSrc,
Jump,
sd,
ld,
bne,
wmask,
MemWrite_o,
Branch_o,
MemRead_o,
RegWrite_o,
MemToReg_o,
ALUOp_o,
ALUSrc_o,
Jump_o,
sd_o,
ld_o,
bne_o,
wmask_o,
pc_in,
pc_out,
inst_in,
inst_out,
jal_imm_in,
jalr_imm_in,
branch_imm_in,
jal_imm_out,
jalr_imm_out,
branch_imm_out
);
input [63:0] ALUResult, rd_data2;
input clk, nrst;
output reg [63:0] ALUResult_out, rd_data2_out;
input [31:0] pc_in, inst_in;
input [31:0] jal_imm_in, jalr_imm_in, branch_imm_in;
output reg [31:0] jal_imm_out, jalr_imm_out, branch_imm_out;
//control signals from prev stage
input MemWrite, RegWrite, Branch, MemRead, ALUSrc; //1+1+1+1+1
input [1:0] MemToReg; //2
input [2:0] ALUOp; //3
input Jump, sd, ld, bne; //1+1+1+1
input [7:0] wmask; //8
//
//output control signals
output reg MemWrite_o, RegWrite_o, Branch_o, MemRead_o, ALUSrc_o; //1+1+1+1+1
output reg [1:0] MemToReg_o; //2
output reg [2:0] ALUOp_o; //3
output reg Jump_o, sd_o, ld_o, bne_o; //1+1+1+1
output reg [7:0] wmask_o; //8
output reg [31:0] pc_out, inst_out;
//
always @(posedge clk) begin
if (!nrst) begin
ALUResult_out <= 64'd0;
pc_out <= 32'd0;
inst_out <= 32'd0;
rd_data2_out <= 64'd0;
end else begin
ALUResult_out <= ALUResult;
pc_out <= pc_in;
inst_out <= inst_in;
rd_data2_out <= rd_data2;
end
end
always @(posedge clk) begin
if (!nrst) begin
MemWrite_o <= 1'b0;
RegWrite_o <= 1'b0;
Branch_o <= 1'b0;
MemRead_o <= 1'b0;
ALUSrc_o <= 1'b0;
MemToReg_o <= 2'd0;
ALUOp_o <= 3'd0;
Jump_o <= 1'b0;
sd_o <= 1'b0;
ld_o <= 1'b0;
bne_o <= 1'b0;
wmask_o <= 8'd0;
end else begin
MemWrite_o <= MemWrite;
RegWrite_o <= RegWrite;
Branch_o <= Branch;
MemRead_o <= MemRead;
ALUSrc_o <= ALUSrc;
MemToReg_o <= MemToReg;
ALUOp_o <= ALUOp;
Jump_o <= Jump;
sd_o <= sd;
ld_o <= ld;
bne_o <= bne;
wmask_o <= wmask;
end
end
endmodule
| 7.090998 |
module stage_EXMEM_tb ();
reg clk, rst, en;
reg [31:0] pc4;
reg [31:0] opcode1, opcode2;
reg [31:0] instruction;
reg [4:0] rs2, rd;
reg [3:0] alu_sel;
reg [2:0] wb_sel;
initial begin
$dumpfile("exmem_dump.vcd");
$dumpvars();
$display("test for EXMEM stage, are the correct values latching");
$monitor("pc:[%h] op1:[%h] op2:[%h] alu:[%h]", pc4, opcode1, opcode2, stageEXMEM.alu_out_in);
clk <= 1'b1;
rst <= 1;
en <= 1;
pc4 = 32'h4;
opcode1 = 32'h1;
opcode2 = 32'h1;
alu_sel = `ALU_ADD;
wb_sel = `WB_ALU;
#10 pc4 = PC44_out;
#10 opcode1 = 32'hab324;
#10 opcode2 = 32'h43c53;
#10 alu_sel = `ALU_AND;
#100 $finish;
end
always begin
#5 clk = ~clk;
end
wire [31:0] alu_out;
alu _alu (
.alu_out(alu_out),
.op1(opcode1),
.op2(opcode2),
.alu_sel(alu_sel)
);
branch_gen _branch_gen (
.inst(instruction),
.pc(pc4),
.alu_out(ALUOUT)
);
branch_predictor _branch_predictor (
.clk(clk),
.rst(rst),
.correct_target(),
.correct_pc4(),
.current_pc4()
);
wire [31:0] PC44_out;
add_const #(4) pc4Next (
.out(PC44_out),
.in (pc4)
);
wire [31:0] ALUOUT;
mux_2_1 #(32) _wb_sel_mux (
.out(ALUOUT),
.in1(PC44_out),
.in2(alu_out),
.sel(1)
);
register_EXMEM stageEXMEM (
.alu_out_in(ALUOUT),
.rs2_in(rs2),
.instruction_rd_in(rd),
.clk(clk),
.rst(rst),
.en(en),
//controls to WB
.register_write_enable_in(0),
//controls to MEM
.mem_request_write_in(0),
.mem_request_type_in(0),
.wb_sel_in(wb_sel)
);
endmodule
| 6.971327 |
module stage_fetch #(
parameter ADDR_MIN = 'h3000,
parameter ADDR_MAX = 'h5000,
parameter ADDR_HANDLER = 'h4180
) (
input wire clk,
input wire reset,
input wire [31:0] next_pc,
output reg [31:0] pc,
output wire [31:0] instr,
output wire [`EXC_CODE_LEN - 1:0] exc
);
localparam WORD_ADDR_MIN = ADDR_MIN >> 2;
localparam WORD_ADDR_MAX = ADDR_MAX >> 2;
reg [31:0] mem[WORD_ADDR_MAX - 1:WORD_ADDR_MIN];
wire [31:0] data = mem[pc[31:2]];
assign exc = pc < ADDR_MIN || pc >= ADDR_MAX || pc[1:0] != 0 ? `EXC_CODE_ADEL : 0;
assign instr = exc || ^data === 1'bx ? 0 : data;
always @(posedge clk) begin
if (reset) begin
pc <= ADDR_MIN;
$readmemh("code.txt", mem);
$readmemh("code_handler.txt", mem, ADDR_HANDLER >> 2, WORD_ADDR_MAX - 1);
end else pc <= next_pc;
end
endmodule
| 9.02626 |
module stage_IDEXE (
clk,
nrst,
inst_IDEXE,
rd_data1,
rd_data2,
jal_imm_in,
jalr_imm_in,
branch_imm_in,
sd_imm_in,
addi_imm_in,
jal_imm_out,
jalr_imm_out,
branch_imm_out,
sd_imm_out,
addi_imm_out,
inst_IDEXE_out,
rd_data1_out,
rd_data2_out,
MemWrite,
Branch,
MemRead,
RegWrite,
MemToReg,
ALUOp,
ALUSrc,
Jump,
sd,
ld,
bne,
wmask,
MemWrite_o,
Branch_o,
MemRead_o,
RegWrite_o,
MemToReg_o,
ALUOp_o,
ALUSrc_o,
Jump_o,
sd_o,
ld_o,
bne_o,
wmask_o,
pc_in,
pc_out
);
input clk, nrst;
input [31:0] inst_IDEXE, pc_in;
input [63:0] rd_data1, rd_data2;
input [31:0] jal_imm_in, jalr_imm_in, branch_imm_in;
input [63:0] sd_imm_in, addi_imm_in;
output reg [31:0] jal_imm_out, jalr_imm_out, branch_imm_out, inst_IDEXE_out, pc_out;
output reg [63:0] sd_imm_out, addi_imm_out;
//[31:25] - funct7
//[24:20] - rs2
//19:15 - rs1
//14:12 - funct3
//11:7 - rd
//6:0 opcode
output reg [63:0] rd_data1_out, rd_data2_out;
//control signals
input MemWrite, RegWrite, Branch, MemRead, ALUSrc; //1+1+1+1+1
input [1:0] MemToReg; //2
input [2:0] ALUOp; //3
input Jump, sd, ld, bne; //1+1+1+1
input [7:0] wmask; //8
//
//output control signals
output reg MemWrite_o, RegWrite_o, Branch_o, MemRead_o, ALUSrc_o; //1+1+1+1+1
output reg [1:0] MemToReg_o; //2
output reg [2:0] ALUOp_o; //3
output reg Jump_o, sd_o, ld_o, bne_o; //1+1+1+1
output reg [7:0] wmask_o; //8
//
always @(posedge clk) begin
if (!nrst) begin
inst_IDEXE_out <= 32'd0;
rd_data1_out <= 64'd0;
rd_data2_out <= 64'd0;
jal_imm_out <= 32'd0;
jalr_imm_out <= 32'd0;
branch_imm_out <= 32'd0;
sd_imm_out <= 64'd0;
addi_imm_out <= 64'd0;
MemWrite_o <= 1'b0;
RegWrite_o <= 1'b0;
Branch_o <= 1'b0;
MemRead_o <= 1'b0;
ALUSrc_o <= 1'b0;
MemToReg_o <= 2'd0;
ALUOp_o <= 3'd0;
Jump_o <= 1'b0;
sd_o <= 1'b0;
ld_o <= 1'b0;
bne_o <= 1'b0;
wmask_o <= 8'd0;
pc_out <= 32'd0;
end else begin
inst_IDEXE_out <= inst_IDEXE;
rd_data1_out <= rd_data1;
rd_data2_out <= rd_data2;
jal_imm_out <= jal_imm_in;
jalr_imm_out <= jalr_imm_in;
branch_imm_out <= branch_imm_in;
sd_imm_out <= sd_imm_in;
addi_imm_out <= addi_imm_in;
MemWrite_o <= MemWrite;
RegWrite_o <= RegWrite;
Branch_o <= Branch;
MemRead_o <= MemRead;
ALUSrc_o <= ALUSrc;
MemToReg_o <= MemToReg;
ALUOp_o <= ALUOp;
Jump_o <= Jump;
sd_o <= sd;
ld_o <= ld;
bne_o <= bne;
wmask_o <= wmask;
pc_out <= pc_in;
end
end
endmodule
| 7.220464 |
module stage_IDEX ();
reg clk, rst, en;
reg [31:0] instruction, pc, pc4, nop;
initial begin
$dumpfile("idex_dump.vcd");
$dumpvars();
$display("test for IDEX stage, are the correct values latching");
$monitor("PC+4:[%h] PC:[%h] INST:[%h] op1:[%h] op2:[%h] RD:[%b] wb_sel:[%b]",
stageIDEX.pc4_out, stageIDEX.pc_out, stageIDEX.inst_out, stageIDEX.operand1_out,
stageIDEX.operand2_out, stageIDEX.instruction_rd_out, stageIDEX.wb_sel_out);
clk <= 1'b1;
rst <= 1;
en <= 1;
nop <= `INST_NOP;
pc4 = 32'h4;
pc = 32'h0;
instruction = 32'h00000013;
#10 pc4 = 32'h8;
#10 pc = 32'h4;
#10 instruction = 32'h00200513;
#20 pc4 = 32'hc;
#20 pc = 32'h8;
#20 instruction = 32'h00200593;
#100 $finish;
end
always begin
#5 clk = ~clk;
end
wire [31:0] data1;
wire [31:0] data2;
register_file reg_file (
.read_data_1(data1),
.read_data_2(data2),
.rs_1(rs1),
.rs_2(rs2),
.register_write(0),
.write_data(0),
.register_write_enable(0)
);
wire [3:0] alu_sel;
wire [31:0] op1, op2;
decode_alu alu_decoder (
.op1(op1),
.op2(op2),
.alu_sel(alu_sel),
.inst(instruction),
.rs1(data1),
.rs2(data2)
);
wire [4:0] rs1, rs2, rd;
wire [6:0] opcode;
wire reg_write_en, mem_req_write, mem_req_type;
wire [2:0] wb_sel;
decode_control control_decoder (
.rs1(rs1),
.rs2(rs2),
.rd(rd),
.opcode(opcode),
.reg_write_en(reg_write_en),
.wb_sel(wb_sel),
.mem_req_write(mem_req_write),
.mem_req_type(mem_req_type),
.inst(instruction)
);
wire IF_kill, ID_kill;
hazard_detect HDU (
.kill_IF(IF_kill),
.kill_DEC(ID_kill),
.regIFID_rs1(rs1),
.regIFID_rs2(rs2),
.regIFID_rd(rd),
.regIDEX_rd(0),
.memReadIDEX(0)
);
wire [4:0] rs2_mux, rd_mux;
wire reg_write_en_mux, mem_req_write_mux, mem_req_type_mux;
wire [2:0] wb_sel_mux;
decode_mux mux_decode (
.rs2_out(rs2_mux),
.rd_out(rd_mux),
.reg_write_en_out(reg_write_en_mux),
.wb_sel_out(wb_sel_mux),
.mem_req_write_out(mem_req_write_mux),
.mem_req_type_out(mem_req_type_mux),
.rs2_in(rs2),
.rd_in(rd),
.reg_write_en_in(reg_write_en),
.wb_sel_in(wb_sel),
.mem_req_write_in(mem_req_write),
.mem_req_type_in(mem_req_type),
.kill_DEC(ID_kill),
.nop(nop)
);
wire [3:0] alu_sel_mux;
mux_2_1 #(4) alu_decode_mux (
.out(alu_sel_mux),
.in1(alu_sel),
.in2(nop[3:0]),
.sel(ID_kill)
);
register_IDEX stageIDEX (
.clk(clk),
.rst(rst),
.en(en),
.pc4_in(pc4),
.pc_in(pc),
.inst_in(instruction),
.operand1_in(op1),
.operand2_in(op2),
.instruction_rd_in(rd_mux),
.rs2_in(rs2_mux),
.prediction_in(0),
//controls to WB
.register_write_enable_in(reg_write_en_mux),
//controls to MEM
.mem_request_write_in(mem_req_write_mux),
.mem_request_type_in(mem_req_type_mux),
//control to EXE
.alu_sel_in(alu_sel_mux),
.wb_sel_in(wb_sel_mux)
);
endmodule
| 7.221435 |
module stage_if (
input wire rst,
input wire [`MemAddrBus] pc_i,
input wire [ `RegBus] mem_data_i,
input wire mem_busy,
input wire mem_done,
input wire br,
input wire right_one,
output reg mem_re,
output reg [`MemAddrBus] mem_addr_o,
output reg [`MemAddrBus] pc_o,
output reg [ `InstBus] inst_o,
output reg stallreq
);
reg mem_taking;
reg waiting_one;
always @(*) begin
if (right_one) begin
waiting_one = 0;
//$display("Right one is here, %h", pc_i);
end
if (rst) begin
stallreq = 0;
mem_taking = 0;
pc_o = 0;
inst_o = 0;
mem_re = 0;
mem_addr_o = 0;
waiting_one = 0;
end else if (br) begin
//$display("br");
pc_o = 0;
inst_o = 0;
mem_taking = 0;
stallreq = 0;
waiting_one = 1;
end else if (!waiting_one && !mem_busy && !mem_taking) begin
//$display("!mem_busy && !mem_taking");
stallreq = 1;
mem_taking = 1;
mem_re = 1;
mem_addr_o = pc_i;
end else if (!waiting_one && !mem_busy && mem_taking) begin
//$display("!mem_busy && mem_taking");
stallreq = 0;
mem_taking = 0;
pc_o = pc_i;
inst_o = mem_data_i;
//$display("IF Get Inst: %h\n", inst_o);
end else if (!waiting_one && mem_busy) begin
//$display("mem_busy, %h", pc_i);
stallreq = 1;
end else if (!waiting_one) begin
stallreq = 0;
mem_taking = 0;
pc_o = 0;
inst_o = 0;
mem_re = 0;
mem_addr_o = 0;
waiting_one = 0;
end
end
endmodule
| 7.09664 |
module stage_IFID (
clk,
nrst,
pc,
out_pc,
inst_IFID,
out_inst
);
input clk, nrst;
input [31:0] pc;
input [31:0] inst_IFID;
output reg [31:0] out_pc, out_inst;
always @(posedge clk) begin
if (!nrst) out_pc <= 32'd0;
else begin
out_pc <= pc;
out_inst <= inst_IFID;
end
end
endmodule
| 7.528671 |
module stage_IFID_tb ();
reg clk, rst, en;
reg [2:0] pc_sel_in;
initial begin
$dumpfile("ifid_dump.vcd");
$dumpvars();
$display("test for IFID stage, are the correct values latching");
$monitor("PC:[%h] PC+4:[%h] INST:[%h]", stageIFID.pc_out, stageIFID.pc4_out,
stageIFID.instruction_out);
clk <= 1'b1;
rst <= 1;
en <= 1;
pc_sel_in = 3'b111; //default
#10 pc_sel_in = 3'b001; // change in next clock
#100 $finish;
end
always begin
#5 clk = ~clk;
end
wire [31:0] mux_address_out;
mux_4_1 PCMUX (
.pc_next(mux_address_out),
.pc_sel(pc_sel_in),
.curr_pc4(PCNext_out),
.branch(),
.predicted_target()
);
wire [31:0] PCReg_out;
register_pc PCReg (
.q (PCReg_out),
.d (mux_address_out),
.en (en),
.clk(clk),
.rst(rst)
);
wire [31:0] Instruction;
inst_mem InstMem (
.request_data(Instruction),
.address(PCReg_out),
.clk(clk),
.rst(rst),
.wb_en(0),
.wb_address(32'b0),
.wb_data(32'b0)
);
wire [31:0] PCNext_out;
add_const #(4) PCNext (
.out(PCNext_out),
.in (PCReg_out)
);
register_IFID stageIFID (
.pc4_out(),
.pc_out(),
.instruction_out(),
.prediction_out(),
.pc4_in(PCNext_out),
.pc_in(PCReg_out),
.instruction_in(Instruction),
.prediction_in(0),
.clk(clk),
.rst(rst),
.en(en)
);
endmodule
| 6.631196 |
module stage_MEMWB (
clk,
nrst,
rdata,
ALUResult,
ALUResult_out,
rdata_out,
MemWrite,
Branch,
MemRead,
RegWrite,
MemToReg,
ALUOp,
ALUSrc,
Jump,
sd,
ld,
bne,
wmask,
MemWrite_o,
Branch_o,
MemRead_o,
RegWrite_o,
MemToReg_o,
ALUOp_o,
ALUSrc_o,
Jump_o,
sd_o,
ld_o,
bne_o,
wmask_o,
pc_in,
pc_out,
inst_in,
inst_out
);
input [63:0] ALUResult, rdata;
input clk, nrst;
output reg [63:0] ALUResult_out, rdata_out;
input [31:0] pc_in, inst_in;
output reg [31:0] pc_out, inst_out;
//control signals from prev stage
input MemWrite, RegWrite, Branch, MemRead, ALUSrc; //1+1+1+1+1
input [1:0] MemToReg; //2
input [2:0] ALUOp; //3
input Jump, sd, ld, bne; //1+1+1+1
input [7:0] wmask; //8
//
//output control signals
output reg MemWrite_o, RegWrite_o, Branch_o, MemRead_o, ALUSrc_o; //1+1+1+1+1
output reg [1:0] MemToReg_o; //2
output reg [2:0] ALUOp_o; //3
output reg Jump_o, sd_o, ld_o, bne_o; //1+1+1+1
output reg [7:0] wmask_o; //8
//
always @(posedge clk) begin
if (!nrst) begin
ALUResult_out <= 64'd0;
rdata_out <= 64'd0;
pc_out <= 32'd0;
inst_out <= 32'd0;
end else begin
ALUResult_out <= ALUResult;
rdata_out <= rdata;
pc_out <= pc_in;
inst_out <= inst_in;
end
end
always @(posedge clk) begin
if (!nrst) begin
MemWrite_o <= 1'b0;
RegWrite_o <= 1'b0;
Branch_o <= 1'b0;
MemRead_o <= 1'b0;
ALUSrc_o <= 1'b0;
MemToReg_o <= 2'd0;
ALUOp_o <= 3'd0;
Jump_o <= 1'b0;
sd_o <= 1'b0;
ld_o <= 1'b0;
bne_o <= 1'b0;
wmask_o <= 8'd0;
end else begin
MemWrite_o <= MemWrite;
RegWrite_o <= RegWrite;
Branch_o <= Branch;
MemRead_o <= MemRead;
ALUSrc_o <= ALUSrc;
MemToReg_o <= MemToReg;
ALUOp_o <= ALUOp;
Jump_o <= Jump;
sd_o <= sd;
ld_o <= ld;
bne_o <= bne;
wmask_o <= wmask;
end
end
endmodule
| 7.201803 |
module stage_MEMWB_tb ();
reg clk, rst, en;
initial begin
$dumpfile("memwb_dump.vcd");
$dumpvars();
$display("test for MEMEX stage, are the correct values latching");
// this one should show before and after MEMWB
//$monitor("", );
clk <= 1'b1;
rst <= 1;
en <= 1;
#100 $finish;
end
always begin
#5 clk = ~clk;
end
writeback _writeback (
.output_data(),
.out_data_mem(),
.out_pc4(),
.out_alu(),
.wb_sel()
);
data_memory _data_memory (
.memory_addr(),
.write_data(),
.write_mask(),
.output_data(),
.instruction(),
.data(),
.addr(),
.load_data()
);
simulated_mem _simulated_mem (
.load_data(),
.valid(),
.clk(),
.reset(),
.addr(),
.mask(),
.enable(),
.cmd(),
.write_data()
);
register_MEMWB _register_MEMWB (
.wb_data_out(),
.instruction_rd_out(),
.register_write_enable_out(),
.wb_data_in(),
.instruction_rd_in(),
.clk(),
.rst(),
.en(),
.register_write_enable_in()
);
register_file _register_file (
.register_write(),
.write_data(),
.register_write_enable()
);
endmodule
| 6.770492 |
module stage_mem_bias (
input bias_int_32_3 bias_int,
input [31:0] bias_int_wr_data,
input clk,
input reset,
output [31:0] bias_int_rd_data
);
// Parameters
// Wires
wire [31:0] read_0; // <32,0>
wire [31:0] write_0; // <32,0>
wire write_sub; // <1,1>
// Registers
// Other
////////////////////////////////////////////////////////////////////////////////
// stage_mem_bias_0
////////////////////////////////////////////////////////////////////////////////
memory_32_3 stage_mem_bias_0 (
.clk(clk),
.m(bias_int),
.m_rd_data(read_0),
.m_wr_data(write_0),
.reset(reset)
);
assign write_0 = bias_int_wr_data[31:0];
assign bias_int_rd_data[31:0] = read_0;
endmodule
| 7.778361 |
module stage_mem_data (
input clk,
input data_int_32_6 data_int,
input [31:0] data_int_wr_data,
input reset,
output [31:0] data_int_rd_data
);
// Parameters
// Wires
wire [31:0] read_0; // <32,0>
wire [31:0] write_0; // <32,0>
wire write_sub; // <1,1>
// Registers
// Other
////////////////////////////////////////////////////////////////////////////////
// stage_mem_data_0
////////////////////////////////////////////////////////////////////////////////
memory_32_6 stage_mem_data_0 (
.clk(clk),
.m(data_int),
.m_rd_data(read_0),
.m_wr_data(write_0),
.reset(reset)
);
assign write_0 = data_int_wr_data[31:0];
assign data_int_rd_data[31:0] = read_0;
endmodule
| 6.766413 |
module STAGE_REG_FD (
input reset_n,
input clk,
input wren,
input [31:0] in_ins,
input [31:0] in_next_pc,
output reg [31:0] ins,
output reg [31:0] next_pc
);
always @(posedge clk) begin
if (!reset_n) begin
ins <= 0;
next_pc <= 0;
end else if (wren) begin
ins <= in_ins;
next_pc <= in_next_pc;
end
end
endmodule
| 8.513962 |
module STAGE_REG_DE (
input reset_n,
input clk,
input wren,
input [31:0] in_next_pc,
input [31:0] in_data0,
input [31:0] in_data1,
input [4:0] in_dst_reg,
input [31:0] in_ins,
input in_dec_alu_src,
input in_dec_mem_to_reg,
input in_dec_reg_write,
input in_dec_mem_read,
input in_dec_mem_write,
input in_dec_branch,
input in_dec_jmp,
input [3:0] in_dec_alu_op,
input in_dec_alu_result_to_pc,
input in_dec_pc_to_ra,
output reg [31:0] next_pc,
output reg [31:0] data0,
output reg [31:0] data1,
output reg [4:0] dst_reg,
output reg [31:0] ins,
output reg dec_alu_src,
output reg dec_mem_to_reg,
output reg dec_reg_write,
output reg dec_mem_read,
output reg dec_mem_write,
output reg dec_branch,
output reg dec_jmp,
output reg [3:0] dec_alu_op,
output reg dec_alu_result_to_pc,
output reg dec_pc_to_ra
);
always @(posedge clk) begin
if (!reset_n) begin
next_pc <= 0;
data0 <= 0;
data1 <= 0;
dst_reg <= 0;
ins <= 0;
dec_alu_src <= 0;
dec_mem_to_reg <= 0;
dec_reg_write <= 0;
dec_mem_read <= 0;
dec_mem_write <= 0;
dec_branch <= 0;
dec_jmp <= 0;
dec_alu_op <= 0;
dec_alu_result_to_pc <= 0;
dec_pc_to_ra <= 0;
end else if (wren) begin
next_pc <= in_next_pc;
data0 <= in_data0;
data1 <= in_data1;
dst_reg <= in_dst_reg;
ins <= in_ins;
dec_alu_src <= in_dec_alu_src;
dec_mem_to_reg <= in_dec_mem_to_reg;
dec_reg_write <= in_dec_reg_write;
dec_mem_read <= in_dec_mem_read;
dec_mem_write <= in_dec_mem_write;
dec_branch <= in_dec_branch;
dec_jmp <= in_dec_jmp;
dec_alu_op <= in_dec_alu_op;
dec_alu_result_to_pc <= in_dec_alu_result_to_pc;
dec_pc_to_ra <= in_dec_pc_to_ra;
end
end
endmodule
| 7.538748 |
module STAGE_REG_EM (
input reset_n,
input clk,
input wren,
input [31:0] in_next_pc,
input [31:0] in_branch_pc,
input [31:0] in_alu_result,
input [31:0] in_mem_write_data,
input [4:0] in_dst_reg,
input [31:0] in_ins,
input in_dec_mem_to_reg,
input in_dec_reg_write,
input in_dec_mem_read,
input in_dec_mem_write,
input in_dec_branch,
input in_dec_jmp,
input in_alu_result_zero,
input in_dec_alu_result_to_pc,
input in_dec_pc_to_ra,
output reg [31:0] next_pc,
output reg [31:0] branch_pc,
output reg [31:0] alu_result,
output reg [31:0] mem_write_data,
output reg [4:0] dst_reg,
output reg [31:0] ins,
output reg dec_mem_to_reg,
output reg dec_reg_write,
output reg dec_mem_read,
output reg dec_mem_write,
output reg dec_branch,
output reg dec_jmp,
output reg alu_result_zero,
output reg dec_alu_result_to_pc,
output reg dec_pc_to_ra
);
always @(posedge clk) begin
if (!reset_n) begin
next_pc <= 0;
branch_pc <= 0;
ins <= 0;
dec_mem_to_reg <= 0;
dec_reg_write <= 0;
dec_mem_read <= 0;
dec_mem_write <= 0;
dec_branch <= 0;
dec_jmp <= 0;
alu_result_zero <= 0;
alu_result <= 0;
dst_reg <= 0;
mem_write_data <= 0;
dec_alu_result_to_pc <= in_dec_alu_result_to_pc;
dec_pc_to_ra <= 0;
end else if (wren) begin
next_pc <= in_next_pc;
branch_pc <= in_branch_pc;
ins <= in_ins;
dec_mem_to_reg <= in_dec_mem_to_reg;
dec_reg_write <= in_dec_reg_write;
dec_mem_read <= in_dec_mem_read;
dec_mem_write <= in_dec_mem_write;
dec_branch <= in_dec_branch;
dec_jmp <= in_dec_jmp;
alu_result_zero <= in_alu_result_zero;
alu_result <= in_alu_result;
dst_reg <= in_dst_reg;
mem_write_data <= in_mem_write_data;
dec_alu_result_to_pc <= in_dec_alu_result_to_pc;
dec_pc_to_ra <= in_dec_pc_to_ra;
end
end
endmodule
| 7.326317 |
module STAGE_REG_MW (
input reset_n,
input clk,
input wren,
input [31:0] in_mem_data,
input [31:0] in_alu_result,
input [4:0] in_dst_reg,
input [31:0] in_return_pc,
input in_dec_mem_to_reg,
input in_dec_reg_write,
input in_dec_pc_to_ra,
output reg [31:0] mem_data,
output reg [31:0] alu_result,
output reg [4:0] dst_reg,
output reg [31:0] return_pc,
output reg dec_mem_to_reg,
output reg dec_reg_write,
output reg dec_pc_to_ra
);
always @(posedge clk) begin
if (!reset_n) begin
mem_data <= 0;
alu_result <= 0;
dst_reg <= 0;
return_pc <= 0;
dec_mem_to_reg <= 0;
dec_reg_write <= 0;
dec_pc_to_ra <= 0;
end else if (wren) begin
mem_data <= in_mem_data;
alu_result <= in_alu_result;
dst_reg <= in_dst_reg;
return_pc <= in_return_pc;
dec_mem_to_reg <= in_dec_mem_to_reg;
dec_reg_write <= in_dec_reg_write;
dec_pc_to_ra <= in_dec_pc_to_ra;
end
end
endmodule
| 7.992598 |
module PC (
input reset_n,
input clk,
input wren,
input [31:0] jmp_to,
output [31:0] pc_data
);
reg [31:0] _pc_data;
assign pc_data = _pc_data;
always @(posedge clk) begin
if (!reset_n) begin
_pc_data <= 0;
end else if (wren) begin
_pc_data <= jmp_to;
end
end
endmodule
| 7.578567 |
module to check execution
module exec_tb();
//Control Unit Signals
reg clk = 0;
reg ALU_Src=1'b1; //Use immediate value for addition
reg regWrite_receive = 1;
reg Mem_Write_receive=1'b0;
reg [1:0] ALU_Op_receive = 2'b10; //Add
reg Mem_to_Reg_receive=1'b0;
reg Mem_Read_receive=1'b1;
reg Branch_receive=1'b0;
//Passed on CU signals
wire regWrite;
wire Mem_Write;
wire Mem_to_Reg;
wire Mem_Read;
wire Branch;
//1st ALU inputs
reg [63:0] pc_receive = 64'b0;
reg [63:0] extended_receive = 64'd12;
//alu 2 ip
reg [63:0] read_data_1_receive = 64'd3;
reg [63:0] read_data_2_receive = 63'd5;
reg [3:0] Func_receive = 4'b0000;
//alu 2 op
wire [63:0] pcbranch;
wire [63:0] Result;
wire Zero;
//Read data 2 passed on 2 Memory stage
wire [63:0] read_data_2;
wire [63:0] read_data_1;
exec exec0(.clk (clk),
.regWrite_receive (regWrite_receive), .ALU_Src (ALU_Src), .Mem_Write_receive (Mem_Write_receive), .ALU_Op_receive (ALU_Op_receive),
.regWrite (regWrite), .Mem_to_Reg_receive (Mem_to_Reg_receive), .Mem_Read_receive (Mem_Read_receive), .Branch_receive (Branch_receive),
.Mem_to_Reg (Mem_to_Reg), .Mem_Write (Mem_Write), .Mem_Read (Mem_Read), .Branch (Branch),
.pc_receive (pc_receive), .extended_receive (extended_receive), .pcbranch (pcbranch),
.read_data_1_receive (read_data_1_receive), .read_data_2_receive (read_data_2_receive), .read_data_2 (read_data_2),
.Func_receive (Func_receive),
.Result (Result), .Zero (Zero) );
initial begin
#1 clk = ~clk;
#5 $display("\n(Addition Operation)\nExecution outputs :- pcbranch= %b, Result=%b,\n Zero= %b, read data 2 = %b",pcbranch, Result, Zero, read_data_2);
end
endmodule
| 7.727827 |
module stage_URAM #(
parameter INDEX_WIDTH = 12
) (
input k,
input [INDEX_WIDTH-1:0] q,
input [INDEX_WIDTH-1:0] pre,
output [INDEX_WIDTH-1:0] out
);
//------------------output of and ------------------------------------//
wire [INDEX_WIDTH-1:0] out_and;
//------------------u_module---------------------------------------------//
and_q_k_URAM #(INDEX_WIDTH) u_and (
k,
q,
out_and
);
xor_ab_URAM #(INDEX_WIDTH) u_xor (
pre,
out_and,
out
);
endmodule
| 7.512729 |
module STALL
(
input i_clk ,
input i_rst_n ,
input i_signal ,
input i_clr ,
output o_stall
);
reg r_stall;
assign o_stall = r_stall;
always@(posedge i_clk or negedge i_rst_n) begin
if(~i_rst_n) begin
r_stall <= `DELAY 1'b0;
end
else begin
if(i_clr) begin
r_stall <= `DELAY 1'b0;
end
else begin
if(i_signal) begin
r_stall <= `DELAY 1'b1;
end
end
end
end
endmodule
| 6.968212 |
module: StallControllBlock
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module StallControllBlock_TB;
// Inputs
reg reset;
reg clk;
reg [23:0] ins;
// Outputs
wire Stall_pm;
wire Stall;
// Instantiate the Unit Under Test (UUT)
StallControllBlock uut (
.Stall_pm(Stall_pm),
.Stall(Stall),
.reset(reset),
.clk(clk),
.ins(ins)
);
initial begin
reset = 1;
ins = 24'h0;
#200;
reset = 0;
ins = 24'h0;
#400;
reset = 1;
ins = 24'h0;
#1000;
reset = 1;
ins = 24'ha00000;
#2000;
reset = 1;
ins = 24'h0;
#1000;
reset = 1;
ins = 24'hf00000;
#3000;
reset = 1;
ins = 24'h0;
#1000;
reset = 1;
ins = 24'h880000;
#4000;
end
initial begin
clk=0;
#500
forever begin
clk=~clk;
#500;
end
end
endmodule
| 6.981038 |
module stallctrl (
//from if
input wire stall_from_if,
//from id
input wire stall_from_id,
//from mem
input wire stall_from_mem,
//to pc id_id id_ex ex_mem mem_wb
output reg [5:0] stall //stall[0] stand for pc stop 1stand for stop
);
always @(*) begin
stall = 0;
if (stall_from_mem == 1) begin
stall = 6'b011111;
end else if (stall_from_id == 1) begin
stall = 6'b000111;
end else if (stall_from_if == 1) begin
stall = 6'b000011;
end
end
endmodule
| 6.556049 |
module Staller (
input clk,
input rst,
input alu_full,
input bra_full,
input lsm_full,
input rob_full,
input icache_enable,
// with Decoder
input [`Opcode_Width-1 : 0] op,
// with PC
input pc_locked,
output reg pc_stall,
// with icache
output reg icache_stall,
// with ROB
input rob_stall,
// with LoadStore
output lsm_stall
);
always @(negedge clk) begin
$display("staller");
$display("op %h", op);
$display("icache_enable %h", icache_enable);
$display("rob_full %h", rob_full);
$display("lsm_full %h", lsm_full);
$display("pc_locked %h", pc_locked);
if (rst) begin
pc_stall <= 1;
icache_stall <= 1;
end else begin
case (op)
`BRANCH_: begin
pc_stall <= !icache_enable || rob_full || bra_full;
icache_stall <= pc_locked || rob_full || bra_full;
end
`Load_: begin
pc_stall <= !icache_enable || rob_full || lsm_full;
icache_stall <= pc_locked || rob_full || lsm_full;
end
`Store_: begin
pc_stall <= !icache_enable || rob_full || lsm_full;
icache_stall <= pc_locked || rob_full || lsm_full;
end
default: begin
pc_stall <= !icache_enable || rob_full || alu_full;
icache_stall <= pc_locked || rob_full || alu_full;
end
endcase
end
end
assign lsm_stall = rob_stall;
endmodule
| 6.729616 |
module stalling_unit (
input EX_MemRead,
input [4:0] EX_rd,
input [4:0] ID_rs1,
input [4:0] ID_rs2,
output MemStall
);
assign MemStall = EX_MemRead & (EX_rd == ID_rs1 | EX_rd == ID_rs2);
endmodule
| 6.994513 |
module produces a "ready" signal;
// if "ready" is not asserted, the read
// or write did not take place.
//
// Reads happen combinationally with zero delay in cycles that ready is high.
// Writes occur on rising clock edge in cycles that ready is high.
// Concurrent read and write not allowed.
//
// On reset, memory loads from file "loadfile_all.img".
// (You may change the name of the file in
// the $readmemh statement below.)
// File format:
// @0
// <hex data 0>
// <hex data 1>
// ...etc
//
// If input "createdump" is true on rising clock,
// contents of memory will be dumped to
// file "dumpfile", from location 0 up through
// the highest location modified by a write.
//
//
//////////////////////////////////////
module stallmem (DataOut, Done, Stall, CacheHit, err, Addr, DataIn, Rd, Wr, createdump, clk, rst);
output [15:0] DataOut;
output Done;
output Stall;
output CacheHit;
input [15:0] DataIn;
input [15:0] Addr;
input Wr;
input Rd;
input createdump;
input clk;
input rst;
output err;
reg [7:0] mem [0:63];
reg loaded;
reg [16:0] largest;
reg [31:0] rand_pat;
wire ready;
wire muxSel;
assign muxSel = ready & (~Wr);
integer mcd;
integer i;
assign ready = (Wr|Rd) & rand_pat[0];
assign Stall = (Wr|Rd) & ~rand_pat[0];
assign err = ready & Addr[0]; //word aligned; odd address is invalid
assign Done = ready;
assign DataOut = err ?
((ready & (~Wr))? {mem[Addr-8'h1],mem[Addr]}: 0) :
((ready & (~Wr))? {mem[Addr],mem[Addr+8'h1]}: 0);
assign CacheHit = 0;
integer seed;
initial begin
loaded = 0;
largest = 0;
// rand_pat = 32'b01010010011000101001111000001010;
seed = 0;
//$value$plusargs("seed=%d", seed);
//$display("Using seed %d", seed);
//rand_pat = $random(seed);
//$display("rand_pat=%08x %32b", rand_pat, rand_pat);
// initialize memories to 0 first
//for (i=0; i<=65535; i=i+1) begin
// mem[i] = 8'd0;
//end
end
always @(posedge clk) begin
if (rst) begin
/*
if (!loaded) begin
$readmemh("loadfile_all.img", mem);
loaded = 1;
end
*/
end
else begin
rand_pat = (rand_pat >> 1) | (rand_pat[0] << 31);
#1;
if (ready & Wr & ~err) begin
mem[Addr] = DataIn[15:8]; // The actual write
mem[Addr+1] = DataIn[7:0]; // The actual write
if ({1'b0, Addr} > largest) largest = Addr; // avoid negative numbers
end
/*
if (createdump) begin
mcd = $fopen("dumpfile");
for (i=0; i<=largest; i=i+1) begin
$fdisplay(mcd,"%4h %4h", i, mem[i]);
end
$fclose(mcd);
end
*/
end
end
endmodule
| 6.523855 |
module produces a "ready" signal;
// if "ready" is not asserted, the read
// or write did not take place.
//
// Reads happen combinationally with zero delay in cycles that ready is high.
// Writes occur on rising clock edge in cycles that ready is high.
// Concurrent read and write not allowed.
//
// On reset, memory loads from file "loadfile_all.img".
// (You may change the name of the file in
// the $readmemh statement below.)
// File format:
// @0
// <hex data 0>
// <hex data 1>
// ...etc
//
// If input "createdump" is true on rising clock,
// contents of memory will be dumped to
// file "dumpfile", from location 0 up through
// the highest location modified by a write.
//
//
//////////////////////////////////////
module stallmem (DataOut, Done, Stall, CacheHit, err, Addr, DataIn, Rd, Wr, createdump, clk, rst);
output [15:0] DataOut;
output Done;
output Stall;
output CacheHit;
input [15:0] DataIn;
input [15:0] Addr;
input Wr;
input Rd;
input createdump;
input clk;
input rst;
output err;
reg [7:0] mem [0:65535];
reg loaded;
reg [16:0] largest;
reg [31:0] rand_pat;
wire ready;
integer mcd;
integer i;
assign ready = (Wr|Rd) & rand_pat[0];
assign Stall = (Wr|Rd) & ~rand_pat[0];
assign err = ready & Addr[0]; //word aligned; odd address is invalid
assign Done = ready;
assign DataOut = err ?
((ready & (~Wr))? {mem[Addr-8'h1],mem[Addr]}: 0) :
((ready & (~Wr))? {mem[Addr],mem[Addr+8'h1]}: 0);
assign CacheHit = 0;
integer seed;
initial begin
loaded = 0;
largest = 0;
// rand_pat = 32'b01010010011000101001111000001010;
seed = 0;
$value$plusargs("seed=%d", seed);
$display("Using seed %d", seed);
rand_pat = $random(seed);
$display("rand_pat=%08x %32b", rand_pat, rand_pat);
// initialize memories to 0 first
for (i=0; i<=65535; i=i+1) begin
mem[i] = 8'd0;
end
end
always @(posedge clk) begin
if (rst) begin
if (!loaded) begin
$readmemh("loadfile_all.img", mem);
loaded = 1;
end
end
else begin
if (ready & Wr & ~err) begin
mem[Addr] = DataIn[15:8]; // The actual write
mem[Addr+1] = DataIn[7:0]; // The actual write
if ({1'b0, Addr} > largest) largest = Addr; // avoid negative numbers
end
if (createdump) begin
mcd = $fopen("dumpfile");
for (i=0; i<=largest; i=i+1) begin
$fdisplay(mcd,"%4h %4h", i, mem[i]);
end
$fclose(mcd);
end
rand_pat = (rand_pat >> 1) | (rand_pat[0] << 31);
end
end
endmodule
| 6.523855 |
module stallmux (
wb,
m,
ex,
MemToReg,
RegWrite,
MemRead,
MemWrite,
RegDst,
AluOp,
AluSrc,
AluMux,
HiLoEnable,
HazardMuxSelect
);
output [1:0] wb;
output [1:0] m;
output [6:0] ex;
reg [ 1:0] wb;
reg [ 1:0] m;
reg [13:0] ex;
input MemToReg, RegWrite, MemRead, MemWrite, RegDst, AluSrc, HazardMuxSelect;
input [1:0] AluMux;
input HiLoEnable;
input [8:0] AluOp;
always @(MemToReg or RegWrite or MemRead or MemWrite or RegDst or AluOp or AluSrc or HazardMuxSelect
or AluMux or HiLoEnable)
begin
if (~HazardMuxSelect) begin
wb = {MemToReg, RegWrite};
m = {MemRead, MemWrite};
ex = {RegDst, AluOp, AluSrc, AluMux, HiLoEnable};
end else begin
wb = 0;
m = 0;
ex = 0;
end
end
endmodule
| 6.622616 |
module stall_controller (
input [4:0] IDA1,
input [1:0] Tuse1,
input [4:0] IDA2,
input [1:0] Tuse2,
input [4:0] DEA3,
input DERegWE,
input [1:0] DETnew,
input [4:0] EMA3,
input EMRegWE,
input [1:0] EMTnew,
input [4:0] MWA3,
input MWRegWE,
input [1:0] MWTnew,
//Busy
input MDUBusy,
input DE_MDUEN,
input MDUreq,
output stall
);
wire [1:0] A1Tnew, A2Tnew;
assign A1Tnew= IDA1==DEA3&&DERegWE ? DETnew :
IDA1==EMA3&&EMRegWE ? EMTnew :
IDA1==MWA3&&MWRegWE ? MWTnew :
2'd0;
assign A2Tnew= IDA2==DEA3&&DERegWE ? DETnew :
IDA2==EMA3&&EMRegWE ? EMTnew :
IDA2==MWA3&&MWRegWE ? MWTnew :
2'd0;
assign stall= (IDA1!=0&&A1Tnew>Tuse1)||(IDA2!=0&&A2Tnew>Tuse2) || (MDUBusy&&MDUreq);
endmodule
| 7.056201 |
module stall_control_block (
stall,
stall_pm,
op,
clk,
reset
);
input [5:0] op;
input clk, reset;
output stall, stall_pm;
//Output of AND Gates will be stored here
wire HLT, LD_op, JUMP;
// Assigning appropriate values
assign HLT = (op[0] && ~op[1] && ~op[2] && ~op[3] && op[4] && ~op[5]);
assign LD_op = (~op[0] && ~op[1] && op[2] && ~op[3] && op[4] && ~op[5] && ~Q[0]);
assign JUMP = (op[2] && op[3] && op[4] && ~op[5] && ~Q[3]);
assign stall = (HLT || JUMP || LD_op);
assign stall_pm = Q[2];
// Outputs of D Flip Flops
wire [3:0] Q;
d_flip_flop dff0 (
Q[0],
LD_op,
clk,
reset
);
d_flip_flop dff1 (
Q[1],
JUMP,
clk,
reset
);
d_flip_flop dff2 (
Q[2],
stall,
clk,
reset
);
d_flip_flop dff3 (
Q[3],
Q[1],
clk,
reset
);
endmodule
| 7.056201 |
module
module d_flip_flop(Q,D,clk,reset);
output reg Q;
input D, clk, reset;
always@(posedge clk)
begin
if(reset)
Q <= D;
else
Q <= 1'b0;
end
endmodule
| 7.744862 |
module: stall_control_block
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module stall_control_block_tb;
// Inputs
reg [5:0] op;
reg clk;
reg reset;
// Outputs
wire stall;
wire stall_pm;
// Instantiate the Unit Under Test (UUT)
stall_control_block uut (
.stall(stall),
.stall_pm(stall_pm),
.op(op),
.clk(clk),
.reset(reset)
);
initial begin
// Initialize Inputs
op = 0;
clk = 0;
reset = 1'b1;
#2;
reset = 0;
#6;
reset = 1;
#8;
op = 6'b010100;
#20;
op = 6'b0;
#10;
op = 6'b011110;
#30;
op = 6'b0;
#10;
op = 6'b010001;
end
always #5 clk = ~clk;
endmodule
| 7.151925 |
module stall_control_module (
stall,
stall_pm,
ins_pm,
clk,
reset
);
output stall, stall_pm; //declaring output
input clk, reset; //declaring input
input [19:0] ins_pm; //declaring input of 20 bits
wire [4:0] temp; //declaring wire of 5 bits
wire Jump, LD, HLT, d1, d2, d3; //declaring wires
assign temp = ins_pm[19:15]; //assigning bits from 15 to 19 of ins_pm to temp
//gate level modeling
and (HLT, temp[0], ~temp[1], ~temp[2], ~temp[3], temp[4]); //checking if the opcode is of HLT
and (
LD, ~temp[0], ~temp[1], temp[2], ~temp[3], temp[4], ~d1
); //checking if the opcode is of Load
and (Jump, temp[2], temp[3], temp[4], ~d3); //checking if the opcode is of Jump
or (stall, Jump, LD, HLT); //if it is HLT or Jump or LD than making stall signal 1
//creating instances of d flip flop ( d_flipflop(input, output, reset, clk) )
d_flipflop dff1 (
LD,
d1,
reset,
clk
); //stalling for 1 clk cycle for LD instruction
//staling for total 2 clk cycles for Jump instruction
d_flipflop dff2 (
Jump,
d2,
reset,
clk
);
d_flipflop dff3 (
d2,
d3,
reset,
clk
);
d_flipflop dff4 (
stall,
stall_pm,
reset,
clk
); //making stall_pm signal 1 after 1 clock cycle of stall
endmodule
| 7.056201 |
module of our microprocessor.
///////////////////////////////////////////////////////////////////
module stall_control_tb;
// Inputs
reg [19:0] ins_pm;
reg clk;
reg reset;
// Outputs
wire stall;
wire stall_pm;
// Instantiate the Unit Under Test (UUT)
stall_control_module uut (
.stall(stall),
.stall_pm(stall_pm),
.ins_pm(ins_pm),
.clk(clk),
.reset(reset)
);
always #500 clk=~clk; //changing the value of clk after every 500 ns
initial begin
// Initialize Inputs
clk = 1'b0;
ins_pm = 20'h00000; //value in hexadecimal
reset = 1'b1; //value in binary
#200; //after 200 ns reset changes from 1 to 0
reset=1'b0;
#550;
reset = 1'b1;
#850;
ins_pm = 20'ha0000;
#2000;
ins_pm=20'h00000;
#1000;
ins_pm=20'hf0000;
#3000;
ins_pm=20'h00000;
#1000;
ins_pm=20'h88000;
end
endmodule
| 7.266313 |
module Stall_Detection_Unit (
input [31:0] InstrD,
input [31:0] InstrE,
input [31:0] InstrM,
input IntReq,
output stall
);
Instruction_Decoder ID_D (
.Instr(InstrD),
.cal_r(cal_r_D),
.cal_s(cal_s_D),
.cal_il(cal_il_D),
.cal_ia(cal_ia_D),
.load(load_D),
.store(store_D),
.b_cmp(b_cmp_D),
.b_cmpz(b_cmpz_D),
.j(j_D),
.jal(jal_D),
.jr(jr_D),
.jalr(jalr_D),
.eret(eret_D)
);
/* ָ
wire cal_r_D;
wire cal_s_D;
wire cal_il_D;
wire cal_ia_D;
wire load_D;
wire store_D;
wire b_cmp_D;
wire b_cmpz_D;
wire j_D;
wire jal_D;
wire jr_D;
wire jalr_D;
wire mult_div_D;
wire mf_D;
wire mt_D;
wire eret_D;
*/
Instruction_Decoder ID_E (
.Instr(InstrE),
.cal_r(cal_r_E),
.cal_s(cal_s_E),
.cal_il(cal_il_E),
.cal_ia(cal_ia_E),
.load(load_E),
.store(store_E),
.b_cmp(b_cmp_E),
.b_cmpz(b_cmpz_E),
.j(j_E),
.jal(jal_E),
.jr(jr_E),
.jalr(jalr_E),
.mtc0(mtc0_E),
.mfc0(mfc0_E)
);
/* ָ
wire cal_r_E;
wire cal_s_E;
wire cal_il_E;
wire cal_ia_E;
wire load_E;
wire store_E;
wire b_cmp_E;
wire b_cmpz_E;
wire j_E;
wire jal_E;
wire jr_E;
wire jalr_E;
wire mult_div_E;
wire mf_E;
wire mt_E;
wire mtc0_E;
wire mfc0_E;
*/
Instruction_Decoder ID_M (
.Instr(InstrM),
.cal_r(cal_r_M),
.cal_s(cal_s_M),
.cal_il(cal_il_M),
.cal_ia(cal_ia_M),
.load(load_M),
.store(store_M),
.b_cmp(b_cmp_M),
.b_cmpz(b_cmpz_M),
.j(j_M),
.jal(jal_M),
.jr(jr_M),
.jalr(jalr_M),
.mtc0(mtc0_M),
.mfc0(mfc0_M)
);
/* ָ
wire cal_r_M;
wire cal_s_M;
wire cal_il_M;
wire cal_ia_M;
wire load_M;
wire store_M;
wire b_cmp_M;
wire b_cmpz_M;
wire j_M;
wire jal_M;
wire jr_M;
wire jalr_M;
wire mult_div_M;
wire mf_M;
wire mt_M;
wire mtc0_M;
wire mfc0_M;
*/
// ͣж
wire rs_use_1_D = cal_r_D || cal_il_D || cal_ia_D || load_D || store_D;
wire rs_use_0_D = b_cmp_D || b_cmpz_D || jr_D || jalr_D;
wire rt_use_1_D = cal_r_D || cal_s_D;
wire rt_use_0_D = b_cmp_D;
wire rd_new_1_E = cal_r_E || cal_s_E;
wire rt_new_1_E = cal_il_E || cal_ia_E;
wire rt_new_2_E = load_E || mfc0_E;
wire rt_new_1_M = load_M || mfc0_M;
wire stall_rs = InstrD[`rs]!=0 && (
(rs_use_1_D && rt_new_2_E && InstrD[`rs]==InstrE[`rt]) ||
(rs_use_0_D && rd_new_1_E && InstrD[`rs]==InstrE[`rd]) ||
(rs_use_0_D && rt_new_1_E && InstrD[`rs]==InstrE[`rt]) ||
(rs_use_0_D && rt_new_2_E && InstrD[`rs]==InstrE[`rt]) ||
(rs_use_0_D && rt_new_1_M && InstrD[`rs]==InstrM[`rt]));
wire stall_rt = InstrD[`rt]!=0 && (
(rt_use_1_D && rt_new_2_E && InstrD[`rt]==InstrE[`rt]) ||
(rt_use_0_D && rd_new_1_E && InstrD[`rt]==InstrE[`rd]) ||
(rt_use_0_D && rt_new_1_E && InstrD[`rt]==InstrE[`rt]) ||
(rt_use_0_D && rt_new_2_E && InstrD[`rt]==InstrE[`rt]) ||
(rt_use_0_D && rt_new_1_M && InstrD[`rt]==InstrM[`rt]));
wire stall_cp0 = eret_D && (
(mtc0_E && InstrE[`rd]==14) ||
(mtc0_M && InstrM[`rd]==14) ); // EPCijͻ
assign stall = !IntReq && (stall_rs || stall_rt || stall_cp0);
endmodule
| 6.686589 |
module stall_solve (
input nop,
input regwrite,
input [2:0] aluc,
input alusrc,
input regdst,
input memtoreg,
input memwrite,
input [1:0] extop,
input branch,
input memread,
output regwriteD,
output [2:0] alucD,
output alusrcD,
output regdstD,
output memtoregD,
output memwriteD,
output [1:0] extopD,
output branchD,
output memreadD
);
assign regwriteD = nop ? 0 : regwrite;
assign alucD = nop ? 0 : aluc;
assign alusrcD = nop ? 0 : alusrc;
assign regdstD = nop ? 0 : regdst;
assign memtoregD = nop ? 0 : memtoreg;
assign memwriteD = nop ? 0 : memwrite;
assign extopD = nop ? 0 : extop;
assign branchD = nop ? 0 : branch;
assign memreadD = nop ? 0 : memread;
endmodule
| 6.674315 |
module stall_unit (
//from mdu
input busy_from_mdu,
input finish_from_mdu,
input [`ZCRV_REG_SIZE-1:0] rd_from_mdu,
//from other clk id/ex stage
input [`ZCRV_REG_SIZE-1:0] rs1_from_id,
input [`ZCRV_REG_SIZE-1:0] rs2_from_id,
input [`ZCRV_REG_SIZE-1:0] rd_from_id,
input md_from_id,
input rs1_en_from_id,
input rs2_en_from_id,
input rd_en_from_id,
//to stall pipeline
output pipe_stall
);
wire mdu_rd_eq_id_rs1 = rs1_en_from_id ? (rs1_from_id == rd_from_mdu) : 1'b0;
wire mdu_rd_eq_id_rs2 = rs2_en_from_id ? (rs2_from_id == rd_from_mdu) : 1'b0;
wire mdu_rd_eq_id_rd = rd_en_from_id ? (rd_from_id == rd_from_mdu) : 1'b0;
wire mdu_busy_but_md = (md_from_id == busy_from_mdu);
wire mdu_finish_need_stall = finish_from_mdu;
wire mdu_stall_t = mdu_finish_need_stall | ((mdu_rd_eq_id_rd | mdu_rd_eq_id_rs1 | mdu_rd_eq_id_rs2 | mdu_busy_but_md) & ~mdu_finish_need_stall) ;
wire mdu_stall = mdu_stall_t & busy_from_mdu;
assign pipe_stall = mdu_stall;
endmodule
| 6.713718 |
module
*
* Copyright notice:
* Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford
* Junior University
*
* Licence:
* This file is part of the NetFPGA 10G development base package.
*
* This file is free code: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 2.1 as
* published by the Free Software Foundation.
*
* This package is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with the NetFPGA source package. If not, see
* http://www.gnu.org/licenses/.
*
*/
module stamp_counter
#(
parameter TIMESTAMP_WIDTH = 64)
(
output [TIMESTAMP_WIDTH-1:0] stamp_counter,
output reg gps_connected,
input [1:0] restart_time,
input [TIMESTAMP_WIDTH-1:0] ntp_timestamp,
input correction_mode,
input pps_rx,
input axi_aclk,
input axi_resetn
);
localparam PPS = 27'h5F5E100;
localparam OVERFLOW = 32'hffffffff;
localparam CNT_INIT = 32'h1312d000;
localparam DDS_WIDTH = 32;
reg [TIMESTAMP_WIDTH-6:0] temp;
wire[TIMESTAMP_WIDTH-1:0] stamp_cnt;
wire pps_valid;
reg pps_rx_d1;
reg pps_rx_d2;
reg pps_rx_d3;
reg [DDS_WIDTH-1:0] accumulator;
reg [31:0] counter;
wire [DDS_WIDTH-1:0] dds_rate;
assign stamp_counter = {temp,5'b0};
assign stamp_cnt = {temp,5'b0};
assign pps_valid = !pps_rx_d2 & pps_rx_d3;
correction
#(
.TIMESTAMP_WIDTH(TIMESTAMP_WIDTH),
.DDS_WIDTH(DDS_WIDTH))
correction
(
// input
.time_pps (stamp_cnt),
.pps_valid (pps_valid),
.correction_mode(correction_mode),
// output
.dds (dds_rate),
// misc
.reset (~axi_resetn),
.clk (axi_aclk)
);
always @(posedge axi_aclk) begin
if (~axi_resetn) begin
pps_rx_d1 <= 0;
pps_rx_d2 <= 0;
pps_rx_d3 <= 0;
counter <= CNT_INIT;
gps_connected <= 0;
end
else begin
pps_rx_d1 <= pps_rx;
pps_rx_d2 <= pps_rx_d1;
pps_rx_d3 <= pps_rx_d2;
if(pps_valid) begin
counter <= CNT_INIT;
gps_connected <= 1;
end
else begin
if(!counter)
gps_connected <= 0;
else begin
gps_connected <= 1;
counter <= counter - 1;
end
end
end
end
always @(posedge axi_aclk) begin
if(~axi_resetn) begin
temp <= 0;
accumulator <= 0;
end
else begin
if(restart_time[0])
temp<= ntp_timestamp[TIMESTAMP_WIDTH-1:5];
else if (restart_time[1])
temp<= 0;
else begin
if(OVERFLOW-accumulator<dds_rate)
temp <= temp + 1;
accumulator <= accumulator + dds_rate;
end
end
end
endmodule
| 6.70034 |
module standardizer #(
parameter EXP_SIZE = `EXP_SIZE,
parameter MANTIS_SIZE = `MANTIS_SIZE
) (
exp_in,
mantis_in,
operator_in,
loss,
exp_out,
mantis_out
);
// Inputs
input [EXP_SIZE -1:0] exp_in; // input exponent
input [(MANTIS_SIZE+3)-1:0] mantis_in; // input mantissa
input loss; // lost detector
input operator_in; // input operator (+ or -)
// Outputs
output [EXP_SIZE -1:0] exp_out; // exponent output
output [MANTIS_SIZE-1:0] mantis_out; // mantissa output
//Wires
wire [ EXP_SIZE -1:0] exp_norm; // normalized exponent
wire [(MANTIS_SIZE+3)-1:0] mantis_norm; // normalized mantissa
// Instances
normalize __normalize (
.exp_in (exp_in),
.mantis_in (mantis_in),
.exp_out (exp_norm),
.mantis_out(mantis_norm)
);
round __round (
.exp (exp_norm),
.mantis (mantis_norm),
.operator (operator_in),
.loss (loss),
.exp_out (exp_out),
.mantis_out(mantis_out)
);
endmodule
| 6.604843 |
module standard_deviation_filter #(
parameter WIDTH = 14,
parameter WINDOW_WIDTH = 7
) (
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out,
input wire reset,
input wire clk
);
wire [WIDTH*2-1:0] variance_out;
variance #(
.WIDTH(WIDTH),
.WINDOW_WIDTH(WINDOW_WIDTH)
) variance_inst (
.data_in(data_in),
.data_out(variance_out),
.reset(reset),
.clk(clk)
);
sqrt #(
.INTEGER_INPUT_WIDTH(28)
) sqrt_inst (
.integer_input(variance_out),
.result(data_out),
.reset(reset),
.clk(clk)
);
endmodule
| 8.302781 |
module stand_1bit (
input clk,
input enable,
input din,
output reg dout
);
/**
* Always checking for positive edge of clock to make the changes
* on output , based on the input and register enable status.
*
*/
always @(posedge clk) begin
if (enable) dout <= din;
end
endmodule
| 7.198945 |
module cordic_sin_cos (
input clock,
input reset,
input [63:0] io_theta,
output [63:0] io_sin,
output [63:0] io_cos
);
wire cordic_unit_clock; // @[Cordic_CR.scala 145:45]
wire cordic_unit_reset; // @[Cordic_CR.scala 145:45]
wire [63:0] cordic_unit_io_x; // @[Cordic_CR.scala 145:45]
wire [63:0] cordic_unit_io_y; // @[Cordic_CR.scala 145:45]
wire [63:0] cordic_unit_io_theta; // @[Cordic_CR.scala 145:45]
wire [63:0] cordic_unit_io_x_n; // @[Cordic_CR.scala 145:45]
wire [63:0] cordic_unit_io_y_n; // @[Cordic_CR.scala 145:45]
wire [63:0] _temp_theta_T_2 = $signed(io_theta) - 64'sh16800000000; // @[Cordic_CR.scala 123:28]
wire [63:0] _temp_theta_T_5 = $signed(io_theta) + 64'sh16800000000; // @[Cordic_CR.scala 125:28]
wire [63:0] _GEN_0 = $signed(
io_theta
) < -64'shb400000000 ? $signed(
_temp_theta_T_5
) : $signed(
io_theta
); // @[Cordic_CR.scala 124:83 125:16 127:16]
wire [63:0] temp_theta = $signed(
io_theta
) > 64'shb400000000 ? $signed(
_temp_theta_T_2
) : $signed(
_GEN_0
); // @[Cordic_CR.scala 122:76 123:16]
wire _T_2 = $signed(temp_theta) > 64'sh5a00000000; // @[Cordic_CR.scala 133:19]
wire [63:0] _real_theta_T_2 = 64'shb400000000 - $signed(temp_theta); // @[Cordic_CR.scala 136:75]
wire [63:0] _real_theta_T_5 = -64'shb400000000 - $signed(
temp_theta
); // @[Cordic_CR.scala 139:76]
wire _GEN_2 = $signed(
temp_theta
) < -64'sh5a00000000 ? 1'h0 : 1'h1; // @[Cordic_CR.scala 137:84 138:15 141:15]
wire [63:0] _GEN_3 = $signed(
temp_theta
) < -64'sh5a00000000 ? $signed(
_real_theta_T_5
) : $signed(
temp_theta
); // @[Cordic_CR.scala 137:84 139:16 142:16]
wire sigma_cos = _T_2 ? 1'h0 : _GEN_2; // @[Cordic_CR.scala 134:5 135:15]
wire [63:0] _io_cos_T_2 = 64'sh0 - $signed(cordic_unit_io_x_n); // @[Cordic_CR.scala 153:15]
CORDIC_CR_ORIGIN cordic_unit ( // @[Cordic_CR.scala 145:45]
.clock(cordic_unit_clock),
.reset(cordic_unit_reset),
.io_x(cordic_unit_io_x),
.io_y(cordic_unit_io_y),
.io_theta(cordic_unit_io_theta),
.io_x_n(cordic_unit_io_x_n),
.io_y_n(cordic_unit_io_y_n)
);
assign io_sin = cordic_unit_io_y_n; // @[Cordic_CR.scala 149:10]
assign io_cos = sigma_cos ? $signed(
cordic_unit_io_x_n
) : $signed(
_io_cos_T_2
); // @[Cordic_CR.scala 150:19 151:12 153:12]
assign cordic_unit_clock = clock;
assign cordic_unit_reset = reset;
assign cordic_unit_io_x = 64'sh100000000; // @[Cordic_CR.scala 146:20]
assign cordic_unit_io_y = 64'sh0; // @[Cordic_CR.scala 147:20]
assign cordic_unit_io_theta = _T_2 ? $signed(
_real_theta_T_2
) : $signed(
_GEN_3
); // @[Cordic_CR.scala 134:5 136:16]
endmodule
| 7.055288 |
module ComplexMul (
input [63:0] io_op1_re,
input [63:0] io_op1_im,
input [63:0] io_op2_re,
input [63:0] io_op2_im,
output [63:0] io_res_re,
output [63:0] io_res_im
);
wire [63:0] _k1_T_2 = $signed(io_op1_re) + $signed(io_op1_im); // @[Complex_Operater.scala 38:35]
wire [127:0] k1 = $signed(io_op2_re) * $signed(_k1_T_2); // @[Complex_Operater.scala 38:22]
wire [63:0] _k2_T_2 = $signed(io_op2_im) - $signed(io_op2_re); // @[Complex_Operater.scala 39:35]
wire [127:0] k2 = $signed(io_op1_re) * $signed(_k2_T_2); // @[Complex_Operater.scala 39:22]
wire [63:0] _k3_T_2 = $signed(io_op2_re) + $signed(io_op2_im); // @[Complex_Operater.scala 40:35]
wire [127:0] k3 = $signed(io_op1_im) * $signed(_k3_T_2); // @[Complex_Operater.scala 40:22]
wire [127:0] _io_res_re_T_2 = $signed(k1) - $signed(k3); // @[Complex_Operater.scala 41:19]
wire [127:0] _io_res_im_T_2 = $signed(k1) + $signed(k2); // @[Complex_Operater.scala 42:19]
wire [95:0] _GEN_0 = _io_res_re_T_2[127:32]; // @[Complex_Operater.scala 41:13]
wire [95:0] _GEN_2 = _io_res_im_T_2[127:32]; // @[Complex_Operater.scala 42:13]
assign io_res_re = _GEN_0[63:0]; // @[Complex_Operater.scala 41:13]
assign io_res_im = _GEN_2[63:0]; // @[Complex_Operater.scala 42:13]
endmodule
| 7.643712 |
module kronecker_v1 (
input [63:0] io_matrixA_1_re,
input [63:0] io_matrixA_1_im,
input [63:0] io_matrixB_1_re,
input [63:0] io_matrixB_1_im,
output [63:0] io_matrixOut_0_re,
output [63:0] io_matrixOut_0_im,
output [63:0] io_matrixOut_1_re,
output [63:0] io_matrixOut_1_im,
output [63:0] io_matrixOut_2_re,
output [63:0] io_matrixOut_2_im,
output [63:0] io_matrixOut_3_re,
output [63:0] io_matrixOut_3_im
);
wire [63:0] unit_io_matrixIn_1_re; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_io_matrixIn_1_im; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_io_valueIn_re; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_io_valueIn_im; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_io_matrixOut_0_re; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_io_matrixOut_0_im; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_io_matrixOut_1_re; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_io_matrixOut_1_im; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_1_io_matrixIn_1_re; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_1_io_matrixIn_1_im; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_1_io_valueIn_re; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_1_io_valueIn_im; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_1_io_matrixOut_0_re; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_1_io_matrixOut_0_im; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_1_io_matrixOut_1_re; // @[Kronecker_V1.scala 39:22]
wire [63:0] unit_1_io_matrixOut_1_im; // @[Kronecker_V1.scala 39:22]
matrix_vlaue_mul unit ( // @[Kronecker_V1.scala 39:22]
.io_matrixIn_1_re(unit_io_matrixIn_1_re),
.io_matrixIn_1_im(unit_io_matrixIn_1_im),
.io_valueIn_re(unit_io_valueIn_re),
.io_valueIn_im(unit_io_valueIn_im),
.io_matrixOut_0_re(unit_io_matrixOut_0_re),
.io_matrixOut_0_im(unit_io_matrixOut_0_im),
.io_matrixOut_1_re(unit_io_matrixOut_1_re),
.io_matrixOut_1_im(unit_io_matrixOut_1_im)
);
matrix_vlaue_mul unit_1 ( // @[Kronecker_V1.scala 39:22]
.io_matrixIn_1_re(unit_1_io_matrixIn_1_re),
.io_matrixIn_1_im(unit_1_io_matrixIn_1_im),
.io_valueIn_re(unit_1_io_valueIn_re),
.io_valueIn_im(unit_1_io_valueIn_im),
.io_matrixOut_0_re(unit_1_io_matrixOut_0_re),
.io_matrixOut_0_im(unit_1_io_matrixOut_0_im),
.io_matrixOut_1_re(unit_1_io_matrixOut_1_re),
.io_matrixOut_1_im(unit_1_io_matrixOut_1_im)
);
assign io_matrixOut_0_re = unit_io_matrixOut_0_re; // @[Kronecker_V1.scala 67:29 68:19]
assign io_matrixOut_0_im = unit_io_matrixOut_0_im; // @[Kronecker_V1.scala 67:29 68:19]
assign io_matrixOut_1_re = unit_io_matrixOut_1_re; // @[Kronecker_V1.scala 67:29 68:19]
assign io_matrixOut_1_im = unit_io_matrixOut_1_im; // @[Kronecker_V1.scala 67:29 68:19]
assign io_matrixOut_2_re = unit_1_io_matrixOut_0_re; // @[Kronecker_V1.scala 67:29 68:19]
assign io_matrixOut_2_im = unit_1_io_matrixOut_0_im; // @[Kronecker_V1.scala 67:29 68:19]
assign io_matrixOut_3_re = unit_1_io_matrixOut_1_re; // @[Kronecker_V1.scala 67:29 68:19]
assign io_matrixOut_3_im = unit_1_io_matrixOut_1_im; // @[Kronecker_V1.scala 67:29 68:19]
assign unit_io_matrixIn_1_re = io_matrixB_1_re; // @[Kronecker_V1.scala 40:22]
assign unit_io_matrixIn_1_im = io_matrixB_1_im; // @[Kronecker_V1.scala 40:22]
assign unit_io_valueIn_re = 64'sh100000000; // @[Kronecker_V1.scala 41:21]
assign unit_io_valueIn_im = 64'sh0; // @[Kronecker_V1.scala 41:21]
assign unit_1_io_matrixIn_1_re = io_matrixB_1_re; // @[Kronecker_V1.scala 40:22]
assign unit_1_io_matrixIn_1_im = io_matrixB_1_im; // @[Kronecker_V1.scala 40:22]
assign unit_1_io_valueIn_re = io_matrixA_1_re; // @[Kronecker_V1.scala 41:21]
assign unit_1_io_valueIn_im = io_matrixA_1_im; // @[Kronecker_V1.scala 41:21]
endmodule
| 6.557244 |
module ComplexAdd (
input [63:0] io_op1_re,
input [63:0] io_op1_im,
input [63:0] io_op2_re,
input [63:0] io_op2_im,
output [63:0] io_res_re,
output [63:0] io_res_im
);
assign io_res_re = $signed(io_op1_re) + $signed(io_op2_re); // @[Complex_Operater.scala 7:26]
assign io_res_im = $signed(io_op1_im) + $signed(io_op2_im); // @[Complex_Operater.scala 8:26]
endmodule
| 8.602364 |
module cordic_cv (
input clock,
input reset,
input [63:0] io_x,
input [63:0] io_y,
output [63:0] io_theta,
output [63:0] io_r
);
wire cordic_cv_unit_clock; // @[Cordic_CV.scala 104:30]
wire cordic_cv_unit_reset; // @[Cordic_CV.scala 104:30]
wire [63:0] cordic_cv_unit_io_x; // @[Cordic_CV.scala 104:30]
wire [63:0] cordic_cv_unit_io_y; // @[Cordic_CV.scala 104:30]
wire [63:0] cordic_cv_unit_io_theta; // @[Cordic_CV.scala 104:30]
wire [63:0] cordic_cv_unit_io_r; // @[Cordic_CV.scala 104:30]
wire [63:0] _cordic_cv_unit_io_x_T_2 = 64'sh0 - $signed(io_x); // @[Cordic_CV.scala 107:28]
wire [63:0] _cordic_cv_unit_io_y_T_2 = 64'sh0 - $signed(io_y); // @[Cordic_CV.scala 108:28]
wire [63:0] _io_theta_T_2 = $signed(
cordic_cv_unit_io_theta
) + 64'shb400000000; // @[Cordic_CV.scala 110:43]
wire [63:0] _io_theta_T_5 = $signed(
cordic_cv_unit_io_theta
) - 64'shb400000000; // @[Cordic_CV.scala 112:43]
wire [63:0] _GEN_0 = $signed(
io_y
) > 64'sh0 ? $signed(
_io_theta_T_2
) : $signed(
_io_theta_T_5
); // @[Cordic_CV.scala 109:71 110:16 112:16]
CORDIC_CV_ORIGIN cordic_cv_unit ( // @[Cordic_CV.scala 104:30]
.clock(cordic_cv_unit_clock),
.reset(cordic_cv_unit_reset),
.io_x(cordic_cv_unit_io_x),
.io_y(cordic_cv_unit_io_y),
.io_theta(cordic_cv_unit_io_theta),
.io_r(cordic_cv_unit_io_r)
);
assign io_theta = $signed(
io_x
) < 64'sh0 ? $signed(
_GEN_0
) : $signed(
cordic_cv_unit_io_theta
); // @[Cordic_CV.scala 106:69 117:14]
assign io_r = cordic_cv_unit_io_r; // @[Cordic_CV.scala 120:8]
assign cordic_cv_unit_clock = clock;
assign cordic_cv_unit_reset = reset;
assign cordic_cv_unit_io_x = $signed(
io_x
) < 64'sh0 ? $signed(
_cordic_cv_unit_io_x_T_2
) : $signed(
io_x
); // @[Cordic_CV.scala 106:69 107:25 115:25]
assign cordic_cv_unit_io_y = $signed(
io_x
) < 64'sh0 ? $signed(
_cordic_cv_unit_io_y_T_2
) : $signed(
io_y
); // @[Cordic_CV.scala 106:69 108:25 116:25]
endmodule
| 7.286598 |
module ComplexSub (
input [63:0] io_op1_re,
input [63:0] io_op1_im,
input [63:0] io_op2_re,
input [63:0] io_op2_im,
output [63:0] io_res_re,
output [63:0] io_res_im
);
assign io_res_re = $signed(io_op1_re) - $signed(io_op2_re); // @[Complex_Operater.scala 22:26]
assign io_res_im = $signed(io_op1_im) - $signed(io_op2_im); // @[Complex_Operater.scala 23:26]
endmodule
| 8.653321 |
module starfield_top (
input wire [0 : 0] clk, // clock
input wire [0 : 0] reset, // reset
output wire [0 : 0] hsync, // horizontal sync
output wire [0 : 0] vsync, // vertical sync
output wire [2 : 0] rgb // RGB VGA
);
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
wire [ 0 : 0] display_on;
wire [ 0 : 0] star_on;
wire [ 0 : 0] star_enable;
wire [15 : 0] hpos;
wire [15 : 0] vpos;
wire [15 : 0] lfsr;
/*******************************************************
* ASSIGNMENT *
*******************************************************/
assign star_enable = (!hpos[15]) && (!vpos[15]);
assign star_on = &lfsr[15 : 9]; // all 7 bits must be set
assign rgb = display_on && star_on ? lfsr[2 : 0] : 3'b000;
/*******************************************************
* MODULE INSTANCES *
*******************************************************/
// creating one hvsync generator
hvsync_generator hvsync_gen (
.clk (clk),
.reset (reset),
.hsync (hsync),
.vsync (vsync),
.display_on(display_on),
.hpos (hpos),
.vpos (vpos)
);
// creating one lfsr_gen
LFSR #(
.NBITS (2048),
.TAPS (8'b11101),
.INVERT(0)
) lfsr_gen (
.clk (clk),
.reset (reset),
.enable(star_enable),
.lfsr (lfsr)
);
endmodule
| 6.655319 |
module StartButton (
input wire clk,
input wire rst_n,
input wire [3:0] key_val,
input wire key_flag,
input wire [1:0] state,
output reg start = 0
);
parameter INITIAL = 2'b00;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) start <= 0;
else if (state != INITIAL) start <= 0;
else if (!key_flag) start <= 0;
else if (key_val == 4'hf) start <= 1;
else start <= 0;
end
endmodule
| 8.192184 |
module StartCounter #(
////////////////////////////////////////////////////
// Parameters
parameter width = 4
) (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
CountEn,
Start,
output reg [width-1:0] Count,
output reg End,
Busy
);
wire [width+1:0] wCount = {Busy, Count} + 1'b1;
wire wCarry = wCount[width+1];
always @(posedge Reset or posedge Clock) begin
if (Reset) begin
Count <= 1'b0;
Busy <= 1'b0;
End <= 1'b0;
end else begin
if (Start) Busy <= 1'b1;
else if (Busy && CountEn) {Busy, Count} <= wCount;
End <= wCarry;
end
end
endmodule
| 7.055272 |
module StartDelay (
clock,
reset,
trigger,
timeOut
);
input clock; // NbN
input reset; // Zbg
input trigger; // NM
output timeOut; // ^CAEgM
reg [2:0] StartDelayCount; // 3rbg̃JE^
always @(posedge clock or negedge reset) begin
if (!reset) begin
StartDelayCount <= 0; // Zbg
end else if (trigger) begin
StartDelayCount <= 1; // 3'b001ɂ
end else if (StartDelayCount) begin
StartDelayCount <= StartDelayCount + 1; // JEg
end
end
// & Zq͑Srbg1ǂ
// ܂3'b111̂Ƃ^CAEĝANeBu
assign timeOut = &StartDelayCount;
endmodule
| 7.07327 |
module starter3e (
input CLK_50MHZ,
input [3:0] SW,
input BTN_EAST,
input BTN_NORTH,
input BTN_SOUTH,
input BTN_WEST,
output [7:0] LED
);
wire [9:0] outputs;
assign LED = outputs[7:0];
top top (
.clock (CLK_50MHZ),
.reset_n(BTN_NORTH),
.buttons({BTN_WEST, BTN_SOUTH, BTN_EAST}),
.inputs ({2'b0, SW, SW}),
.outputs(outputs)
);
endmodule
| 7.120118 |
module startscreen_rom (
input clk,
input [7:0] x,
input [6:0] y,
output reg [2:0] dout
);
parameter IMAGE_FILE = "startscreen.mem";
wire [14:0] addr = 160 * y + x;
reg [2:0] mem[0:19199];
initial $readmemh(IMAGE_FILE, mem);
always @(posedge clk) dout <= mem[addr];
endmodule
| 7.426057 |
module startStopConfig (
clk,
rst_n,
start,
stop,
clr,
din,
sin,
dout,
sout
);
input clk;
input rst_n;
input start;
input stop;
input clr;
input [7:0] din;
input sin;
output [7:0] dout;
output sout;
reg enable; //1:ok 2:nonono
always @(posedge clk or negedge rst_n)
if (!rst_n) enable = 0;
else if (clr) enable = 1;
else if (stop) enable = 0;
else if (start) enable = 1;
else enable = enable;
//assign dout=enable?din:8'd0; is unnecessary
assign dout = din;
assign sout = enable ? sin : 1'd0;
endmodule
| 7.190821 |
module startStopLapReset_LCD ( CLK_50M,
SW,
PUSH_BTN_SS, PUSH_BTN_LR,
LED,
LCD_DB,
LCD_E, LCD_RS, LCD_RW);
input CLK_50M;
input SW;
input PUSH_BTN_SS;
input PUSH_BTN_LR;
output [7:0] LED;
output [7:0] LCD_DB;
output LCD_E;
output LCD_RS;
output LCD_RW;
wire [15:0] wb_counter;
wire [15:0] wb_counter_toShow;
wire w_startstop_pulse;
wire w_startStop;
wire w_lapreset_pulse_0;
wire w_lapreset_pulse_1;
wire w_lapreset_pulse_2;
wire w_lap_pulse;
wire w_lapFlag;
wire w_reset;
wire w_clock_1kHz;
wire w_clock_100_Hz;
wire w_enabled_clock_100_Hz;
wire w_clock_10_Hz;
wire w_clock_1_Hz;
wire w_clock_01_Hz;
//commands
Module_FrequencyDivider clock_1kHz_generator_for_monostables ( .clk_in(CLK_50M),
.period(`1_kHz_Period),
.clk_out(w_clock_1kHz));
Module_Monostable startstop_pulse ( .clk_in(w_clock_1kHz), // .clk_in(CLK_50M),
.monostable_input(PUSH_BTN_SS),
.N(28'd5), // .N(28'd5000000),
.monostable_output(w_startstop_pulse));
Module_ToggleFlipFlop startstop_ff ( .clk_in(CLK_50M),
.ff_input(w_startstop_pulse),
.ff_output(w_startStop));
Module_Monostable lapreset_pulse_0 ( .clk_in(w_clock_1kHz), // .clk_in(CLK_50M),
.monostable_input(PUSH_BTN_LR),
.N(28'd5), // .N(28'd5000000),
.monostable_output(w_lapreset_pulse_0));
Module_Monostable lapreset_pulse_1 ( .clk_in(w_clock_1kHz),
.monostable_input(!w_lapreset_pulse_0),
.N(28'd5), // .N(28'd5000000),
.monostable_output(w_lapreset_pulse_1));
Module_Monostable lapreset_pulse_2 ( .clk_in(w_clock_1kHz),
.monostable_input(!w_lapreset_pulse_1),
.N(28'd5), // .N(28'd5000000),
.monostable_output(w_lapreset_pulse_2));
assign w_lap_pulse = ((w_startStop | w_lapFlag) & w_lapreset_pulse_2);
assign w_reset = (!w_startStop & !w_lapFlag & w_lapreset_pulse_0);
Module_ToggleFlipFlop lap_ff ( .clk_in(CLK_50M),
.ff_input(w_lap_pulse),
.ff_output(w_lapFlag));
/*********************/
/* TIMING GENERATION */
/*********************/
Module_FrequencyDivider clock_100_Hz ( .clk_in(CLK_50M),
.period(`100_Hz_Period),
.clk_out(w_clock_100_Hz));
and(w_enabled_clock_100_Hz, w_clock_100_Hz, w_startStop);
Module_SynchroCounter_8_bit_SR counter_100_Hz ( .qzt_clk(CLK_50M),
.clk_in(w_enabled_clock_100_Hz),
.reset(w_reset),
.set(0),
.limit(8'b00001010),
.presetValue(0),
.out(wb_counter[3:0]),
.carry(w_clock_10_Hz));
Module_SynchroCounter_8_bit_SR counter_10_Hz ( .qzt_clk(CLK_50M),
.clk_in(w_clock_10_Hz),
.reset(w_reset),
.set(0),
.limit(8'b00001010),
.presetValue(0),
.out(wb_counter[7:4]),
.carry(w_clock_1_Hz));
Module_SynchroCounter_8_bit_SR counter_1_Hz ( .qzt_clk(CLK_50M),
.clk_in(w_clock_1_Hz),
.reset(w_reset),
.set(0),
.limit(8'b00001010),
.presetValue(0),
.out(wb_counter[11:8]),
.carry(w_clock_01_Hz));
Module_SynchroCounter_8_bit_SR counter_01_Hz ( .qzt_clk(CLK_50M),
.clk_in(w_clock_01_Hz),
.reset(w_reset),
.set(0),
.limit(8'b00001010),
.presetValue(0),
.out(wb_counter[15:12]));
//visualization
Module_Latch_16_bit latch ( .clk_in(CLK_50M),
.holdFlag(w_lapFlag),
.twoByteInput(wb_counter),
.twoByteOuput(wb_counter_toShow));
Module_Multiplexer_2_input_8_bit_sync slide_switch ( .clk_in(CLK_50M),
.address(SW),
.input_0(wb_counter[7:0]),
.input_1(wb_counter[15:8]),
.mux_output(LED[7:0]));
buf(LCD_RW, 0);
buf(LCD_DB[3:0], 4'b1111);
LCD_Driver_forChrono lcd_driver ( .qzt_clk(CLK_50M),
.fourDigitInput(wb_counter_toShow),
.lapFlag(w_lapFlag),
.lcd_flags({LCD_RS, LCD_E}),
.lcd_data(LCD_DB[7:4]));
endmodule
| 6.955501 |
module StartStopSequencer (
clock,
reset,
start,
run,
stop,
running
);
input clock; // NbN
input reset; // Zbg
input start; // Q[Jn
input run; // NE
input stop; // Xgbv
output running; // ꂪ8iJE^ւenableMɂrunԂ\M
wire clock, reset;
wire start, run, stop; // X^[gXCb`̐Mstartrunɐڑ
wire running;
reg [1:0] currState; // 2rbgŕ\݂̏(S/W/R)
always @(posedge clock or negedge reset) begin
if (!reset) begin
currState <= `STOP;
end else if ((currState == `STOP) && start) begin
if (~run) begin // NĂȂ
currState <= `WAIT;
end else begin // Ă
currState <= `RUN;
end
end else if ((currState == `WAIT) && run) begin
currState <= `RUN; // Ԃɂ
end else if ((currState == `RUN) && `STOP) begin
currState <= `STOP; // XgbvԂɂ
end
end
assign running = (currState == `RUN);
endmodule
| 6.731442 |
module startsync ( /*AUTOARG*/
// Outputs
startsync_sampler_start_r_sync,
// Inputs
clk_sampler,
rst_sampler_n_sync,
samplertop_startsync_start_sync
);
`include "sync_params.v"
//-------------Input Ports--------------------
input clk_sampler;
input rst_sampler_n_sync;
input samplertop_startsync_start_sync;
//-------------Output Ports-------------------
output reg startsync_sampler_start_r_sync;
//-------------Registers----------------------
reg start_m;
always @(posedge clk_sampler or negedge rst_sampler_n_sync) begin
if (!rst_sampler_n_sync) begin
startsync_sampler_start_r_sync <= 1'b0;
start_m <= 1'b0;
end else begin
start_m <= samplertop_startsync_start_sync;
startsync_sampler_start_r_sync <= start_m;
end
end
endmodule
| 7.058302 |
module startup #(
parameter RESET_TIMEOUT = 32'h0000FFFF
) (
input clk,
output reg startup_rst = 1
);
//Local Parameters
//Registers/Wires
reg [31:0] startup_count;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @(posedge clk) begin
if (startup_count < RESET_TIMEOUT) begin
startup_count <= startup_count + 1;
startup_rst <= 1;
end else begin
startup_rst <= 0;
end
end
endmodule
| 7.419674 |
module startup_wrapper #(
) (
// Flash Interface Pins
output wire [3:0] flash_DQ_I,
input wire [3:0] flash_DQ_O,
input wire [3:0] flash_DQ_tri_ctrl,
input wire flash_CS_N,
input wire flash_CS_N_tri_ctrl,
input wire flash_clk,
output wire startup_eos
);
// STARTUPE3: STARTUP Block
// Kintex UltraScale
// Xilinx HDL Language Template, version 2014.4
STARTUPE3 #(
.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation
) STARTUPE3_inst (
.CFGCLK(), // 1-bit output: Configuration main clock output
.CFGMCLK(), // 1-bit output: Configuration internal oscillator clock output
.DI(flash_DQ_I[3:0]), // 4-bit output: Allow receiving on the D input pin
.EOS(startup_eos), // 1-bit output: Active-High output signal indicating the End Of Startup
.PREQ(), // 1-bit output: PROGRAM request to fabric output
.DO(flash_DQ_O[3:0]), // 4-bit input: Allows control of the D pin output
.DTS(flash_DQ_tri_ctrl[3:0]), // 4-bit input: Allows tristate of the D pin
.FCSBO(flash_CS_N), // 1-bit input: Contols the FCS_B pin for flash access
.FCSBTS(flash_CS_N_tri_ctrl), // 1-bit input: Tristate the FCS_B pin
.GSR(1'b0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port)
.GTS(1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
.KEYCLEARB(1'b1), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
.PACK(1'b0), // 1-bit input: PROGRAM acknowledge input
.USRCCLKO(flash_clk), // 1-bit input: User CCLK input
.USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input
.USRDONEO(1'b0), // 1-bit input: User DONE pin output control
.USRDONETS(1'b0) // 1-bit input: User DONE 3-state enable output
);
endmodule
| 7.588911 |
module start_bgm (
input mp3_clk,
input rst,
input DREQ,
output RSET,
output CS,
output DCS,
output MOSI,
output SCLK
);
parameter MUSIC_SIZE = 21698;
wire [20:0] mp3_addr;
wire [31:0] mp3_data;
wire music_over;
mp3_driver #(
.MUSIC_SIZE(MUSIC_SIZE)
) display_music (
.mp3_clk(mp3_clk),
.rst(rst),
.DREQ(DREQ),
.RSET(RSET),
.CS(CS),
.DCS(DCS),
.MOSI(MOSI),
.SCLK(SCLK),
.music_over(music_over),
.mp3_addr(mp3_addr),
.mp3_data0(mp3_data)
);
rom_start_music start_music (
.clka (mp3_clk), // input wire clka
.ena (~rst), // input wire ena
.addra(mp3_addr[13:0]), // input wire [13 : 0] addra
.douta(mp3_data) // output wire [31 : 0] douta
);
endmodule
| 6.998339 |
module start_bit_det (
input clk,
input n_Rst,
input data_in,
output wire start_detected
);
reg Q_1, Q_2, Q_3;
always @(posedge clk, negedge n_Rst) begin
if (n_Rst == 1'b0) begin
Q_1 <= 1'b1;
Q_2 <= 1'b1;
Q_3 <= 1'b1;
end else begin
Q_3 <= Q_2;
Q_2 <= Q_1;
Q_1 <= data_in;
end
end
//detecting a start bit
assign start_detected = ~(Q_2) & Q_3;
endmodule
| 6.610416 |
module start_for_And_3_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.904696 |
module start_for_And_3_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_And_3_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_And_3_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.904696 |
module start_for_app_aes_end_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd13;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_aes_end_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd13;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_aes_end_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_aes_end_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_aes_process_0_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_aes_process_0_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_aes_process_0_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_aes_process_0_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_aes_process_1_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_aes_process_1_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_aes_process_1_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_aes_process_1_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_aes_process_2_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd6;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_aes_process_2_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd6;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_aes_process_2_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_aes_process_2_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_aes_process_3_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_aes_process_3_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_aes_process_3_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_aes_process_3_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_aes_process_4_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_aes_process_4_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_aes_process_4_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_aes_process_4_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_aes_process_5_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_aes_process_5_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd9;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_aes_process_5_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_aes_process_5_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_aes_process_6_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd10;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_aes_process_6_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd10;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_aes_process_6_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_aes_process_6_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_aes_process_7_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd11;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_aes_process_7_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd11;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_aes_process_7_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_aes_process_7_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_aes_process_8_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd12;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_aes_process_8_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd12;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_aes_process_8_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_aes_process_8_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_aes_start_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_aes_start_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_aes_start_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_aes_start_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_conv_combine_l0_0_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_conv_combine_l0_0_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd9;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_conv_combine_l0_0_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_conv_combine_l0_0_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_conv_combine_l0_1_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd13;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_conv_combine_l0_1_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 32'd13;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_conv_combine_l0_1_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_conv_combine_l0_1_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_conv_combine_l0_2_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd5;
parameter DEPTH = 32'd17;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_conv_combine_l0_2_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd5;
parameter DEPTH = 32'd17;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_conv_combine_l0_2_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_conv_combine_l0_2_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
module start_for_app_conv_combine_l0_3_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd5;
parameter DEPTH = 32'd21;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.739074 |
module start_for_app_conv_combine_l0_3_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd5;
parameter DEPTH = 32'd21;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_app_conv_combine_l0_3_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_app_conv_combine_l0_3_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.739074 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.