code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module counter_14_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 14) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.798894 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module shift_register_unit_12 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else i... | 6.854847 |
module counter_8_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 8) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
en... | 6.902674 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module weight_buffer_18_16_1_64_bc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_1_64_bo_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_1_64_Woc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:... | 6.6283 |
module weight_buffer_18_16_1_64_bf_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_1_64_Wfc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:... | 6.6283 |
module weight_buffer_18_16_1_64_bi_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_1_64_Wic_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:... | 6.6283 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module weight_buffer_18_16_2_64_bc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_2_64_bo_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_2_64_Woc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:... | 6.6283 |
module weight_buffer_18_16_2_64_bf_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_2_64_Wfc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:... | 6.6283 |
module weight_buffer_18_16_2_64_bi_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0... | 6.6283 |
module weight_buffer_18_16_2_64_Wic_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:... | 6.6283 |
module counter_63_2 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 2) <= 63) begin
count <= count + 2;
end else begin
count <= 14'd0;
end
... | 7.360162 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module counter_63_3 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 3) <= 63) begin
count <= count + 3;
end else begin
count <= 14'd0;
end
... | 7.231427 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module STAGE1_tb;
integer i, j, f;
reg clk, rst_n, valid, stop;
reg [27:0] before_ff[0:31];
reg [13:0] data_in_r, data_in_i;
wire [14:0] data_out_i, data_out_r;
wire finish;
STAGE2 test (
.clk(clk),
.rst_n(rst_n),
.valid_i(valid),
.data_in_r(data_in_r),
.data_in_i(data_in_i... | 6.94027 |
module Stage3Ctrl (
CurrentIR,
IRStage4,
IRStage5,
byPassB1,
byPassA1,
byPassB2,
byPassA2,
OvfIn,
OvfFlag,
OvfOut,
OvfStage4,
OvfStage5,
TakeOvf4A,
TakeOvf5A,
TakeOvf4B,
TakeOvf5B
);
input [31:0] CurrentIR, IRStage4, IRStage5;
output [31:0] OvfOut;
... | 6.608673 |
module stage3_forward_unit (
MEM_WRITE,
ADDR1,
ADDR2,
OP1_MUX,
OP2_MUX,
STAGE_3_ADDR,
STAGE_3_REGWRITE_EN,
STAGE_4_ADDR,
STAGE_4_REGWRITE_EN,
STAGE_5_EXTRA_ADDR,
STAGE_5_EXTRA_REGWRITE_EN,
OP1_MUX_OUT,
OP2_MUX_OUT
);
input [4:0] ADDR1, ADDR2; //declare the inputs
... | 6.726185 |
module weight_buffer_18_9_1_64_2048_Wym_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [10:0] index
);
... | 6.6283 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module weight_buffer_18_9_1_64_2048_Wym_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [10:0] index
);
... | 6.6283 |
module counter_31_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 31) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.103667 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module weight_buffer_18_9_2_64_2048_Wym_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module weight_buffer_18_9_2_64_2048_Wym_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module counter_31_2 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 2) <= 31) begin
count <= count + 2;
end else begin
count <= 14'd0;
end
... | 7.08126 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module weight_buffer_18_9_3_64_2048_Wym_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module weight_buffer_18_9_3_64_2048_Wym_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module counter_31_3 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 3) <= 31) begin
count <= count + 3;
end else begin
count <= 14'd0;
end
... | 7.299146 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module STAGE1_tb;
integer i, j, f;
reg clk, rst_n, valid, stop;
reg [29:0] before_ff[0:31];
reg [14:0] data_in_r, data_in_i;
wire [15:0] data_out_i, data_out_r;
wire finish;
STAGE3 test (
.clk(clk),
.rst_n(rst_n),
.valid_i(valid),
.data_in_r(data_in_r),
.data_in_i(data_in_i... | 6.94027 |
module shift_register_unit_1_2 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else ... | 6.854847 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.876859 |
module counter_41_1_32 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 32;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.324518 |
module shift_register_unit_1_2 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else ... | 6.854847 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module counter_31_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 31) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.103667 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.876859 |
module counter_41_1_32 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 32;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.324518 |
module shift_register_unit_1_2 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else ... | 6.854847 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module counter_20_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 20) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.020974 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.876859 |
module counter_41_1_32 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 32;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.324518 |
module Stage4Control (
OpCode,
wrEn,
IR_Stage4,
IR_Stage5,
ByPassData
);
input [31:0] IR_Stage5, IR_Stage4;
input [4:0] OpCode;
output ByPassData;
output wrEn;
wire nA, nB;
not not1 (nA, OpCode[4]);
not not2 (nB, OpCode[3]);
//not not3(nC,OpCode[2]);
//not not4(nD,OpCode[1]);
//... | 7.838739 |
module stage4_forward_unit (
REG_READ_ADDR2_S3,
STAGE4_REG_ADDR,
STAGE_3_MEM_WRITE,
STAGE_4_MEM_READ,
MUX_OUT
);
input [4:0] REG_READ_ADDR2_S3, STAGE4_REG_ADDR; //declare the inputs
input [31:0] STAGE_3_DATA;
input STAGE_3_MEM_WRITE, STAGE_4_MEM_READ;
output reg MUX_OUT;
always @ (*) //... | 8.133404 |
module STAGE1_tb;
integer i, j, f;
reg clk, rst_n, valid, stop;
reg [31:0] before_ff[0:31];
reg [15:0] data_in_r, data_in_i;
wire [16:0] data_out_i, data_out_r;
wire finish;
STAGE4 test (
.clk(clk),
.rst_n(rst_n),
.valid_i(valid),
.data_in_r(data_in_r),
.data_in_i(data_in_i... | 6.94027 |
module STAGE5_tb;
integer i, j, f;
reg clk, rst_n, valid, stop;
reg [33:0] before_ff[0:31];
reg [16:0] data_in_r, data_in_i;
wire [16:0] data_out_i, data_out_r;
wire finish;
STAGE5 test (
.clk(clk),
.rst_n(rst_n),
.valid_i(valid),
.data_in_r(data_in_r),
.data_in_i(data_in_i... | 7.579124 |
module: stage7FullIntegration
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module stage7FullIntegrationTest;
// Inputs
reg CLK;
// Instantiate the Unit Under Test (UUT)
stage7FullI... | 6.956856 |
module stageen #(
parameter N_BITS = 8
) (
input clk,
input load,
input [N_BITS-1:0] data_i,
output [N_BITS-1:0] data_o,
input swap_i,
output swap_o,
input run_i,
input run_late_i,
output run_o,
input bit_i,
output bit_o,
input value_i,
output value_o
);
reg[N_... | 7.771743 |
module StageExecute (
clk,
reset,
dp,
dp_ce,
dp_down,
dp_cache,
dce,
da,
dd,
cd,
crda,
cack,
a,
operation_in,
ack_in,
operation,
ack
);
parameter A_WIDTH = 12;
parameter D_WIDTH = 8;
input clk;
input reset;
input [A_WIDTH - 1:0] dp;... | 7.036182 |
module StageID (
input clk,
input rst,
input stall,
input flush,
input TP_flush,
input [31:0] instIn,
input [31:0] PC,
input [31:0] rsFwd,
input [31:0] rtFwd,
output reg [31:0] nextPC,
output [1:0] fwdEN,
output reg [31:0] opA,
output reg [31:0] opB,
output [12:0... | 6.777696 |
module StageIDecode (
clk,
reset,
opcode_in,
ack,
operation,
ack_in
);
input clk;
input reset;
input [7:0] opcode_in;
output ack;
output reg [`OPCODE_MSB:0] operation;
input ack_in;
assign ack = ack_in;
always @(posedge clk) begin
if (reset) begin
operation <= 0;... | 6.979932 |
module StageIFetch (
clk,
reset,
pc,
ice,
ia,
id,
step_pc,
opcode,
ack_in
);
parameter A_WIDTH = 12;
parameter D_WIDTH = 8;
input clk;
input reset;
input [A_WIDTH - 1:0] pc;
output ice;
output [A_WIDTH - 1:0] ia;
input [D_WIDTH - 1:0] id;
output step_pc;
... | 6.811314 |
module StageMem (
input clk,
input rst,
input flush,
input stall,
//Input: Sequential
input [2:0] memCtrl,
input [2:0] wbSrc,
input [4:0] wbRegIn,
input [31:0] ALUout,
input [31:0] rtFwdMem,
//Input: Combinatorial
input [31:0] regHi,
input [31:0] regLo,
input [31:... | 7.663388 |
module StageModify (
clk,
reset,
a_in,
a,
operation_in,
ack_in,
operation,
ack
);
parameter D_WIDTH = 8;
input clk;
input reset;
input [D_WIDTH - 1:0] a_in;
output reg [D_WIDTH - 1:0] a;
input [`OPCODE_MSB:0] operation_in;
output ack;
output reg [`OPCODE_MSB:0] op... | 7.949615 |
module StageReg (
input clock,
input reset,
input [31:0] io_in_instruction,
input [31:0] io_in_pc,
input io_flush,
input io_valid,
output [31:0] io_data_instruction,
output [31:0] io_data_pc
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0]... | 7.496723 |
module IFIDRegister (
input reset_n,
input clk,
input stall,
input flush,
input [`opcode_bitno - 1 : 0] IF_inst_addr_MSB,
input [`WORD_SIZE - 1 : 0] IF_inst_addr_seq,
input [`WORD_SIZE - 1 : 0] IF_instruction,
input [`WORD_SIZE - 1 : 0] IF_num_inst,
//input jump_decision,
output ... | 6.787752 |
module IDEXRegister (
input reset_n,
input clk,
input stall,
input flush,
input [`WORD_SIZE - 1 : 0] ID_inst_addr_seq,
input [`WORD_SIZE - 1 : 0] ID_rs_value,
input [`WORD_SIZE - 1 : 0] ID_rt_value,
input [`WORD_SIZE - 1 : 0] ID_I_imm,
input [`target_loc_l : `target_loc_r] ID_J_targe... | 7.099567 |
module EXControlRegister (
input reset_n,
input clk,
input stall,
input flush,
input IN_ALUPathIntercept,
input [1:0] IN_ALUSrc,
input [`ALU_opcode_bitno - 1 : 0] IN_ALU_OP,
output reg OUT_ALUPathIntercept,
output reg [1:0] OUT_ALUSrc,
output reg [`ALU_opcode_bitno - 1 : 0] OUT_A... | 6.625355 |
module WBControlRegister (
input reset_n,
input clk,
input stall,
input flush,
input IN_MemtoReg,
input IN_RegWrite,
input IN_is_halted,
output reg OUT_MemtoReg,
output reg OUT_RegWrite,
output reg OUT_is_halted
);
always @(posedge clk) begin
if (~reset_n || flush) begin ... | 7.932201 |
module OutputRegister (
input reset_n,
input clk,
input stall,
input flush,
input IN_output_update,
input [`WORD_SIZE - 1 : 0] IN_num_inst,
input [`WORD_SIZE - 1 : 0] IN_output_value,
input [`WORD_SIZE - 1 : 0] IN_output_forwarded_value,
output reg OUT_output_update,
output reg [... | 7.011115 |
module PC (
input CLK,
input PCWrite,
input [31:0] in,
output reg [31:0] out
);
/*
* Implementation Notes
* --------------------
* INPUTS:
* CLK -> the clock signal
* PCWrite -> the control signal enables PC to write
* in -> ... | 7.578567 |
module IF_ID (
input CLK,
input Write,
input [31:0] PC_IN,
input [31:0] INS_IN,
output reg [31:0] PC_OUT,
output reg [31:0] INS_OUT
);
/* Implementation Notes
* --------------------
* INPUTS:
* CLK -> the clock signal
* Write -> ... | 7.719833 |
module ID_EX (
input CLK,
input Flush,
input MemtoReg,
input RegWrite,
input MemWrite,
input MemRead,
input [ 1:0] Branch,
input Jump,
input PCSrc,
input [ 3:0] ALUControl,
... | 8.23208 |
module StageReg_1 (
input clock,
input reset,
input [31:0] io_in_pc,
input [31:0] io_in_instruction,
input [31:0] io_in_sextImm,
input [31:0] io_in_readdata1,
input [31:0] io_in_readdata2,
input io_flush,
input io_valid,
output [31:0] io_data_... | 7.20915 |
module StageReg_3 (
input clock,
input reset,
input [31:0] io_in_ex_result,
input [31:0] io_in_mem_writedata,
input [31:0] io_in_instruction,
input [31:0] io_in_next_pc,
input io_in_taken,
input io_flush,
input io_valid,
output [31:0] i... | 7.51311 |
module StageReg_4 (
input clock,
input reset,
input [1:0] io_in_mem_ctrl_memop,
input io_in_wb_ctrl_toreg,
input io_in_wb_ctrl_regwrite,
input io_flush,
input io_valid,
output [1:0] io_data_mem_ctrl_memop,
output io_data_wb_ctrl_toreg,... | 6.679582 |
module StageReg_5 (
input clock,
input reset,
input [31:0] io_in_instruction,
input [31:0] io_in_readdata,
input [31:0] io_in_ex_result,
input io_flush,
input io_valid,
output [31:0] io_data_instruction,
output [31:0] io_data_readdata,
output [3... | 7.658383 |
module StageReg_6 (
input clock,
input reset,
input io_in_wb_ctrl_toreg,
input io_in_wb_ctrl_regwrite,
input io_flush,
input io_valid,
output io_data_wb_ctrl_toreg,
output io_data_wb_ctrl_regwrite
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // R... | 7.016389 |
module stages #(
parameter rotation_stage = 1,
data_width = 16,
cordic_steps = 16
) (
input clk,
input nreset,
input enable,
input signed [data_width-1:0] x_vec_in,
input signed [data_width-1:0] y_vec_in,
input [cordic_steps-1:0] micro_rotation_in,
input [1:0] quad_in,
outp... | 6.846107 |
module StageX (
clk,
reset,
operation_in,
ack_in,
operation,
ack,
);
input clk;
input reset;
input [`OPCODE_MSB:0] operation_in;
output reg ack;
output reg [`OPCODE_MSB:0] operation;
input ack_in;
assign ack = ack_in;
always @(posedge clk) begin
if (reset) begin
operation <= 0;
end... | 7.237141 |
module StageWriteback (
clk,
reset,
dp,
dce,
da,
dq,
cq,
cwre,
cbsy,
a_in,
operation_in,
ack_in,
operation,
ack
);
parameter A_WIDTH = 12;
parameter D_WIDTH = 8;
input clk;
input reset;
input [A_WIDTH - 1:0] dp;
output dce;
output [A_WIDTH ... | 8.006443 |
module stage_00 #(
parameter DATA_WIDTH = 16,
parameter MINI_BATCH = 8,
parameter ADDR_WIDTH = 3
) (
input clk,
input rst_n,
input [DATA_WIDTH-1:0] x_in,
input valid_in,
output [DATA_WIDTH-1:0] x_out,
output [ADDR_WIDTH-1:0] addr_out,
output valid_out
);
reg [ADDR_WIDTH-1:0] co... | 7.475236 |
module stage_01 #(
parameter DATA_WIDTH = 16,
parameter MINI_BATCH = 64,
parameter ADDR_WIDTH = 6
) (
input clk,
input rst_n,
input [DATA_WIDTH-1:0] max_in,
input [DATA_WIDTH-1:0] min_in,
input [DATA_WIDTH-1:0] partsum_in,
input valid_in,
input [ADDR_WIDTH-1:0] addr_in,
out... | 7.533847 |
module stage_02 (
rst_n,
clk,
stan_dev_in,
avg_in,
valid_in,
stan_dev_out,
avg_out,
valid_out
);
parameter DATA_WIDTH = 16;
input clk;
input rst_n;
input valid_in;
input [DATA_WIDTH-1:0] stan_dev_in;
input [DATA_WIDTH-1:0] avg_in;
output [DATA_WIDTH-1:0] stan_dev_out;
... | 6.749407 |
module stage_10 (
rst_n,
clk,
start_bn_tra_in,
addr_out,
start_bn_tra_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = 6;
input clk;
input rst_n;
input start_bn_tra_in;
output [ADDR_WIDTH-1:0] addr_out;
output start_bn_tra_out;
reg [ADDR_WIDTH-... | 7.322371 |
module stage_12 (
rst_n,
clk,
start_bn_tra_in,
x_in,
x_out,
start_bn_tra_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input clk;
input rst_n;
input [DATA_WIDTH-1:0] x_in;
input start_bn_tra_in;
output [DATA_WIDTH-1:0] ... | 7.237185 |
module stage_13 (
rst_n,
clk,
start_bn_tra_in,
x_in,
x_out,
start_bn_tra_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input clk;
input rst_n;
input [DATA_WIDTH-1:0] x_in;
input start_bn_tra_in;
output [DATA_WIDTH-1:0] ... | 7.079739 |
module stage_20 (
rst_n,
clk,
valid_in,
stan_dev_in,
avg_in,
stan_dev_out,
avg_out,
valid_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input clk;
input rst_n;
input valid_in;
input [DATA_WIDTH-1:0] stan_dev_in;
... | 7.230615 |
module stage_22 (
rst_n,
clk,
valid_in,
g_var_in,
g_avg_in,
partvar_out,
partavg_out,
g_var_out,
g_avg_out,
valid_out,
res_valid_in
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter TOTAL_BATCH = 128;
parameter BATCH_NUM = TOTAL_BATCH / MINI_BATCH;
... | 6.543289 |
module stage_23 #(
parameter DATA_WIDTH = 16,
parameter MINI_BATCH = 64,
parameter ADDR_WIDTH = $clog2(MINI_BATCH)
) (
input clk,
input rst_n,
input valid_in,
input [DATA_WIDTH-1:0] g_stan_dev_in,
input [DATA_WIDTH-1:0] g_avg_in,
output [DATA_WIDTH-1:0] g_stan_dev_out,
output [... | 7.2563 |
module stage_24 #(
parameter DATA_WIDTH = 16,
parameter MINI_BATCH = 64,
parameter ADDR_WIDTH = $clog2(MINI_BATCH)
) (
input clk,
input rst_n,
input valid_in,
input [DATA_WIDTH-1:0] a_in,
input [DATA_WIDTH-1:0] b_in,
output [DATA_WIDTH-1:0] a_out,
output [DATA_WIDTH-1:0] b_out,... | 6.939542 |
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