code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module counter_14_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 14) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 6.798894 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.034248 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module shift_register_unit_12 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else if (enable) begin
shift_registers_0 <= in;
shift_registers_1 <= shift_registers_0;
end
end
assign out = shift_registers_1;
endmodule
| 6.854847 |
module counter_8_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 8) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 6.902674 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.034248 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module weight_buffer_18_16_1_64_bc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
endmodule
| 6.6283 |
module weight_buffer_18_16_1_64_bo_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
endmodule
| 6.6283 |
module weight_buffer_18_16_1_64_Woc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
endmodule
| 6.6283 |
module weight_buffer_18_16_1_64_bf_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
endmodule
| 6.6283 |
module weight_buffer_18_16_1_64_Wfc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
endmodule
| 6.6283 |
module weight_buffer_18_16_1_64_bi_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
endmodule
| 6.6283 |
module weight_buffer_18_16_1_64_Wic_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
endmodule
| 6.6283 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.034248 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data;
end else begin
out <= ram[addr];
end
end
endmodule
| 8.023817 |
module weight_buffer_18_16_2_64_bc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_1_9,
output [17:0] q_1_10,
output [17:0] q_1_11,
output [17:0] q_1_12,
output [17:0] q_1_13,
output [17:0] q_1_14,
output [17:0] q_1_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
wire [287:0] packed_result_1;
reg [ 5:0] addrs_1;
reg [ 5:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 1;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(288'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_1_9 = packed_result_1[179:162];
assign q_1_10 = packed_result_1[197:180];
assign q_1_11 = packed_result_1[215:198];
assign q_1_12 = packed_result_1[233:216];
assign q_1_13 = packed_result_1[251:234];
assign q_1_14 = packed_result_1[269:252];
assign q_1_15 = packed_result_1[287:270];
endmodule
| 6.6283 |
module weight_buffer_18_16_2_64_bo_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_1_9,
output [17:0] q_1_10,
output [17:0] q_1_11,
output [17:0] q_1_12,
output [17:0] q_1_13,
output [17:0] q_1_14,
output [17:0] q_1_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
wire [287:0] packed_result_1;
reg [ 5:0] addrs_1;
reg [ 5:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 1;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(288'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_1_9 = packed_result_1[179:162];
assign q_1_10 = packed_result_1[197:180];
assign q_1_11 = packed_result_1[215:198];
assign q_1_12 = packed_result_1[233:216];
assign q_1_13 = packed_result_1[251:234];
assign q_1_14 = packed_result_1[269:252];
assign q_1_15 = packed_result_1[287:270];
endmodule
| 6.6283 |
module weight_buffer_18_16_2_64_Woc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_1_9,
output [17:0] q_1_10,
output [17:0] q_1_11,
output [17:0] q_1_12,
output [17:0] q_1_13,
output [17:0] q_1_14,
output [17:0] q_1_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
wire [287:0] packed_result_1;
reg [ 5:0] addrs_1;
reg [ 5:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 1;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(288'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_1_9 = packed_result_1[179:162];
assign q_1_10 = packed_result_1[197:180];
assign q_1_11 = packed_result_1[215:198];
assign q_1_12 = packed_result_1[233:216];
assign q_1_13 = packed_result_1[251:234];
assign q_1_14 = packed_result_1[269:252];
assign q_1_15 = packed_result_1[287:270];
endmodule
| 6.6283 |
module weight_buffer_18_16_2_64_bf_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_1_9,
output [17:0] q_1_10,
output [17:0] q_1_11,
output [17:0] q_1_12,
output [17:0] q_1_13,
output [17:0] q_1_14,
output [17:0] q_1_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
wire [287:0] packed_result_1;
reg [ 5:0] addrs_1;
reg [ 5:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 1;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(288'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_1_9 = packed_result_1[179:162];
assign q_1_10 = packed_result_1[197:180];
assign q_1_11 = packed_result_1[215:198];
assign q_1_12 = packed_result_1[233:216];
assign q_1_13 = packed_result_1[251:234];
assign q_1_14 = packed_result_1[269:252];
assign q_1_15 = packed_result_1[287:270];
endmodule
| 6.6283 |
module weight_buffer_18_16_2_64_Wfc_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_1_9,
output [17:0] q_1_10,
output [17:0] q_1_11,
output [17:0] q_1_12,
output [17:0] q_1_13,
output [17:0] q_1_14,
output [17:0] q_1_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
wire [287:0] packed_result_1;
reg [ 5:0] addrs_1;
reg [ 5:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 1;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(288'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_1_9 = packed_result_1[179:162];
assign q_1_10 = packed_result_1[197:180];
assign q_1_11 = packed_result_1[215:198];
assign q_1_12 = packed_result_1[233:216];
assign q_1_13 = packed_result_1[251:234];
assign q_1_14 = packed_result_1[269:252];
assign q_1_15 = packed_result_1[287:270];
endmodule
| 6.6283 |
module weight_buffer_18_16_2_64_bi_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_1_9,
output [17:0] q_1_10,
output [17:0] q_1_11,
output [17:0] q_1_12,
output [17:0] q_1_13,
output [17:0] q_1_14,
output [17:0] q_1_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
wire [287:0] packed_result_1;
reg [ 5:0] addrs_1;
reg [ 5:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 1;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(288'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_1_9 = packed_result_1[179:162];
assign q_1_10 = packed_result_1[197:180];
assign q_1_11 = packed_result_1[215:198];
assign q_1_12 = packed_result_1[233:216];
assign q_1_13 = packed_result_1[251:234];
assign q_1_14 = packed_result_1[269:252];
assign q_1_15 = packed_result_1[287:270];
endmodule
| 6.6283 |
module weight_buffer_18_16_2_64_Wic_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_0_9,
output [17:0] q_0_10,
output [17:0] q_0_11,
output [17:0] q_0_12,
output [17:0] q_0_13,
output [17:0] q_0_14,
output [17:0] q_0_15,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_1_9,
output [17:0] q_1_10,
output [17:0] q_1_11,
output [17:0] q_1_12,
output [17:0] q_1_13,
output [17:0] q_1_14,
output [17:0] q_1_15,
input [5:0] index
);
wire [287:0] packed_result_0;
reg [ 5:0] addrs_0;
reg [ 5:0] addrs_base_0;
wire [287:0] packed_result_1;
reg [ 5:0] addrs_1;
reg [ 5:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 1;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(288'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(288'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_0_9 = packed_result_0[179:162];
assign q_0_10 = packed_result_0[197:180];
assign q_0_11 = packed_result_0[215:198];
assign q_0_12 = packed_result_0[233:216];
assign q_0_13 = packed_result_0[251:234];
assign q_0_14 = packed_result_0[269:252];
assign q_0_15 = packed_result_0[287:270];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_1_9 = packed_result_1[179:162];
assign q_1_10 = packed_result_1[197:180];
assign q_1_11 = packed_result_1[215:198];
assign q_1_12 = packed_result_1[233:216];
assign q_1_13 = packed_result_1[251:234];
assign q_1_14 = packed_result_1[269:252];
assign q_1_15 = packed_result_1[287:270];
endmodule
| 6.6283 |
module counter_63_2 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 2) <= 63) begin
count <= count + 2;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.360162 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data;
end else begin
out <= ram[addr];
end
end
endmodule
| 8.023817 |
module counter_63_3 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 3) <= 63) begin
count <= count + 3;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.231427 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data;
end else begin
out <= ram[addr];
end
end
endmodule
| 8.023817 |
module STAGE1_tb;
integer i, j, f;
reg clk, rst_n, valid, stop;
reg [27:0] before_ff[0:31];
reg [13:0] data_in_r, data_in_i;
wire [14:0] data_out_i, data_out_r;
wire finish;
STAGE2 test (
.clk(clk),
.rst_n(rst_n),
.valid_i(valid),
.data_in_r(data_in_r),
.data_in_i(data_in_i),
.valid_o(finish),
.data_out_r(data_out_r),
.data_out_i(data_out_i)
);
initial begin
$readmemb("stage1_o.txt", before_ff);
f = $fopen("stage2_o.txt", "w");
end
initial begin
clk = 1'b1;
rst_n = 1'b1;
valid = 1'b0;
stop = 1'b0;
i = 0;
j = 0;
#2.5 rst_n = 1'b0;
#2.5 rst_n = 1'b1;
end
always begin
#(`CYCLE / 2) clk = ~clk;
end
initial begin
$dumpfile("stage2");
$dumpvars;
end
always @(negedge clk) begin
if (i < 32) begin
valid = 1;
data_in_r = before_ff[i][27:14];
data_in_i = before_ff[i][13:0];
i = i + 1;
end else if (i < 42) begin
data_in_r = 0;
i = i + 1;
end else begin
data_in_r = 0;
stop = 1;
end
end
always @(negedge clk) begin
if (finish) begin
$fwrite(f, "%b_%b\n", data_out_r, data_out_i);
$display("Output %0d: Real->%b / Img->%b", j, data_out_r, data_out_i);
j = j + 1;
end
end
always @(posedge stop) begin
$fclose(f);
$finish;
end
// always @(posedge clk)begin
// if(dataout !== out_temp && out_temp!==16'h0000) begin
// $display("ERROR at %d:output %h !=expect %h ",pattern_num-2, dataout, out_temp);
// $fdisplay(out_f,"ERROR at %d:output %h !=expect %h ",pattern_num-2, dataout, out_temp);
// err = err + 1 ;
// end
// pattern_num = pattern_num + 1;
// if(pattern_num === OUT_LENGTH) over = 1'b1;
// end
// initial begin
// @(posedge stop)
// if(over) begin
// $display("---------------------------------------------\n");
// if (err == 0) begin
// $display("All data have been generated successfully!\n");
// $display("You will get 80 score in this RTL!\n");
// $display("-------------------PASS-------------------\n");
// end
// else begin
// $display("There are %d errors!\n", err);
// $display("You will get %d score in this RTL!\n", 80-err);
// end
// $display("---------------------------------------------\n");
// end
// else begin
// $display("---------------------------------------------\n");
// $display("Error!!! There is no any data output ...!\n");
// $display("-------------------FAIL-------------------\n");
// $display("---------------------------------------------\n");
// end
// $finish;
// end
endmodule
| 6.94027 |
module Stage3Ctrl (
CurrentIR,
IRStage4,
IRStage5,
byPassB1,
byPassA1,
byPassB2,
byPassA2,
OvfIn,
OvfFlag,
OvfOut,
OvfStage4,
OvfStage5,
TakeOvf4A,
TakeOvf5A,
TakeOvf4B,
TakeOvf5B
);
input [31:0] CurrentIR, IRStage4, IRStage5;
output [31:0] OvfOut;
input OvfIn, OvfStage4, OvfStage5;
output byPassA1,byPassA2, byPassB1, byPassB2,OvfFlag,TakeOvf4A,TakeOvf5A,TakeOvf4B, TakeOvf5B;
wire [31:0] IR_Stage3;
wire branchIsn, branchIsn4, branchIsn5;
assign branchIsn = (!IR_Stage3[31] && !IR_Stage3[30] && !IR_Stage3[29] && IR_Stage3[28] && !IR_Stage3[27]) || (!IR_Stage3[31] && !IR_Stage3[30] && IR_Stage3[29] && IR_Stage3[28] && !IR_Stage3[27]);
assign branchIsn4 = (!IRStage4[31] && !IRStage4[30] && !IRStage4[29] && IRStage4[28] && !IRStage4[27]) || (!IRStage4[31] && !IRStage4[30] && IRStage4[29] && IRStage4[28] && !IRStage4[27]);
assign branchIsn5 = (!IRStage5[31] && !IRStage5[30] && !IRStage5[29] && IRStage5[28] && !IRStage5[27]) || (!IRStage5[31] && !IRStage5[30] && IRStage5[29] && IRStage5[28] && !IRStage5[27]);
assign IR_Stage3 = CurrentIR;
assign byPassA1 = (CurrentIR[21:17] == IRStage4[26:22]) && !(!IRStage4[31] && !IRStage4[30] && IRStage4[29] && IRStage4[28] && IRStage4[27]) && (IRStage4[26:22] != 0) && !branchIsn4;
assign byPassA2 = (CurrentIR[21:17] == IRStage5[26:22]) && !(!IRStage5[31] && !IRStage5[30] && IRStage5[29] && IRStage5[28] && IRStage5[27]) && (IRStage5[26:22] != 0) && !branchIsn5;
assign byPassB1 = (CurrentIR[16:12] == IRStage4[26:22] || (branchIsn && (CurrentIR[26:22] == IRStage4[26:22]))) && !(!CurrentIR[31] && !CurrentIR[30] && CurrentIR[29] && CurrentIR[28] && CurrentIR[27]) && (IRStage4[26:22] != 0) && !branchIsn4;
assign byPassB2 = (CurrentIR[16:12] == IRStage5[26:22] || (branchIsn && (CurrentIR[26:22] == IRStage5[26:22]))) && !(!CurrentIR[31] && !CurrentIR[30] && CurrentIR[29] && CurrentIR[28] && CurrentIR[27]) && (IRStage5[26:22] != 0) && !branchIsn5;
assign TakeOvf4A = OvfStage4 && (CurrentIR[21:17] == 5'b11110) && !(!IRStage4[30] && IRStage4[29] && IRStage4[28] && IRStage4[27]);
assign TakeOvf5A = OvfStage5 && (CurrentIR[21:17] == 5'b11110) && !(!IRStage4[30] && IRStage4[29] && IRStage4[28] && IRStage4[27]);
assign TakeOvf4B = OvfStage4 && (CurrentIR[16:12] == 5'b11110) && !(!IRStage4[30] && IRStage4[29] && IRStage4[28] && IRStage4[27]);
assign TakeOvf5B = OvfStage5 && (CurrentIR[16:12] == 5'b11110) && !(!IRStage4[30] && IRStage4[29] && IRStage4[28] && IRStage4[27]);
wire OvFlag1, OvFlag2;
wire [31:0] OvfIm1, OvfIm2, OvfIm3, OvfIm4;
assign OvFlag1 = (!IR_Stage3[31] && !IR_Stage3[30] && !IR_Stage3[29] && !IR_Stage3[28] && !IR_Stage3[27]) && ((!IR_Stage3[6] && !IR_Stage3[5] && !IR_Stage3[4] && !IR_Stage3[3] && !IR_Stage3[2]) || (!IR_Stage3[6] && !IR_Stage3[5] && !IR_Stage3[4] && !IR_Stage3[3] && IR_Stage3[2]) || (!IR_Stage3[6] && !IR_Stage3[5] && !IR_Stage3[4] && !IR_Stage3[3] && !IR_Stage3[2]) || (!IR_Stage3[6] && !IR_Stage3[5] && IR_Stage3[4] && IR_Stage3[3] && !IR_Stage3[2]) || (!IR_Stage3[6] && !IR_Stage3[5] && IR_Stage3[4] && IR_Stage3[3] && IR_Stage3[2]));
assign OvFlag2 = (!IR_Stage3[31] && !IR_Stage3[30] && IR_Stage3[29] && !IR_Stage3[28] && IR_Stage3[27]);
assign OvfFlag = OvfIn && (OvFlag1 || OvFlag2);
assign OvfIm1 = (!IR_Stage3[6] && !IR_Stage3[5] && !IR_Stage3[4] && !IR_Stage3[3] && !IR_Stage3[2]) ? 1 : 0;
assign OvfIm2 = (!IR_Stage3[31] && !IR_Stage3[30] && IR_Stage3[29] && !IR_Stage3[28] && IR_Stage3[27]) ? 2 : OvfIm1;
assign OvfIm3 = (!IR_Stage3[6] && !IR_Stage3[5] && !IR_Stage3[4] && !IR_Stage3[3] && IR_Stage3[2]) ? 3 : OvfIm2;
assign OvfIm4 = (!IR_Stage3[6] && !IR_Stage3[5] && IR_Stage3[4] && IR_Stage3[3] && !IR_Stage3[2]) ? 4 :OvfIm3;
assign OvfOut = (!IR_Stage3[6] && !IR_Stage3[5] && IR_Stage3[4] && IR_Stage3[3] && IR_Stage3[2]) ? 5 : OvfIm4;
endmodule
| 6.608673 |
module stage3_forward_unit (
MEM_WRITE,
ADDR1,
ADDR2,
OP1_MUX,
OP2_MUX,
STAGE_3_ADDR,
STAGE_3_REGWRITE_EN,
STAGE_4_ADDR,
STAGE_4_REGWRITE_EN,
STAGE_5_EXTRA_ADDR,
STAGE_5_EXTRA_REGWRITE_EN,
OP1_MUX_OUT,
OP2_MUX_OUT
);
input [4:0] ADDR1, ADDR2; //declare the inputs
input OP1_MUX, OP2_MUX;
input [4:0] STAGE_3_ADDR, STAGE_4_ADDR, STAGE_5_EXTRA_ADDR;
input STAGE_3_REGWRITE_EN, STAGE_4_REGWRITE_EN, STAGE_5_EXTRA_REGWRITE_EN;
input MEM_WRITE; // data memory write enabke signal
output reg [1:0] OP1_MUX_OUT, OP2_MUX_OUT; // declare the outputs as registers
always @ (*) // always block to simulate the procedure
begin
// The logic flow for the operand 1
if (STAGE_3_REGWRITE_EN == 1'b1 && STAGE_3_ADDR == ADDR1) begin
// fowarding the data from stage 3
OP1_MUX_OUT = 2'b01;
end else if (STAGE_4_REGWRITE_EN == 1'b1 && STAGE_4_ADDR == ADDR1) begin
// fowarding the data from stage 4
OP1_MUX_OUT = 2'b10;
end else if (STAGE_5_EXTRA_REGWRITE_EN == 1'b1 && STAGE_5_EXTRA_ADDR == ADDR1) begin
// fowarding the data from stage 5 extra stage for forwarding
OP1_MUX_OUT = 2'b11;
end else begin
// no fowarding
OP1_MUX_OUT = 2'b00;
end
// The logic flow for the operand 1
if (STAGE_3_REGWRITE_EN == 1'b1 && STAGE_3_ADDR == ADDR2) begin
// fowarding the data from stage 3
OP2_MUX_OUT = 2'b01;
end else if (STAGE_4_REGWRITE_EN == 1'b1 && STAGE_4_ADDR == ADDR2) begin
// fowarding the data from stage 4
OP2_MUX_OUT = 2'b10;
end else if (STAGE_5_EXTRA_REGWRITE_EN == 1'b1 && STAGE_5_EXTRA_ADDR == ADDR2) begin
// fowarding the data from stage 5 extra stage for forwarding
OP2_MUX_OUT = 2'b11;
end else begin
// no fowarding
OP2_MUX_OUT = 2'b00;
end
end
endmodule
| 6.726185 |
module weight_buffer_18_9_1_64_2048_Wym_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [10:0] index
);
wire [161:0] packed_result_0;
reg [ 10:0] addrs_0;
reg [ 10:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
endmodule
| 6.6283 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data;
end else begin
out <= ram[addr];
end
end
endmodule
| 8.023817 |
module weight_buffer_18_9_1_64_2048_Wym_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [10:0] index
);
wire [161:0] packed_result_0;
reg [ 10:0] addrs_0;
reg [ 10:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
endmodule
| 6.6283 |
module counter_31_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 31) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.103667 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.034248 |
module weight_buffer_18_9_2_64_2048_Wym_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
input [10:0] index
);
wire [161:0] packed_result_0;
reg [ 10:0] addrs_0;
reg [ 10:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 10:0] addrs_1;
reg [ 10:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 64;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162; defparam ram_inst_1.ADDR_WIDTH = 12;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
endmodule
| 6.6283 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data;
end else begin
out <= ram[addr];
end
end
endmodule
| 8.023817 |
module weight_buffer_18_9_2_64_2048_Wym_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
input [10:0] index
);
wire [161:0] packed_result_0;
reg [ 10:0] addrs_0;
reg [ 10:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 10:0] addrs_1;
reg [ 10:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 64;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162; defparam ram_inst_1.ADDR_WIDTH = 12;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
endmodule
| 6.6283 |
module counter_31_2 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 2) <= 31) begin
count <= count + 2;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.08126 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.034248 |
module weight_buffer_18_9_3_64_2048_Wym_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_2_0,
output [17:0] q_2_1,
output [17:0] q_2_2,
output [17:0] q_2_3,
output [17:0] q_2_4,
output [17:0] q_2_5,
output [17:0] q_2_6,
output [17:0] q_2_7,
output [17:0] q_2_8,
input [10:0] index
);
wire [161:0] packed_result_0;
reg [ 10:0] addrs_0;
reg [ 10:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 10:0] addrs_1;
reg [ 10:0] addrs_base_1;
wire [161:0] packed_result_2;
reg [ 10:0] addrs_2;
reg [ 10:0] addrs_base_2;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 64;
addrs_base_2 <= 128;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
addrs_2 <= index + addrs_base_2;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162;
defparam ram_inst_0.ADDR_WIDTH = 11;
defparam ram_inst_1.DATA_WIDTH = 162;
defparam ram_inst_1.ADDR_WIDTH = 11;
defparam ram_inst_2.DATA_WIDTH = 162;
defparam ram_inst_2.ADDR_WIDTH = 11;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
single_port_ram ram_inst_2 (
.we (rom_we),
.addr(addrs_2),
.data(162'd0),
.out (packed_result_2),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_2_0 = packed_result_2[17:0];
assign q_2_1 = packed_result_2[35:18];
assign q_2_2 = packed_result_2[53:36];
assign q_2_3 = packed_result_2[71:54];
assign q_2_4 = packed_result_2[89:72];
assign q_2_5 = packed_result_2[107:90];
assign q_2_6 = packed_result_2[125:108];
assign q_2_7 = packed_result_2[143:126];
assign q_2_8 = packed_result_2[161:144];
endmodule
| 6.6283 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data;
end else begin
out <= ram[addr];
end
end
endmodule
| 8.023817 |
module weight_buffer_18_9_3_64_2048_Wym_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_2_0,
output [17:0] q_2_1,
output [17:0] q_2_2,
output [17:0] q_2_3,
output [17:0] q_2_4,
output [17:0] q_2_5,
output [17:0] q_2_6,
output [17:0] q_2_7,
output [17:0] q_2_8,
input [10:0] index
);
wire [161:0] packed_result_0;
reg [ 10:0] addrs_0;
reg [ 10:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 10:0] addrs_1;
reg [ 10:0] addrs_base_1;
wire [161:0] packed_result_2;
reg [ 10:0] addrs_2;
reg [ 10:0] addrs_base_2;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 64;
addrs_base_2 <= 128;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
addrs_2 <= index + addrs_base_2;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162;
defparam ram_inst_0.ADDR_WIDTH = 11;
defparam ram_inst_1.DATA_WIDTH = 162;
defparam ram_inst_1.ADDR_WIDTH = 11;
defparam ram_inst_2.DATA_WIDTH = 162;
defparam ram_inst_2.ADDR_WIDTH = 11;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
single_port_ram ram_inst_2 (
.we (rom_we),
.addr(addrs_2),
.data(162'd0),
.out (packed_result_2),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_2_0 = packed_result_2[17:0];
assign q_2_1 = packed_result_2[35:18];
assign q_2_2 = packed_result_2[53:36];
assign q_2_3 = packed_result_2[71:54];
assign q_2_4 = packed_result_2[89:72];
assign q_2_5 = packed_result_2[107:90];
assign q_2_6 = packed_result_2[125:108];
assign q_2_7 = packed_result_2[143:126];
assign q_2_8 = packed_result_2[161:144];
endmodule
| 6.6283 |
module counter_31_3 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 3) <= 31) begin
count <= count + 3;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.299146 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.034248 |
module STAGE1_tb;
integer i, j, f;
reg clk, rst_n, valid, stop;
reg [29:0] before_ff[0:31];
reg [14:0] data_in_r, data_in_i;
wire [15:0] data_out_i, data_out_r;
wire finish;
STAGE3 test (
.clk(clk),
.rst_n(rst_n),
.valid_i(valid),
.data_in_r(data_in_r),
.data_in_i(data_in_i),
.valid_o(finish),
.data_out_r(data_out_r),
.data_out_i(data_out_i)
);
initial begin
$readmemb("stage2_o.txt", before_ff);
f = $fopen("stage3_o.txt", "w");
end
initial begin
clk = 1'b1;
rst_n = 1'b1;
valid = 1'b0;
stop = 1'b0;
i = 0;
j = 0;
#2.5 rst_n = 1'b0;
#2.5 rst_n = 1'b1;
end
always begin
#(`CYCLE / 2) clk = ~clk;
end
initial begin
$dumpfile("stage3");
$dumpvars;
end
always @(negedge clk) begin
if (i < 32) begin
valid = 1;
data_in_r = before_ff[i][29:15];
data_in_i = before_ff[i][14:0];
i = i + 1;
end else if (i < 42) begin
data_in_r = 0;
i = i + 1;
end else begin
data_in_r = 0;
stop = 1;
end
end
always @(negedge clk) begin
if (finish) begin
$fwrite(f, "%b_%b\n", data_out_r, data_out_i);
$display("Output %0d: Real->%b / Img->%b", j, data_out_r, data_out_i);
j = j + 1;
end
end
always @(posedge stop) begin
$fclose(f);
$finish;
end
// always @(posedge clk)begin
// if(dataout !== out_temp && out_temp!==16'h0000) begin
// $display("ERROR at %d:output %h !=expect %h ",pattern_num-2, dataout, out_temp);
// $fdisplay(out_f,"ERROR at %d:output %h !=expect %h ",pattern_num-2, dataout, out_temp);
// err = err + 1 ;
// end
// pattern_num = pattern_num + 1;
// if(pattern_num === OUT_LENGTH) over = 1'b1;
// end
// initial begin
// @(posedge stop)
// if(over) begin
// $display("---------------------------------------------\n");
// if (err == 0) begin
// $display("All data have been generated successfully!\n");
// $display("You will get 80 score in this RTL!\n");
// $display("-------------------PASS-------------------\n");
// end
// else begin
// $display("There are %d errors!\n", err);
// $display("You will get %d score in this RTL!\n", 80-err);
// end
// $display("---------------------------------------------\n");
// end
// else begin
// $display("---------------------------------------------\n");
// $display("Error!!! There is no any data output ...!\n");
// $display("-------------------FAIL-------------------\n");
// $display("---------------------------------------------\n");
// end
// $finish;
// end
endmodule
| 6.94027 |
module shift_register_unit_1_2 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else if (enable) begin
shift_registers_0 <= in;
shift_registers_1 <= shift_registers_0;
end
end
assign out = shift_registers_1;
endmodule
| 6.854847 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.034248 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 6.876859 |
module counter_41_1_32 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 32;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.324518 |
module shift_register_unit_1_2 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else if (enable) begin
shift_registers_0 <= in;
shift_registers_1 <= shift_registers_0;
end
end
assign out = shift_registers_1;
endmodule
| 6.854847 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module counter_31_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 31) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.103667 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 6.876859 |
module counter_41_1_32 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 32;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.324518 |
module shift_register_unit_1_2 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else if (enable) begin
shift_registers_0 <= in;
shift_registers_1 <= shift_registers_0;
end
end
assign out = shift_registers_1;
endmodule
| 6.854847 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module counter_20_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 20) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.020974 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 6.876859 |
module counter_41_1_32 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 32;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.324518 |
module Stage4Control (
OpCode,
wrEn,
IR_Stage4,
IR_Stage5,
ByPassData
);
input [31:0] IR_Stage5, IR_Stage4;
input [4:0] OpCode;
output ByPassData;
output wrEn;
wire nA, nB;
not not1 (nA, OpCode[4]);
not not2 (nB, OpCode[3]);
//not not3(nC,OpCode[2]);
//not not4(nD,OpCode[1]);
//ot not5(nE,OpCode[0]);
assign ByPassData = (IR_Stage5[26:22] == IR_Stage4[26:22]);
assign wrEn = !IR_Stage4[31] && !IR_Stage4[30] && IR_Stage4[29] && IR_Stage4[28] && IR_Stage4[27];
endmodule
| 7.838739 |
module stage4_forward_unit (
REG_READ_ADDR2_S3,
STAGE4_REG_ADDR,
STAGE_3_MEM_WRITE,
STAGE_4_MEM_READ,
MUX_OUT
);
input [4:0] REG_READ_ADDR2_S3, STAGE4_REG_ADDR; //declare the inputs
input [31:0] STAGE_3_DATA;
input STAGE_3_MEM_WRITE, STAGE_4_MEM_READ;
output reg MUX_OUT;
always @ (*) // always block to simulate the procedure
begin
// The logic flow for the mux
if (STAGE_4_MEM_READ == 1'b1 && STAGE_3_MEM_WRITE == 1'b1) begin
// if stage 3 and stage 4 use same address foward the stage 4 memory read
if (REG_READ_ADDR2_S3 == STAGE4_REG_ADDR) MUX_OUT = 1'b1;
//else no change
else
MUX_OUT = 1'b0;
end else MUX_OUT = 1'b0;
end
endmodule
| 8.133404 |
module STAGE1_tb;
integer i, j, f;
reg clk, rst_n, valid, stop;
reg [31:0] before_ff[0:31];
reg [15:0] data_in_r, data_in_i;
wire [16:0] data_out_i, data_out_r;
wire finish;
STAGE4 test (
.clk(clk),
.rst_n(rst_n),
.valid_i(valid),
.data_in_r(data_in_r),
.data_in_i(data_in_i),
.valid_o(finish),
.data_out_r(data_out_r),
.data_out_i(data_out_i)
);
initial begin
$readmemb("stage3_o.txt", before_ff);
f = $fopen("stage4_o.txt", "w");
end
initial begin
clk = 1'b1;
rst_n = 1'b1;
valid = 1'b0;
stop = 1'b0;
i = 0;
j = 0;
#2.5 rst_n = 1'b0;
#2.5 rst_n = 1'b1;
end
always begin
#(`CYCLE / 2) clk = ~clk;
end
initial begin
$dumpfile("stage4");
$dumpvars;
end
always @(negedge clk) begin
if (i < 32) begin
valid = 1;
data_in_r = before_ff[i][31:16];
data_in_i = before_ff[i][15:0];
i = i + 1;
end else if (i < 42) begin
data_in_r = 0;
i = i + 1;
end else begin
data_in_r = 0;
stop = 1;
end
end
always @(negedge clk) begin
if (finish) begin
$fwrite(f, "%b_%b\n", data_out_r, data_out_i);
$display("Output %0d: Real->%b / Img->%b", j, data_out_r, data_out_i);
j = j + 1;
end
end
always @(posedge stop) begin
$fclose(f);
$finish;
end
// always @(posedge clk)begin
// if(dataout !== out_temp && out_temp!==16'h0000) begin
// $display("ERROR at %d:output %h !=expect %h ",pattern_num-2, dataout, out_temp);
// $fdisplay(out_f,"ERROR at %d:output %h !=expect %h ",pattern_num-2, dataout, out_temp);
// err = err + 1 ;
// end
// pattern_num = pattern_num + 1;
// if(pattern_num === OUT_LENGTH) over = 1'b1;
// end
// initial begin
// @(posedge stop)
// if(over) begin
// $display("---------------------------------------------\n");
// if (err == 0) begin
// $display("All data have been generated successfully!\n");
// $display("You will get 80 score in this RTL!\n");
// $display("-------------------PASS-------------------\n");
// end
// else begin
// $display("There are %d errors!\n", err);
// $display("You will get %d score in this RTL!\n", 80-err);
// end
// $display("---------------------------------------------\n");
// end
// else begin
// $display("---------------------------------------------\n");
// $display("Error!!! There is no any data output ...!\n");
// $display("-------------------FAIL-------------------\n");
// $display("---------------------------------------------\n");
// end
// $finish;
// end
endmodule
| 6.94027 |
module STAGE5_tb;
integer i, j, f;
reg clk, rst_n, valid, stop;
reg [33:0] before_ff[0:31];
reg [16:0] data_in_r, data_in_i;
wire [16:0] data_out_i, data_out_r;
wire finish;
STAGE5 test (
.clk(clk),
.rst_n(rst_n),
.valid_i(valid),
.data_in_r(data_in_r),
.data_in_i(data_in_i),
.valid_o(finish),
.data_out_r(data_out_r),
.data_out_i(data_out_i)
);
initial begin
$readmemb("stage4_o.txt", before_ff);
f = $fopen("stage5_o.txt", "w");
end
initial begin
clk = 1'b1;
rst_n = 1'b1;
valid = 1'b0;
stop = 1'b0;
i = 0;
j = 0;
#2.5 rst_n = 1'b0;
#2.5 rst_n = 1'b1;
end
always begin
#(`CYCLE / 2) clk = ~clk;
end
initial begin
$dumpfile("stage5");
$dumpvars;
end
always @(negedge clk) begin
if (i < 32) begin
valid = 1;
data_in_r = before_ff[i][33:17];
data_in_i = before_ff[i][16:0];
i = i + 1;
end else if (i < 42) begin
data_in_r = 0;
i = i + 1;
end else begin
data_in_r = 0;
stop = 1;
end
end
always @(negedge clk) begin
if (finish) begin
$fwrite(f, "%b_%b\n", data_out_r, data_out_i);
$display("Output %0d: Real->%b / Img->%b", j, data_out_r, data_out_i);
j = j + 1;
end
end
always @(posedge stop) begin
$fclose(f);
$finish;
end
// always @(posedge clk)begin
// if(dataout !== out_temp && out_temp!==16'h0000) begin
// $display("ERROR at %d:output %h !=expect %h ",pattern_num-2, dataout, out_temp);
// $fdisplay(out_f,"ERROR at %d:output %h !=expect %h ",pattern_num-2, dataout, out_temp);
// err = err + 1 ;
// end
// pattern_num = pattern_num + 1;
// if(pattern_num === OUT_LENGTH) over = 1'b1;
// end
// initial begin
// @(posedge stop)
// if(over) begin
// $display("---------------------------------------------\n");
// if (err == 0) begin
// $display("All data have been generated successfully!\n");
// $display("You will get 80 score in this RTL!\n");
// $display("-------------------PASS-------------------\n");
// end
// else begin
// $display("There are %d errors!\n", err);
// $display("You will get %d score in this RTL!\n", 80-err);
// end
// $display("---------------------------------------------\n");
// end
// else begin
// $display("---------------------------------------------\n");
// $display("Error!!! There is no any data output ...!\n");
// $display("-------------------FAIL-------------------\n");
// $display("---------------------------------------------\n");
// end
// $finish;
// end
endmodule
| 7.579124 |
module: stage7FullIntegration
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module stage7FullIntegrationTest;
// Inputs
reg CLK;
// Instantiate the Unit Under Test (UUT)
stage7FullIntegration uut (
.CLK(CLK)
);
initial begin
// Initialize Inputs
CLK = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 10;
initial begin // Clock process for CLK
CLK = 0;
#OFFSET;
forever begin
#(PERIOD-(PERIOD*DUTY_CYCLE)) CLK = ~CLK;
#(PERIOD*DUTY_CYCLE);
end
end
endmodule
| 6.956856 |
module stageen #(
parameter N_BITS = 8
) (
input clk,
input load,
input [N_BITS-1:0] data_i,
output [N_BITS-1:0] data_o,
input swap_i,
output swap_o,
input run_i,
input run_late_i,
output run_o,
input bit_i,
output bit_o,
input value_i,
output value_o
);
reg[N_BITS-1:0] r_data;
wire w_large_bit;
wire w_small_bit;
wire w_swap_o;
wire w_run_o;
always @(posedge clk) begin
if (load) begin
r_data <= data_i;
end else if (run_i | run_late_i) begin
r_data <= {r_data[N_BITS-2:0], value_i};
end
end
bitsplit split_module (
.clk(clk),
.bit1_i(bit_i),
.bit2_i(r_data[N_BITS-1]),
.largebit_o(w_large_bit),
.smallbit_o(w_small_bit),
.swap_i(swap_i),
.swap_o(w_swap_o),
.run_i(run_i),
.run_o(w_run_o)
);
assign data_o = r_data;
assign swap_o = w_swap_o;
assign run_o = w_run_o;
assign bit_o = w_large_bit;
assign value_o = w_small_bit;
endmodule
| 7.771743 |
module StageExecute (
clk,
reset,
dp,
dp_ce,
dp_down,
dp_cache,
dce,
da,
dd,
cd,
crda,
cack,
a,
operation_in,
ack_in,
operation,
ack
);
parameter A_WIDTH = 12;
parameter D_WIDTH = 8;
input clk;
input reset;
input [A_WIDTH - 1:0] dp;
output dp_ce;
output dp_down;
output dce;
output [A_WIDTH - 1:0] da;
input [D_WIDTH - 1:0] dd;
input [7:0] cd;
input crda;
output cack;
output reg [D_WIDTH - 1:0] a;
input [`OPCODE_MSB:0] operation_in;
output ack;
output reg [`OPCODE_MSB:0] operation;
input ack_in;
reg prefetched;
/*
* Data pointer manipulation
*/
assign dp_ce = ack_in && (operation_in[`OP_INCDP] || operation_in[`OP_DECDP]);
assign dp_down = ack_in && operation_in[`OP_DECDP];
output reg [A_WIDTH - 1:0] dp_cache;
/*
* RAW hazard handling: register forwarding
*/
wire dirty_datum;
assign dirty_datum = operation[`OP_INC] || operation[`OP_DEC] || operation[`OP_IN] ||
/* These do not make change the datum. It is an optimization: *
* memfetch costs 2 cycles, and regforward only one. */
operation[`OP_LOOPBEGIN] || operation[`OP_LOOPEND];
wire do_mem_fetch, do_reg_forward;
assign do_mem_fetch = need_fetch_mem && !dirty_datum;
assign do_reg_forward = need_fetch_mem && dirty_datum;
/*
* Reading from DRAM
*/
wire need_fetch_mem;
assign need_fetch_mem = (operation_in[`OP_INC] || operation_in[`OP_DEC] ||
operation_in[`OP_OUT] || operation_in[`OP_LOOPBEGIN] ||
operation_in[`OP_LOOPEND]);
assign da = dp;
assign dce = do_mem_fetch;
wire [D_WIDTH - 1:0] data_input;
assign data_input = do_reg_forward ? a : dd;
assign datum_ready = (do_mem_fetch && prefetched) || do_reg_forward;
/*
* Reading from EXT
*/
wire need_fetch_ext;
assign need_fetch_ext = operation_in[`OP_IN];
assign cack = crda && need_fetch_ext;
/*
* Wait states
*/
wire ext_wait;
assign ext_wait = (need_fetch_ext && !crda) || (do_mem_fetch && !prefetched);
/*
* ACKing the previous stage
*/
assign ack = ack_in && !ext_wait;
always @(posedge clk) begin
if (reset) prefetched <= 0;
else prefetched <= do_mem_fetch;
end
always @(posedge clk) begin
if (reset) begin
operation <= 0;
dp_cache <= 0;
a <= 0;
end else begin
dp_cache <= dp;
if (ack_in && ext_wait) begin
operation <= 0; /* Bubble */
a <= 0;
end else if (ack_in) begin
operation <= operation_in;
if (datum_ready)
if (operation_in[`OP_INC]) a <= data_input + 1;
else if (operation_in[`OP_DEC]) a <= data_input - 1;
else a <= data_input;
else if (need_fetch_ext && crda) a <= cd;
else a <= 0;
end
end
end
endmodule
| 7.036182 |
module StageID (
input clk,
input rst,
input stall,
input flush,
input TP_flush,
input [31:0] instIn,
input [31:0] PC,
input [31:0] rsFwd,
input [31:0] rtFwd,
output reg [31:0] nextPC,
output [1:0] fwdEN,
output reg [31:0] opA,
output reg [31:0] opB,
output [12:0] exCtrl,
output [7:0] memCtrl,
output reg [4:0] wbReg,
output [2:0] wbCond,
output [2:0] wbSrc,
output [2:0] branchCond,
output RIexception,
output syscall,
output breakpoint,
output [2:0] cp0Op,
output [1:0] cacheOp,
input [3:0] copAccess,
output cpU,
output reg [31:0] instOut,
output reg [31:0] PCOut,
output reg bd,
output bd_IF,
output reg instValid
);
//exCtrl: ALUOp(4), mulOp(4), ALUValid(1), mulWait(1), trap(3)
//memCtrl: memOp(4), read(1), write(1), addrMask(2)
wire [1:0] ALUSrcA, ALUSrcB, branch, wbDest;
InstDecoder decoder (
.inst(instOut),
.forward(fwdEN),
.ALUSrcA(ALUSrcA),
.ALUSrcB(ALUSrcB),
.branch(branch),
.branchCond(branchCond),
.ALUOp(exCtrl[12:9]),
.mulOp(exCtrl[8:5]),
.ALUValid(exCtrl[4]),
.mulWait(exCtrl[3]),
.trap(exCtrl[2:0]),
.wbDest(wbDest),
.wbSrc(wbSrc),
.wbCond(wbCond),
.RIexception(RIexception),
.cp0Op(cp0Op),
.memCtrl(memCtrl[7:4]),
.syscall(syscall),
.breakpoint(breakpoint)
);
wire [31:0] imm_signExt = {{16{instOut[15]}}, instOut[15:0]};
wire [31:0] PCincr = PC + 32'd4;
always @(posedge clk) begin
if (rst | flush) begin
instOut <= 32'h0;
instValid <= 1'b0;
end else if (~stall) begin
instOut <= instIn;
instValid <= 1'b1;
end
if (~stall) begin
if (~(bd_IF | TP_flush)) //If in delay slot OR translate predict miss then keep PC unchanged.
PCOut <= PC;
bd <= bd_IF;
end
end
assign bd_IF = |branch;
reg memW, memR;
reg [1:0] addrMask;
assign cpU = (instOut[31:28] == 3'b0100) & (
(~copAccess[0] & (instOut[27:26] == 2'b00)) |
(~copAccess[1] & (instOut[27:26] == 2'b01)) |
(~copAccess[2] & (instOut[27:26] == 2'b10)) |
(~copAccess[3] & (instOut[27:26] == 2'b11))
);
always @* begin
case (ALUSrcA)
2'b00: opA <= 32'h0;
2'b01: opA <= rsFwd;
2'b10: opA <= {27'h0, instOut[10:6]};
2'b11: opA <= PCincr;
endcase
case (ALUSrcB)
2'b00: opB <= 32'h0;
2'b01: opB <= rtFwd;
2'b10: opB <= imm_signExt;
2'b11: opB <= {16'h0, instOut[15:0]};
endcase
case (branch)
2'b00: nextPC <= PCincr;
2'b01: nextPC <= PC + {imm_signExt[29:0], 2'b00};
2'b10: nextPC <= rsFwd;
2'b11: nextPC <= {PC[31:28], instOut[25:0], 2'b00};
endcase
case (wbDest)
2'b00: wbReg <= 5'h0;
2'b01: wbReg <= 5'h1f;
2'b10: wbReg <= instOut[20:16];
2'b11: wbReg <= instOut[15:11];
endcase
case (memCtrl[7:4])
4'b1000, 4'b1001, 4'b1010, 4'b1011, 4'b1110: memW <= 1'b1;
default: memW <= 1'b0;
endcase
case (memCtrl[7:4])
4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110: memR <= 1'b1;
default: memR <= 1'b0;
endcase
case (memCtrl[7:4])
4'b0001, 4'b0101, 4'b1001: addrMask <= 2'b01;
4'b0011, 4'b1011: addrMask <= 2'b11;
default: addrMask <= 2'b00;
endcase
end
assign memCtrl[3:0] = {memR, memW, addrMask};
assign cacheOp[1] = (instOut[31:26] == 6'b101111) & (instOut[17:16] == 2'b01);
assign cacheOp[0] = (instOut[31:26] == 6'b101111) & (instOut[17:16] == 2'b00);
endmodule
| 6.777696 |
module StageIDecode (
clk,
reset,
opcode_in,
ack,
operation,
ack_in
);
input clk;
input reset;
input [7:0] opcode_in;
output ack;
output reg [`OPCODE_MSB:0] operation;
input ack_in;
assign ack = ack_in;
always @(posedge clk) begin
if (reset) begin
operation <= 0;
end else begin
if (ack_in) begin
case (opcode_in)
8'h3E: operation <= 8'b0000_0001;
8'h3C: operation <= 8'b0000_0010;
8'h2B: operation <= 8'b0000_0100;
8'h2D: operation <= 8'b0000_1000;
8'h2E: operation <= 8'b0001_0000;
8'h2C: operation <= 8'b0010_0000;
8'h5B: operation <= 8'b0100_0000;
8'h5D: operation <= 8'b1000_0000;
default: operation <= 8'b0000_0000;
endcase
end
end
end
endmodule
| 6.979932 |
module StageIFetch (
clk,
reset,
pc,
ice,
ia,
id,
step_pc,
opcode,
ack_in
);
parameter A_WIDTH = 12;
parameter D_WIDTH = 8;
input clk;
input reset;
input [A_WIDTH - 1:0] pc;
output ice;
output [A_WIDTH - 1:0] ia;
input [D_WIDTH - 1:0] id;
output step_pc;
output reg [D_WIDTH - 1:0] opcode;
input ack_in;
assign ia = pc;
assign ice = !reset && ack_in;
/*
* step_pc=1 means that at the _next_ cycle PC will be
* increased. Thus, if we will do a successful fetch
* _now_, we should increase it _then_.
*/
assign step_pc = !reset && ack_in;
reg prefetched;
always @(posedge clk) begin
if (reset) begin
prefetched <= 0;
opcode <= 0;
end else begin
prefetched <= 1'b1;
if (ack_in && prefetched) opcode <= id;
end
end
endmodule
| 6.811314 |
module StageMem (
input clk,
input rst,
input flush,
input stall,
//Input: Sequential
input [2:0] memCtrl,
input [2:0] wbSrc,
input [4:0] wbRegIn,
input [31:0] ALUout,
input [31:0] rtFwdMem,
//Input: Combinatorial
input [31:0] regHi,
input [31:0] regLo,
input [31:0] cp0RegOut,
input [31:0] memDataIn,
output reg [ 4:0] wbRegOut,
output reg [31:0] wbData,
input [31:0] PCIn,
output reg [31:0] PCOut,
input bdIn,
output reg bdOut
);
//MEM stage pipeline registers
reg [31:0] ALUout_reg;
reg [31:0] rtFwd_reg;
reg [ 2:0] memCtrl_reg;
reg [ 2:0] wbSrc_reg;
always @(posedge clk) begin
if (rst | flush) begin
memCtrl_reg <= 3'b111;
wbRegOut <= 5'h00;
wbSrc_reg <= 3'b000;
end else if (~stall) begin
memCtrl_reg <= memCtrl;
wbRegOut <= wbRegIn;
wbSrc_reg <= wbSrc;
end
if (~stall) begin
ALUout_reg <= ALUout;
rtFwd_reg <= rtFwdMem;
PCOut <= PCIn;
bdOut <= bdIn;
end
end
//Memory read logic
reg [31:0] lbRes, lwlRes, lbuRes, lwrRes;
wire [31:0] lhRes, lhuRes;
reg [31:0] memRes;
wire [ 1:0] addr = ALUout_reg[1:0];
always @* begin
case (addr)
2'b00: lbRes <= {{24{memDataIn[7]}}, memDataIn[7:0]};
2'b01: lbRes <= {{24{memDataIn[15]}}, memDataIn[15:8]};
2'b10: lbRes <= {{24{memDataIn[23]}}, memDataIn[23:16]};
2'b11: lbRes <= {{24{memDataIn[31]}}, memDataIn[31:24]};
endcase
case (addr)
2'b00: lbuRes <= {24'h0, memDataIn[7:0]};
2'b01: lbuRes <= {24'h0, memDataIn[15:8]};
2'b10: lbuRes <= {24'h0, memDataIn[23:16]};
2'b11: lbuRes <= {24'h0, memDataIn[31:24]};
endcase
case (addr)
2'b00: lwlRes <= {memDataIn[7:0], rtFwd_reg[23:0]};
2'b01: lwlRes <= {memDataIn[15:0], rtFwd_reg[15:0]};
2'b10: lwlRes <= {memDataIn[23:0], rtFwd_reg[7:0]};
2'b11: lwlRes <= memDataIn;
endcase
case (addr)
2'b00: lwrRes <= memDataIn;
2'b01: lwrRes <= {rtFwd_reg[31:24], memDataIn[31:8]};
2'b10: lwrRes <= {rtFwd_reg[31:16], memDataIn[31:16]};
2'b11: lwrRes <= {rtFwd_reg[31:8], memDataIn[31:24]};
endcase
end
assign lhRes = addr[1]? {{16{memDataIn[31]}}, memDataIn[31:16]}: {{16{memDataIn[15]}}, memDataIn[15:0]};
assign lhuRes = addr[1] ? {16'h0, memDataIn[31:16]} : {16'h0, memDataIn[15:0]};
always @* begin
case (memCtrl_reg[2:0])
3'b000: memRes <= lbRes;
3'b001: memRes <= lhRes;
3'b010: memRes <= lwlRes;
3'b011: memRes <= memDataIn;
3'b100: memRes <= lbuRes;
3'b101: memRes <= lhuRes;
3'b110: memRes <= lwrRes;
default: memRes <= 32'h0;
endcase
//Write back logic
case (wbSrc_reg)
3'b000: wbData <= ALUout_reg;
3'b001: wbData <= memRes;
3'b010: wbData <= regHi;
3'b011: wbData <= regLo;
3'b100: wbData <= cp0RegOut;
default: wbData <= 32'h0;
endcase
end
endmodule
| 7.663388 |
module StageModify (
clk,
reset,
a_in,
a,
operation_in,
ack_in,
operation,
ack
);
parameter D_WIDTH = 8;
input clk;
input reset;
input [D_WIDTH - 1:0] a_in;
output reg [D_WIDTH - 1:0] a;
input [`OPCODE_MSB:0] operation_in;
output ack;
output reg [`OPCODE_MSB:0] operation;
input ack_in;
assign ack = ack_in;
always @(posedge clk) begin
if (reset) begin
operation <= 0;
a <= 0;
end else begin
if (ack_in) begin
operation <= operation_in;
if (operation_in[`OP_INC]) a <= a_in + 1;
else if (operation_in[`OP_DEC]) a <= a_in - 1;
else if (operation_in[`OP_IN] || operation_in[`OP_OUT]) a <= a_in;
else a <= 0;
end
end
end
endmodule
| 7.949615 |
module StageReg (
input clock,
input reset,
input [31:0] io_in_instruction,
input [31:0] io_in_pc,
input io_flush,
input io_valid,
output [31:0] io_data_instruction,
output [31:0] io_data_pc
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg [31:0] reg_instruction;
reg [31:0] reg_pc;
assign io_data_instruction = reg_instruction;
assign io_data_pc = reg_pc;
always @(posedge clock) begin
if (reset) begin
reg_instruction <= 32'h0;
end else if (io_flush) begin
reg_instruction <= 32'h0;
end else if (io_valid) begin
reg_instruction <= io_in_instruction;
end
if (reset) begin
reg_pc <= 32'h0;
end else if (io_flush) begin
reg_pc <= 32'h0;
end else if (io_valid) begin
reg_pc <= io_in_pc;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_instruction = _RAND_0[31:0];
_RAND_1 = {1{`RANDOM}};
reg_pc = _RAND_1[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 7.496723 |
module IFIDRegister (
input reset_n,
input clk,
input stall,
input flush,
input [`opcode_bitno - 1 : 0] IF_inst_addr_MSB,
input [`WORD_SIZE - 1 : 0] IF_inst_addr_seq,
input [`WORD_SIZE - 1 : 0] IF_instruction,
input [`WORD_SIZE - 1 : 0] IF_num_inst,
//input jump_decision,
output reg [`opcode_bitno - 1 : 0] ID_inst_addr_MSB,
output reg [`WORD_SIZE - 1 : 0] ID_inst_addr_seq,
output reg [`WORD_SIZE - 1 : 0] ID_instruction,
output reg [`WORD_SIZE - 1 : 0] ID_num_inst
//,reg ID_jump_decision;
);
always @(posedge clk) begin
if (~reset_n || flush) begin // reset on reset or flush
ID_inst_addr_MSB = 0;
ID_inst_addr_seq = 0;
ID_instruction = `INST_FLUSH;
ID_num_inst = 0;
//ID_jump_decision = 0;
end else if (~stall) begin // proceed on not stall and not flush
ID_inst_addr_MSB = IF_inst_addr_MSB;
ID_inst_addr_seq = IF_inst_addr_seq;
ID_instruction = IF_instruction;
ID_num_inst = IF_num_inst;
//ID_jump_decision = jump_decision;
end
end
endmodule
| 6.787752 |
module IDEXRegister (
input reset_n,
input clk,
input stall,
input flush,
input [`WORD_SIZE - 1 : 0] ID_inst_addr_seq,
input [`WORD_SIZE - 1 : 0] ID_rs_value,
input [`WORD_SIZE - 1 : 0] ID_rt_value,
input [`WORD_SIZE - 1 : 0] ID_I_imm,
input [`target_loc_l : `target_loc_r] ID_J_target,
input [`addr_bitno - 1 : 0] ID_write_addr,
input [`WORD_SIZE - 1 : 0] EX_rs_forwarded_value,
input [`WORD_SIZE - 1 : 0] EX_rt_forwarded_value,
output reg [`WORD_SIZE - 1 : 0] EX_inst_addr_seq,
output reg [`WORD_SIZE - 1 : 0] EX_rs_value,
output reg [`WORD_SIZE - 1 : 0] EX_rt_value,
output reg [`WORD_SIZE - 1 : 0] EX_I_imm,
output reg [`target_loc_l : `target_loc_r] EX_J_target,
output reg [`addr_bitno - 1 : 0] EX_write_addr
);
always @(posedge clk) begin
if (~reset_n || flush) begin // reset on reset or flush
EX_inst_addr_seq = 0;
EX_rs_value = 0;
EX_rt_value = 0;
EX_I_imm = 0;
EX_J_target = 0;
EX_write_addr = 0;
end else if (~stall) begin // proceed on not stall and not flush
EX_inst_addr_seq = ID_inst_addr_seq;
EX_rs_value = ID_rs_value;
EX_rt_value = ID_rt_value;
EX_I_imm = ID_I_imm;
EX_J_target = ID_J_target;
EX_write_addr = ID_write_addr;
end else begin
EX_rs_value = EX_rs_forwarded_value;
EX_rt_value = EX_rt_forwarded_value;
end
end
endmodule
| 7.099567 |
module EXControlRegister (
input reset_n,
input clk,
input stall,
input flush,
input IN_ALUPathIntercept,
input [1:0] IN_ALUSrc,
input [`ALU_opcode_bitno - 1 : 0] IN_ALU_OP,
output reg OUT_ALUPathIntercept,
output reg [1:0] OUT_ALUSrc,
output reg [`ALU_opcode_bitno - 1 : 0] OUT_ALU_OP
);
always @(posedge clk) begin
if (~reset_n || flush) begin // reset on reset or flush
OUT_ALUPathIntercept = 0;
OUT_ALUSrc = 0;
OUT_ALU_OP = 0;
end else if (~stall) begin // proceed on not stall and not flush
OUT_ALUPathIntercept = IN_ALUPathIntercept;
OUT_ALUSrc = IN_ALUSrc;
OUT_ALU_OP = IN_ALU_OP;
end
end
endmodule
| 6.625355 |
module WBControlRegister (
input reset_n,
input clk,
input stall,
input flush,
input IN_MemtoReg,
input IN_RegWrite,
input IN_is_halted,
output reg OUT_MemtoReg,
output reg OUT_RegWrite,
output reg OUT_is_halted
);
always @(posedge clk) begin
if (~reset_n || flush) begin // reset on reset or flush
OUT_MemtoReg = 0;
OUT_RegWrite = 0;
OUT_is_halted = 0;
end else if (~stall) begin // proceed on not stall and not flush
OUT_MemtoReg = IN_MemtoReg;
OUT_RegWrite = IN_RegWrite;
OUT_is_halted = IN_is_halted;
end
end
endmodule
| 7.932201 |
module OutputRegister (
input reset_n,
input clk,
input stall,
input flush,
input IN_output_update,
input [`WORD_SIZE - 1 : 0] IN_num_inst,
input [`WORD_SIZE - 1 : 0] IN_output_value,
input [`WORD_SIZE - 1 : 0] IN_output_forwarded_value,
output reg OUT_output_update,
output reg [`WORD_SIZE - 1 : 0] OUT_num_inst,
output reg [`WORD_SIZE - 1 : 0] OUT_output_value
);
always @(posedge clk) begin
if (~reset_n || flush) begin // reset on reset or flush
OUT_output_update = 0;
OUT_num_inst = 0;
OUT_output_update = 0;
end else if (~stall) begin // proceed on not stall and not flush
OUT_output_update = IN_output_update;
OUT_num_inst = IN_num_inst;
OUT_output_value = IN_output_value;
end else OUT_output_value = IN_output_forwarded_value;
end
endmodule
| 7.011115 |
module PC (
input CLK,
input PCWrite,
input [31:0] in,
output reg [31:0] out
);
/*
* Implementation Notes
* --------------------
* INPUTS:
* CLK -> the clock signal
* PCWrite -> the control signal enables PC to write
* in -> input address
* OUTPUTS:
* out -> new address
*/
/* Inputs declaration */
wire CLK;
wire PCWrite;
wire [31:0] in;
/* Initialization */
initial begin
out <= 32'd0;
end
/* Main function */
always @(posedge CLK) begin
if (PCWrite) out <= in;
// $display("From PC. OUT: %32b", out);
end
endmodule
| 7.578567 |
module IF_ID (
input CLK,
input Write,
input [31:0] PC_IN,
input [31:0] INS_IN,
output reg [31:0] PC_OUT,
output reg [31:0] INS_OUT
);
/* Implementation Notes
* --------------------
* INPUTS:
* CLK -> the clock signal
* Write -> the control signal enables IF_ID to write
* PC_IN -> input PC
* INS_IN -> input binary code of the instruction fetched
* OUTPUTS:
* PC_OUT -> output PC
* INS_OUT -> output instruction
*/
/* Inputs declaration */
wire CLK;
wire Write;
wire [31:0] PC_IN;
wire [31:0] INS_IN;
/* Main function */
always @(posedge CLK) begin
if (Write) begin
PC_OUT <= PC_IN;
INS_OUT <= INS_IN;
end
end
endmodule
| 7.719833 |
module ID_EX (
input CLK,
input Flush,
input MemtoReg,
input RegWrite,
input MemWrite,
input MemRead,
input [ 1:0] Branch,
input Jump,
input PCSrc,
input [ 3:0] ALUControl,
input ALUSrc,
input RegDst,
input [31:0] readData1,
input [31:0] readData2,
input [31:0] extendedData,
input [ 4:0] IF_ID_RegisterRs,
input [ 4:0] IF_ID_RegisterRt,
input [ 4:0] IF_ID_RegisterRd,
input [ 4:0] Shamt,
input ShiftSrc,
output reg MemtoReg_OUT,
output reg RegWrite_OUT,
output reg MemWrite_OUT,
output reg MemRead_OUT,
output reg [ 1:0] Branch_OUT,
output reg Jump_OUT,
output reg PCSrc_OUT,
output reg [ 3:0] ALUControl_OUT,
output reg ALUSrc_OUT,
output reg RegDst_OUT,
output reg [31:0] readData1_OUT,
output reg [31:0] readData2_OUT,
output reg [31:0] extendedData_OUT,
output reg [ 4:0] ID_EX_RegisterRs_OUT,
output reg [ 4:0] ID_EX_RegisterRt_OUT,
output reg [ 4:0] ID_EX_RegisterRd_OUT,
output reg [ 4:0] ID_EX_Shamt_OUT,
output reg ID_EX_ShiftSrc_OUT
);
/* Inputs declaration */
wire CLK;
wire Flush;
wire MemtoReg;
wire RegWrite;
wire MemWrite;
wire MemRead;
wire [ 1:0] Branch;
wire Jump;
wire PCSrc;
wire [ 3:0] ALUControl;
wire ALUSrc;
wire RegDst;
wire [31:0] readData1;
wire [31:0] readData2;
wire [31:0] extendedData;
wire [ 4:0] IF_ID_RegisterRs;
wire [ 4:0] IF_ID_RegisterRt;
wire [ 4:0] IF_ID_RegisterRd;
wire [ 4:0] Shamt;
wire ShiftSrc;
/* Main function */
always @(posedge CLK) begin
if (!Flush) begin
MemtoReg_OUT <= MemtoReg;
RegWrite_OUT <= RegWrite;
MemWrite_OUT <= MemWrite;
MemRead_OUT <= MemRead;
Branch_OUT <= Branch;
Jump_OUT <= Jump;
PCSrc_OUT <= PCSrc;
ALUControl_OUT <= ALUControl;
ALUSrc_OUT <= ALUSrc;
RegDst_OUT <= RegDst;
readData1_OUT <= readData1;
readData2_OUT <= readData2;
extendedData_OUT <= extendedData;
ID_EX_RegisterRs_OUT <= IF_ID_RegisterRs;
ID_EX_RegisterRt_OUT <= IF_ID_RegisterRt;
ID_EX_RegisterRd_OUT <= IF_ID_RegisterRd;
ID_EX_Shamt_OUT <= Shamt;
ID_EX_ShiftSrc_OUT <= ShiftSrc;
end else begin
MemtoReg_OUT <= 0;
RegWrite_OUT <= 0;
MemWrite_OUT <= 0;
MemRead_OUT <= 0;
Branch_OUT <= 0;
Jump_OUT <= 0;
PCSrc_OUT <= 0;
ALUControl_OUT <= 0;
ALUSrc_OUT <= 0;
RegDst_OUT <= 0;
readData1_OUT <= 0;
readData2_OUT <= 0;
extendedData_OUT <= 0;
ID_EX_RegisterRs_OUT <= 0;
ID_EX_RegisterRt_OUT <= 0;
ID_EX_RegisterRd_OUT <= 0;
ID_EX_Shamt_OUT <= 0;
ID_EX_ShiftSrc_OUT <= 0;
end
end
endmodule
| 8.23208 |
module StageReg_1 (
input clock,
input reset,
input [31:0] io_in_pc,
input [31:0] io_in_instruction,
input [31:0] io_in_sextImm,
input [31:0] io_in_readdata1,
input [31:0] io_in_readdata2,
input io_flush,
input io_valid,
output [31:0] io_data_pc,
output [31:0] io_data_instruction,
output [31:0] io_data_sextImm,
output [31:0] io_data_readdata1,
output [31:0] io_data_readdata2
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
reg [31:0] reg_pc;
reg [31:0] reg_instruction;
reg [31:0] reg_sextImm;
reg [31:0] reg_readdata1;
reg [31:0] reg_readdata2;
assign io_data_pc = reg_pc;
assign io_data_instruction = reg_instruction;
assign io_data_sextImm = reg_sextImm;
assign io_data_readdata1 = reg_readdata1;
assign io_data_readdata2 = reg_readdata2;
always @(posedge clock) begin
if (reset) begin
reg_pc <= 32'h0;
end else if (io_flush) begin
reg_pc <= 32'h0;
end else if (io_valid) begin
reg_pc <= io_in_pc;
end
if (reset) begin
reg_instruction <= 32'h0;
end else if (io_flush) begin
reg_instruction <= 32'h0;
end else if (io_valid) begin
reg_instruction <= io_in_instruction;
end
if (reset) begin
reg_sextImm <= 32'h0;
end else if (io_flush) begin
reg_sextImm <= 32'h0;
end else if (io_valid) begin
reg_sextImm <= io_in_sextImm;
end
if (reset) begin
reg_readdata1 <= 32'h0;
end else if (io_flush) begin
reg_readdata1 <= 32'h0;
end else if (io_valid) begin
reg_readdata1 <= io_in_readdata1;
end
if (reset) begin
reg_readdata2 <= 32'h0;
end else if (io_flush) begin
reg_readdata2 <= 32'h0;
end else if (io_valid) begin
reg_readdata2 <= io_in_readdata2;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_pc = _RAND_0[31:0];
_RAND_1 = {1{`RANDOM}};
reg_instruction = _RAND_1[31:0];
_RAND_2 = {1{`RANDOM}};
reg_sextImm = _RAND_2[31:0];
_RAND_3 = {1{`RANDOM}};
reg_readdata1 = _RAND_3[31:0];
_RAND_4 = {1{`RANDOM}};
reg_readdata2 = _RAND_4[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 7.20915 |
module StageReg_3 (
input clock,
input reset,
input [31:0] io_in_ex_result,
input [31:0] io_in_mem_writedata,
input [31:0] io_in_instruction,
input [31:0] io_in_next_pc,
input io_in_taken,
input io_flush,
input io_valid,
output [31:0] io_data_ex_result,
output [31:0] io_data_mem_writedata,
output [31:0] io_data_instruction,
output [31:0] io_data_next_pc,
output io_data_taken
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
reg [31:0] reg_ex_result;
reg [31:0] reg_mem_writedata;
reg [31:0] reg_instruction;
reg [31:0] reg_next_pc;
reg reg_taken;
assign io_data_ex_result = reg_ex_result;
assign io_data_mem_writedata = reg_mem_writedata;
assign io_data_instruction = reg_instruction;
assign io_data_next_pc = reg_next_pc;
assign io_data_taken = reg_taken;
always @(posedge clock) begin
if (reset) begin
reg_ex_result <= 32'h0;
end else if (io_flush) begin
reg_ex_result <= 32'h0;
end else if (io_valid) begin
reg_ex_result <= io_in_ex_result;
end
if (reset) begin
reg_mem_writedata <= 32'h0;
end else if (io_flush) begin
reg_mem_writedata <= 32'h0;
end else if (io_valid) begin
reg_mem_writedata <= io_in_mem_writedata;
end
if (reset) begin
reg_instruction <= 32'h0;
end else if (io_flush) begin
reg_instruction <= 32'h0;
end else if (io_valid) begin
reg_instruction <= io_in_instruction;
end
if (reset) begin
reg_next_pc <= 32'h0;
end else if (io_flush) begin
reg_next_pc <= 32'h0;
end else if (io_valid) begin
reg_next_pc <= io_in_next_pc;
end
if (reset) begin
reg_taken <= 1'h0;
end else if (io_flush) begin
reg_taken <= 1'h0;
end else if (io_valid) begin
reg_taken <= io_in_taken;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_ex_result = _RAND_0[31:0];
_RAND_1 = {1{`RANDOM}};
reg_mem_writedata = _RAND_1[31:0];
_RAND_2 = {1{`RANDOM}};
reg_instruction = _RAND_2[31:0];
_RAND_3 = {1{`RANDOM}};
reg_next_pc = _RAND_3[31:0];
_RAND_4 = {1{`RANDOM}};
reg_taken = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 7.51311 |
module StageReg_4 (
input clock,
input reset,
input [1:0] io_in_mem_ctrl_memop,
input io_in_wb_ctrl_toreg,
input io_in_wb_ctrl_regwrite,
input io_flush,
input io_valid,
output [1:0] io_data_mem_ctrl_memop,
output io_data_wb_ctrl_toreg,
output io_data_wb_ctrl_regwrite
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg [1:0] reg_mem_ctrl_memop;
reg reg_wb_ctrl_toreg;
reg reg_wb_ctrl_regwrite;
assign io_data_mem_ctrl_memop = reg_mem_ctrl_memop;
assign io_data_wb_ctrl_toreg = reg_wb_ctrl_toreg;
assign io_data_wb_ctrl_regwrite = reg_wb_ctrl_regwrite;
always @(posedge clock) begin
if (reset) begin
reg_mem_ctrl_memop <= 2'h0;
end else if (io_flush) begin
reg_mem_ctrl_memop <= 2'h0;
end else if (io_valid) begin
reg_mem_ctrl_memop <= io_in_mem_ctrl_memop;
end
if (reset) begin
reg_wb_ctrl_toreg <= 1'h0;
end else if (io_flush) begin
reg_wb_ctrl_toreg <= 1'h0;
end else if (io_valid) begin
reg_wb_ctrl_toreg <= io_in_wb_ctrl_toreg;
end
if (reset) begin
reg_wb_ctrl_regwrite <= 1'h0;
end else if (io_flush) begin
reg_wb_ctrl_regwrite <= 1'h0;
end else if (io_valid) begin
reg_wb_ctrl_regwrite <= io_in_wb_ctrl_regwrite;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_mem_ctrl_memop = _RAND_0[1:0];
_RAND_1 = {1{`RANDOM}};
reg_wb_ctrl_toreg = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
reg_wb_ctrl_regwrite = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.679582 |
module StageReg_5 (
input clock,
input reset,
input [31:0] io_in_instruction,
input [31:0] io_in_readdata,
input [31:0] io_in_ex_result,
input io_flush,
input io_valid,
output [31:0] io_data_instruction,
output [31:0] io_data_readdata,
output [31:0] io_data_ex_result
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg [31:0] reg_instruction;
reg [31:0] reg_readdata;
reg [31:0] reg_ex_result;
assign io_data_instruction = reg_instruction;
assign io_data_readdata = reg_readdata;
assign io_data_ex_result = reg_ex_result;
always @(posedge clock) begin
if (reset) begin
reg_instruction <= 32'h0;
end else if (io_flush) begin
reg_instruction <= 32'h0;
end else if (io_valid) begin
reg_instruction <= io_in_instruction;
end
if (reset) begin
reg_readdata <= 32'h0;
end else if (io_flush) begin
reg_readdata <= 32'h0;
end else if (io_valid) begin
reg_readdata <= io_in_readdata;
end
if (reset) begin
reg_ex_result <= 32'h0;
end else if (io_flush) begin
reg_ex_result <= 32'h0;
end else if (io_valid) begin
reg_ex_result <= io_in_ex_result;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_instruction = _RAND_0[31:0];
_RAND_1 = {1{`RANDOM}};
reg_readdata = _RAND_1[31:0];
_RAND_2 = {1{`RANDOM}};
reg_ex_result = _RAND_2[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 7.658383 |
module StageReg_6 (
input clock,
input reset,
input io_in_wb_ctrl_toreg,
input io_in_wb_ctrl_regwrite,
input io_flush,
input io_valid,
output io_data_wb_ctrl_toreg,
output io_data_wb_ctrl_regwrite
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg reg_wb_ctrl_toreg;
reg reg_wb_ctrl_regwrite;
assign io_data_wb_ctrl_toreg = reg_wb_ctrl_toreg;
assign io_data_wb_ctrl_regwrite = reg_wb_ctrl_regwrite;
always @(posedge clock) begin
if (reset) begin
reg_wb_ctrl_toreg <= 1'h0;
end else if (io_flush) begin
reg_wb_ctrl_toreg <= 1'h0;
end else if (io_valid) begin
reg_wb_ctrl_toreg <= io_in_wb_ctrl_toreg;
end
if (reset) begin
reg_wb_ctrl_regwrite <= 1'h0;
end else if (io_flush) begin
reg_wb_ctrl_regwrite <= 1'h0;
end else if (io_valid) begin
reg_wb_ctrl_regwrite <= io_in_wb_ctrl_regwrite;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_wb_ctrl_toreg = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
reg_wb_ctrl_regwrite = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 7.016389 |
module stages #(
parameter rotation_stage = 1,
data_width = 16,
cordic_steps = 16
) (
input clk,
input nreset,
input enable,
input signed [data_width-1:0] x_vec_in,
input signed [data_width-1:0] y_vec_in,
input [cordic_steps-1:0] micro_rotation_in,
input [1:0] quad_in,
output signed [data_width-1:0] x_vec_out,
output signed [data_width-1:0] y_vec_out,
output reg [cordic_steps-1:0] micro_rotation_out,
output reg [1:0] quad_out,
output reg done
);
reg [data_width-1:0] x_temp_out, y_temp_out;
assign x_vec_out = x_temp_out;
assign y_vec_out = y_temp_out;
always @(posedge clk or negedge nreset) begin
if (~nreset) begin
x_temp_out <= {data_width{1'b0}};
y_temp_out <= {data_width{1'b0}};
micro_rotation_out <= 1'b0;
done <= 1'b0;
end else begin
if (enable) begin
done <= 1'b1;
if (!y_vec_in[data_width-1]) begin
x_temp_out <= x_vec_in + (y_vec_in >>> rotation_stage);
y_temp_out <= y_vec_in - (x_vec_in >>> rotation_stage);
micro_rotation_out <= {
{(cordic_steps - 1 - rotation_stage) {1'b0}},
1'b1,
micro_rotation_in[rotation_stage-1:0]
};
end else begin
x_temp_out <= x_vec_in - (y_vec_in >>> rotation_stage);
y_temp_out <= y_vec_in + (x_vec_in >>> rotation_stage);
micro_rotation_out <= {
{(cordic_steps - 1 - rotation_stage) {1'b0}},
1'b0,
micro_rotation_in[rotation_stage-1:0]
};
end
quad_out <= quad_in;
end else begin
done <= 1'b0;
end
end
end
endmodule
| 6.846107 |
module StageX (
clk,
reset,
operation_in,
ack_in,
operation,
ack,
);
input clk;
input reset;
input [`OPCODE_MSB:0] operation_in;
output reg ack;
output reg [`OPCODE_MSB:0] operation;
input ack_in;
assign ack = ack_in;
always @(posedge clk) begin
if (reset) begin
operation <= 0;
end else begin
if (ack_in) begin
operation <= operation_in;
end
end
end
endmodule
| 7.237141 |
module StageWriteback (
clk,
reset,
dp,
dce,
da,
dq,
cq,
cwre,
cbsy,
a_in,
operation_in,
ack_in,
operation,
ack
);
parameter A_WIDTH = 12;
parameter D_WIDTH = 8;
input clk;
input reset;
input [A_WIDTH - 1:0] dp;
output dce;
output [A_WIDTH - 1:0] da;
output [D_WIDTH - 1:0] dq;
output [7:0] cq;
output cwre;
input cbsy;
input [D_WIDTH - 1:0] a_in;
input [`OPCODE_MSB:0] operation_in;
output ack;
output reg [`OPCODE_MSB:0] operation;
input ack_in;
/*
* Writing to DRAM
*/
wire need_write_mem;
assign need_write_mem = (operation_in[`OP_INC] || operation_in[`OP_DEC] || operation_in[`OP_IN]);
assign da = dp;
assign dce = need_write_mem;
assign dq = a_in;
/*
* Writing to EXT
*/
wire need_write_ext;
assign need_write_ext = operation_in[`OP_OUT];
assign cq = a_in;
assign cwre = !cbsy && need_write_ext;
wire ext_wait;
assign ext_wait = need_write_ext && cbsy;
/*
* ACKing the previous stage
*/
assign ack = ack_in && !ext_wait;
always @(posedge clk) begin
if (reset) begin
operation <= 0;
end else begin
if (ack_in && !ext_wait) operation <= operation_in;
else if (ack_in) operation <= 0; /* Bubble */
end
end
endmodule
| 8.006443 |
module stage_00 #(
parameter DATA_WIDTH = 16,
parameter MINI_BATCH = 8,
parameter ADDR_WIDTH = 3
) (
input clk,
input rst_n,
input [DATA_WIDTH-1:0] x_in,
input valid_in,
output [DATA_WIDTH-1:0] x_out,
output [ADDR_WIDTH-1:0] addr_out,
output valid_out
);
reg [ADDR_WIDTH-1:0] counter;
assign x_out = valid_in ? x_in : {DATA_WIDTH{1'b0}};
assign valid_out = valid_in ? 1 : 0;
assign addr_out = (valid_in && rst_n) ? (counter) : {ADDR_WIDTH{1'b0}};
always @(posedge clk) begin
if (!rst_n) begin
counter <= {ADDR_WIDTH{1'b0}};
end else if (valid_in) counter <= counter + 1;
end
endmodule
| 7.475236 |
module stage_01 #(
parameter DATA_WIDTH = 16,
parameter MINI_BATCH = 64,
parameter ADDR_WIDTH = 6
) (
input clk,
input rst_n,
input [DATA_WIDTH-1:0] max_in,
input [DATA_WIDTH-1:0] min_in,
input [DATA_WIDTH-1:0] partsum_in,
input valid_in,
input [ADDR_WIDTH-1:0] addr_in,
output [DATA_WIDTH-1:0] max_out,
output [DATA_WIDTH-1:0] min_out,
output [DATA_WIDTH-1:0] max_res_out,
output [DATA_WIDTH-1:0] min_res_out,
output [DATA_WIDTH-1:0] partsum_out,
output valid_out,
output [DATA_WIDTH-1:0] sum_out
);
reg [DATA_WIDTH-1:0] max, min, partsum, sum, max_res, min_res;
//reg [DATA_WIDTH-1:0] tmpmax,tmpmin;
reg valid;
reg [ADDR_WIDTH:0] counter;
assign max_out = max;
assign min_out = min;
assign max_res_out = max_res;
assign min_res_out = min_res;
assign partsum_out = partsum;
assign valid_out = valid;
assign sum_out = sum;
always @(posedge clk) begin
if (!rst_n) begin
min <= {{1'b0}, {(DATA_WIDTH - 1) {1'b1}}};
max <= {DATA_WIDTH{1'b0}};
min_res <= {DATA_WIDTH{1'b0}};
max_res <= {DATA_WIDTH{1'b0}};
// tmpmax <= {DATA_WIDTH{1'b0}};
// tmpmin <= {{1'b0},{(DATA_WIDTH-1){1'b1}}};
end else begin
max <= max_in;
min <= min_in;
// tmpmax <= max_in;
// tmpmin <= min_in;
if (addr_in == MINI_BATCH - 1) begin
max_res <= max_in;
min_res <= min_in;
min <= {{1'b0}, {(DATA_WIDTH - 1) {1'b1}}};
max <= {DATA_WIDTH{1'b0}};
end
end
end
always @(posedge clk) begin
if (!rst_n) begin
valid <= 1'b0;
partsum <= {DATA_WIDTH{1'b0}};
sum <= {DATA_WIDTH{1'b0}};
counter <= {(ADDR_WIDTH + 1) {1'b0}};
end else begin
if (valid_in) counter <= counter + 1;
partsum <= partsum_in;
if (addr_in == MINI_BATCH - 1) begin
sum <= partsum_in;
partsum <= {DATA_WIDTH{1'b0}};
counter <= {(ADDR_WIDTH + 1) {1'b0}};
end
end
end
always @(posedge clk) begin
if (!rst_n) valid <= 1'b0;
else begin
if (addr_in == MINI_BATCH - 1 && valid_in) valid <= 1'b1;
else valid <= 1'b0;
end
end
endmodule
| 7.533847 |
module stage_02 (
rst_n,
clk,
stan_dev_in,
avg_in,
valid_in,
stan_dev_out,
avg_out,
valid_out
);
parameter DATA_WIDTH = 16;
input clk;
input rst_n;
input valid_in;
input [DATA_WIDTH-1:0] stan_dev_in;
input [DATA_WIDTH-1:0] avg_in;
output [DATA_WIDTH-1:0] stan_dev_out;
output [DATA_WIDTH-1:0] avg_out;
output valid_out;
reg [DATA_WIDTH-1:0] avg, stan_dev;
reg valid;
assign stan_dev_out = stan_dev;
assign avg_out = avg;
assign valid_out = valid;
always @(posedge clk) begin
if (!rst_n) begin
avg <= {DATA_WIDTH{1'b0}};
stan_dev <= {DATA_WIDTH{1'b0}};
valid <= 1'b0;
end else if (valid_in) begin
avg <= avg_in;
stan_dev <= stan_dev_in;
valid <= 1'b1;
end else begin
avg <= {DATA_WIDTH{1'b0}};
stan_dev <= {DATA_WIDTH{1'b0}};
valid <= 1'b0;
end
end
endmodule
| 6.749407 |
module stage_10 (
rst_n,
clk,
start_bn_tra_in,
addr_out,
start_bn_tra_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = 6;
input clk;
input rst_n;
input start_bn_tra_in;
output [ADDR_WIDTH-1:0] addr_out;
output start_bn_tra_out;
reg [ADDR_WIDTH-1:0] counter;
reg start_bn_tra;
reg counter_flag;
assign addr_out = (rst_n && counter_flag) ? counter : {ADDR_WIDTH{1'b0}};
assign start_bn_tra_out = start_bn_tra;
always @(posedge clk) begin
if (!rst_n) begin
counter <= {ADDR_WIDTH{1'b0}};
start_bn_tra <= 0;
counter_flag <= 1'b0;
end else if (start_bn_tra_in) begin
start_bn_tra <= 1;
counter_flag <= 1'b1;
end else if (counter == MINI_BATCH - 1) begin
start_bn_tra <= 0;
counter_flag <= 1'b0;
end
end
always @(posedge clk) begin
if (!rst_n) counter <= {ADDR_WIDTH{1'b0}};
else if (counter_flag) begin
counter <= counter + 1;
end
end
endmodule
| 7.322371 |
module stage_12 (
rst_n,
clk,
start_bn_tra_in,
x_in,
x_out,
start_bn_tra_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input clk;
input rst_n;
input [DATA_WIDTH-1:0] x_in;
input start_bn_tra_in;
output [DATA_WIDTH-1:0] x_out;
output start_bn_tra_out;
reg start_bn_tra;
reg [DATA_WIDTH-1:0] x;
assign start_bn_tra_out = start_bn_tra;
assign x_out = x;
always @(posedge clk) begin
if (!rst_n) begin
start_bn_tra <= 1'b0;
x <= {DATA_WIDTH{1'b0}};
end else begin
start_bn_tra <= start_bn_tra_in;
if (start_bn_tra_in) x <= x_in;
else x <= {DATA_WIDTH{1'b0}};
end
end
endmodule
| 7.237185 |
module stage_13 (
rst_n,
clk,
start_bn_tra_in,
x_in,
x_out,
start_bn_tra_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input clk;
input rst_n;
input [DATA_WIDTH-1:0] x_in;
input start_bn_tra_in;
output [DATA_WIDTH-1:0] x_out;
output start_bn_tra_out;
reg start_bn_tra;
reg [DATA_WIDTH-1:0] x;
assign start_bn_tra_out = start_bn_tra;
assign x_out = x;
always @(posedge clk) begin
if (!rst_n) begin
start_bn_tra <= 1'b0;
x <= {DATA_WIDTH{1'b0}};
end else begin
if (start_bn_tra_in) begin
x <= x_in;
start_bn_tra <= start_bn_tra_in;
end else begin
x <= {DATA_WIDTH{1'b0}};
start_bn_tra <= 1'b0;
end
end
end
endmodule
| 7.079739 |
module stage_20 (
rst_n,
clk,
valid_in,
stan_dev_in,
avg_in,
stan_dev_out,
avg_out,
valid_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input clk;
input rst_n;
input valid_in;
input [DATA_WIDTH-1:0] stan_dev_in;
input [DATA_WIDTH-1:0] avg_in;
output [DATA_WIDTH-1:0] stan_dev_out;
output [DATA_WIDTH-1:0] avg_out;
output valid_out;
reg valid;
reg [DATA_WIDTH-1:0] avg, stan_dev;
assign valid_out = valid;
assign avg_out = avg;
assign stan_dev_out = stan_dev;
always @(posedge clk) begin
if (!rst_n) begin
valid <= 1'b0;
avg <= {DATA_WIDTH{1'b0}};
stan_dev <= {DATA_WIDTH{1'b0}};
end else begin
valid <= valid_in;
if (valid_in) begin
stan_dev <= stan_dev_in;
avg <= avg_in;
end else begin
avg <= {DATA_WIDTH{1'b0}};
stan_dev <= {DATA_WIDTH{1'b0}};
end
end
end
endmodule
| 7.230615 |
module stage_22 (
rst_n,
clk,
valid_in,
g_var_in,
g_avg_in,
partvar_out,
partavg_out,
g_var_out,
g_avg_out,
valid_out,
res_valid_in
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter TOTAL_BATCH = 128;
parameter BATCH_NUM = TOTAL_BATCH / MINI_BATCH;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input clk;
input rst_n;
input valid_in;
input [DATA_WIDTH-1:0] g_var_in;
input [DATA_WIDTH-1:0] g_avg_in;
input res_valid_in;
output [DATA_WIDTH-1:0] partvar_out;
output [DATA_WIDTH-1:0] partavg_out;
output [DATA_WIDTH-1:0] g_var_out;
output [DATA_WIDTH-1:0] g_avg_out;
output valid_out;
reg valid;
reg [DATA_WIDTH-1:0] g_avg, g_var, partavg, partvar;
reg [ADDR_WIDTH:0] counter;
reg flag;
assign valid_out = valid;
assign partavg_out = partavg;
assign partvar_out = partvar;
assign g_avg_out = g_avg;
assign g_var_out = g_var;
always @(posedge clk) begin
if (!rst_n) begin
counter <= {(ADDR_WIDTH + 1) {1'b0}};
valid <= 1'b0;
flag <= 1'b0;
end else begin
if (valid_in) counter <= counter + 1;
if (counter == BATCH_NUM) begin
counter <= {(ADDR_WIDTH + 1) {1'b0}};
valid <= 1'b1;
flag <= 1;
end else if (!res_valid_in && flag) valid <= 1'b1;
else if (res_valid_in) begin
flag = 1'b0;
valid <= 1'b0;
end else valid <= 1'b0;
end
end
always @(posedge clk) begin
if (!rst_n) begin
g_avg <= {DATA_WIDTH{1'b0}};
g_var <= {DATA_WIDTH{1'b0}};
partavg <= {DATA_WIDTH{1'b0}};
partvar <= {DATA_WIDTH{1'b0}};
end else begin
if (valid_in) begin
partvar <= g_var_in;
partavg <= g_avg_in;
end
if (counter == BATCH_NUM) begin
g_avg <= partavg;
g_var <= partvar;
end
end
end
endmodule
| 6.543289 |
module stage_23 #(
parameter DATA_WIDTH = 16,
parameter MINI_BATCH = 64,
parameter ADDR_WIDTH = $clog2(MINI_BATCH)
) (
input clk,
input rst_n,
input valid_in,
input [DATA_WIDTH-1:0] g_stan_dev_in,
input [DATA_WIDTH-1:0] g_avg_in,
output [DATA_WIDTH-1:0] g_stan_dev_out,
output [DATA_WIDTH-1:0] g_avg_out,
output valid_out
);
reg valid;
reg [DATA_WIDTH-1:0] g_avg, g_stan_dev;
assign valid_out = valid;
assign g_avg_out = g_avg;
assign g_stan_dev_out = g_stan_dev;
always @(posedge clk) begin
if (!rst_n) begin
valid <= 1'b0;
g_avg <= {DATA_WIDTH{1'b0}};
g_stan_dev <= {DATA_WIDTH{1'b0}};
end else begin
valid <= valid_in;
if (valid_in) begin
g_stan_dev <= g_stan_dev_in;
g_avg <= g_avg_in;
end else begin
g_avg <= {DATA_WIDTH{1'b0}};
g_stan_dev <= {DATA_WIDTH{1'b0}};
end
end
end
endmodule
| 7.2563 |
module stage_24 #(
parameter DATA_WIDTH = 16,
parameter MINI_BATCH = 64,
parameter ADDR_WIDTH = $clog2(MINI_BATCH)
) (
input clk,
input rst_n,
input valid_in,
input [DATA_WIDTH-1:0] a_in,
input [DATA_WIDTH-1:0] b_in,
output [DATA_WIDTH-1:0] a_out,
output [DATA_WIDTH-1:0] b_out,
output valid_out
);
reg valid_flag;
reg valid;
reg [DATA_WIDTH-1:0] b, a;
reg valid_rise;
assign valid_out = valid_rise;
assign b_out = b;
assign a_out = a;
always @(posedge clk) begin
if (!rst_n) begin
valid <= 1'b0;
b <= {DATA_WIDTH{1'b0}};
a <= {DATA_WIDTH{1'b0}};
end else begin
valid <= valid_in;
valid_rise <= (~valid) & valid_in;
if (valid_in) begin
a <= a_in;
b <= b_in;
end else begin
b <= {DATA_WIDTH{1'b0}};
a <= {DATA_WIDTH{1'b0}};
end
end
end
endmodule
| 6.939542 |
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