code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module SS_OCT_SOPC_clock_3_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <=... | 7.008946 |
module SS_OCT_SOPC_clock_3_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to... | 7.008946 |
module SS_OCT_SOPC_clock_4_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <=... | 7.008946 |
module SS_OCT_SOPC_clock_4_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to... | 7.008946 |
module SS_OCT_SOPC_clock_5_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <=... | 7.008946 |
module SS_OCT_SOPC_clock_5_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to... | 7.008946 |
module SS_OCT_SOPC_clock_6_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <=... | 7.008946 |
module SS_OCT_SOPC_clock_6_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to... | 7.008946 |
module SS_OCT_SOPC_clock_7_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <=... | 7.008946 |
module SS_OCT_SOPC_clock_7_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to... | 7.008946 |
module pcm_slv_top (
clk,
rst,
ssel,
// PCM
pcm_clk_i,
pcm_sync_i,
pcm_din_i,
pcm_dout_o,
// Internal Interface
din_i,
dout_o,
re_i,
we_i
);
input clk, rst;
input [2:0] ssel; // Number of bits to delay (0-7)
input pcm_clk_i, pcm_sync_i, pcm_din_i;
output ... | 6.694229 |
module ss_rcvr #(
parameter WIDTH = 16
) (
input rxclk,
input sysclk,
input rst,
input [WIDTH-1:0] data_in,
output [WIDTH-1:0] data_out,
output reg clock_present
);
wire [3:0] rd_addr, wr_addr;
// Distributed RAM
reg [WIDTH-1:0] buffer[0:15];
always @(posedge rxclk) buffer[wr_addr... | 7.30315 |
module st4_mem ( // ´
input clk, // ʱ
input MEM_valid, // ´漶Чź
input [105:0] EXE_MEM_bus_r, //EXE->MEM
input [31:0] dm_rdata, // ´
output [31:0] dm_addr, // ´д
output reg [3:0] dm_wen, // ´дʹ
output reg [31:0] dm_wdata, // ´д
output MEM_over, // MEMģִ
output [69:0] MEM_WB_bu... | 6.928061 |
module sta (
input clk,
input reset,
output reg phy_mdc,
output phy_mdio_out,
output phy_mdio_tri,
input phy_mdio_in
);
// In general FALL_COUNT = 2*RISE_COUNT
parameter RISE_COUNT = 5;
parameter FALL_COUNT = 10;
reg mdc_rising, mdc_falling;
reg [7:0] mdc_counter;
always @(posedge ... | 7.400852 |
module PC #(
parameter Kw = 8,
parameter Km = 8,
parameter M = 8,
parameter W = 8
) (
clk,
rst,
addr,
wdata,
wen,
rdata
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value - 1;
for (log2 = 0; temp > 0; log2 = log2 + 1) te... | 7.441066 |
module MIsMatch #(
parameter Kw = 8,
parameter Km = 8,
parameter M = 8,
parameter W = 8
) (
clk,
rst,
waddr1,
wdata1,
wen1,
waddr2,
wdata2,
wen2,
raddr,
rdata
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value ... | 6.509431 |
module WIsMatch #(
parameter Kw = 8,
parameter Km = 8,
parameter M = 8,
parameter W = 8
) (
clk,
rst,
addr,
wdata,
wen,
rdata
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value - 1;
for (log2 = 0; temp > 0; log2 = log2 +... | 6.832205 |
module stable_matching_comb_BMR //Kr = m, S = n/2
#(
parameter Ks = 12, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 16, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parame... | 6.763333 |
module stable_matching_comb_BMR_2_4 #(
parameter Ks = 2, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 4, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parameter logR = logS... | 6.763333 |
module stable_matching_comb_BMR_4_4 #(
parameter Ks = 4, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 4, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parameter logR = logS... | 6.763333 |
module stable_matching_comb_BMR_3_6 #(
parameter Ks = 3, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 6, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parameter logR = logS... | 6.763333 |
module stable_matching_comb_BMR_6_6 #(
parameter Ks = 6, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 6, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parameter logR = logS... | 6.763333 |
module stable_matching_comb_BMR_4_8 #(
parameter Ks = 4, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 8, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parameter logR = logS... | 6.763333 |
module stable_matching_comb_BMR_8_8 #(
parameter Ks = 8, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 8, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parameter logR = logS... | 6.763333 |
module testBench;
parameter Kr = 4; //number of preferences for list B
parameter Ks = 4; //number of preferences for list A
parameter S = 4; //number of members in list A
parameter R = 4; //number of members in list B
parameter N = S * S - S + 2; //number of iterations
//-----------------------------... | 6.519976 |
module stack #(
parameter WIDTH = 8,
parameter DEPTH_LOG = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input stack_write_req,
input [WIDTH - 1:0] stack_write_data,
input stack_read_req,
output [WIDTH - 1:0] stack_read_data,
output stack_empty,
outp... | 7.074538 |
module reg_3 (
input wire clk,
reset,
load,
input wire [2:0] d,
output wire [2:0] q
);
dfrl dl[2:0] (
clk,
reset,
load,
d[2:0],
q[2:0]
);
endmodule
| 6.947963 |
module mux2_3 (
input wire op,
input wire [2:0] i0,
i1,
output wire [2:0] out
);
mux2 a0 (
i0[0],
i1[0],
op,
out[0]
);
mux2 a1 (
i0[1],
i1[1],
op,
out[1]
);
mux2 a2 (
i0[2],
i1[2],
op,
out[2]
);
endmodule
| 7.033659 |
module reg_3 (
input wire clk,
reset,
load,
input wire [2:0] d,
output wire [2:0] q
);
dfrl dl[2:0] (
clk,
reset,
load,
d[2:0],
q[2:0]
);
endmodule
| 6.947963 |
module mux2_3 (
input wire op,
input wire [2:0] i0,
i1,
output wire [2:0] out
);
mux2 a0 (
i0[0],
i1[0],
op,
out[0]
);
mux2 a1 (
i0[1],
i1[1],
op,
out[1]
);
mux2 a2 (
i0[2],
i1[2],
op,
out[2]
);
endmodule
| 7.033659 |
module mux4_3 (
input wire op2,
op1,
input wire [2:0] i0,
i1,
i2,
i3,
output wire [2:0] out
);
mux4 a0 (
{i0[0], i1[0], i2[0], i3[0]},
op2,
op1,
out[0]
);
mux4 a1 (
{i0[1], i1[1], i2[1], i3[1]},
op2,
op1,
out[1]
);
mux4 a2 (
{i0... | 6.899192 |
module stackAdder_tb ();
parameter period = 10;
reg push_pop, stack_op, clk;
reg [31:0] in;
wire [31:0] out;
always #(period / 2) clk = ~clk;
stackAdder add (
clk,
stack_op,
push_pop,
in,
out
);
initial begin
clk = 0;
in = 3;
stack_op = 0;
push_pop = 1;
... | 6.762767 |
module
module DARMUX(OLDDAR,SPR,NEWDAR,DARsel);
input [6:0] SPR,OLDDAR;
input [2:0] DARsel;
output reg [6:0] NEWDAR;
always@(*)
begin
case(DARsel)
`SPR_DAR: NEWDAR<=SPR; //2
`DEC_DAR_DAR: NEWDAR<=OLDDAR-1;//1
`INC_DAR_DAR: NEWDAR<=OLDDAR+1;//0
`INC_SPR_DAR2: NEWDAR<= SPR+2;//3
`DAR_CLR: NEWDAR <= ... | 7.020123 |
module DVRMUX (
dataIn,
arithOut,
DVRSel,
nextDVR
);
input [7:0] dataIn, arithOut;
input [1:0] DVRSel;
output reg [7:0] nextDVR;
always @(*) begin
case (DVRSel)
`BUS_DVR: nextDVR <= dataIn;
`ADD_DVR: nextDVR <= arithOut;
`DVR_CLR: nextDVR <= 0;
default: nextDVR <= ... | 6.853209 |
module arithRegAdder (
arithReg1,
arithReg2,
arithAddSub,
arithOut
);
input [7:0] arithReg1;
input [7:0] arithReg2;
input arithAddSub;
output reg [7:0] arithOut;
always @(*) begin
case (arithAddSub)
`ADD: begin
arithOut = arithReg1 + arithReg2;
end
`SUB: begin
... | 7.184829 |
module SPRMux (
oldSPR,
SPRsel,
newSPR
);
input [6:0] oldSPR;
input [1:0] SPRsel;
output reg [6:0] newSPR;
always @(*) begin
case (SPRsel)
0: newSPR <= 7'b1111111;
1: newSPR <= oldSPR + 1;
2: newSPR <= oldSPR - 1;
default: newSPR <= 0;
endcase
end
endmodule
| 6.585641 |
module DFF (
d,
clk,
out,
outN
);
input wire d, clk;
output wire out, outN;
reg qInternal;
always @(posedge clk) begin
qInternal <= d;
end
assign out = qInternal;
assign outN = ~qInternal;
endmodule
| 7.243009 |
module divider10Hz (
clk100MHz,
clk10Hz
);
input clk100MHz;
output clk10Hz;
reg [22:0] counter;
assign clk10Hz = counter[22]; // slightly over 40Hz
initial begin
counter = 0;
end
always @(posedge clk100MHz) begin
counter <= counter + 1;
end
endmodule
| 6.622063 |
module MIPSCntlr (
input [2:0] op,
input clk,
rst,
zero,
start,
output reg pcwrite,
IorD,
memwrite,
memread,
IRwrite,
memTostack,
push,
tos,
pop,
Awrite,
ALUsrcA,
pcsrc,
J,
r_or_not,
output reg [1:0] ALUsrcB,
output reg [1:0] aluop
);
... | 6.979126 |
module stacked_systolic_array_tb;
reg clk, ce;
reg [31:0] ctrl;
reg [3:0] mem_addr;
reg signed [39:0] x_ins;
wire signed [7:0] y_out;
integer i;
stacked_systolic_array dut (
clk,
ce,
ctrl,
mem_addr,
x_ins,
y_out
);
defparam dut.WIDTH = 8; defparam dut.ARRAY_COUNT... | 6.713899 |
module stacked_systolic_array (
clk,
ce,
ctrl,
mem_addr,
x_ins,
y_out
);
// Parameters
parameter WIDTH = 8;
parameter ARRAY_COUNT = 3;
parameter CELLS_PER_ARRAY_COUNT = 3;
parameter CELL_MEM_ADDR_WIDTH = 4;
parameter CELL_ROM_BASENAME = "weights/cell-weights-";
parameter CELL_ROM_... | 6.713899 |
module stacker (
clk,
reset,
go,
s_rate,
s_blocks,
column,
row
);
input clk;
input reset;
input go;
input [2:0] s_rate;
input [1:0] s_blocks;
output [7:0] column;
output [7:0] row;
wire [7:0] row_d_to_rc;
wire [7:0] lrow_c_to_d;
reg [7:0] lrow_main_to_c;
wire [3:0] ro... | 6.600209 |
module datapath (
clk,
reset,
en,
set,
row_in,
row_out
);
input clk; //from topmodule
input reset; //from topmodule
input en; //from topmodule
input set; //from control
input [7:0] row_in; //from control
output reg [7:0] row_out; //to row_controller
reg [7:0] prev_row;
reg... | 6.91752 |
module rate_divider (
clk,
reset,
freq,
out
);
input clk;
input reset;
input [27:0] freq;
output reg [27:0] out;
always @(posedge clk, negedge reset) begin
if (!reset) out = freq;
else begin
if (out == 1'b0) out <= freq;
else out <= out - 1'b1;
end
end
endmodule
| 7.346866 |
module stack_controller #(
parameter DEPTH_LOG = 4,
parameter WIDTH = 8
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input stack_write_req,
input [WIDTH - 1:0] stack_write_data,
input stack_read_req,
output reg stack_empty,
output stack_full,
output ... | 7.595483 |
module STACK_MEMORY #(
parameter DATA_WIDTH_MEM = 8,
parameter ADDR_WIDTH_MEM = 12
) (
input [(DATA_WIDTH_MEM-1):0] DATA_IN,
input [(ADDR_WIDTH_MEM-1):0] ADDR_IN,
input CTRL_MEM_WRITE,
clk_mem,
output wire [(DATA_WIDTH_MEM-1):0] DATA_OUT
);
// Declare the RAM variable
reg [DATA_WIDTH_ME... | 7.683349 |
module stack_tb;
reg clk;
reg [7:0] r0;
reg [1:0] rw;
wire [7:0] address;
stack st1 (
.clk(clk),
.r0(r0),
.rw(rw),
.address(address)
);
localparam period = 10;
always begin
#5 clk = 1'b1;
#5 clk = 1'b0;
end
initial begin
$dumpfile("stack1.vcd");
$dumpvars(... | 7.388626 |
module stack_test (
input wire clk,
reset,
input wire btnL,
btnR,
input wire [2:0] sw,
output wire [7:0] led
);
// signal declaration
wire db_btn[1:0];
// debounce circuits
debounce db_unit0 (
.clk(clk),
.reset(reset),
.sw(btnR),
.db_level(),
... | 7.413295 |
module stage0 (
input wire clk,
input wire rst,
input wire branch_mispredict,
output wire inst_rd_en,
output wire PC_en,
input wire next_rdy,
output wire vld
);
//If next stage is ready, we can read an instruction
//However, if the branch_mispredict signal is asserted, it means PC i... | 6.706914 |
module stage0_point_5 (
input wire clk,
input wire rst,
input wire [7:0] instr_in,
output wire [7:0] instr_out,
//counts how many cycles instruction has been in pipeline
input wire PC_en,
input wire [5:0] icount,
output wire [5:0] ocount,
input wire branch_mispredict,
input ... | 6.857962 |
module Stage1Ctrl (
NewIR,
IR_Stage1,
nop,
jal,
jump,
jmpIsn
);
input [31:0] NewIR, IR_Stage1;
output nop, jump, jal;
output [31:0] jmpIsn;
assign nop = (!IR_Stage1[31] && IR_Stage1[30] && !IR_Stage1[29] && !IR_Stage1[28] && !IR_Stage1[27]) && ((IR_Stage1[26:22] == NewIR[21:17]));
a... | 7.088187 |
module weight_buffer_18_9_42_1_2688Wcxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module weight_buffer_18_9_42_1_2688Wcxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module weight_buffer_18_9_42_1_2688Woxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module weight_buffer_18_9_42_1_2688Woxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module weight_buffer_18_9_42_1_2688Wfxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module weight_buffer_18_9_42_1_2688Wfxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module weight_buffer_18_9_42_1_2688Wixr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module weight_buffer_18_9_42_1_2688Wixr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
... | 6.6283 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.876859 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module weight_buffer_18_9_42_2_2688Wcxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Wcxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Woxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Woxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Wfxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Wfxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Wixr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_2_2688Wixr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.876859 |
module counter_63_2 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 2) <= 63) begin
count <= count + 2;
end else begin
count <= 14'd0;
end
... | 7.360162 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module weight_buffer_18_9_42_3_2688Wcxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_3_2688Wcxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_3_2688Woxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_3_2688Woxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_3_2688Wfxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_3_2688Wfxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_3_2688Wixr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module weight_buffer_18_9_42_3_2688Wixr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.876859 |
module counter_63_3 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 3) <= 63) begin
count <= count + 3;
end else begin
count <= 14'd0;
end
... | 7.231427 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module STAGE1_tb;
integer i, j, f;
reg clk, rst_n, valid, stop;
reg [10:0] before_ff [0:31];
reg [10:0] data_in_r;
wire [13:0] data_out_i, data_out_r;
wire finish;
STAGE1 test (
.clk(clk),
.rst_n(rst_n),
.valid_i(valid),
.data_in_r(data_in_r),
.data_in_i(10'd0),
.val... | 6.94027 |
module stage1_top #(
parameter XLEN_PIXEL = 8,
parameter NUM_OF_PIXELS = 784,
parameter NUM_OF_SV = 87,
parameter DECISION_FUNCT_SIZE = 56
) (
input clk,
rst,
en,
output y_class
);
wire re, we, stall_MEM, decision_funct_en;
// Variables we are storing in BRAM
//wire [XLEN_PIXEL-1... | 7.560058 |
module stage1_top_hwf #(
parameter XLEN_PIXEL = 8,
parameter NUM_OF_PIXELS = 784,
parameter NUM_OF_SV = 10,
parameter DECISION_FUNCT_SIZE = 24
) (
input clk,
rst,
en,
output y_class
);
wire re, we, stall_MEM, decision_funct_en;
wire [XLEN_PIXEL-1:0] x_test;
// Instantiate control... | 7.275562 |
module stage1_top_tb #(
parameter XLEN_PIXEL = 8,
parameter NUM_OF_PIXELS = 4,
parameter NUM_OF_SV = 10
);
reg clk, rst, en;
wire y_class;
stage1_top_hwf uut (
.clk(clk),
.rst(rst),
.en(en),
.y_class(y_class)
);
initial begin
rst = 0;
#5 rst = 1;
clk = 0;
... | 6.541323 |
module Stage2Ctrl (
IR_Stage1,
isSW,
jr,
bexIsn
);
input [31:0] IR_Stage1;
output [31:0] bexIsn;
output isSW, jr;
assign isSW = (!IR_Stage1[31] && !IR_Stage1[30] && IR_Stage1[29] && IR_Stage1[28] && IR_Stage1[27]) || (!IR_Stage1[31] && !IR_Stage1[30] && !IR_Stage1[29] && IR_Stage1[28] && !IR_Sta... | 7.225913 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module shift_register_unit_12 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else i... | 6.854847 |
module counter_30_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 30) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 6.816296 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module shift_register_unit_12 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else i... | 6.854847 |
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