code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SS_OCT_SOPC_clock_3_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
assign data_out = data_in ^ data_in_d1;
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_3_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk1 or negedge reset_clk1_n) begin
if (reset_clk1_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk2 or negedge reset_clk2_n) begin
if (reset_clk2_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_4_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
assign data_out = data_in ^ data_in_d1;
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_4_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk1 or negedge reset_clk1_n) begin
if (reset_clk1_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk2 or negedge reset_clk2_n) begin
if (reset_clk2_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_5_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
assign data_out = data_in ^ data_in_d1;
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_5_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk1 or negedge reset_clk1_n) begin
if (reset_clk1_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk2 or negedge reset_clk2_n) begin
if (reset_clk2_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_6_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
assign data_out = data_in ^ data_in_d1;
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_6_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk1 or negedge reset_clk1_n) begin
if (reset_clk1_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk2 or negedge reset_clk2_n) begin
if (reset_clk2_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_7_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
assign data_out = data_in ^ data_in_d1;
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_7_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk1 or negedge reset_clk1_n) begin
if (reset_clk1_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk2 or negedge reset_clk2_n) begin
if (reset_clk2_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 7.008946 |
module pcm_slv_top (
clk,
rst,
ssel,
// PCM
pcm_clk_i,
pcm_sync_i,
pcm_din_i,
pcm_dout_o,
// Internal Interface
din_i,
dout_o,
re_i,
we_i
);
input clk, rst;
input [2:0] ssel; // Number of bits to delay (0-7)
input pcm_clk_i, pcm_sync_i, pcm_din_i;
output pcm_dout_o;
input [7:0] din_i;
output [7:0] dout_o;
input re_i;
input [1:0] we_i;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
reg pclk_t, pclk_s, pclk_r;
wire pclk_ris, pclk_fal;
reg psync;
reg pcm_sync_r1, pcm_sync_r2, pcm_sync_r3;
reg tx_go;
wire tx_data_le;
reg [15:0] tx_hold_reg;
reg [7:0] tx_hold_byte_h, tx_hold_byte_l;
reg [3:0] tx_cnt;
wire tx_done;
reg [15:0] rx_hold_reg, rx_reg;
wire rx_data_le;
reg rxd_t, rxd;
reg tx_go_r1, tx_go_r2;
reg [7:0] psa;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk) pclk_t <= #1 pcm_clk_i;
always @(posedge clk) pclk_s <= #1 pclk_t;
always @(posedge clk) pclk_r <= #1 pclk_s;
assign pclk_ris = !pclk_r & pclk_s;
assign pclk_fal = pclk_r & !pclk_s;
///////////////////////////////////////////////////////////////////
//
// Retrieve Sync Signal
//
always @(posedge clk) // Latch it at falling edge
if (pclk_fal)
pcm_sync_r1 <= #1 pcm_sync_i;
always @(posedge clk) // resync to rising edge
if (pclk_ris)
psa <= #1{psa[6:0], pcm_sync_r1};
always @(posedge clk) //delay bit N
pcm_sync_r2 <= #1 psa[ssel];
always @(posedge clk) // edge detector
pcm_sync_r3 <= #1 pcm_sync_r2;
always @(posedge clk) psync <= #1 !pcm_sync_r3 & pcm_sync_r2;
///////////////////////////////////////////////////////////////////
//
// Transmit Logic
//
assign tx_data_le = tx_go & pclk_ris;
always @(posedge clk) if (we_i[1]) tx_hold_byte_h <= #1 din_i;
always @(posedge clk) if (we_i[0]) tx_hold_byte_l <= #1 din_i;
always @(posedge clk)
if (!rst) tx_go <= #1 1'b0;
else if (psync) tx_go <= #1 1'b1;
else if (tx_done) tx_go <= #1 1'b0;
always @(posedge clk)
if (!rst) tx_hold_reg <= #1 16'h0;
else if (psync) tx_hold_reg <= #1{tx_hold_byte_h, tx_hold_byte_l};
else if (tx_data_le) tx_hold_reg <= #1{tx_hold_reg[14:0], 1'b0};
assign pcm_dout_o = tx_hold_reg[15];
always @(posedge clk)
if (!rst) tx_cnt <= #1 4'h0;
else if (tx_data_le) tx_cnt <= tx_cnt + 4'h1;
assign tx_done = (tx_cnt == 4'hf) & tx_data_le;
///////////////////////////////////////////////////////////////////
//
// Recieve Logic
//
always @(posedge clk) if (pclk_ris) tx_go_r1 <= #1 tx_go;
always @(posedge clk) if (pclk_ris) tx_go_r2 <= #1 tx_go_r1;
// Receive is in sync with transmit ...
always @(posedge clk) if (pclk_fal) rxd_t <= #1 pcm_din_i;
always @(posedge clk) rxd <= #1 rxd_t;
assign rx_data_le = (tx_go_r1 | tx_go) & pclk_fal;
always @(posedge clk)
if (!rst) rx_hold_reg <= #1 16'h0;
else if (rx_data_le) rx_hold_reg <= #1{rx_hold_reg[14:0], rxd};
always @(posedge clk)
if (!rst) rx_reg <= #1 16'h0;
else if (tx_go_r1 & !tx_go & pclk_ris) rx_reg <= #1 rx_hold_reg;
assign dout_o = re_i ? rx_reg[15:8] : rx_reg[7:0];
endmodule
| 6.694229 |
module ss_rcvr #(
parameter WIDTH = 16
) (
input rxclk,
input sysclk,
input rst,
input [WIDTH-1:0] data_in,
output [WIDTH-1:0] data_out,
output reg clock_present
);
wire [3:0] rd_addr, wr_addr;
// Distributed RAM
reg [WIDTH-1:0] buffer[0:15];
always @(posedge rxclk) buffer[wr_addr] <= data_in;
assign data_out = buffer[rd_addr];
// Write address generation
reg [3:0] wr_counter;
always @(posedge rxclk or posedge rst)
if (rst) wr_counter <= 0;
else wr_counter <= wr_counter + 1;
assign wr_addr = {wr_counter[3], ^wr_counter[3:2], ^wr_counter[2:1], ^wr_counter[1:0]};
// Read Address generation
wire [3:0] wr_ctr_sys, diff, abs_diff;
reg [3:0] wr_addr_sys_d1, wr_addr_sys_d2;
reg [3:0] rd_counter;
assign rd_addr = {rd_counter[3], ^rd_counter[3:2], ^rd_counter[2:1], ^rd_counter[1:0]};
always @(posedge sysclk) wr_addr_sys_d1 <= wr_addr;
always @(posedge sysclk) wr_addr_sys_d2 <= wr_addr_sys_d1;
assign wr_ctr_sys = {
wr_addr_sys_d2[3], ^wr_addr_sys_d2[3:2], ^wr_addr_sys_d2[3:1], ^wr_addr_sys_d2[3:0]
};
assign diff = wr_ctr_sys - rd_counter;
assign abs_diff = diff[3] ? (~diff + 1) : diff;
always @(posedge sysclk)
if (rst) begin
clock_present <= 0;
rd_counter <= 0;
end else if (~clock_present)
if (abs_diff > 5) clock_present <= 1;
else;
else if (abs_diff < 3) clock_present <= 0;
else rd_counter <= rd_counter + 1;
endmodule
| 7.30315 |
module st4_mem ( // ´
input clk, // ʱ
input MEM_valid, // ´漶Чź
input [105:0] EXE_MEM_bus_r, //EXE->MEM
input [31:0] dm_rdata, // ´
output [31:0] dm_addr, // ´д
output reg [3:0] dm_wen, // ´дʹ
output reg [31:0] dm_wdata, // ´д
output MEM_over, // MEMģִ
output [69:0] MEM_WB_bus, // MEM->WB
// չʾpc
output [31:0] MEM_pc
);
// EXE->MEM begin
// ´Ҫõ load / store Ϣ
wire [3:0] mem_control; // MEMҪʹõĿź
wire [31:0] store_data; // storeĴ
// alu
wire [31:0] alu_result;
// дҪõϢ
wire rf_wen; // дصļĴдʹ
wire [4:0] rf_wdest; // дصĿļĴ
// pc
wire [31:0] pc;
assign {mem_control, store_data, alu_result, rf_wen, rf_wdest, pc} = EXE_MEM_bus_r;
// EXE->MEM end
// load / store ´ begin
wire inst_load; // load
wire inst_store; // store
wire Is_word; // load / store Ϊֽڻ 0: byte; 1: word
wire lb_sign; // loadһֽΪзload
assign {inst_load, inst_store, Is_word, lb_sign} = mem_control;
// ´дַ
assign dm_addr = alu_result;
// storeдʹ
always @(*) begin
if (MEM_valid && inst_store) begin //´漶Чʱ Ϊstore
if (Is_word) begin
dm_wen <= 4'b1111; // 洢ָ дʹȫ1
end else begin // SBָ Ҫݵַλ ȷӦдʹ
case (dm_addr[1:0])
2'b00: dm_wen <= 4'b0001;
2'b01: dm_wen <= 4'b0010;
2'b10: dm_wen <= 4'b0100;
2'b11: dm_wen <= 4'b1000;
default: dm_wen <= 4'b0000;
endcase
end
end else begin
dm_wen <= 4'b0000;
end
end
// storeд
always @(*) begin // SBָ Ҫݵַλ ƶstoreֽӦλ
case (dm_addr[1:0])
2'b00: dm_wdata <= store_data;
2'b01: dm_wdata <= {16'd0, store_data[7:0], 8'd0};
2'b10: dm_wdata <= {8'd0, store_data[7:0], 16'd0};
2'b11: dm_wdata <= {store_data[7:0], 24'd0};
default: dm_wdata <= store_data;
endcase
end
//load
wire load_sign;
wire [31:0] load_result;
assign load_sign = (dm_addr[1:0]==2'd0) ? dm_rdata[ 7] : (dm_addr[1:0]==2'd1) ? dm_rdata[15] : (dm_addr[1:0]==2'd2) ? dm_rdata[23] : dm_rdata[31] ;
assign load_result[7:0] = (dm_addr[1:0]==2'd0) ? dm_rdata[ 7:0 ] : (dm_addr[1:0]==2'd1) ? dm_rdata[15:8 ] : (dm_addr[1:0]==2'd2) ? dm_rdata[23:16] : dm_rdata[31:24] ;
assign load_result[31:8] = Is_word ? dm_rdata[31:8] : {24{lb_sign & load_sign}};
// load / store ´ end
// MEMִ begin
// data_ramΪͬд
// ʶloadָ
// ȡʱһʱ
// ַһʱӲܵõload
// memڽloadʱҪʱȡ
// ֻҪһʱ
reg MEM_valid_r;
always @(posedge clk) begin // ͬ
// always @(*) begin // 첽
MEM_valid_r <= MEM_valid;
end
assign MEM_over = inst_load ? MEM_valid_r : MEM_valid;
// data_ramΪ첽
// MEM_validMEM_overź
// loadһ
// MEMִ end
// MEM->WB begin
wire [31:0] mem_result; // MEMWBresultΪloadALU
assign mem_result = inst_load ? load_result : alu_result;
assign MEM_WB_bus = {
rf_wen,
rf_wdest, // WBҪʹõź
mem_result, // ҪдؼĴ
pc // pcֵ
};
// MEM->WB end
// display MEM_pc begin
assign MEM_pc = pc;
//display MEM_pc end
endmodule
| 6.928061 |
module sta (
input clk,
input reset,
output reg phy_mdc,
output phy_mdio_out,
output phy_mdio_tri,
input phy_mdio_in
);
// In general FALL_COUNT = 2*RISE_COUNT
parameter RISE_COUNT = 5;
parameter FALL_COUNT = 10;
reg mdc_rising, mdc_falling;
reg [7:0] mdc_counter;
always @(posedge clk)
if (reset | (mdc_counter == FALL_COUNT)) mdc_counter <= 1;
else mdc_counter <= mdc_counter + 1;
always @(posedge clk) begin
mdc_rising <= (mdc_counter == RISE_COUNT);
mdc_falling <= (mdc_counter == FALL_COUNT);
phy_mdc <= reset ? 0 : (mdc_rising ? 1 : (mdc_falling ? 0 : phy_mdc));
end
reg [1:0] state, state_nxt;
parameter IDLE = 0, START = 1, RUN = 2;
reg [31:0] cmd_reg, tri_ctrl;
always @(posedge clk or posedge reset) begin
if (reset) begin
cmd_reg <= 'h0;
tri_ctrl <= 'h0;
end else if ((state == RUN) && mdc_falling) begin
cmd_reg <= {cmd_reg[30:0], 1'b0};
tri_ctrl <= {tri_ctrl[30:0], 1'b0};
end
end
assign phy_mdio_out = cmd_reg[31];
assign phy_mdio_tri = tri_ctrl[31];
endmodule
| 7.400852 |
module PC #(
parameter Kw = 8,
parameter Km = 8,
parameter M = 8,
parameter W = 8
) (
clk,
rst,
addr,
wdata,
wen,
rdata
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value - 1;
for (log2 = 0; temp > 0; log2 = log2 + 1) temp = temp >> 1;
end
endfunction
localparam logM = log2(M);
localparam logW = log2(W);
localparam logKm = log2(Km);
localparam logKw = log2(Kw);
input clk, rst;
input [logM-1:0] addr;
input [logKm:0] wdata;
input wen;
output [logKm:0] rdata;
reg [logKm:0] pc[M-1:0]; // 2*nlogn + n = 15n
integer k;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (k = 0; k < M; k = k + 1) begin : always_line
pc[k] <= Km;
end
end else if (wen) begin
pc[addr] <= wdata;
end
end
assign rdata = pc[addr];
endmodule
| 7.441066 |
module MIsMatch #(
parameter Kw = 8,
parameter Km = 8,
parameter M = 8,
parameter W = 8
) (
clk,
rst,
waddr1,
wdata1,
wen1,
waddr2,
wdata2,
wen2,
raddr,
rdata
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value - 1;
for (log2 = 0; temp > 0; log2 = log2 + 1) temp = temp >> 1;
end
endfunction
localparam logM = log2(M);
localparam logW = log2(W);
localparam logKm = log2(Km);
localparam logKw = log2(Kw);
input clk, rst;
input [logM-1:0] waddr1;
input wdata1;
input wen1;
input [logM-1:0] waddr2;
input wdata2;
input wen2;
input [logM-1:0] raddr;
output rdata;
reg [M-1:0] mIsMatch; // 7n
integer k;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (k = 0; k < M; k = k + 1) begin : always_line
mIsMatch[k] <= 1'b0;
end
end else if (wen1) begin
mIsMatch[waddr1] <= wdata1;
end else if (wen2) begin
mIsMatch[waddr2] <= wdata2;
end
end
assign rdata = mIsMatch[raddr];
endmodule
| 6.509431 |
module WIsMatch #(
parameter Kw = 8,
parameter Km = 8,
parameter M = 8,
parameter W = 8
) (
clk,
rst,
addr,
wdata,
wen,
rdata
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value - 1;
for (log2 = 0; temp > 0; log2 = log2 + 1) temp = temp >> 1;
end
endfunction
localparam logM = log2(M);
localparam logW = log2(W);
localparam logKm = log2(Km);
localparam logKw = log2(Kw);
input clk, rst;
input [logW-1:0] addr;
input wdata;
input wen;
output rdata;
reg wIsMatch[W-1:0]; // 3n
integer k;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (k = 0; k < W; k = k + 1) begin : always_line
wIsMatch[k] <= 1'b0;
end
end else if (wen) begin
wIsMatch[addr] <= wdata;
end
end
assign rdata = wIsMatch[addr];
endmodule
| 6.832205 |
module stable_matching_comb_BMR //Kr = m, S = n/2
#(
parameter Ks = 12, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 16, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parameter logR = logS
) (
p_input,
o
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value - 1;
for (log2 = 0; temp > 0; log2 = log2 + 1) temp = temp >> 1;
end
endfunction
//------------------------------- Local Parameters
localparam logS = log2(S);
localparam logR = log2(R);
localparam N = (S == Ks) ? S * S - S + 2 : S * Ks; //number of iterations
input [R*Kr*logS-1 + S*Ks*logR-1 + 1:0] p_input;
output [R*logS-1:0] o;
stable_matching_comb #(
.Kr(Kr),
.Ks(Ks),
.S (S),
.R (R),
.N (N)
) stable_matching_comb_ (
.p_input(p_input),
.o(o)
);
endmodule
| 6.763333 |
module stable_matching_comb_BMR_2_4 #(
parameter Ks = 2, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 4, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parameter logR = logS
) (
input [R*Kr*logS-1 + S*Ks*logR-1 + 1:0] p_input,
output [R*logS-1:0] o
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value - 1;
for (log2 = 0; temp > 0; log2 = log2 + 1) temp = temp >> 1;
end
endfunction
//------------------------------- Local Parameters
localparam logS = log2(S);
localparam logR = log2(R);
localparam N = (S == Ks) ? S * S - S + 2 : S * Ks; //number of iterations
stable_matching_comb #(
.Kr(Kr),
.Ks(Ks),
.S (S),
.R (R),
.N (N)
) stable_matching_comb_ (
.p_input(p_input),
.o(o)
);
endmodule
| 6.763333 |
module stable_matching_comb_BMR_4_4 #(
parameter Ks = 4, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 4, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parameter logR = logS
) (
input [R*Kr*logS-1 + S*Ks*logR-1 + 1:0] p_input,
output [R*logS-1:0] o
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value - 1;
for (log2 = 0; temp > 0; log2 = log2 + 1) temp = temp >> 1;
end
endfunction
//------------------------------- Local Parameters
localparam logS = log2(S);
localparam logR = log2(R);
localparam N = (S == Ks) ? S * S - S + 2 : S * Ks; //number of iterations
stable_matching_comb #(
.Kr(Kr),
.Ks(Ks),
.S (S),
.R (R),
.N (N)
) stable_matching_comb_ (
.p_input(p_input),
.o(o)
);
endmodule
| 6.763333 |
module stable_matching_comb_BMR_3_6 #(
parameter Ks = 3, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 6, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parameter logR = logS
) (
input [R*Kr*logS-1 + S*Ks*logR-1 + 1:0] p_input,
output [R*logS-1:0] o
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value - 1;
for (log2 = 0; temp > 0; log2 = log2 + 1) temp = temp >> 1;
end
endfunction
//------------------------------- Local Parameters
localparam logS = log2(S);
localparam logR = log2(R);
localparam N = (S == Ks) ? S * S - S + 2 : S * Ks; //number of iterations
stable_matching_comb #(
.Kr(Kr),
.Ks(Ks),
.S (S),
.R (R),
.N (N)
) stable_matching_comb_ (
.p_input(p_input),
.o(o)
);
endmodule
| 6.763333 |
module stable_matching_comb_BMR_6_6 #(
parameter Ks = 6, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 6, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parameter logR = logS
) (
input [R*Kr*logS-1 + S*Ks*logR-1 + 1:0] p_input,
output [R*logS-1:0] o
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value - 1;
for (log2 = 0; temp > 0; log2 = log2 + 1) temp = temp >> 1;
end
endfunction
//------------------------------- Local Parameters
localparam logS = log2(S);
localparam logR = log2(R);
localparam N = (S == Ks) ? S * S - S + 2 : S * Ks; //number of iterations
stable_matching_comb #(
.Kr(Kr),
.Ks(Ks),
.S (S),
.R (R),
.N (N)
) stable_matching_comb_ (
.p_input(p_input),
.o(o)
);
endmodule
| 6.763333 |
module stable_matching_comb_BMR_4_8 #(
parameter Ks = 4, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 8, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parameter logR = logS
) (
input [R*Kr*logS-1 + S*Ks*logR-1 + 1:0] p_input,
output [R*logS-1:0] o
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value - 1;
for (log2 = 0; temp > 0; log2 = log2 + 1) temp = temp >> 1;
end
endfunction
//------------------------------- Local Parameters
localparam logS = log2(S);
localparam logR = log2(R);
localparam N = (S == Ks) ? S * S - S + 2 : S * Ks; //number of iterations
stable_matching_comb #(
.Kr(Kr),
.Ks(Ks),
.S (S),
.R (R),
.N (N)
) stable_matching_comb_ (
.p_input(p_input),
.o(o)
);
endmodule
| 6.763333 |
module stable_matching_comb_BMR_8_8 #(
parameter Ks = 8, //number of preferences for list A
parameter Kr = Ks, //number of preferences for list B
parameter S = 8, //number of members in list A
parameter R = S //number of members in list B
// parameter logS = 4,
// parameter logR = logS
) (
input [R*Kr*logS-1 + S*Ks*logR-1 + 1:0] p_input,
output [R*logS-1:0] o
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value - 1;
for (log2 = 0; temp > 0; log2 = log2 + 1) temp = temp >> 1;
end
endfunction
//------------------------------- Local Parameters
localparam logS = log2(S);
localparam logR = log2(R);
localparam N = (S == Ks) ? S * S - S + 2 : S * Ks; //number of iterations
stable_matching_comb #(
.Kr(Kr),
.Ks(Ks),
.S (S),
.R (R),
.N (N)
) stable_matching_comb_ (
.p_input(p_input),
.o(o)
);
endmodule
| 6.763333 |
module testBench;
parameter Kr = 4; //number of preferences for list B
parameter Ks = 4; //number of preferences for list A
parameter S = 4; //number of members in list A
parameter R = 4; //number of members in list B
parameter N = S * S - S + 2; //number of iterations
//------------------------------------------------------------------------------------------------------------------------------------- Functions
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value - 1;
for (log2 = 0; temp > 0; log2 = log2 + 1) temp = temp >> 1;
end
endfunction
//------------------------------------------------------------------------------------------------------------------------------------- Local Parameters
localparam logS = log2(S);
localparam logR = log2(R);
localparam logKs = log2(Ks);
localparam logKr = log2(Kr);
parameter stopTime =(S*S-S+1)*2 ;// *2 for converting to clk cycles each clk=#2 and the first term s^2 - s +1 is the worst case scenario
//------------------------------------------------------------------------------------------------------------------------------------- I/O
wire [R*logS-1:0] o;
reg [R*Kr*logS-1 + S*Ks*logR-1 + 1:0] g;
reg [logS-1:0] gMatrix[R*Kr-1 + S*Ks-1 +1:0];
integer op_out;
reg clk, rst;
wire [R*logS-1:0] matchListTB;
wire finish;
//wire [S-1:0] sIsMatchWire;
reg [logS-1:0] matchListMatrix[R-1:0];
initial begin
clk = 0;
op_out = $fopen("matchListVerilog.txt", "w");
//$readmemb("e.txt",eMatrix);
$readmemb("g.txt", gMatrix);
end
assign finish = o[R*logS];
assign matchListTB = o[R*logS-1:0];
//------------------------------------------------------------------------------------------------------------------------------------- Instantiate the Unit Under Test (UUT)
stable_matching_comb #(
.Kr(Kr),
.Ks(Ks),
.S (S),
.R (R) //,
//.N(N)
) uut (
g,
o
);
//------------------------------------------------------------------------------------------------------------------------------------- test bench
always #1 clk = ~clk;
initial begin
// clk=0;
// rst=1;
// #2;
// rst=0;
#stopTime;
$writememb("matchListVerilog.txt", matchListMatrix);
#N $stop;
end
/* always@(posedge clk) begin
if (|sIsMatchWire & ~rst) begin
$fwrite(op_out,"%b\n",matchListTB);
end
end */
//------------------------------------------------------------------------------------------------------------------------------------- Translating wires, changing matrix to array
genvar i, j;
// generate //creating final rPrefTB
// for (i=0;i<R*Kr+S*Ks;i=i+1)begin : e_asgn1
// always @(*) begin
// e [logS*(i+1) -1 : logS*i ] = eMatrix [i] ;
// end
// end
// endgenerate
generate // creating final sPrefTB
for (i = 0; i < R * Kr + S * Ks; i = i + 1) begin : g_asgn1
always @(*) begin
g[logS*(i+1)-1 : logS*i] = gMatrix[i];
end
end
endgenerate
generate //translating results
for (i = 0; i < R; i = i + 1) begin : matchList_asgn2
always @(*) begin
matchListMatrix[i] = matchListTB[logS*(i+1)-1 : logS*i];
end
end
endgenerate
endmodule
| 6.519976 |
module stack #(
parameter WIDTH = 8,
parameter DEPTH_LOG = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input stack_write_req,
input [WIDTH - 1:0] stack_write_data,
input stack_read_req,
output [WIDTH - 1:0] stack_read_data,
output stack_empty,
output stack_full
);
wire ram_write_req;
wire [DEPTH_LOG - 1:0] ram_addr;
wire [WIDTH - 1:0] ram_write_data;
stack_controller #(
.WIDTH (WIDTH),
.DEPTH_LOG(DEPTH_LOG)
) u_stack_control (
.clk (clk),
.rst_n (rst_n),
.stack_write_req (stack_write_req),
.stack_write_data(stack_write_data),
.stack_read_req (stack_read_req),
.stack_empty (stack_empty),
.stack_full (stack_full),
.ram_write_req (ram_write_req),
.ram_addr (ram_addr),
.ram_write_data (ram_write_data)
);
pkg_simple_ram #(
.RAM_WIDTH (WIDTH),
.RAM_DEPTH_LOG(DEPTH_LOG)
) u_stack_ram (
.clk (clk),
.write_req(ram_write_req),
.addr (ram_addr),
.data (ram_write_data),
.q (stack_read_data)
);
endmodule
| 7.074538 |
module reg_3 (
input wire clk,
reset,
load,
input wire [2:0] d,
output wire [2:0] q
);
dfrl dl[2:0] (
clk,
reset,
load,
d[2:0],
q[2:0]
);
endmodule
| 6.947963 |
module mux2_3 (
input wire op,
input wire [2:0] i0,
i1,
output wire [2:0] out
);
mux2 a0 (
i0[0],
i1[0],
op,
out[0]
);
mux2 a1 (
i0[1],
i1[1],
op,
out[1]
);
mux2 a2 (
i0[2],
i1[2],
op,
out[2]
);
endmodule
| 7.033659 |
module reg_3 (
input wire clk,
reset,
load,
input wire [2:0] d,
output wire [2:0] q
);
dfrl dl[2:0] (
clk,
reset,
load,
d[2:0],
q[2:0]
);
endmodule
| 6.947963 |
module mux2_3 (
input wire op,
input wire [2:0] i0,
i1,
output wire [2:0] out
);
mux2 a0 (
i0[0],
i1[0],
op,
out[0]
);
mux2 a1 (
i0[1],
i1[1],
op,
out[1]
);
mux2 a2 (
i0[2],
i1[2],
op,
out[2]
);
endmodule
| 7.033659 |
module mux4_3 (
input wire op2,
op1,
input wire [2:0] i0,
i1,
i2,
i3,
output wire [2:0] out
);
mux4 a0 (
{i0[0], i1[0], i2[0], i3[0]},
op2,
op1,
out[0]
);
mux4 a1 (
{i0[1], i1[1], i2[1], i3[1]},
op2,
op1,
out[1]
);
mux4 a2 (
{i0[2], i1[2], i2[2], i3[2]},
op2,
op1,
out[2]
);
endmodule
| 6.899192 |
module stackAdder_tb ();
parameter period = 10;
reg push_pop, stack_op, clk;
reg [31:0] in;
wire [31:0] out;
always #(period / 2) clk = ~clk;
stackAdder add (
clk,
stack_op,
push_pop,
in,
out
);
initial begin
clk = 0;
in = 3;
stack_op = 0;
push_pop = 1;
#(period * 2);
if (out == in) $display("no stack pass");
stack_op = 1;
push_pop = 1;
#(period * 2);
if (out == in - 1) $display("push stack pass");
stack_op = 1;
push_pop = 0;
#(period * 2);
if (out == in + 1) $display("pop stack pass");
$finish;
end
endmodule
| 6.762767 |
module
module DARMUX(OLDDAR,SPR,NEWDAR,DARsel);
input [6:0] SPR,OLDDAR;
input [2:0] DARsel;
output reg [6:0] NEWDAR;
always@(*)
begin
case(DARsel)
`SPR_DAR: NEWDAR<=SPR; //2
`DEC_DAR_DAR: NEWDAR<=OLDDAR-1;//1
`INC_DAR_DAR: NEWDAR<=OLDDAR+1;//0
`INC_SPR_DAR2: NEWDAR<= SPR+2;//3
`DAR_CLR: NEWDAR <= 0;//4
`INC_SPR_DAR1: NEWDAR <= SPR + 1;//4
default: NEWDAR<=0;
endcase
end
endmodule
| 7.020123 |
module DVRMUX (
dataIn,
arithOut,
DVRSel,
nextDVR
);
input [7:0] dataIn, arithOut;
input [1:0] DVRSel;
output reg [7:0] nextDVR;
always @(*) begin
case (DVRSel)
`BUS_DVR: nextDVR <= dataIn;
`ADD_DVR: nextDVR <= arithOut;
`DVR_CLR: nextDVR <= 0;
default: nextDVR <= 0;
endcase
end
endmodule
| 6.853209 |
module arithRegAdder (
arithReg1,
arithReg2,
arithAddSub,
arithOut
);
input [7:0] arithReg1;
input [7:0] arithReg2;
input arithAddSub;
output reg [7:0] arithOut;
always @(*) begin
case (arithAddSub)
`ADD: begin
arithOut = arithReg1 + arithReg2;
end
`SUB: begin
arithOut = arithReg1 - arithReg2;
end
endcase
end
endmodule
| 7.184829 |
module SPRMux (
oldSPR,
SPRsel,
newSPR
);
input [6:0] oldSPR;
input [1:0] SPRsel;
output reg [6:0] newSPR;
always @(*) begin
case (SPRsel)
0: newSPR <= 7'b1111111;
1: newSPR <= oldSPR + 1;
2: newSPR <= oldSPR - 1;
default: newSPR <= 0;
endcase
end
endmodule
| 6.585641 |
module DFF (
d,
clk,
out,
outN
);
input wire d, clk;
output wire out, outN;
reg qInternal;
always @(posedge clk) begin
qInternal <= d;
end
assign out = qInternal;
assign outN = ~qInternal;
endmodule
| 7.243009 |
module divider10Hz (
clk100MHz,
clk10Hz
);
input clk100MHz;
output clk10Hz;
reg [22:0] counter;
assign clk10Hz = counter[22]; // slightly over 40Hz
initial begin
counter = 0;
end
always @(posedge clk100MHz) begin
counter <= counter + 1;
end
endmodule
| 6.622063 |
module MIPSCntlr (
input [2:0] op,
input clk,
rst,
zero,
start,
output reg pcwrite,
IorD,
memwrite,
memread,
IRwrite,
memTostack,
push,
tos,
pop,
Awrite,
ALUsrcA,
pcsrc,
J,
r_or_not,
output reg [1:0] ALUsrcB,
output reg [1:0] aluop
);
parameter[3:0] IF = 4'b0000, ID = 4'b0001, JMP = 4'b0011, JZ = 4'b0100 ,POP = 4'b0101,
PUSH = 4'b0110, Rtype = 4'b0111, POP2 = 4'b1000, PUSH2 = 4'b1001, ADD = 4'b1010,
SUB = 4'b1011, AND = 4'b1100, PTOstack = 4'b1101, Rtype2 = 4'b1110;
reg [3:0] ps, ns;
reg jump;
assign J = zero & jump;
always @(ps, op, start) begin
ns = IF;
case (ps)
(IF): ns = ID;
(ID):
ns = (op[2] == 0) ? Rtype :
(op == 3'b100) ? PUSH:
(op == 3'b101) ? POP :
(op == 3'b110) ? JMP :
(op == 3'b111) ? JZ : 4'b0000;
(JMP): ns = IF;
(JZ): ns = IF;
(POP): ns = POP2;
(POP2): ns = IF;
(PUSH): ns = PUSH2;
(PUSH2): ns = IF;
(Rtype): ns = Rtype2;
(Rtype2):
ns = (op == 3'b000) ? ADD :
(op == 3'b001) ? SUB :
(op == 3'b010) ? AND :
(op == 3'b011) ? PTOstack : IF;//NOT
(ADD): ns = PTOstack;
(SUB): ns = PTOstack;
(AND): ns = PTOstack;
(PTOstack): ns = IF;
default: ns = IF;
endcase
end
always @(ps, op, start) begin
{pcwrite, IorD, memwrite, memread, IRwrite,
memTostack, push, tos, pop, Awrite, ALUsrcA, pcsrc, J, jump} = 0;
case (ps)
IF: begin // instruction fetch
pcwrite = 1'b1;
IorD = 1'b0;
IRwrite = 1'b1;
r_or_not = 1'b0; //new
ALUsrcA = 1'b0;
ALUsrcB = 2'b01;
aluop = 2'b00;
pcsrc = 1'b1;
jump = 1'b0;
memread = 1'b1; //new
end
//////////////////////////////////////////////
ID: begin //instruction decode
//memread <= 1'b1;//new
//Awrite = 1'b1;
ALUsrcB = 2'b10;
ALUsrcA = 1'b1;
tos = 1'b1; //new
end
//////////////////////////////////////////////
JMP: begin //jump
pcsrc = 1'b0;
jump = 1'b0;
end
//////////////////////////////////////////////
JZ: begin //jump
jump = 1'b1;
aluop = 2'b01;
end
//////////////////////////////////////////////
POP: begin // pop
pop = 1'b1;
end
//////////////////////////////////////////////
POP2: begin
IorD = 1'b1;
memwrite = 1'b1;
end
/////////////////////////////////////////////
PUSH: begin // push
IorD = 1'b1;
memread = 1'b1;
end
//////////////////////////////////////////////
PUSH2: begin
memTostack = 1'b0;
push = 1'b1;
end
//////////////////////////////////////////////
ADD: begin //Add
ALUsrcB = 2'b00;
ALUsrcA = 1'b1;
aluop = 2'b00;
end
//////////////////////////////////////////////
SUB: begin //sub
ALUsrcB = 2'b00;
ALUsrcA = 1'b1;
aluop = 2'b01;
end
//////////////////////////////////////////////
AND: begin //and
ALUsrcB = 2'b00;
ALUsrcA = 1'b1;
aluop = 2'b11;
end
//////////////////////////////////////////////
Rtype: begin // rtype and not
pop = 1'b1;
ALUsrcB = 2'b00;
ALUsrcA = 1'b1;
aluop = 2'b10;
Awrite = 1'b1;
end
//////////////////////////////////////////////
Rtype2: pop = 1'b1;
//////////////////////////////////////////////
PTOstack: begin //end rtype
memTostack = 1'b1;
push = 1'b1;
end
//////////////////////////////////////////////
endcase
end
always @(posedge clk, posedge rst) begin
if (rst) ps <= IF;
else ps <= ns;
end
endmodule
| 6.979126 |
module stacked_systolic_array_tb;
reg clk, ce;
reg [31:0] ctrl;
reg [3:0] mem_addr;
reg signed [39:0] x_ins;
wire signed [7:0] y_out;
integer i;
stacked_systolic_array dut (
clk,
ce,
ctrl,
mem_addr,
x_ins,
y_out
);
defparam dut.WIDTH = 8; defparam dut.ARRAY_COUNT = 3;
defparam dut.CELLS_PER_ARRAY_COUNT = 3; defparam dut.CELL_MEM_ADDR_WIDTH = 4;
defparam dut.CELL_ROM_BASENAME = "build/raw-mnist-weights-int8/conv2d/cell-weight-";
defparam dut.CELL_ROM_EXTENSION = ".mem";
initial begin
$dumpfile("./build/rtl-sim/vcd/stacked-systolic-array.vcd");
$dumpvars;
end
initial begin
clk = 0;
ce = 1;
x_ins = {8'd0, 8'd0, 8'd0, 8'd0, 8'd0};
;
ctrl = 0;
mem_addr = 0;
i = 0;
#100;
for (i = 0; i < 64; i = i + 1) begin
/*
0, 1, 4, 2, 2, 0, 0, 3
7, 0, 0, 2, 3, 3, 1, 2
4, 10, 0, 0, 0, 1, 1, 2
2, 5, 6, 6, 3, 6, 0, 0
11, 0, 1, 12, 10, 3, 6, 0
0, 10, 0, 1, 2, 11, 3, 0
4, 0, 2, 0, 1, 0, 2, 3
3, 4, 1, 1, 1, 4, 0, 2
*/
case (i)
32'd0: x_ins = {8'd11, 8'd2, 8'd4, 8'd7, 8'd0};
32'd1: x_ins = {8'd0, 8'd5, 8'd10, 8'd0, 8'd1};
32'd2: x_ins = {8'd1, 8'd6, 8'd0, 8'd0, 8'd4};
32'd3: x_ins = {8'd12, 8'd6, 8'd0, 8'd2, 8'd2};
32'd4: x_ins = {8'd10, 8'd3, 8'd0, 8'd3, 8'd2};
32'd5: x_ins = {8'd3, 8'd6, 8'd1, 8'd3, 8'd0};
32'd6: x_ins = {8'd6, 8'd0, 8'd1, 8'd1, 8'd0};
32'd7: x_ins = {8'd0, 8'd0, 8'd2, 8'd2, 8'd3};
32'd8: x_ins = {8'd0, 8'd11, 8'd2, 8'd4, 8'd7};
32'd9: x_ins = {8'd10, 8'd0, 8'd5, 8'd10, 8'd0};
32'd10: x_ins = {8'd0, 8'd1, 8'd6, 8'd0, 8'd0};
32'd11: x_ins = {8'd1, 8'd12, 8'd6, 8'd0, 8'd2};
32'd12: x_ins = {8'd2, 8'd10, 8'd3, 8'd0, 8'd3};
32'd13: x_ins = {8'd11, 8'd3, 8'd6, 8'd1, 8'd3};
32'd14: x_ins = {8'd3, 8'd6, 8'd0, 8'd1, 8'd1};
32'd15: x_ins = {8'd0, 8'd0, 8'd0, 8'd2, 8'd2};
32'd16: x_ins = {8'd4, 8'd0, 8'd11, 8'd2, 8'd4};
32'd17: x_ins = {8'd0, 8'd10, 8'd0, 8'd5, 8'd10};
32'd18: x_ins = {8'd2, 8'd0, 8'd1, 8'd6, 8'd0};
32'd19: x_ins = {8'd0, 8'd1, 8'd12, 8'd6, 8'd0};
32'd20: x_ins = {8'd1, 8'd2, 8'd10, 8'd3, 8'd0};
32'd21: x_ins = {8'd0, 8'd11, 8'd3, 8'd6, 8'd1};
32'd22: x_ins = {8'd2, 8'd3, 8'd6, 8'd0, 8'd1};
32'd23: x_ins = {8'd3, 8'd0, 8'd0, 8'd0, 8'd2};
32'd24: x_ins = {8'd3, 8'd4, 8'd0, 8'd11, 8'd2};
32'd25: x_ins = {8'd4, 8'd0, 8'd10, 8'd0, 8'd5};
32'd26: x_ins = {8'd1, 8'd2, 8'd0, 8'd1, 8'd6};
32'd27: x_ins = {8'd1, 8'd0, 8'd1, 8'd12, 8'd6};
32'd28: x_ins = {8'd1, 8'd1, 8'd2, 8'd10, 8'd3};
32'd29: x_ins = {8'd4, 8'd0, 8'd11, 8'd3, 8'd6};
32'd30: x_ins = {8'd0, 8'd2, 8'd3, 8'd6, 8'd0};
32'd31: x_ins = {8'd2, 8'd3, 8'd0, 8'd0, 8'd0};
default: x_ins = {8'd0, 8'd0, 8'd0, 8'd0, 8'd0};
endcase
clk = ~clk;
#100;
clk = ~clk;
#100;
end
end
endmodule
| 6.713899 |
module stacked_systolic_array (
clk,
ce,
ctrl,
mem_addr,
x_ins,
y_out
);
// Parameters
parameter WIDTH = 8;
parameter ARRAY_COUNT = 3;
parameter CELLS_PER_ARRAY_COUNT = 3;
parameter CELL_MEM_ADDR_WIDTH = 4;
parameter CELL_ROM_BASENAME = "weights/cell-weights-";
parameter CELL_ROM_EXTENSION = ".mem";
localparam X_INS_BUS_WIDTH = WIDTH * ARRAY_COUNT;
localparam Y_OUTS_BUS_WIDTH = X_INS_BUS_WIDTH;
localparam ADDER_TREE_BUS_COUNT = ARRAY_COUNT + (ARRAY_COUNT - 2);
// Port connections
input clk, ce;
input [31:0] ctrl;
input [CELL_MEM_ADDR_WIDTH-1:0] mem_addr;
input signed [X_INS_BUS_WIDTH-1:0] x_ins;
output signed [Y_OUTS_BUS_WIDTH-1:0] y_out;
// Internals
wire signed [WIDTH-1:0] x_ins_array[0:ARRAY_COUNT-1];
wire signed [WIDTH-1:0] systolic_array_y_outs[0:ARRAY_COUNT-1];
// Instantiate the systolic arrays and saturated adders for output adder tree
genvar gi;
generate
for (gi = 0; gi < ARRAY_COUNT; gi = gi + 1) begin
systolic_array systolic_array_inst (
clk,
ce,
ctrl,
mem_addr,
x_ins_array[gi]
, /* x_out not needed */,
systolic_array_y_outs[gi]
);
defparam systolic_array_inst.WIDTH = WIDTH; defparam systolic_array_inst.CELL_MEM_ADDR_WIDTH =
CELL_MEM_ADDR_WIDTH; defparam systolic_array_inst.CELL_COUNT = CELLS_PER_ARRAY_COUNT;
defparam systolic_array_inst.ARRAY_IDX = gi;
defparam systolic_array_inst.CELL_ROM_BASENAME = CELL_ROM_BASENAME;
defparam systolic_array_inst.CELL_ROM_EXTENSION = CELL_ROM_EXTENSION;
// Assign x_ins and y_outs
assign x_ins_array[gi] = x_ins[((gi+1)*WIDTH)-1:gi*WIDTH];
assign y_out[((gi+1)*WIDTH)-1:gi*WIDTH] = systolic_array_y_outs[gi];
end
endgenerate
endmodule
| 6.713899 |
module stacker (
clk,
reset,
go,
s_rate,
s_blocks,
column,
row
);
input clk;
input reset;
input go;
input [2:0] s_rate;
input [1:0] s_blocks;
output [7:0] column;
output [7:0] row;
wire [7:0] row_d_to_rc;
wire [7:0] lrow_c_to_d;
reg [7:0] lrow_main_to_c;
wire [3:0] rowd_c_to_rc;
wire [1:0] gstate_d_to_c;
wire [27:0] rd1hz, rd2hz, rd4hz, rd8hz, rd10hz, rd16hz, rd24hz, rd32hz, rddriver;
wire set_c_to_d;
reg en_rd_to_d;
wire display_clk;
wire driver_clk;
wire game_state;
wire [7:0] row0;
wire [7:0] row1;
wire [7:0] row2;
wire [7:0] row3;
wire [7:0] row4;
wire [7:0] row5;
wire [7:0] row6;
wire [7:0] row7;
wire shift;
wire [4:0] current_state, next_state;
wire [7:0] prev_row;
reg rate;
rate_divider rddriver0 (
.clk (clk),
.reset(reset),
.freq (27'd499),
.out (rddriver)
);
rate_divider rd0 (
.clk (clk),
.reset(reset),
.freq (27'd49999999),
.out (rd1hz)
);
rate_divider rd1 (
.clk (clk),
.reset(reset),
.freq (27'd24999999),
.out (rd2hz)
);
rate_divider rd2 (
.clk (clk),
.reset(reset),
.freq (27'd12499999),
.out (rd4hz)
);
rate_divider rd3 (
.clk (clk),
.reset(reset),
.freq (27'd6249999),
.out (rd8hz)
);
rate_divider rd4 (
.clk (clk),
.reset(reset),
.freq (27'd4999999),
.out (rd10hz)
);
rate_divider rd5 (
.clk (clk),
.reset(reset),
.freq (27'd3124999),
.out (rd16hz)
);
rate_divider rd6 (
.clk (clk),
.reset(reset),
.freq (27'd2083332),
.out (rd24hz)
);
rate_divider rd7 (
.clk (clk),
.reset(reset),
.freq (27'd1562499),
.out (rd32hz)
);
assign display_clk = (rd10hz == 0) ? 1 : 0;
assign driver_clk = (rddriver == 0) ? 1 : 0;
always @(*) begin //select rate
case (s_rate)
0: en_rd_to_d = (rd1hz == 0) ? 1 : 0;
1: en_rd_to_d = (rd2hz == 0) ? 1 : 0;
2: en_rd_to_d = (rd4hz == 0) ? 1 : 0;
3: en_rd_to_d = (rd8hz == 0) ? 1 : 0;
4: en_rd_to_d = (rd10hz == 0) ? 1 : 0;
5: en_rd_to_d = (rd16hz == 0) ? 1 : 0;
6: en_rd_to_d = (rd24hz == 0) ? 1 : 0;
7: en_rd_to_d = (rd32hz == 0) ? 1 : 0;
endcase
end
always @(*) begin //select blocks
case (s_blocks)
0: lrow_main_to_c = 8'b0000_0001;
1: lrow_main_to_c = 8'b0000_0011;
2: lrow_main_to_c = 8'b0000_0111;
3: lrow_main_to_c = 8'b0000_1111;
endcase
end
driver dr1 (
.row0(row0),
.row1(row1),
.row2(row2),
.row3(row3),
.row4(row4),
.row5(row5),
.row6(row6),
.row7(row7),
.clk(driver_clk),
.reset(reset),
.column_out(column),
.row_out(row)
);
row_controller r1 (
.clk(clk),
.reset(reset),
.display_clk(display_clk),
.row_in(row_d_to_rc),
.row_data_in(rowd_c_to_rc),
.game_state(game_state),
.row0(row0),
.row1(row1),
.row2(row2),
.row3(row3),
.row4(row4),
.row5(row5),
.row6(row6),
.row7(row7)
);
control c1 (
.clk(clk),
.reset(reset),
.go(go),
.s_blocks(lrow_main_to_c),
.set(set_c_to_d),
.row_data(rowd_c_to_rc),
.load_row(lrow_c_to_d)
);
datapath d1 (
.clk(clk),
.reset(reset),
.en(en_rd_to_d),
.set(set_c_to_d),
.row_in(lrow_c_to_d),
.row_out(row_d_to_rc),
);
endmodule
| 6.600209 |
module datapath (
clk,
reset,
en,
set,
row_in,
row_out
);
input clk; //from topmodule
input reset; //from topmodule
input en; //from topmodule
input set; //from control
input [7:0] row_in; //from control
output reg [7:0] row_out; //to row_controller
reg [7:0] prev_row;
reg shift; //0: left, 1: right
always @(posedge clk or negedge reset)
if (!reset) begin
row_out <= row_in;
shift <= 0;
end else if (set == 0) begin
if (en == 1)
case (shift) //shifting blocks or not
0: begin
if (row_out[7] == 1) begin
row_out <= row_out >> 1;
shift <= 1;
end else begin
row_out <= row_out << 1;
end
end
1: begin
if (row_out[0] == 1) begin
row_out <= row_out << 1;
shift <= 0;
end else begin
row_out <= row_out >> 1;
end
end
default: row_out <= row_in;
endcase
end else begin
row_out <= row_out & prev_row;
end
always @(posedge set or negedge reset)
if (!reset) begin
prev_row = 8'b1111_1111;
end else begin
prev_row <= row_out & prev_row;
end
endmodule
| 6.91752 |
module rate_divider (
clk,
reset,
freq,
out
);
input clk;
input reset;
input [27:0] freq;
output reg [27:0] out;
always @(posedge clk, negedge reset) begin
if (!reset) out = freq;
else begin
if (out == 1'b0) out <= freq;
else out <= out - 1'b1;
end
end
endmodule
| 7.346866 |
module stack_controller #(
parameter DEPTH_LOG = 4,
parameter WIDTH = 8
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input stack_write_req,
input [WIDTH - 1:0] stack_write_data,
input stack_read_req,
output reg stack_empty,
output stack_full,
output reg ram_write_req,
output reg [DEPTH_LOG - 1:0] ram_addr,
output reg [WIDTH - 1:0] ram_write_data
);
reg [DEPTH_LOG:0] stack_point;
wire is_full = (stack_point == 2 ** DEPTH_LOG) ? 1'b1 : 1'b0;
wire is_empty = (stack_point == 'b0) ? 1'b1 : 1'b0;
always @(posedge clk or negedge rst_n) begin //control point of stack
if (~rst_n) begin
stack_point <= 'b0;
end else if (stack_write_req && stack_read_req) begin //lock
stack_point <= stack_point;
end else if (stack_write_req && !is_full) begin //write when stack is not full
stack_point <= stack_point + 1'b1;
end else if (stack_read_req && !is_empty) begin // read when stack is not empty
stack_point <= stack_point - 1'b1;
end
end
assign stack_full = stack_point[DEPTH_LOG];
always @(posedge clk or negedge rst_n) begin //generate empty signal
if (~rst_n) begin
stack_empty <= 'b0;
end else if (ram_addr == 'b0 && is_empty) begin // delay signal
stack_empty <= 1'b1;
end else begin
stack_empty <= 'b0;
end
end
always @(posedge clk or negedge rst_n) begin //generate ram_write_req
if (~rst_n) begin
ram_write_req <= 'b0;
end else if (!is_full) begin
ram_write_req <= stack_write_req;
end else begin
ram_write_req <= 'b0;
end
end
always @(posedge clk or negedge rst_n) begin //prepare the addr and data for push
if (~rst_n) begin
ram_addr <= 'b0;
ram_write_data <= stack_write_data;
end else begin
ram_addr <= stack_point[DEPTH_LOG-1:0];
ram_write_data <= stack_write_data;
end
end
endmodule
| 7.595483 |
module STACK_MEMORY #(
parameter DATA_WIDTH_MEM = 8,
parameter ADDR_WIDTH_MEM = 12
) (
input [(DATA_WIDTH_MEM-1):0] DATA_IN,
input [(ADDR_WIDTH_MEM-1):0] ADDR_IN,
input CTRL_MEM_WRITE,
clk_mem,
output wire [(DATA_WIDTH_MEM-1):0] DATA_OUT
);
// Declare the RAM variable
reg [DATA_WIDTH_MEM-1:0] ram[2**ADDR_WIDTH_MEM-1:0];
// Variable to hold the registered read ADDR_INess
reg [ADDR_WIDTH_MEM-1:0] ADDR_IN_reg;
always @(posedge clk_mem) begin
// Write
if (CTRL_MEM_WRITE) ram[ADDR_IN] <= DATA_IN;
ADDR_IN_reg <= ADDR_IN;
end
// Continuous assignment implies read returns NEW DATA_IN.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign DATA_OUT = ram[ADDR_IN_reg];
endmodule
| 7.683349 |
module stack_tb;
reg clk;
reg [7:0] r0;
reg [1:0] rw;
wire [7:0] address;
stack st1 (
.clk(clk),
.r0(r0),
.rw(rw),
.address(address)
);
localparam period = 10;
always begin
#5 clk = 1'b1;
#5 clk = 1'b0;
end
initial begin
$dumpfile("stack1.vcd");
$dumpvars(1, stack_tb);
$monitor("address -> %h , rw -> %b , r0 -> %h", address, rw, r0);
#period rw <= 2'b00;
#period rw <= 2'b00;
#period rw <= 2'b01;
#period rw <= 2'b00;
#period rw <= 2'b01;
#period rw <= 2'b00;
#period rw <= 2'b10;
#period rw <= 2'b00;
#period r0 <= 8'hfa;
rw <= 2'b00;
#period
//en <= 0;
rw <= 2'b11;
#period rw <= 2'b10;
#period r0 <= 8'hef;
rw <= 2'b00;
#period rw <= 2'b11;
#period rw <= 2'b01;
#period rw <= 2'b10;
#period rw <= 2'b00;
#period rw <= 2'b10;
#period rw <= 2'b00;
end
endmodule
| 7.388626 |
module stack_test (
input wire clk,
reset,
input wire btnL,
btnR,
input wire [2:0] sw,
output wire [7:0] led
);
// signal declaration
wire db_btn[1:0];
// debounce circuits
debounce db_unit0 (
.clk(clk),
.reset(reset),
.sw(btnR),
.db_level(),
.db_tick(db_btn[0])
);
debounce db_unit1 (
.clk(clk),
.reset(reset),
.sw(btnL),
.db_level(),
.db_tick(db_btn[1])
);
// instanciate a 2^2-by-3 stack
stack #(
.B(3),
.W(2)
) stack_unit (
.clk(clk),
.reset(reset),
.push(db_btn[0]),
.pop(db_btn[1]),
.w_data(sw),
.r_data(led[2:0]),
.full(led[7]),
.empty(led[6])
);
// disable unused leds
assign led[5:3] = 3'b000;
endmodule
| 7.413295 |
module stage0 (
input wire clk,
input wire rst,
input wire branch_mispredict,
output wire inst_rd_en,
output wire PC_en,
input wire next_rdy,
output wire vld
);
//If next stage is ready, we can read an instruction
//However, if the branch_mispredict signal is asserted, it means PC is being
//changed on this cycle, and we should wait
assign inst_rd_en = next_rdy && !branch_mispredict;
//We should increment PC if we read an instruction, or if we need to jump
assign PC_en = inst_rd_en || branch_mispredict;
reg vld_r = 0;
always @(posedge clk) begin
if (rst || branch_mispredict) vld_r <= 0;
else if (inst_rd_en) vld_r <= 1;
else if (next_rdy) vld_r <= 0;
end
assign vld = vld_r;
endmodule
| 6.706914 |
module stage0_point_5 (
input wire clk,
input wire rst,
input wire [7:0] instr_in,
output wire [7:0] instr_out,
//counts how many cycles instruction has been in pipeline
input wire PC_en,
input wire [5:0] icount,
output wire [5:0] ocount,
input wire branch_mispredict,
input wire prev_vld,
output wire rdy,
input wire next_rdy,
output wire vld
);
bhand_cycle_count #(
.DATA_WIDTH (8),
.ENABLE_COUNT(1),
.COUNT_WIDTH (6)
) delay_stage (
.clk(clk),
.rst(rst || branch_mispredict),
.idata(instr_in),
.idata_vld(prev_vld),
.idata_rdy(rdy),
.odata(instr_out),
.odata_vld(vld),
.odata_rdy(next_rdy),
.cnt_en(PC_en),
.icount(icount),
.ocount(ocount)
);
endmodule
| 6.857962 |
module Stage1Ctrl (
NewIR,
IR_Stage1,
nop,
jal,
jump,
jmpIsn
);
input [31:0] NewIR, IR_Stage1;
output nop, jump, jal;
output [31:0] jmpIsn;
assign nop = (!IR_Stage1[31] && IR_Stage1[30] && !IR_Stage1[29] && !IR_Stage1[28] && !IR_Stage1[27]) && ((IR_Stage1[26:22] == NewIR[21:17]));
assign jump = (!IR_Stage1[31] && !IR_Stage1[30] && !IR_Stage1[29] && !IR_Stage1[28] && IR_Stage1[27]);
assign jal = (!IR_Stage1[31] && !IR_Stage1[30] && !IR_Stage1[29] && IR_Stage1[28] && IR_Stage1[27]);
assign jmpIsn[31:27] = 5'b00000;
assign jmpIsn[26:0] = IR_Stage1[26:0];
endmodule
| 7.088187 |
module weight_buffer_18_9_42_1_2688Wcxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_1_2688Wcxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_1_2688Woxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_1_2688Woxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_1_2688Wfxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_1_2688Wfxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_1_2688Wixr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_1_2688Wixr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_0 <= index + addrs_base_0;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
endmodule
| 6.6283 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 6.876859 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.034248 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data;
end else begin
out <= ram[addr];
end
end
endmodule
| 8.023817 |
module weight_buffer_18_9_42_2_2688Wcxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162; defparam ram_inst_1.ADDR_WIDTH = 12;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_2_2688Wcxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162; defparam ram_inst_1.ADDR_WIDTH = 12;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_2_2688Woxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162; defparam ram_inst_1.ADDR_WIDTH = 12;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_2_2688Woxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162; defparam ram_inst_1.ADDR_WIDTH = 12;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_2_2688Wfxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162; defparam ram_inst_1.ADDR_WIDTH = 12;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_2_2688Wfxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162; defparam ram_inst_1.ADDR_WIDTH = 12;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_2_2688Wixr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162; defparam ram_inst_1.ADDR_WIDTH = 12;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_2_2688Wixr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
end
wire rom_we;
assign rom_we = 1'b0;
defparam ram_inst_0.DATA_WIDTH = 162; defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162; defparam ram_inst_1.ADDR_WIDTH = 12;
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
endmodule
| 6.6283 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 6.876859 |
module counter_63_2 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 2) <= 63) begin
count <= count + 2;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.360162 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data;
end else begin
out <= ram[addr];
end
end
endmodule
| 8.023817 |
module weight_buffer_18_9_42_3_2688Wcxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_2_0,
output [17:0] q_2_1,
output [17:0] q_2_2,
output [17:0] q_2_3,
output [17:0] q_2_4,
output [17:0] q_2_5,
output [17:0] q_2_6,
output [17:0] q_2_7,
output [17:0] q_2_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
wire [161:0] packed_result_2;
reg [ 11:0] addrs_2;
reg [ 11:0] addrs_base_2;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_base_2 <= 84;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
addrs_2 <= index + addrs_base_2;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162;
defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162;
defparam ram_inst_1.ADDR_WIDTH = 12;
defparam ram_inst_2.DATA_WIDTH = 162;
defparam ram_inst_2.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
single_port_ram ram_inst_2 (
.we (rom_we),
.addr(addrs_2),
.data(162'd0),
.out (packed_result_2),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_2_0 = packed_result_2[17:0];
assign q_2_1 = packed_result_2[35:18];
assign q_2_2 = packed_result_2[53:36];
assign q_2_3 = packed_result_2[71:54];
assign q_2_4 = packed_result_2[89:72];
assign q_2_5 = packed_result_2[107:90];
assign q_2_6 = packed_result_2[125:108];
assign q_2_7 = packed_result_2[143:126];
assign q_2_8 = packed_result_2[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_3_2688Wcxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_2_0,
output [17:0] q_2_1,
output [17:0] q_2_2,
output [17:0] q_2_3,
output [17:0] q_2_4,
output [17:0] q_2_5,
output [17:0] q_2_6,
output [17:0] q_2_7,
output [17:0] q_2_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
wire [161:0] packed_result_2;
reg [ 11:0] addrs_2;
reg [ 11:0] addrs_base_2;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_base_2 <= 84;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
addrs_2 <= index + addrs_base_2;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162;
defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162;
defparam ram_inst_1.ADDR_WIDTH = 12;
defparam ram_inst_2.DATA_WIDTH = 162;
defparam ram_inst_2.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
single_port_ram ram_inst_2 (
.we (rom_we),
.addr(addrs_2),
.data(162'd0),
.out (packed_result_2),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_2_0 = packed_result_2[17:0];
assign q_2_1 = packed_result_2[35:18];
assign q_2_2 = packed_result_2[53:36];
assign q_2_3 = packed_result_2[71:54];
assign q_2_4 = packed_result_2[89:72];
assign q_2_5 = packed_result_2[107:90];
assign q_2_6 = packed_result_2[125:108];
assign q_2_7 = packed_result_2[143:126];
assign q_2_8 = packed_result_2[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_3_2688Woxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_2_0,
output [17:0] q_2_1,
output [17:0] q_2_2,
output [17:0] q_2_3,
output [17:0] q_2_4,
output [17:0] q_2_5,
output [17:0] q_2_6,
output [17:0] q_2_7,
output [17:0] q_2_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
wire [161:0] packed_result_2;
reg [ 11:0] addrs_2;
reg [ 11:0] addrs_base_2;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_base_2 <= 84;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
addrs_2 <= index + addrs_base_2;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162;
defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162;
defparam ram_inst_1.ADDR_WIDTH = 12;
defparam ram_inst_2.DATA_WIDTH = 162;
defparam ram_inst_2.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
single_port_ram ram_inst_2 (
.we (rom_we),
.addr(addrs_2),
.data(162'd0),
.out (packed_result_2),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_2_0 = packed_result_2[17:0];
assign q_2_1 = packed_result_2[35:18];
assign q_2_2 = packed_result_2[53:36];
assign q_2_3 = packed_result_2[71:54];
assign q_2_4 = packed_result_2[89:72];
assign q_2_5 = packed_result_2[107:90];
assign q_2_6 = packed_result_2[125:108];
assign q_2_7 = packed_result_2[143:126];
assign q_2_8 = packed_result_2[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_3_2688Woxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_2_0,
output [17:0] q_2_1,
output [17:0] q_2_2,
output [17:0] q_2_3,
output [17:0] q_2_4,
output [17:0] q_2_5,
output [17:0] q_2_6,
output [17:0] q_2_7,
output [17:0] q_2_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
wire [161:0] packed_result_2;
reg [ 11:0] addrs_2;
reg [ 11:0] addrs_base_2;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_base_2 <= 84;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
addrs_2 <= index + addrs_base_2;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162;
defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162;
defparam ram_inst_1.ADDR_WIDTH = 12;
defparam ram_inst_2.DATA_WIDTH = 162;
defparam ram_inst_2.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
single_port_ram ram_inst_2 (
.we (rom_we),
.addr(addrs_2),
.data(162'd0),
.out (packed_result_2),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_2_0 = packed_result_2[17:0];
assign q_2_1 = packed_result_2[35:18];
assign q_2_2 = packed_result_2[53:36];
assign q_2_3 = packed_result_2[71:54];
assign q_2_4 = packed_result_2[89:72];
assign q_2_5 = packed_result_2[107:90];
assign q_2_6 = packed_result_2[125:108];
assign q_2_7 = packed_result_2[143:126];
assign q_2_8 = packed_result_2[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_3_2688Wfxr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_2_0,
output [17:0] q_2_1,
output [17:0] q_2_2,
output [17:0] q_2_3,
output [17:0] q_2_4,
output [17:0] q_2_5,
output [17:0] q_2_6,
output [17:0] q_2_7,
output [17:0] q_2_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
wire [161:0] packed_result_2;
reg [ 11:0] addrs_2;
reg [ 11:0] addrs_base_2;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_base_2 <= 84;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
addrs_2 <= index + addrs_base_2;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162;
defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162;
defparam ram_inst_1.ADDR_WIDTH = 12;
defparam ram_inst_2.DATA_WIDTH = 162;
defparam ram_inst_2.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
single_port_ram ram_inst_2 (
.we (rom_we),
.addr(addrs_2),
.data(162'd0),
.out (packed_result_2),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_2_0 = packed_result_2[17:0];
assign q_2_1 = packed_result_2[35:18];
assign q_2_2 = packed_result_2[53:36];
assign q_2_3 = packed_result_2[71:54];
assign q_2_4 = packed_result_2[89:72];
assign q_2_5 = packed_result_2[107:90];
assign q_2_6 = packed_result_2[125:108];
assign q_2_7 = packed_result_2[143:126];
assign q_2_8 = packed_result_2[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_3_2688Wfxr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_2_0,
output [17:0] q_2_1,
output [17:0] q_2_2,
output [17:0] q_2_3,
output [17:0] q_2_4,
output [17:0] q_2_5,
output [17:0] q_2_6,
output [17:0] q_2_7,
output [17:0] q_2_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
wire [161:0] packed_result_2;
reg [ 11:0] addrs_2;
reg [ 11:0] addrs_base_2;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_base_2 <= 84;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
addrs_2 <= index + addrs_base_2;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162;
defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162;
defparam ram_inst_1.ADDR_WIDTH = 12;
defparam ram_inst_2.DATA_WIDTH = 162;
defparam ram_inst_2.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
single_port_ram ram_inst_2 (
.we (rom_we),
.addr(addrs_2),
.data(162'd0),
.out (packed_result_2),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_2_0 = packed_result_2[17:0];
assign q_2_1 = packed_result_2[35:18];
assign q_2_2 = packed_result_2[53:36];
assign q_2_3 = packed_result_2[71:54];
assign q_2_4 = packed_result_2[89:72];
assign q_2_5 = packed_result_2[107:90];
assign q_2_6 = packed_result_2[125:108];
assign q_2_7 = packed_result_2[143:126];
assign q_2_8 = packed_result_2[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_3_2688Wixr_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_2_0,
output [17:0] q_2_1,
output [17:0] q_2_2,
output [17:0] q_2_3,
output [17:0] q_2_4,
output [17:0] q_2_5,
output [17:0] q_2_6,
output [17:0] q_2_7,
output [17:0] q_2_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
wire [161:0] packed_result_2;
reg [ 11:0] addrs_2;
reg [ 11:0] addrs_base_2;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_base_2 <= 84;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
addrs_2 <= index + addrs_base_2;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162;
defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162;
defparam ram_inst_1.ADDR_WIDTH = 12;
defparam ram_inst_2.DATA_WIDTH = 162;
defparam ram_inst_2.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
single_port_ram ram_inst_2 (
.we (rom_we),
.addr(addrs_2),
.data(162'd0),
.out (packed_result_2),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_2_0 = packed_result_2[17:0];
assign q_2_1 = packed_result_2[35:18];
assign q_2_2 = packed_result_2[53:36];
assign q_2_3 = packed_result_2[71:54];
assign q_2_4 = packed_result_2[89:72];
assign q_2_5 = packed_result_2[107:90];
assign q_2_6 = packed_result_2[125:108];
assign q_2_7 = packed_result_2[143:126];
assign q_2_8 = packed_result_2[161:144];
endmodule
| 6.6283 |
module weight_buffer_18_9_42_3_2688Wixr_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
output [17:0] q_1_1,
output [17:0] q_1_2,
output [17:0] q_1_3,
output [17:0] q_1_4,
output [17:0] q_1_5,
output [17:0] q_1_6,
output [17:0] q_1_7,
output [17:0] q_1_8,
output [17:0] q_2_0,
output [17:0] q_2_1,
output [17:0] q_2_2,
output [17:0] q_2_3,
output [17:0] q_2_4,
output [17:0] q_2_5,
output [17:0] q_2_6,
output [17:0] q_2_7,
output [17:0] q_2_8,
input [11:0] index
);
wire [161:0] packed_result_0;
reg [ 11:0] addrs_0;
reg [ 11:0] addrs_base_0;
wire [161:0] packed_result_1;
reg [ 11:0] addrs_1;
reg [ 11:0] addrs_base_1;
wire [161:0] packed_result_2;
reg [ 11:0] addrs_2;
reg [ 11:0] addrs_base_2;
always @(posedge clk) begin
addrs_base_0 <= 0;
addrs_base_1 <= 42;
addrs_base_2 <= 84;
addrs_0 <= index + addrs_base_0;
addrs_1 <= index + addrs_base_1;
addrs_2 <= index + addrs_base_2;
end
wire rom_we;
assign rom_we = 1'b0;
`ifdef SIMULATION_MEMORY
defparam ram_inst_0.DATA_WIDTH = 162;
defparam ram_inst_0.ADDR_WIDTH = 12;
defparam ram_inst_1.DATA_WIDTH = 162;
defparam ram_inst_1.ADDR_WIDTH = 12;
defparam ram_inst_2.DATA_WIDTH = 162;
defparam ram_inst_2.ADDR_WIDTH = 12;
`endif
single_port_ram ram_inst_0 (
.we (rom_we),
.addr(addrs_0),
.data(162'd0),
.out (packed_result_0),
.clk (clk)
);
single_port_ram ram_inst_1 (
.we (rom_we),
.addr(addrs_1),
.data(162'd0),
.out (packed_result_1),
.clk (clk)
);
single_port_ram ram_inst_2 (
.we (rom_we),
.addr(addrs_2),
.data(162'd0),
.out (packed_result_2),
.clk (clk)
);
// Unpack result
assign q_0_0 = packed_result_0[17:0];
assign q_0_1 = packed_result_0[35:18];
assign q_0_2 = packed_result_0[53:36];
assign q_0_3 = packed_result_0[71:54];
assign q_0_4 = packed_result_0[89:72];
assign q_0_5 = packed_result_0[107:90];
assign q_0_6 = packed_result_0[125:108];
assign q_0_7 = packed_result_0[143:126];
assign q_0_8 = packed_result_0[161:144];
assign q_1_0 = packed_result_1[17:0];
assign q_1_1 = packed_result_1[35:18];
assign q_1_2 = packed_result_1[53:36];
assign q_1_3 = packed_result_1[71:54];
assign q_1_4 = packed_result_1[89:72];
assign q_1_5 = packed_result_1[107:90];
assign q_1_6 = packed_result_1[125:108];
assign q_1_7 = packed_result_1[143:126];
assign q_1_8 = packed_result_1[161:144];
assign q_2_0 = packed_result_2[17:0];
assign q_2_1 = packed_result_2[35:18];
assign q_2_2 = packed_result_2[53:36];
assign q_2_3 = packed_result_2[71:54];
assign q_2_4 = packed_result_2[89:72];
assign q_2_5 = packed_result_2[107:90];
assign q_2_6 = packed_result_2[125:108];
assign q_2_7 = packed_result_2[143:126];
assign q_2_8 = packed_result_2[161:144];
endmodule
| 6.6283 |
module counter_41_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 41) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 6.876859 |
module counter_63_3 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 3) <= 63) begin
count <= count + 3;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.231427 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data;
end else begin
out <= ram[addr];
end
end
endmodule
| 8.023817 |
module STAGE1_tb;
integer i, j, f;
reg clk, rst_n, valid, stop;
reg [10:0] before_ff [0:31];
reg [10:0] data_in_r;
wire [13:0] data_out_i, data_out_r;
wire finish;
STAGE1 test (
.clk(clk),
.rst_n(rst_n),
.valid_i(valid),
.data_in_r(data_in_r),
.data_in_i(10'd0),
.valid_o(finish),
.data_out_r(data_out_r),
.data_out_i(data_out_i)
);
initial begin
$readmemb("input_11bit_1.txt", before_ff);
f = $fopen("stage1_o.txt", "w");
end
initial begin
clk = 1'b1;
rst_n = 1'b1;
valid = 1'b0;
stop = 1'b0;
i = 0;
j = 0;
#2.5 rst_n = 1'b0;
#2.5 rst_n = 1'b1;
end
always begin
#(`CYCLE / 2) clk = ~clk;
end
initial begin
$dumpfile("stage1");
$dumpvars;
end
always @(negedge clk) begin
if (i < 32) begin
valid = 1;
data_in_r = before_ff[i];
i = i + 1;
end else if (i < 49) begin
data_in_r = 0;
i = i + 1;
end else begin
data_in_r = 0;
stop = 1;
end
end
always @(negedge clk) begin
if (finish) begin
$fwrite(f, "%b_%b\n", data_out_r, data_out_i);
$display("Output %0d: Real->%b / Img->%b", j, data_out_r, data_out_i);
j = j + 1;
end
end
always @(posedge stop) begin
$fclose(f);
$finish;
end
// always @(posedge clk)begin
// if(dataout !== out_temp && out_temp!==16'h0000) begin
// $display("ERROR at %d:output %h !=expect %h ",pattern_num-2, dataout, out_temp);
// $fdisplay(out_f,"ERROR at %d:output %h !=expect %h ",pattern_num-2, dataout, out_temp);
// err = err + 1 ;
// end
// pattern_num = pattern_num + 1;
// if(pattern_num === OUT_LENGTH) over = 1'b1;
// end
// initial begin
// @(posedge stop)
// if(over) begin
// $display("---------------------------------------------\n");
// if (err == 0) begin
// $display("All data have been generated successfully!\n");
// $display("You will get 80 score in this RTL!\n");
// $display("-------------------PASS-------------------\n");
// end
// else begin
// $display("There are %d errors!\n", err);
// $display("You will get %d score in this RTL!\n", 80-err);
// end
// $display("---------------------------------------------\n");
// end
// else begin
// $display("---------------------------------------------\n");
// $display("Error!!! There is no any data output ...!\n");
// $display("-------------------FAIL-------------------\n");
// $display("---------------------------------------------\n");
// end
// $finish;
// end
endmodule
| 6.94027 |
module stage1_top #(
parameter XLEN_PIXEL = 8,
parameter NUM_OF_PIXELS = 784,
parameter NUM_OF_SV = 87,
parameter DECISION_FUNCT_SIZE = 56
) (
input clk,
rst,
en,
output y_class
);
wire re, we, stall_MEM, decision_funct_en;
// Variables we are storing in BRAM
//wire [XLEN_PIXEL-1:0] sv_load1, sv_load2;
// Instantiate control module
mem_control mem_control_inst (
.clk(clk),
.rst(rst),
.en(en),
.re(re),
.we(we),
.stall_MEM(stall_MEM),
.x_test(x_test),
.decision_funct_en(decision_funct_en)
);
// Load support vectors from RAM
reg [NUM_OF_PIXELS*XLEN_PIXEL-1:0] support_vectors[NUM_OF_SV-1:0];
reg [4*XLEN_PIXEL-1:0] kernel_out_arr[NUM_OF_SV-1:0];
reg [16:0] support_vectors_counter;
integer i, j;
initial begin
$readmemb(
"E:/CURRICULUM/ECE Core/8th sem/FYP/Vivado files/FYP_SVM_on_FPGA/FYP_SVM_on_FPGA.srcs/support_vect_bin_edited.data",
support_vectors, 0, 86);
support_vectors_counter = 17'b0_00000000_00000000;
//for(i=0;i<NUM_OF_SV-1;i=i+1) begin
// $display("support_vectors=%b",support_vectors[i]);
//end
end
//Instantiating kernel modules for each support vector
genvar c;
generate
for (c = 0; c < NUM_OF_SV; c = c + 1) begin
dot_prod dspslice1 (
.clk(clk),
.rst(rst),
.stall_MEM(stall_MEM),
.x_test(x_test),
.x_sv(support_vectors[c]),
.mac_out(kernel_out[(c*5*XLEN_PIXEL)+:5*XLEN_PIXEL])
); //kernel_out_arr[c]));//
end
endgenerate
//Main register containing output from all kernel modules
wire [((5*XLEN_PIXEL*NUM_OF_SV)-1):0] kernel_out;
//-------------------------------Decision Function Module---------------------------------
reg [XLEN_PIXEL-1:0] product_load;
wire [XLEN_PIXEL-1:0] product_out;
reg [(2*XLEN_PIXEL)-1:0] b = 16'b10000000_00000001;
reg [(2*XLEN_PIXEL)-1:0] product_arr[NUM_OF_SV-1:0];
reg [(2*XLEN_PIXEL)-1:0] product;
integer row_count;
//Product values
always @(posedge clk) begin
if (row_count < NUM_OF_SV && decision_funct_en) begin
product = product_arr[row_count];
row_count = row_count + 1;
//$display("product=%d row_count=%d", product, row_count);
end
end
initial begin
$readmemb(
"E:/CURRICULUM/ECE Core/8th sem/FYP/Vivado files/FYP_SVM_on_FPGA/FYP_SVM_on_FPGA.srcs/product_bin.data",
product_arr, 0, 86);
row_count = 0;
end
//RAM_fetch product_fetch(.clk(clk), .re(re), .we(re), .stall_MEM(!decision_funct_en), .data_load(product_load), .data_out(product_out));
decision_funct decision_funct_module (
.clk(clk),
.kernel_out(kernel_out),
.decision_funct_en(decision_funct_en),
.product(product),
.b(b),
.decision_funct_out(decision_funct_out),
.y_class(y_class)
);
endmodule
| 7.560058 |
module stage1_top_hwf #(
parameter XLEN_PIXEL = 8,
parameter NUM_OF_PIXELS = 784,
parameter NUM_OF_SV = 10,
parameter DECISION_FUNCT_SIZE = 24
) (
input clk,
rst,
en,
output y_class
);
wire re, we, stall_MEM, decision_funct_en;
wire [XLEN_PIXEL-1:0] x_test;
// Instantiate control module
mem_control_hwf mem_control_inst (
.clk(clk),
.rst(rst),
.en(en),
.re(re),
.we(we),
.stall_MEM(stall_MEM),
.x_test(x_test),
.decision_funct_en(decision_funct_en)
);
// -------Hardware Friendly Kernel----------------------------------------
//Load alpha_values for HWF
reg [2*XLEN_PIXEL-1:0] alpha_values[NUM_OF_SV-1:0];
reg [2*XLEN_PIXEL-1:0] Bi; //Bi for HWF compuation
//reg [6:0] alpha_values_counter;
initial begin
$readmemb(
"E:/CURRICULUM/ECE Core/8th sem/FYP/Vivado files/FYP_SVM_on_FPGA/FYP_SVM_on_FPGA.srcs/alpha_hwf_bin.data",
alpha_values, 0, 9);
//alpha_values_counter=7'b0000000;
end
/*always @(posedge clk) begin
Bi <= alpha_values[alpha_values_counter];
alpha_values_counter = alpha_values_counter + 1;
if(alpha_values_counter == 7'b1010110) begin
alpha_values_counter=7'b0000000;
end
$display("TOP HERE - Bi = %d",alpha_values[alpha_values_counter]);
end */
// Load support vectors from RAM
reg [NUM_OF_PIXELS*XLEN_PIXEL-1:0] support_vectors[NUM_OF_SV-1:0];
reg [16:0] support_vectors_counter;
initial begin
$readmemb(
"E:/CURRICULUM/ECE Core/8th sem/FYP/Vivado files/FYP_SVM_on_FPGA/FYP_SVM_on_FPGA.srcs/support_vect_bin_hwf_edited.data",
support_vectors, 0, 9);
support_vectors_counter = 17'b0_00000000_00000000;
end
genvar c;
genvar i;
generate
for (c = 0; c < NUM_OF_SV; c = c + 1) begin
for (i = 0; i < NUM_OF_PIXELS; i = i + 1) begin
hwf_kernel hwf_kernel_inst1 (
.clk(clk),
.rst(rst),
.stall_MEM(stall_MEM),
.Bi(alpha_values[c]),
.x_test(x_test),
.x_sv(support_vectors[c]),
.hwf_out(hwf_kernel_out[(c*2*XLEN_PIXEL)+:2*XLEN_PIXEL]),
.c(c)
);
end
end
endgenerate
//Instantiating HWF Kernel modules
//Shifting values across registers
wire [(2*XLEN_PIXEL*NUM_OF_SV)-1:0] hwf_kernel_out;
always @(posedge clk) begin //or posedge rst && en) begin
//$display("Kernel big reg out = %d", hwf_kernel_out);
//$display("x_sv=%d", support_vectors[7]);
end
//-------------------------------Decision Function Module---------------------------------
reg [XLEN_PIXEL-1:0] product_load;
wire [XLEN_PIXEL-1:0] product_out;
reg [(2*XLEN_PIXEL)-1:0] b = 16'b10000000_00000001;
reg [(2*XLEN_PIXEL)-1:0] product_arr[NUM_OF_SV-1:0];
reg [(2*XLEN_PIXEL)-1:0] product;
integer row_count;
//Product values for testing
initial begin
$readmemb(
"E:/CURRICULUM/ECE Core/8th sem/FYP/Vivado files/FYP_SVM_on_FPGA/FYP_SVM_on_FPGA.srcs/alpha_bin.data",
product_arr, 0, 9);
row_count = 0;
end
//Product values
always @(posedge clk) begin
if (row_count < NUM_OF_SV && decision_funct_en) begin
product = product_arr[row_count];
row_count = row_count + 1;
//$display("product=%d row_count=%d", product, row_count);
end
end
//RAM_fetch product_fetch(.clk(clk), .re(re), .we(re), .stall_MEM(!decision_funct_en), .data_load(product_load), .data_out(product_out));
decision_funct_hwf decision_funct_module (
.clk(clk),
.kernel_out(hwf_kernel_out),
.decision_funct_en(decision_funct_en),
.product(product),
.b(b),
.y_class(y_class)
);
endmodule
| 7.275562 |
module stage1_top_tb #(
parameter XLEN_PIXEL = 8,
parameter NUM_OF_PIXELS = 4,
parameter NUM_OF_SV = 10
);
reg clk, rst, en;
wire y_class;
stage1_top_hwf uut (
.clk(clk),
.rst(rst),
.en(en),
.y_class(y_class)
);
initial begin
rst = 0;
#5 rst = 1;
clk = 0;
en = 0;
#10 rst = 0;
en = 1;
//$readmemb("alpha_bin.txt", alpha_values);
end
always #5 clk = ~clk;
endmodule
| 6.541323 |
module Stage2Ctrl (
IR_Stage1,
isSW,
jr,
bexIsn
);
input [31:0] IR_Stage1;
output [31:0] bexIsn;
output isSW, jr;
assign isSW = (!IR_Stage1[31] && !IR_Stage1[30] && IR_Stage1[29] && IR_Stage1[28] && IR_Stage1[27]) || (!IR_Stage1[31] && !IR_Stage1[30] && !IR_Stage1[29] && IR_Stage1[28] && !IR_Stage1[27]) || (!IR_Stage1[31] && !IR_Stage1[30] && IR_Stage1[29] && IR_Stage1[28] && !IR_Stage1[27]);
assign jr = !IR_Stage1[31] && !IR_Stage1[30] && IR_Stage1[29] && !IR_Stage1[28] && !IR_Stage1[27];
assign bexIsn[31:27] = 5'b00000;
assign bexIsn[26:0] = IR_Stage1[26:0];
endmodule
| 7.225913 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.034248 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.034248 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.034248 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module shift_register_unit_12 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else if (enable) begin
shift_registers_0 <= in;
shift_registers_1 <= shift_registers_0;
end
end
assign out = shift_registers_1;
endmodule
| 6.854847 |
module counter_30_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 30) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 6.816296 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
end
end
endmodule
| 7.034248 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module shift_register_unit_12 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else if (enable) begin
shift_registers_0 <= in;
shift_registers_1 <= shift_registers_0;
end
end
assign out = shift_registers_1;
endmodule
| 6.854847 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.