code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module \$safe_pmux (
A,
B,
S,
Y
);
parameter WIDTH = 1;
parameter S_WIDTH = 1;
input [WIDTH-1:0] A;
input [WIDTH*S_WIDTH-1:0] B;
input [S_WIDTH-1:0] S;
output [WIDTH-1:0] Y;
wire [S_WIDTH-1:0] status_found_first;
wire [S_WIDTH-1:0] status_found_second;
genvar i;
generate
for (i = 0; i < S_WIDTH; i = i + 1) begin : GEN1
wire pre_first;
if (i > 0) begin : GEN2
assign pre_first = status_found_first[i-1];
end : GEN2
else begin : GEN3
assign pre_first = 0;
end : GEN3
assign status_found_first[i] = pre_first | S[i];
assign status_found_second[i] = pre_first & S[i];
end : GEN1
endgenerate
\$pmux #(
.WIDTH (WIDTH),
.S_WIDTH(S_WIDTH)
) pmux_cell (
.A(A),
.B(B),
.S(S & {S_WIDTH{~|status_found_second}}),
.Y(Y)
);
endmodule
| 6.711891 |
module stdio (
input wire [7:0] addr,
input wire clk,
input wire reset,
input wire read_write,
input wire enable,
input wire [31:0] data_in,
output reg [31:0] data_out,
output reg exit = 0
);
integer err;
parameter STDIN = 32'h8000_0000;
parameter STDOUT = 32'h8000_0001;
parameter STDERR = 32'h8000_0002;
always @(posedge clk) begin
if (reset) begin
data_out <= 0;
exit <= 1'b0;
end else if (enable) begin
if (read_write) begin
case (addr)
`IO_CHAR: data_out = $fgetc(STDIN);
`IO_INT: err = $fscanf(STDIN, "%d", data_out);
`IO_FLOAT: err = $fscanf(STDIN, "%f", data_out);
`IO_HEX: err = $fscanf(STDIN, "%x", data_out);
`IO_EXIT: $finish;
default: `WARN(("[IO] Unknown operation"))
endcase
end else begin
case (addr)
`IO_CHAR: $fwrite(STDERR, "%0c", data_in);
`IO_INT: $fwrite(STDERR, "%0d", data_in);
`IO_FLOAT: $fwrite(STDERR, "%0f", data_in);
`IO_HEX: $fwrite(STDERR, "%0x", data_in);
`IO_EXIT: exit <= 1'b1;
default: `WARN(("[IO] Unknown operation"))
endcase
$fflush(STDERR);
end
end
end
endmodule
| 7.369583 |
module normClkGenerator (
clk_in,
reset_n,
clk_out
);
// parameter [31:1] param_05Second = 32'h00FBC520; //33MHz0.5b
// parameter [31:0] param_05Second = 32'h00000100;
parameter [31:0] param_05Second = 32'h00FBC520;
input clk_in;
input reset_n;
output clk_out;
reg [31:0] interreg;
reg clk_out;
always @(posedge clk_in or negedge reset_n) begin
if (~reset_n) begin
interreg <= 32'h00000000;
clk_out <= 1'b0;
end else if (interreg == param_05Second) begin
interreg <= 32'h00000000;
clk_out <= ~clk_out;
end else interreg <= interreg + 1;
end
endmodule
| 6.693178 |
module main; //: root_module
reg [15:0] A_NET; //: {0}(#:80,174)(145,174)(145,174)(213,174){1}
//: {2}(1:217,174)(271,174){3}
//: {4}(#:215,176)(215,352)(268,352){5}
reg [3:0] OP_NET; //: {0}(#:80,416)(91,416)(91,416)(109,416){1}
//: {2}(-18:113,416)(268,416){3}
//: {4}(111,414)(111,238)(271,238){5}
reg w0; //: /sn:0 {0}(59,380)(105,380)(105,380)(149,380){1}
//: {2}(151,378)(151,222)(271,222){3}
//: {4}(151,382)(151,400)(268,400){5}
reg w3; //: /sn:0 {0}(59,323)(111,323)(111,323)(163,323){1}
//: {2}(165,321)(165,206)(271,206){3}
//: {4}(165,325)(165,384)(268,384){5}
reg [15:0] B_NET; //: {0}(#:80,228)(103,228)(64:103,190)(178,190){1}
//: {2}(182,190)(271,190){3}
//: {4}(#:180,192)(180,368)(268,368){5}
wire [15:0] pulse; //: /sn:0 {0}(#:514,190)(415,190){1}
wire [15:0] propagation; //: /sn:0 {0}(#:514,368)(466,368){1}
wire w11; //: /sn:0 {0}(479,325)(479,352)(466,352){1}
wire w5; //: /sn:0 {0}(415,174)(479,174)(479,148){1}
//: enddecls
//: SWITCH M (w0) @(42,380) /w:[ 0 ] /st:0 /dn:1
//: joint g4 (A_NET) @(215, 174) /w:[ 2 -1 1 4 ]
//: joint g8 (w0) @(151, 380) /w:[ -1 2 1 4 ]
//: comment back_link @(11,11) /sn:0 /anc:1
//: /line:"<a href=\"../index.v\">[НАЗАД]</a>"
//: /end
//: LED g1 (w5) @(479,141) /sn:0 /w:[ 1 ] /type:0
//: DIP B_DIP (B_NET) @(42,228) /R:1 /w:[ 0 ] /st:10818 /dn:1
//: DIP OP_DIP (OP_NET) @(42,416) /R:1 /w:[ 0 ] /st:2 /dn:1
//: LED g11 (propagation) @(521,368) /sn:0 /R:3 /w:[ 0 ] /type:2
//: LED g10 (w11) @(479,318) /sn:0 /w:[ 0 ] /type:0
ALU16_74181 ALU_OSC (
.A (A_NET),
.B (B_NET),
.CI(w3),
.M (w0),
.S (OP_NET),
.CO(w5),
.F (pulse)
); //: @(272, 158) /sz:(142, 96) /sn:0 /p:[ Li0>3 Li1>3 Li2>3 Li3>3 Li4>5 Ro0<0 Ro1<1 ]
//: LED g6 (pulse) @(521,190) /sn:0 /R:3 /w:[ 0 ] /type:2
//: joint g7 (w3) @(165, 323) /w:[ -1 2 1 4 ]
//: joint g9 (OP_NET) @(111, 416) /w:[ 2 4 1 -1 ]
//: comment REF_ARITH @(230,7) /sn:0 /anc:1
//: /line:"Арифметичні (M=0)"
//: /line:"<b>A</b>"
//: /line:"<b>A</b> АБО <b>B</b>"
//: /line:"<b>A</b> АБО НІ <b>B</b>"
//: /line:"(<b>A</b> АБО <b>B</b>)+(<b>A</b> АБО НІ <b>B</b>)"
//: /line:"<b>A</b> - <b>B</b> - 1"
//: /line:"<b>A</b> + <b>B</b>"
//: /line:"<b>A</b> І <b>B</b> - 1"
//: /line:"<b>A</b> АБО <b>B</b>"
//: /end
//: SWITCH CI (w3) @(42,323) /w:[ 0 ] /st:1 /dn:1
//: joint g5 (B_NET) @(180, 190) /w:[ 2 -1 1 4 ]
//: comment REF_LOGIC @(90,7) /sn:0 /anc:1
//: /line:"Logical (M=1)"
//: /line:"00 - NOT <b>A</b>"
//: /line:"01 - <b>A</b> NOR <b>B</b>"
//: /line:"02 - NOT <b>A</b> AND <b>B</b>"
//: /line:"05 - NOT <b>B</b>"
//: /line:"06 - <b>A</b> XOR <b>B</b>"
//: /line:"09 - <b>A</b> XNOR <b>B</b>"
//: /line:"0B - <b>A</b> AND <b>B</b>"
//: /line:"0E - <b>A</b> OR <b>B</b>"
//: /end
//: DIP A_DIP (A_NET) @(42,174) /R:1 /w:[ 0 ] /st:28555 /dn:1
ALU16_74181_74182 ALU_PROP (
.A (A_NET),
.B (B_NET),
.CI(w3),
.M (w0),
.OP(OP_NET),
.CO(w11),
.F (propagation)
); //: @(269, 336) /sz:(196, 96) /sn:0 /p:[ Li0>5 Li1>5 Li2>5 Li3>5 Li4>3 Ro0<1 Ro1<1 ]
endmodule
| 6.5859 |
module std_2s60_reset_clk_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else if (1) data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (1) data_out <= data_in_d1;
end
endmodule
| 7.428197 |
module ext_flash_lane0_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [23:0] rdaddress;
input rdclken;
input [23:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [16777215:0];
wire [ 7:0] q;
reg [23:0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress) begin
if (1) read_address <= rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial $readmemh("ext_flash.dat", mem_array);
always @(posedge wrclock) begin
// Write data
if (wren) mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// if (1)
// read_address <= rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "ext_flash.mif",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 8,
// lpm_ram_dp_component.lpm_widthad = 24,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.952907 |
module ext_flash (
// inputs:
address,
read_n,
select_n,
write_n,
// outputs:
data
);
inout [7:0] data;
input [23:0] address;
input read_n;
input select_n;
input write_n;
wire [7:0] data;
wire [7:0] data_0;
wire [7:0] logic_vector_gasket;
wire [7:0] q_0;
//s1, which is an e_ptf_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign logic_vector_gasket = data;
assign data_0 = logic_vector_gasket[7 : 0];
//ext_flash_lane0, which is an e_ram
ext_flash_lane0_module ext_flash_lane0 (
.data (data_0),
.q (q_0),
.rdaddress(address),
.rdclken (1'b1),
.wraddress(address),
.wrclock (write_n),
.wren (~select_n)
);
assign data = (~select_n & ~read_n) ? q_0 : {8{1'bz}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 6.719908 |
module ext_ram_lane0_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [17:0] rdaddress;
input rdclken;
input [17:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [262143:0];
wire [ 7:0] q;
reg [17:0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress) begin
if (1) read_address <= rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial $readmemh("ext_ram_lane0.dat", mem_array);
always @(posedge wrclock) begin
// Write data
if (wren) mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// if (1)
// read_address <= rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "ext_ram_lane0.mif",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 8,
// lpm_ram_dp_component.lpm_widthad = 18,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.982298 |
module ext_ram_lane1_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [17:0] rdaddress;
input rdclken;
input [17:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [262143:0];
wire [ 7:0] q;
reg [17:0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress) begin
if (1) read_address <= rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial $readmemh("ext_ram_lane1.dat", mem_array);
always @(posedge wrclock) begin
// Write data
if (wren) mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// if (1)
// read_address <= rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "ext_ram_lane1.mif",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 8,
// lpm_ram_dp_component.lpm_widthad = 18,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.716371 |
module ext_ram_lane2_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [17:0] rdaddress;
input rdclken;
input [17:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [262143:0];
wire [ 7:0] q;
reg [17:0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress) begin
if (1) read_address <= rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial $readmemh("ext_ram_lane2.dat", mem_array);
always @(posedge wrclock) begin
// Write data
if (wren) mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// if (1)
// read_address <= rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "ext_ram_lane2.mif",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 8,
// lpm_ram_dp_component.lpm_widthad = 18,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.946152 |
module ext_ram_lane3_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [17:0] rdaddress;
input rdclken;
input [17:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [262143:0];
wire [ 7:0] q;
reg [17:0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress) begin
if (1) read_address <= rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial $readmemh("ext_ram_lane3.dat", mem_array);
always @(posedge wrclock) begin
// Write data
if (wren) mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// if (1)
// read_address <= rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "ext_ram_lane3.mif",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 8,
// lpm_ram_dp_component.lpm_widthad = 18,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.668691 |
module ext_ram (
// inputs:
address,
be_n,
read_n,
select_n,
write_n,
// outputs:
data
);
inout [31:0] data;
input [17:0] address;
input [3:0] be_n;
input read_n;
input select_n;
input write_n;
wire [31:0] data;
wire [ 7:0] data_0;
wire [ 7:0] data_1;
wire [ 7:0] data_2;
wire [ 7:0] data_3;
wire [31:0] logic_vector_gasket;
wire [ 7:0] q_0;
wire [ 7:0] q_1;
wire [ 7:0] q_2;
wire [ 7:0] q_3;
//s1, which is an e_ptf_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign logic_vector_gasket = data;
assign data_0 = logic_vector_gasket[7 : 0];
//ext_ram_lane0, which is an e_ram
ext_ram_lane0_module ext_ram_lane0 (
.data (data_0),
.q (q_0),
.rdaddress(address),
.rdclken (1'b1),
.wraddress(address),
.wrclock (write_n),
.wren (~select_n & ~be_n[0])
);
assign data_1 = logic_vector_gasket[15 : 8];
//ext_ram_lane1, which is an e_ram
ext_ram_lane1_module ext_ram_lane1 (
.data (data_1),
.q (q_1),
.rdaddress(address),
.rdclken (1'b1),
.wraddress(address),
.wrclock (write_n),
.wren (~select_n & ~be_n[1])
);
assign data_2 = logic_vector_gasket[23 : 16];
//ext_ram_lane2, which is an e_ram
ext_ram_lane2_module ext_ram_lane2 (
.data (data_2),
.q (q_2),
.rdaddress(address),
.rdclken (1'b1),
.wraddress(address),
.wrclock (write_n),
.wren (~select_n & ~be_n[2])
);
assign data_3 = logic_vector_gasket[31 : 24];
//ext_ram_lane3, which is an e_ram
ext_ram_lane3_module ext_ram_lane3 (
.data (data_3),
.q (q_3),
.rdaddress(address),
.rdclken (1'b1),
.wraddress(address),
.wrclock (write_n),
.wren (~select_n & ~be_n[3])
);
assign data = (~select_n & ~read_n) ? {q_3, q_2, q_1, q_0} : {32{1'bz}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 6.990033 |
module inv ( /*AUTOARG*/
// Outputs
zn,
// Inputs
i
);
parameter DELAY = 1;
input i;
output zn;
assign #DELAY zn = !i;
endmodule
| 6.837475 |
module buff ( /*AUTOARG*/
// Outputs
z,
// Inputs
i
);
parameter DELAY = 1;
input i;
output z;
assign #DELAY z = i;
endmodule
| 6.920533 |
module and2 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b
);
parameter DELAY = 1;
input a, b;
output z;
assign #DELAY z = a & b;
endmodule
| 6.958302 |
module nand2 ( /*AUTOARG*/
// Outputs
zn,
// Inputs
a,
b
);
parameter DELAY = 1;
input a, b;
output zn;
assign #DELAY zn = !(a & b);
endmodule
| 7.655066 |
module and3 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b,
c
);
parameter DELAY = 1;
input a, b, c;
output z;
assign #DELAY z = a & b & c;
endmodule
| 6.663943 |
module nand3 ( /*AUTOARG*/
// Outputs
zn,
// Inputs
a,
b,
c
);
parameter DELAY = 1;
input a, b, c;
output zn;
assign #DELAY zn = !(a & b & c);
endmodule
| 7.167416 |
module nand4 ( /*AUTOARG*/
// Outputs
zn,
// Inputs
a,
b,
c,
d
);
parameter DELAY = 1;
input a, b, c, d;
output zn;
assign #DELAY zn = !(a & b & c & d);
endmodule
| 7.740076 |
module or2 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b
);
parameter DELAY = 1;
input a, b;
output z;
assign #DELAY z = a | b;
endmodule
| 6.979061 |
module xor2 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b
);
parameter DELAY = 1;
input a, b;
output z;
assign #DELAY z = a ^ b;
endmodule
| 7.190934 |
module mux2 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a0,
a1,
s
);
input a0;
input a1;
input s;
output z;
parameter DELAY = 1;
assign #DELAY z = s ? a1 : a0;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
endmodule
| 6.72973 |
module latch ( /*AUTOARG*/
// Outputs
q,
// Inputs
en,
i,
rstn
);
input en;
input i;
input rstn;
output q;
reg q;
always @* begin
if (rstn == 1'b0) q <= 0;
else if (en) q <= i;
end
endmodule
| 6.776901 |
module std_dffe #(
parameter WIDTH = 8
) (
input clk,
input en,
input [WIDTH-1:0] d,
output [WIDTH-1:0] q
);
reg [WIDTH-1:0] dff_q;
always @(posedge clk) begin
if (en | ~en) begin
dff_q <= d;
end
end
assign q = en ? dff_q : '0;
endmodule
| 7.805632 |
module std_dffr #(
parameter WIDTH = 8
) (
input clk,
input rstn,
input [WIDTH-1:0] d,
output [WIDTH-1:0] q
);
reg [WIDTH-1:0] dff_q;
always @(posedge clk) begin
if (rstn) begin
dff_q <= {WIDTH{1'b0}};
end else begin
dff_q <= d;
end
end
assign q = dff_q;
endmodule
| 7.584522 |
module std_dffre (
clk,
rstn,
en,
d,
q
);
parameter WIDTH = 8;
input clk;
input rstn;
input en;
input [WIDTH - 1:0] d;
output wire [WIDTH - 1:0] q;
reg [WIDTH - 1:0] dff_q;
always @(posedge clk or negedge rstn)
if (~rstn) dff_q <= {WIDTH{1'b0}};
else if (en) dff_q <= d;
assign q = dff_q;
endmodule
| 7.78136 |
module std_dffrve (
clk,
rstn,
rst_val,
en,
d,
q
);
parameter WIDTH = 8;
input clk;
input rstn;
input [WIDTH - 1:0] rst_val;
input en;
input [WIDTH - 1:0] d;
output wire [WIDTH - 1:0] q;
reg [WIDTH - 1:0] dff_q;
always @(posedge clk or negedge rstn)
if (~rstn) dff_q <= rst_val;
else if (en) dff_q <= d;
assign q = dff_q;
endmodule
| 8.134307 |
module std_fifo_tb;
reg rst, clk;
reg push, pop;
reg [7:0] d;
wire [7:0] q;
wire full, empty;
wire [3:0] count;
wire almost_empty;
wire almost_full;
std_fifo #(8, 16) dut (
rst,
clk,
push,
pop,
d,
q,
full,
empty,
count,
almost_empty,
almost_full
);
integer i;
initial begin
$display("starting testbench");
rst = 1;
push = 0;
pop = 0;
d = 0;
#101 rst = 0;
$display("time: %d", $time);
#10
if (empty != 1) begin
$display("test1:failed");
end else begin
$display("test1:passed");
end
#10 push <= 1;
d <= 1;
if (empty == 0) $display("test2:failed");
if (full == 1) $display("test2:failed full high");
for (i = 2; i < 64; i = i + 1) begin
#10 push <= 1;
d <= i;
if (empty == 1) begin
$display("test3:failed empty high, round %d", i);
end
if (full == 1) $display("test3:failed full high");
end
#10 push <= 1;
d <= 64;
if (empty == 1) $display("error");
if (full == 1) $display("error");
#10
if (full == 1) $display("test4:passed");
else $display("test4:error");
push <= 0;
pop <= 1;
for (i = 1; i < 65; i = i + 1) begin
#10
if (q != i) begin
$display("ERROR:");
end
end
pop <= 0;
#10
if (empty != 1) $display("ERROR:");
else $display("test5:passed");
if (full != 0) $display("ERROR:");
#100 $finish;
//TODO: check empty
end
initial begin
clk = 1;
forever #5 clk = ~clk;
end
initial $monitor("At time %t, value ", $time);
endmodule
| 6.582685 |
module not(o,i1);
input i1;
output o;
assign o = ~i1;
endmodule
| 7.490638 |
module and(o,i1,i2);
input i1, i2;
output o;
assign o = i1 & i2;
endmodule
| 7.615987 |
module or(o,i1,i2);
input i1, i2;
output o;
assign o = i1 | i2;
endmodule
| 7.703227 |
module xor(o,i1,i2);
input i1, i2;
output o;
assign o = i1 ^ i2;
endmodule
| 7.914568 |
module nor(o,i1,i2);
input i1, i2;
output o;
wire tem1;
assign tem1 = i1 | i2;
assign o = ~tem1;
endmodule
| 7.543454 |
module nand(o,i1,i2);
input i1, i2;
output o;
wire tem1;
assign tem1 = i1 & i2;
assign o = ~tem1;
endmodule
| 7.556739 |
module xnor(o,i1,i2);
input i1, i2;
output o;
wire tem1;
assign tem1 = i1 ^ i2;
assign o = ~tem1;
endmodule
| 7.175695 |
module and3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
wire tem1;
assign tem1 = i1 & i2;
assign o = tem1 & i3;
endmodule
| 6.783095 |
module and4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
wire tem1;
wire tem2;
assign tem1 = i1 & i2;
assign tem2 = tem1 & i3;
assign o = tem2 & i4;
endmodule
| 7.000535 |
module and5 (
o,
i1,
i2,
i3,
i4,
i5
);
input i1, i2, i3, i4, i5;
output o;
wire tem1;
wire tem2;
assign tem1 = i1 & i2;
assign tem2 = tem1 & i3;
assign tem3 = tem2 & i4;
assign o = tem3 & i5;
endmodule
| 6.560006 |
module or3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
wire tem1;
assign tem1 = i1 | i2;
assign o = tem1 | i3;
endmodule
| 7.109001 |
module or4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
wire tem1;
wire tem2;
assign tem1 = i1 | i2;
assign tem2 = tem1 | i3;
assign o = tem2 | i4;
endmodule
| 7.141237 |
module xor3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
wire tem1;
assign tem1 = i1 ^ i2;
assign o = tem1 ^ i3;
endmodule
| 7.092493 |
module nor3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
wire tem1;
wire tem2;
assign tem1 = i1 | i2;
assign tem2 = tem1 | i3;
assign o = ~tem2;
endmodule
| 6.982417 |
module nor4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
wire tem1;
wire tem2;
wire tem3;
assign tem1 = i1 | i2;
assign tem2 = tem1 | i3;
assign tem3 = tem2 | i4;
assign o = ~tem3;
endmodule
| 7.058914 |
module nand3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
wire tem1;
wire tem2;
assign tem1 = i1 & i2;
assign tem2 = tem1 & i3;
assign o = ~tem2;
endmodule
| 7.061822 |
module nand4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
wire tem1;
wire tem2;
wire tem3;
assign tem1 = i1 & i2;
assign tem2 = tem1 & i3;
assign tem3 = tem2 & i4;
assign o = ~tem3;
endmodule
| 6.994556 |
module xnor3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
wire tem1, tem2;
assign tem1 = i1 ^ i2;
assign tem2 = tem1 ^ i2;
assign o = ~tem2;
endmodule
| 6.696172 |
module dffrsb_udp5 (
o,
i1,
i2,
i3,
i4,
i5
);
input i1, i2, i3, i4, i5;
output o;
assign o = i1;
endmodule
| 6.884559 |
module dlhrb_udp4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
assign o = i1;
endmodule
| 6.802018 |
module dlhsb_udp4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
assign o = i1;
endmodule
| 6.524958 |
module AN2B1LEHMX1 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
not g0 (i2, B1);
and g1 (O, I1, i2);
endmodule
| 7.270065 |
module AN2B1LEHMX2 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
not g0 (i2, B1);
and g1 (O, I1, i2);
endmodule
| 7.272952 |
module AN2B1LEHMX3 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
not g0 (i2, B1);
and g1 (O, I1, i2);
endmodule
| 7.496027 |
module AN2B1LEHMX4 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
not g0 (i2, B1);
and g1 (O, I1, i2);
endmodule
| 7.327311 |
module AN2B1LEHMX6 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
not g0 (i2, B1);
and g1 (O, I1, i2);
endmodule
| 7.266689 |
module AN2B1LEHMX8 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
not g0 (i2, B1);
and g1 (O, I1, i2);
endmodule
| 7.04304 |
module AN2CKLEHMX1 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.723041 |
module AN2CKLEHMX2 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.843524 |
module AN2CKLEHMX3 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.688082 |
module AN2CKLEHMX6 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.649814 |
module AN2CKLEHMX8 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.561497 |
module AN2LEHMX1 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.729963 |
module AN2LEHMX2 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.857099 |
module AN2LEHMX3 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.749397 |
module AN2LEHMX6 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.634758 |
module AN2LEHMX8 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.55185 |
module AN3B2LEHMX1 (
O,
I1,
B1,
B2
);
output O;
input I1, B1, B2;
wire i2;
wire i3;
not g0 (i3, B2);
and3 g1 (
O,
I1,
i2,
i3
);
not g2 (i2, B1);
endmodule
| 7.467694 |
module AN3B2LEHMX2 (
O,
I1,
B1,
B2
);
output O;
input I1, B1, B2;
wire i2;
wire i3;
not g0 (i3, B2);
and3 g1 (
O,
I1,
i2,
i3
);
not g2 (i2, B1);
endmodule
| 7.439767 |
module AN3B2LEHMX3 (
O,
I1,
B1,
B2
);
output O;
input I1, B1, B2;
wire i2;
wire i3;
not g0 (i3, B2);
and3 g1 (
O,
I1,
i2,
i3
);
not g2 (i2, B1);
endmodule
| 7.565571 |
module AN3B2LEHMX4 (
O,
I1,
B1,
B2
);
output O;
input I1, B1, B2;
wire i2;
wire i3;
not g0 (i3, B2);
and3 g1 (
O,
I1,
i2,
i3
);
not g2 (i2, B1);
endmodule
| 7.432697 |
module AN3LEHMX1 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
and3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 6.746014 |
module AN3LEHMX2 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
and3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 6.835269 |
module AN3LEHMX3 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
and3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 6.832581 |
module AN3LEHMX4 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
and3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 6.687032 |
module AN4LEHMX1 (
O,
I1,
I2,
I3,
I4
);
output O;
input I1, I2, I3, I4;
and4 g1 (
O,
I1,
I2,
I3,
I4
);
endmodule
| 6.738252 |
module AN4LEHMX2 (
O,
I1,
I2,
I3,
I4
);
output O;
input I1, I2, I3, I4;
and4 g1 (
O,
I1,
I2,
I3,
I4
);
endmodule
| 6.779265 |
module AN4LEHMX3 (
O,
I1,
I2,
I3,
I4
);
output O;
input I1, I2, I3, I4;
and4 g1 (
O,
I1,
I2,
I3,
I4
);
endmodule
| 6.951743 |
module AN4LEHMX4 (
O,
I1,
I2,
I3,
I4
);
output O;
input I1, I2, I3, I4;
and4 g1 (
O,
I1,
I2,
I3,
I4
);
endmodule
| 6.676583 |
module AO112LEHMX1 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
o2,
A1,
B1,
o1
);
not g3 (O, o2);
endmodule
| 7.09162 |
module AO112LEHMX2 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
o2,
A1,
B1,
o1
);
not g3 (O, o2);
endmodule
| 7.052544 |
module AO112LEHMX3 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
o2,
A1,
B1,
o1
);
not g3 (O, o2);
endmodule
| 7.365024 |
module AO12LEHMX1 (
O,
A1,
B1,
B2
);
output O;
input A1, B1, B2;
wire o2;
wire o1;
and g1 (o1, B1, B2);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 7.010401 |
module AO12LEHMX2 (
O,
A1,
B1,
B2
);
output O;
input A1, B1, B2;
wire o2;
wire o1;
and g1 (o1, B1, B2);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 7.022075 |
module AO12LEHMX3 (
O,
A1,
B1,
B2
);
output O;
input A1, B1, B2;
wire o2;
wire o1;
and g1 (o1, B1, B2);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 7.259549 |
module AO12LEHMX4 (
O,
A1,
B1,
B2
);
output O;
input A1, B1, B2;
wire o2;
wire o1;
and g1 (o1, B1, B2);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 7.28266 |
module AO13LEHMX1 (
O,
A1,
B1,
B2,
B3
);
output O;
input A1, B1, B2, B3;
wire o2;
wire o1;
and3 g1 (
o1,
B1,
B2,
B3
);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 6.860029 |
module AO13LEHMX2 (
O,
A1,
B1,
B2,
B3
);
output O;
input A1, B1, B2, B3;
wire o2;
wire o1;
and3 g1 (
o1,
B1,
B2,
B3
);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 6.88578 |
module AO13LEHMX3 (
O,
A1,
B1,
B2,
B3
);
output O;
input A1, B1, B2, B3;
wire o2;
wire o1;
and3 g1 (
o1,
B1,
B2,
B3
);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 6.948515 |
module AO222LEHMX1 (
O,
A1,
A2,
B1,
B2,
C1,
C2
);
output O;
input A1, A2, B1, B2, C1, C2;
wire o4;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
and g4 (o3, C1, C2);
nor3 g2 (
o4,
o1,
o2,
o3
);
not g5 (O, o4);
endmodule
| 6.923015 |
module AO222LEHMX2 (
O,
A1,
A2,
B1,
B2,
C1,
C2
);
output O;
input A1, A2, B1, B2, C1, C2;
wire o4;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
and g4 (o3, C1, C2);
nor3 g2 (
o4,
o1,
o2,
o3
);
not g5 (O, o4);
endmodule
| 6.990822 |
module AO222LEHMX3 (
O,
A1,
A2,
B1,
B2,
C1,
C2
);
output O;
input A1, A2, B1, B2, C1, C2;
wire o4;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
and g4 (o3, C1, C2);
nor3 g2 (
o4,
o1,
o2,
o3
);
not g5 (O, o4);
endmodule
| 7.289033 |
module AO22LEHMX1 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
nor g2 (o3, o1, o2);
not g4 (O, o3);
endmodule
| 6.861303 |
module AO22LEHMX2 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
nor g2 (o3, o1, o2);
not g4 (O, o3);
endmodule
| 6.82428 |
module AO22LEHMX3 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
nor g2 (o3, o1, o2);
not g4 (O, o3);
endmodule
| 7.029447 |
module AO22LEHMX4 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
nor g2 (o3, o1, o2);
not g4 (O, o3);
endmodule
| 6.976089 |
module AO22LEHMX6 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
nor g2 (o3, o1, o2);
not g4 (O, o3);
endmodule
| 6.675797 |
module AOI112LEHMX1 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
O,
A1,
B1,
o1
);
endmodule
| 7.381578 |
module AOI112LEHMX2 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
O,
A1,
B1,
o1
);
endmodule
| 7.356703 |
module AOI112LEHMX3 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
O,
A1,
B1,
o1
);
endmodule
| 7.63859 |
module AOI112LEHMX4 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
O,
A1,
B1,
o1
);
endmodule
| 7.357629 |
module AOI122LEHMX1 (
O,
A1,
B1,
B2,
C1,
C2
);
output O;
input A1, B1, B2, C1, C2;
wire o2;
wire o1;
and g1 (o1, B1, B2);
and g2 (o2, C1, C2);
nor3 g3 (
O,
A1,
o1,
o2
);
endmodule
| 7.67369 |
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