code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module \$safe_pmux (
A,
B,
S,
Y
);
parameter WIDTH = 1;
parameter S_WIDTH = 1;
input [WIDTH-1:0] A;
input [WIDTH*S_WIDTH-1:0] B;
input [S_WIDTH-1:0] S;
output [WIDTH-1:0] Y;
wire [S_WIDTH-1:0] status_found_first;
wire [S_WIDTH-1:0] status_found_second;
genvar i;
generate
for ... | 6.711891 |
module stdio (
input wire [7:0] addr,
input wire clk,
input wire reset,
input wire read_write,
input wire enable,
input wire [31:0] data_in,
output reg [31:0] data_out,
output reg exit = 0
);
integer err;
parameter STDIN = 32'h8000_0000;
parameter STDOUT = 32'h8000_0001;
parame... | 7.369583 |
module normClkGenerator (
clk_in,
reset_n,
clk_out
);
// parameter [31:1] param_05Second = 32'h00FBC520; //33MHz0.5b
// parameter [31:0] param_05Second = 32'h00000100;
parameter [31:0] param_05Second = 32'h00FBC520;
input clk_in;
input reset_n;
output clk_out;
reg [31:0] interreg;
reg clk... | 6.693178 |
module main; //: root_module
reg [15:0] A_NET; //: {0}(#:80,174)(145,174)(145,174)(213,174){1}
//: {2}(1:217,174)(271,174){3}
//: {4}(#:215,176)(215,352)(268,352){5}
reg [3:0] OP_NET; //: {0}(#:80,416)(91,416)(91,416)(109,416){1}
//: {2}(-18:113,416)(268,416){3}
//: {4}(111,414)(111,238)(271,238){5}
re... | 6.5859 |
module std_2s60_reset_clk_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_... | 7.428197 |
module ext_flash_lane0_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [23:0] rdaddress;
input rdclken;
input [23:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [167... | 6.952907 |
module ext_flash (
// inputs:
address,
read_n,
select_n,
write_n,
// outputs:
data
);
inout [7:0] data;
input [23:0] address;
input read_n;
input select_n;
input write_n;
wire [7:0] data;
wire [7:0] data_0;
wire [7:0] logic_vector_gasket;
wire [7:0] q_0;
//s1, which is... | 6.719908 |
module ext_ram_lane0_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [17:0] rdaddress;
input rdclken;
input [17:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [26214... | 6.982298 |
module ext_ram_lane1_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [17:0] rdaddress;
input rdclken;
input [17:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [26214... | 6.716371 |
module ext_ram_lane2_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [17:0] rdaddress;
input rdclken;
input [17:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [26214... | 6.946152 |
module ext_ram_lane3_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [17:0] rdaddress;
input rdclken;
input [17:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [26214... | 6.668691 |
module ext_ram (
// inputs:
address,
be_n,
read_n,
select_n,
write_n,
// outputs:
data
);
inout [31:0] data;
input [17:0] address;
input [3:0] be_n;
input read_n;
input select_n;
input write_n;
wire [31:0] data;
wire [ 7:0] data_0;
wire [ 7:0] data_1;
wire [ 7:0] d... | 6.990033 |
module inv ( /*AUTOARG*/
// Outputs
zn,
// Inputs
i
);
parameter DELAY = 1;
input i;
output zn;
assign #DELAY zn = !i;
endmodule
| 6.837475 |
module buff ( /*AUTOARG*/
// Outputs
z,
// Inputs
i
);
parameter DELAY = 1;
input i;
output z;
assign #DELAY z = i;
endmodule
| 6.920533 |
module and2 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b
);
parameter DELAY = 1;
input a, b;
output z;
assign #DELAY z = a & b;
endmodule
| 6.958302 |
module nand2 ( /*AUTOARG*/
// Outputs
zn,
// Inputs
a,
b
);
parameter DELAY = 1;
input a, b;
output zn;
assign #DELAY zn = !(a & b);
endmodule
| 7.655066 |
module and3 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b,
c
);
parameter DELAY = 1;
input a, b, c;
output z;
assign #DELAY z = a & b & c;
endmodule
| 6.663943 |
module nand3 ( /*AUTOARG*/
// Outputs
zn,
// Inputs
a,
b,
c
);
parameter DELAY = 1;
input a, b, c;
output zn;
assign #DELAY zn = !(a & b & c);
endmodule
| 7.167416 |
module nand4 ( /*AUTOARG*/
// Outputs
zn,
// Inputs
a,
b,
c,
d
);
parameter DELAY = 1;
input a, b, c, d;
output zn;
assign #DELAY zn = !(a & b & c & d);
endmodule
| 7.740076 |
module or2 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b
);
parameter DELAY = 1;
input a, b;
output z;
assign #DELAY z = a | b;
endmodule
| 6.979061 |
module xor2 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b
);
parameter DELAY = 1;
input a, b;
output z;
assign #DELAY z = a ^ b;
endmodule
| 7.190934 |
module mux2 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a0,
a1,
s
);
input a0;
input a1;
input s;
output z;
parameter DELAY = 1;
assign #DELAY z = s ? a1 : a0;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
endmodule
| 6.72973 |
module latch ( /*AUTOARG*/
// Outputs
q,
// Inputs
en,
i,
rstn
);
input en;
input i;
input rstn;
output q;
reg q;
always @* begin
if (rstn == 1'b0) q <= 0;
else if (en) q <= i;
end
endmodule
| 6.776901 |
module std_dffe #(
parameter WIDTH = 8
) (
input clk,
input en,
input [WIDTH-1:0] d,
output [WIDTH-1:0] q
);
reg [WIDTH-1:0] dff_q;
always @(posedge clk) begin
if (en | ~en) begin
dff_q <= d;
end
end
assign q = en ? dff_q : '0;
endmodule
| 7.805632 |
module std_dffr #(
parameter WIDTH = 8
) (
input clk,
input rstn,
input [WIDTH-1:0] d,
output [WIDTH-1:0] q
);
reg [WIDTH-1:0] dff_q;
always @(posedge clk) begin
if (rstn) begin
dff_q <= {WIDTH{1'b0}};
end else begin
dff_q <= d;
end
end
a... | 7.584522 |
module std_dffre (
clk,
rstn,
en,
d,
q
);
parameter WIDTH = 8;
input clk;
input rstn;
input en;
input [WIDTH - 1:0] d;
output wire [WIDTH - 1:0] q;
reg [WIDTH - 1:0] dff_q;
always @(posedge clk or negedge rstn)
if (~rstn) dff_q <= {WIDTH{1'b0}};
else if (en) dff_q <= d;
ass... | 7.78136 |
module std_dffrve (
clk,
rstn,
rst_val,
en,
d,
q
);
parameter WIDTH = 8;
input clk;
input rstn;
input [WIDTH - 1:0] rst_val;
input en;
input [WIDTH - 1:0] d;
output wire [WIDTH - 1:0] q;
reg [WIDTH - 1:0] dff_q;
always @(posedge clk or negedge rstn)
if (~rstn) dff_q <= rst_... | 8.134307 |
module std_fifo_tb;
reg rst, clk;
reg push, pop;
reg [7:0] d;
wire [7:0] q;
wire full, empty;
wire [3:0] count;
wire almost_empty;
wire almost_full;
std_fifo #(8, 16) dut (
rst,
clk,
push,
pop,
d,
q,
full,
empty,
count,
almost_empty,
... | 6.582685 |
module not(o,i1);
input i1;
output o;
assign o = ~i1;
endmodule
| 7.490638 |
module and(o,i1,i2);
input i1, i2;
output o;
assign o = i1 & i2;
endmodule
| 7.615987 |
module or(o,i1,i2);
input i1, i2;
output o;
assign o = i1 | i2;
endmodule
| 7.703227 |
module xor(o,i1,i2);
input i1, i2;
output o;
assign o = i1 ^ i2;
endmodule
| 7.914568 |
module nor(o,i1,i2);
input i1, i2;
output o;
wire tem1;
assign tem1 = i1 | i2;
assign o = ~tem1;
endmodule
| 7.543454 |
module nand(o,i1,i2);
input i1, i2;
output o;
wire tem1;
assign tem1 = i1 & i2;
assign o = ~tem1;
endmodule
| 7.556739 |
module xnor(o,i1,i2);
input i1, i2;
output o;
wire tem1;
assign tem1 = i1 ^ i2;
assign o = ~tem1;
endmodule
| 7.175695 |
module and3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
wire tem1;
assign tem1 = i1 & i2;
assign o = tem1 & i3;
endmodule
| 6.783095 |
module and4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
wire tem1;
wire tem2;
assign tem1 = i1 & i2;
assign tem2 = tem1 & i3;
assign o = tem2 & i4;
endmodule
| 7.000535 |
module and5 (
o,
i1,
i2,
i3,
i4,
i5
);
input i1, i2, i3, i4, i5;
output o;
wire tem1;
wire tem2;
assign tem1 = i1 & i2;
assign tem2 = tem1 & i3;
assign tem3 = tem2 & i4;
assign o = tem3 & i5;
endmodule
| 6.560006 |
module or3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
wire tem1;
assign tem1 = i1 | i2;
assign o = tem1 | i3;
endmodule
| 7.109001 |
module or4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
wire tem1;
wire tem2;
assign tem1 = i1 | i2;
assign tem2 = tem1 | i3;
assign o = tem2 | i4;
endmodule
| 7.141237 |
module xor3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
wire tem1;
assign tem1 = i1 ^ i2;
assign o = tem1 ^ i3;
endmodule
| 7.092493 |
module nor3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
wire tem1;
wire tem2;
assign tem1 = i1 | i2;
assign tem2 = tem1 | i3;
assign o = ~tem2;
endmodule
| 6.982417 |
module nor4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
wire tem1;
wire tem2;
wire tem3;
assign tem1 = i1 | i2;
assign tem2 = tem1 | i3;
assign tem3 = tem2 | i4;
assign o = ~tem3;
endmodule
| 7.058914 |
module nand3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
wire tem1;
wire tem2;
assign tem1 = i1 & i2;
assign tem2 = tem1 & i3;
assign o = ~tem2;
endmodule
| 7.061822 |
module nand4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
wire tem1;
wire tem2;
wire tem3;
assign tem1 = i1 & i2;
assign tem2 = tem1 & i3;
assign tem3 = tem2 & i4;
assign o = ~tem3;
endmodule
| 6.994556 |
module xnor3 (
o,
i1,
i2,
i3
);
input i1, i2, i3;
output o;
wire tem1, tem2;
assign tem1 = i1 ^ i2;
assign tem2 = tem1 ^ i2;
assign o = ~tem2;
endmodule
| 6.696172 |
module dffrsb_udp5 (
o,
i1,
i2,
i3,
i4,
i5
);
input i1, i2, i3, i4, i5;
output o;
assign o = i1;
endmodule
| 6.884559 |
module dlhrb_udp4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
assign o = i1;
endmodule
| 6.802018 |
module dlhsb_udp4 (
o,
i1,
i2,
i3,
i4
);
input i1, i2, i3, i4;
output o;
assign o = i1;
endmodule
| 6.524958 |
module AN2B1LEHMX1 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
not g0 (i2, B1);
and g1 (O, I1, i2);
endmodule
| 7.270065 |
module AN2B1LEHMX2 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
not g0 (i2, B1);
and g1 (O, I1, i2);
endmodule
| 7.272952 |
module AN2B1LEHMX3 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
not g0 (i2, B1);
and g1 (O, I1, i2);
endmodule
| 7.496027 |
module AN2B1LEHMX4 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
not g0 (i2, B1);
and g1 (O, I1, i2);
endmodule
| 7.327311 |
module AN2B1LEHMX6 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
not g0 (i2, B1);
and g1 (O, I1, i2);
endmodule
| 7.266689 |
module AN2B1LEHMX8 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
not g0 (i2, B1);
and g1 (O, I1, i2);
endmodule
| 7.04304 |
module AN2CKLEHMX1 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.723041 |
module AN2CKLEHMX2 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.843524 |
module AN2CKLEHMX3 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.688082 |
module AN2CKLEHMX6 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.649814 |
module AN2CKLEHMX8 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.561497 |
module AN2LEHMX1 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.729963 |
module AN2LEHMX2 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.857099 |
module AN2LEHMX3 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.749397 |
module AN2LEHMX6 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.634758 |
module AN2LEHMX8 (
O,
I1,
I2
);
output O;
input I1, I2;
and g1 (O, I1, I2);
endmodule
| 6.55185 |
module AN3B2LEHMX1 (
O,
I1,
B1,
B2
);
output O;
input I1, B1, B2;
wire i2;
wire i3;
not g0 (i3, B2);
and3 g1 (
O,
I1,
i2,
i3
);
not g2 (i2, B1);
endmodule
| 7.467694 |
module AN3B2LEHMX2 (
O,
I1,
B1,
B2
);
output O;
input I1, B1, B2;
wire i2;
wire i3;
not g0 (i3, B2);
and3 g1 (
O,
I1,
i2,
i3
);
not g2 (i2, B1);
endmodule
| 7.439767 |
module AN3B2LEHMX3 (
O,
I1,
B1,
B2
);
output O;
input I1, B1, B2;
wire i2;
wire i3;
not g0 (i3, B2);
and3 g1 (
O,
I1,
i2,
i3
);
not g2 (i2, B1);
endmodule
| 7.565571 |
module AN3B2LEHMX4 (
O,
I1,
B1,
B2
);
output O;
input I1, B1, B2;
wire i2;
wire i3;
not g0 (i3, B2);
and3 g1 (
O,
I1,
i2,
i3
);
not g2 (i2, B1);
endmodule
| 7.432697 |
module AN3LEHMX1 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
and3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 6.746014 |
module AN3LEHMX2 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
and3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 6.835269 |
module AN3LEHMX3 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
and3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 6.832581 |
module AN3LEHMX4 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
and3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 6.687032 |
module AN4LEHMX1 (
O,
I1,
I2,
I3,
I4
);
output O;
input I1, I2, I3, I4;
and4 g1 (
O,
I1,
I2,
I3,
I4
);
endmodule
| 6.738252 |
module AN4LEHMX2 (
O,
I1,
I2,
I3,
I4
);
output O;
input I1, I2, I3, I4;
and4 g1 (
O,
I1,
I2,
I3,
I4
);
endmodule
| 6.779265 |
module AN4LEHMX3 (
O,
I1,
I2,
I3,
I4
);
output O;
input I1, I2, I3, I4;
and4 g1 (
O,
I1,
I2,
I3,
I4
);
endmodule
| 6.951743 |
module AN4LEHMX4 (
O,
I1,
I2,
I3,
I4
);
output O;
input I1, I2, I3, I4;
and4 g1 (
O,
I1,
I2,
I3,
I4
);
endmodule
| 6.676583 |
module AO112LEHMX1 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
o2,
A1,
B1,
o1
);
not g3 (O, o2);
endmodule
| 7.09162 |
module AO112LEHMX2 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
o2,
A1,
B1,
o1
);
not g3 (O, o2);
endmodule
| 7.052544 |
module AO112LEHMX3 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
o2,
A1,
B1,
o1
);
not g3 (O, o2);
endmodule
| 7.365024 |
module AO12LEHMX1 (
O,
A1,
B1,
B2
);
output O;
input A1, B1, B2;
wire o2;
wire o1;
and g1 (o1, B1, B2);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 7.010401 |
module AO12LEHMX2 (
O,
A1,
B1,
B2
);
output O;
input A1, B1, B2;
wire o2;
wire o1;
and g1 (o1, B1, B2);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 7.022075 |
module AO12LEHMX3 (
O,
A1,
B1,
B2
);
output O;
input A1, B1, B2;
wire o2;
wire o1;
and g1 (o1, B1, B2);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 7.259549 |
module AO12LEHMX4 (
O,
A1,
B1,
B2
);
output O;
input A1, B1, B2;
wire o2;
wire o1;
and g1 (o1, B1, B2);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 7.28266 |
module AO13LEHMX1 (
O,
A1,
B1,
B2,
B3
);
output O;
input A1, B1, B2, B3;
wire o2;
wire o1;
and3 g1 (
o1,
B1,
B2,
B3
);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 6.860029 |
module AO13LEHMX2 (
O,
A1,
B1,
B2,
B3
);
output O;
input A1, B1, B2, B3;
wire o2;
wire o1;
and3 g1 (
o1,
B1,
B2,
B3
);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 6.88578 |
module AO13LEHMX3 (
O,
A1,
B1,
B2,
B3
);
output O;
input A1, B1, B2, B3;
wire o2;
wire o1;
and3 g1 (
o1,
B1,
B2,
B3
);
nor g2 (o2, A1, o1);
not g3 (O, o2);
endmodule
| 6.948515 |
module AO222LEHMX1 (
O,
A1,
A2,
B1,
B2,
C1,
C2
);
output O;
input A1, A2, B1, B2, C1, C2;
wire o4;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
and g4 (o3, C1, C2);
nor3 g2 (
o4,
o1,
o2,
o3
);
not g5 (O, o4);
endmodule... | 6.923015 |
module AO222LEHMX2 (
O,
A1,
A2,
B1,
B2,
C1,
C2
);
output O;
input A1, A2, B1, B2, C1, C2;
wire o4;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
and g4 (o3, C1, C2);
nor3 g2 (
o4,
o1,
o2,
o3
);
not g5 (O, o4);
endmodule... | 6.990822 |
module AO222LEHMX3 (
O,
A1,
A2,
B1,
B2,
C1,
C2
);
output O;
input A1, A2, B1, B2, C1, C2;
wire o4;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
and g4 (o3, C1, C2);
nor3 g2 (
o4,
o1,
o2,
o3
);
not g5 (O, o4);
endmodule... | 7.289033 |
module AO22LEHMX1 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
nor g2 (o3, o1, o2);
not g4 (O, o3);
endmodule
| 6.861303 |
module AO22LEHMX2 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
nor g2 (o3, o1, o2);
not g4 (O, o3);
endmodule
| 6.82428 |
module AO22LEHMX3 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
nor g2 (o3, o1, o2);
not g4 (O, o3);
endmodule
| 7.029447 |
module AO22LEHMX4 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
nor g2 (o3, o1, o2);
not g4 (O, o3);
endmodule
| 6.976089 |
module AO22LEHMX6 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
wire o3;
and g1 (o1, B1, B2);
and g3 (o2, A1, A2);
nor g2 (o3, o1, o2);
not g4 (O, o3);
endmodule
| 6.675797 |
module AOI112LEHMX1 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
O,
A1,
B1,
o1
);
endmodule
| 7.381578 |
module AOI112LEHMX2 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
O,
A1,
B1,
o1
);
endmodule
| 7.356703 |
module AOI112LEHMX3 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
O,
A1,
B1,
o1
);
endmodule
| 7.63859 |
module AOI112LEHMX4 (
O,
A1,
B1,
C1,
C2
);
output O;
input A1, B1, C1, C2;
wire o1;
and g1 (o1, C1, C2);
nor3 g2 (
O,
A1,
B1,
o1
);
endmodule
| 7.357629 |
module AOI122LEHMX1 (
O,
A1,
B1,
B2,
C1,
C2
);
output O;
input A1, B1, B2, C1, C2;
wire o2;
wire o1;
and g1 (o1, B1, B2);
and g2 (o2, C1, C2);
nor3 g3 (
O,
A1,
o1,
o2
);
endmodule
| 7.67369 |
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