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module AOI122LEHMX2 ( O, A1, B1, B2, C1, C2 ); output O; input A1, B1, B2, C1, C2; wire o2; wire o1; and g1 (o1, B1, B2); and g2 (o2, C1, C2); nor3 g3 ( O, A1, o1, o2 ); endmodule
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module AOI122LEHMX3 ( O, A1, B1, B2, C1, C2 ); output O; input A1, B1, B2, C1, C2; wire o2; wire o1; and g1 (o1, B1, B2); and g2 (o2, C1, C2); nor3 g3 ( O, A1, o1, o2 ); endmodule
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module AOI122LEHMX4 ( O, A1, B1, B2, C1, C2 ); output O; input A1, B1, B2, C1, C2; wire o2; wire o1; and g1 (o1, B1, B2); and g2 (o2, C1, C2); nor3 g3 ( O, A1, o1, o2 ); endmodule
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module AOI12B2LEHMX1 ( O, A1, B1, B2 ); output O; input A1, B1, B2; wire i1; wire i2; wire i3; not g1 (i1, B1); not g2 (i2, B2); and g3 (i3, i2, i1); nor g4 (O, i3, A1); endmodule
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module AOI12B2LEHMX2 ( O, A1, B1, B2 ); output O; input A1, B1, B2; wire i1; wire i2; wire i3; not g1 (i1, B1); not g2 (i2, B2); and g3 (i3, i2, i1); nor g4 (O, i3, A1); endmodule
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module AOI12B2LEHMX3 ( O, A1, B1, B2 ); output O; input A1, B1, B2; wire i1; wire i2; wire i3; not g1 (i1, B1); not g2 (i2, B2); and g3 (i3, i2, i1); nor g4 (O, i3, A1); endmodule
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module AOI12LEHMX1 ( O, A1, B1, B2 ); output O; input A1, B1, B2; wire o1; and g1 (o1, B1, B2); nor g2 (O, A1, o1); endmodule
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module AOI12LEHMX2 ( O, A1, B1, B2 ); output O; input A1, B1, B2; wire o1; and g1 (o1, B1, B2); nor g2 (O, A1, o1); endmodule
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module AOI12LEHMX3 ( O, A1, B1, B2 ); output O; input A1, B1, B2; wire o1; and g1 (o1, B1, B2); nor g2 (O, A1, o1); endmodule
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module AOI12LEHMX4 ( O, A1, B1, B2 ); output O; input A1, B1, B2; wire o1; and g1 (o1, B1, B2); nor g2 (O, A1, o1); endmodule
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module AOI12LEHMX6 ( O, A1, B1, B2 ); output O; input A1, B1, B2; wire o1; and g1 (o1, B1, B2); nor g2 (O, A1, o1); endmodule
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module AOI12M2HLEHMX4 ( O, A1, B1, B2 ); output O; input A1, B1, B2; wire o1; and g1 (o1, B1, B2); nor g2 (O, A1, o1); endmodule
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module AOI12M2HLEHMX6 ( O, A1, B1, B2 ); output O; input A1, B1, B2; wire o1; and g1 (o1, B1, B2); nor g2 (O, A1, o1); endmodule
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module AOI12M2HLEHMX8 ( O, A1, B1, B2 ); output O; input A1, B1, B2; wire o1; and g1 (o1, B1, B2); nor g2 (O, A1, o1); endmodule
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module AOI13LEHMX1 ( O, A1, B1, B2, B3 ); output O; input A1, B1, B2, B3; wire o1; and3 g1 ( o1, B1, B2, B3 ); nor g2 (O, A1, o1); endmodule
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module AOI13LEHMX2 ( O, A1, B1, B2, B3 ); output O; input A1, B1, B2, B3; wire o1; and3 g1 ( o1, B1, B2, B3 ); nor g2 (O, A1, o1); endmodule
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module AOI13LEHMX3 ( O, A1, B1, B2, B3 ); output O; input A1, B1, B2, B3; wire o1; and3 g1 ( o1, B1, B2, B3 ); nor g2 (O, A1, o1); endmodule
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module AOI13LEHMX4 ( O, A1, B1, B2, B3 ); output O; input A1, B1, B2, B3; wire o1; and3 g1 ( o1, B1, B2, B3 ); nor g2 (O, A1, o1); endmodule
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module AOI21B1ISLEHMX1 ( O, A1, A2, B1B ); output O; input A1, A2, B1B; wire A1A2; wire b1b_bar; and g1 (A1A2, A1, A2); not g2 (b1b_bar, B1B); nor g3 (O, A1A2, b1b_bar); endmodule
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module AOI21B1ISLEHMX2 ( O, A1, A2, B1B ); output O; input A1, A2, B1B; wire A1A2; wire b1b_bar; and g1 (A1A2, A1, A2); not g2 (b1b_bar, B1B); nor g3 (O, A1A2, b1b_bar); endmodule
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module AOI21B1ISLEHMX3 ( O, A1, A2, B1B ); output O; input A1, A2, B1B; wire A1A2; wire b1b_bar; and g1 (A1A2, A1, A2); not g2 (b1b_bar, B1B); nor g3 (O, A1A2, b1b_bar); endmodule
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module AOI21B1LEHMX1 ( O, A1, A2, B1B ); output O; input A1, A2, B1B; wire A1A2; wire b1b_bar; and g1 (A1A2, A1, A2); not g2 (b1b_bar, B1B); nor g3 (O, A1A2, b1b_bar); endmodule
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module AOI21B1LEHMX2 ( O, A1, A2, B1B ); output O; input A1, A2, B1B; wire A1A2; wire b1b_bar; and g1 (A1A2, A1, A2); not g2 (b1b_bar, B1B); nor g3 (O, A1A2, b1b_bar); endmodule
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module AOI21B1LEHMX3 ( O, A1, A2, B1B ); output O; input A1, A2, B1B; wire A1A2; wire b1b_bar; and g1 (A1A2, A1, A2); not g2 (b1b_bar, B1B); nor g3 (O, A1A2, b1b_bar); endmodule
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module AOI222LEHMX1 ( O, A1, A2, B1, B2, C1, C2 ); output O; input A1, A2, B1, B2, C1, C2; wire o2; wire o1; wire o3; and g1 (o1, B1, B2); and g3 (o2, A1, A2); and g4 (o3, C1, C2); nor3 g2 ( O, o1, o2, o3 ); endmodule
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module AOI222LEHMX2 ( O, A1, A2, B1, B2, C1, C2 ); output O; input A1, A2, B1, B2, C1, C2; wire o2; wire o1; wire o3; and g1 (o1, B1, B2); and g3 (o2, A1, A2); and g4 (o3, C1, C2); nor3 g2 ( O, o1, o2, o3 ); endmodule
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module AOI222LEHMX3 ( O, A1, A2, B1, B2, C1, C2 ); output O; input A1, A2, B1, B2, C1, C2; wire o2; wire o1; wire o3; and g1 (o1, B1, B2); and g3 (o2, A1, A2); and g4 (o3, C1, C2); nor3 g2 ( O, o1, o2, o3 ); endmodule
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module AOI22B2LEHMX1 ( O, A1, A2, B1B, B2B ); output O; input A1, A2, B1B, B2B; wire o2; wire o1; and g1 (o1, A1, A2); nor g2 (o2, B1B, B2B); nor g3 (O, o1, o2); endmodule
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module AOI22B2LEHMX2 ( O, A1, A2, B1B, B2B ); output O; input A1, A2, B1B, B2B; wire o2; wire o1; and g1 (o1, A1, A2); nor g2 (o2, B1B, B2B); nor g3 (O, o1, o2); endmodule
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module AOI22B2LEHMX3 ( O, A1, A2, B1B, B2B ); output O; input A1, A2, B1B, B2B; wire o2; wire o1; and g1 (o1, A1, A2); nor g2 (o2, B1B, B2B); nor g3 (O, o1, o2); endmodule
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module AOI22LEHMX1 ( O, A1, A2, B1, B2 ); output O; input A1, A2, B1, B2; wire o2; wire o1; and g1 (o1, B1, B2); and g3 (o2, A1, A2); nor g2 (O, o1, o2); endmodule
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module AOI22LEHMX2 ( O, A1, A2, B1, B2 ); output O; input A1, A2, B1, B2; wire o2; wire o1; and g1 (o1, B1, B2); and g3 (o2, A1, A2); nor g2 (O, o1, o2); endmodule
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module AOI22LEHMX3 ( O, A1, A2, B1, B2 ); output O; input A1, A2, B1, B2; wire o2; wire o1; and g1 (o1, B1, B2); and g3 (o2, A1, A2); nor g2 (O, o1, o2); endmodule
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module AOI22LEHMX4 ( O, A1, A2, B1, B2 ); output O; input A1, A2, B1, B2; wire o2; wire o1; and g1 (o1, B1, B2); and g3 (o2, A1, A2); nor g2 (O, o1, o2); endmodule
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module AOI22M2HLEHMX3 ( O, A1, A2, B1, B2 ); output O; input A1, A2, B1, B2; wire o2; wire o1; and g1 (o1, B1, B2); and g3 (o2, A1, A2); nor g2 (O, o1, o2); endmodule
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module AOI22M2HLEHMX4 ( O, A1, A2, B1, B2 ); output O; input A1, A2, B1, B2; wire o2; wire o1; and g1 (o1, B1, B2); and g3 (o2, A1, A2); nor g2 (O, o1, o2); endmodule
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module AOI22M2HLEHMX6 ( O, A1, A2, B1, B2 ); output O; input A1, A2, B1, B2; wire o2; wire o1; and g1 (o1, B1, B2); and g3 (o2, A1, A2); nor g2 (O, o1, o2); endmodule
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module AOI22M2HLEHMX8 ( O, A1, A2, B1, B2 ); output O; input A1, A2, B1, B2; wire o2; wire o1; and g1 (o1, B1, B2); and g3 (o2, A1, A2); nor g2 (O, o1, o2); endmodule
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module BUFCKLEHMX20 ( O, I ); output O; input I; buf g1 (O, I); endmodule
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module BUFLEHMX20 ( O, I ); output O; input I; buf g1 (O, I); endmodule
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module BUFM2HLEHMX20 ( O, I ); output O; input I; buf g1 (O, I); endmodule
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module FA1LEHMX1 ( S, CO, A, B, CI ); output S, CO; input A, B, CI; wire a2; wire a1; wire a3; and g1 (a1, A, B); and g2 (a2, B, CI); and g3 (a3, A, CI); or3 g4 ( CO, a1, a2, a3 ); xor3 g5 ( S, A, B, CI ); endmodule
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module FA1LEHMX2 ( S, CO, A, B, CI ); output S, CO; input A, B, CI; wire a2; wire a1; wire a3; and g1 (a1, A, B); and g2 (a2, B, CI); and g3 (a3, A, CI); or3 g4 ( CO, a1, a2, a3 ); xor3 g5 ( S, A, B, CI ); endmodule
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module FA1LEHMX3 ( S, CO, A, B, CI ); output S, CO; input A, B, CI; wire a2; wire a1; wire a3; and g1 (a1, A, B); and g2 (a2, B, CI); and g3 (a3, A, CI); or3 g4 ( CO, a1, a2, a3 ); xor3 g5 ( S, A, B, CI ); endmodule
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module FA1M2HLEHMX3 ( S, CO, A, B, CI ); output S, CO; input A, B, CI; wire a2; wire a1; wire a3; and g1 (a1, A, B); and g2 (a2, B, CI); and g3 (a3, A, CI); or3 g4 ( CO, a1, a2, a3 ); xor3 g5 ( S, A, B, CI ); endmodule
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module FA1M2HLEHMX4 ( S, CO, A, B, CI ); output S, CO; input A, B, CI; wire a2; wire a1; wire a3; and g1 (a1, A, B); and g2 (a2, B, CI); and g3 (a3, A, CI); or3 g4 ( CO, a1, a2, a3 ); xor3 g5 ( S, A, B, CI ); endmodule
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module FA1M2HLEHMX6 ( S, CO, A, B, CI ); output S, CO; input A, B, CI; wire a2; wire a1; wire a3; and g1 (a1, A, B); and g2 (a2, B, CI); and g3 (a3, A, CI); or3 g4 ( CO, a1, a2, a3 ); xor g5 (S, A, B, CI); endmodule
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module HA1LEHMX1 ( S, C, A, B ); output S, C; input A, B; and g1 (C, A, B); xor g2 (S, A, B); endmodule
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module HA1LEHMX2 ( S, C, A, B ); output S, C; input A, B; and g1 (C, A, B); xor g2 (S, A, B); endmodule
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module HA1LEHMX3 ( S, C, A, B ); output S, C; input A, B; and g1 (C, A, B); xor g2 (S, A, B); endmodule
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module INVCKLEHMX12 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVCKLEHMX16 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVCKLEHMX2 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVCKLEHMX20 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVCKLEHMX3 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVCKLEHMX6 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVCKLEHMX8 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVCKM2HLEHMX12 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVCKM2HLEHMX16 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVCKM2HLEHMX20 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVCKM2HLEHMX24 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVCKM2HLEHMX32 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVLEHMX12 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVLEHMX16 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVLEHMX2 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVLEHMX20 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVM2HLEHMX16 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module INVM2HLEHMX20 ( O, I ); output O; input I; not g1 (O, I); endmodule
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module ND2BPNLEHMX1 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2BPNLEHMX2 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2BPNLEHMX3 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2BPNLEHMX4 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2BPNLEHMX6 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2BPNLEHMX8 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2BPNM2HLEHMX12 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2BPNM2HLEHMX16 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2BPNM2HLEHMX6 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2BPNM2HLEHMX8 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2CKLEHMX1 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2CKLEHMX2 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2CKLEHMX3 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2CKLEHMX4 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2CKLEHMX6 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2CKLEHMX8 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2LEHMX1 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2LEHMX2 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2LEHMX3 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2LEHMX4 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2LEHMX6 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2LEHMX8 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2M2HLEHMX12 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2M2HLEHMX16 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2M2HLEHMX6 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND2M2HLEHMX8 ( O, I1, I2 ); output O; input I1, I2; nand g1 (O, I1, I2); endmodule
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module ND3LEHMX2 ( O, I1, I2, I3 ); output O; input I1, I2, I3; nand3 g1 ( O, I1, I2, I3 ); endmodule
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module ND3LEHMX6 ( O, I1, I2, I3 ); output O; input I1, I2, I3; nand3 g1 ( O, I1, I2, I3 ); endmodule
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module ND3M2HLEHMX10 ( O, I1, I2, I3 ); output O; input I1, I2, I3; nand3 g1 ( O, I1, I2, I3 ); endmodule
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module ND3M2HLEHMX6 ( O, I1, I2, I3 ); output O; input I1, I2, I3; nand3 g1 ( O, I1, I2, I3 ); endmodule
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module ND3M2HLEHMX8 ( O, I1, I2, I3 ); output O; input I1, I2, I3; nand3 g1 ( O, I1, I2, I3 ); endmodule
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module ND4B1LEHMX1 ( O, I1, I2, I3, B1 ); output O; input I1, I2, I3, B1; wire o2; wire o1; wire n1; and g1 (o1, I1, I2); not g2 (n1, B1); and g3 (o2, n1, I3); nand g4 (O, o1, o2); endmodule
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