code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module st_weight_addr_gen_Equal_17Sx16U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Equal_17Sx16U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Equal_17Sx16U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Equal_17Sx16U_1U_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Equal_17Sx16U_1U_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Equal_17Sx16U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Equal_17Sx16U_1U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Equal_17Sx16U_1U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Equal_17Sx16U_1U_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Equal_17Sx16U_1U_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Equal_17Sx16U_1U_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Equal_17Sx16U_1U_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Equal_17Sx16U_1U_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul3u16u16u16_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
assign asc001 = +(asc002 * in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul3u16u16u16_4_0 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
assign asc001 = +(asc002 * in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul3u16u16u16_4_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
assign asc001 = +(asc002 * in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul3u16u16u16_4_10 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
assign asc001 = +(asc002 * in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul3u16u16u16_4_2 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
assign asc001 = +(asc002 * in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul3u16u16u16_4_3 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
assign asc001 = +(asc002 * in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul3u16u16u16_4_4 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
assign asc001 = +(asc002 * in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul3u16u16u16_4_5 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
assign asc001 = +(asc002 * in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul3u16u16u16_4_6 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
assign asc001 = +(asc002 * in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul3u16u16u16_4_7 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
assign asc001 = +(asc002 * in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul3u16u16u16_4_8 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
assign asc001 = +(asc002 * in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul3u16u16u16_4_9 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
assign asc001 = +(asc002 * in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul_16Ux16U_16U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul_16Ux16U_16U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul_16Ux16U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul_16Ux16U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul_16Ux16U_32U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul_16Ux16U_32U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_16Ux16U_32U_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_16Ux16U_32U_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_16Ux16U_32U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_16Ux16U_32U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Mul_16Ux16U_32U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_16Ux16U_32U_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_16Ux16U_32U_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_16Ux16U_32U_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_16Ux16U_32U_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_16Ux16U_32U_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_32Ux16U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_32Ux16U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_32Ux16U_32U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_32Ux16U_32U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_32Ux16U_32U_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_32Ux16U_32U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_32Ux16U_32U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_32Ux16U_32U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_32Ux16U_32U_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_32Ux16U_32U_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_32Ux16U_32U_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_32Ux16U_32U_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Mul_32Ux16U_32U_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_4_10 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_4_11 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_4_2 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_4_3 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_4_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_4_5 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_4_6 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_4_7 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_4_8 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i1u16u16u1_4_9 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i32u16u16u1_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000100000);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i32u16u16u1_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000100000);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i32u16u16u1_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000100000);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i32u16u16u1_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000100000);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_MuxAdd2i32u16u16u1_4_2 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000100000);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0Add2Cati0u1u16u1_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input in2, ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [5:0] asc003;
assign asc003 = {in2, 5'B00000};
assign asc002 = +(in3) + (asc003);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc002;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0Add2Cati0u1u16u1_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input in2, ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [5:0] asc003;
assign asc003 = {in2, 5'B00000};
assign asc002 = +(in3) + (asc003);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc002;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0Add2Cati0u1u16u1_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input in2, ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [5:0] asc003;
assign asc003 = {in2, 5'B00000};
assign asc002 = +(in3) + (asc003);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc002;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0Add2Cati0u1u16u1_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input in2, ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [5:0] asc003;
assign asc003 = {in2, 5'B00000};
assign asc002 = +(in3) + (asc003);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc002;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0Add2Cati0u1u16u1_4_10 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input in2, ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [5:0] asc003;
assign asc003 = {in2, 5'B00000};
assign asc002 = +(in3) + (asc003);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc002;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0Add2Cati0u1u16u1_4_2 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input in2, ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [5:0] asc003;
assign asc003 = {in2, 5'B00000};
assign asc002 = +(in3) + (asc003);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc002;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0Add2Cati0u1u16u1_4_3 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input in2, ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [5:0] asc003;
assign asc003 = {in2, 5'B00000};
assign asc002 = +(in3) + (asc003);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc002;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0Add2Cati0u1u16u1_4_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input in2, ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [5:0] asc003;
assign asc003 = {in2, 5'B00000};
assign asc002 = +(in3) + (asc003);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc002;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0Add2Cati0u1u16u1_4_5 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input in2, ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [5:0] asc003;
assign asc003 = {in2, 5'B00000};
assign asc002 = +(in3) + (asc003);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc002;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0Add2Cati0u1u16u1_4_6 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input in2, ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [5:0] asc003;
assign asc003 = {in2, 5'B00000};
assign asc002 = +(in3) + (asc003);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc002;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0Add2Cati0u1u16u1_4_7 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input in2, ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [5:0] asc003;
assign asc003 = {in2, 5'B00000};
assign asc002 = +(in3) + (asc003);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc002;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0Add2Cati0u1u16u1_4_8 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input in2, ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [5:0] asc003;
assign asc003 = {in2, 5'B00000};
assign asc002 = +(in3) + (asc003);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc002;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0Add2Cati0u1u16u1_4_9 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input in2, ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [5:0] asc003;
assign asc003 = {in2, 5'B00000};
assign asc002 = +(in3) + (asc003);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc002;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_10 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_11 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_12 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_13 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_14 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_2 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_3 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_5 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Muxi0u16u1_4_6 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.57659 |
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