code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module st_weight_addr_gen_Add_16Ux8U_16U_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux8U_16U_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux8U_16U_4_12 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Add_16Ux8U_16U_4_13 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux8U_16U_4_14 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux8U_16U_4_15 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Add_16Ux8U_16U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Add_16Ux8U_16U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux8U_16U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux8U_16U_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux8U_16U_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Add_16Ux8U_16U_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux8U_16U_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux8U_16U_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_17S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_17S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_17S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_17S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_17S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_17Sx9U_18S_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [8:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +({in2[16], in2}) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_1Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_1Ux1U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_1Ux1U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_1Ux1U_2U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_1Ux1U_2U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_1Ux1U_2U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_1Ux1U_2U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_2Ux1U_2U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_2Ux1U_2U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_2Ux1U_2U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_2Ux1U_2U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_2Ux1U_3U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_2Ux1U_3U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_2Ux1U_3U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_2Ux1U_3U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4_12 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux16U_32U_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_32Ux32U_32U_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_12 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_13 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx16U_33S_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx32U_33S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [31:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx32U_33S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [31:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx32U_33S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [31:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx32U_33S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [31:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx32U_33S_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [31:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_33Sx32U_33S_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [32:0] in2;
input [31:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
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