code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module st_weight_addr_gen_Subi32u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_10 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_11 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_12 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_13 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Subi32u16_4_14 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_5 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_6 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_7 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_8 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Subi32u16_4_9 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_16U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_16U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_16U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_16U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_16U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_17S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_17S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_17S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_17S_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_12 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
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module st_weight_addr_gen_Sub_16Ux16U_17S_4_13 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_14 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_15 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux16U_17S_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux1U_17S_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_12 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_13 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_14 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Sub_16Ux6U_17S_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module for the st_weight_addr_gen module.
*
* This module contains the followng items:
* - A foreign module definition for use in instantiatin the type_wrapper module
* which contains the BEH module instance.
* - An instance of the type_wrapper foreign module.
* - alwyas blocks each type_wrapper output.
*
******... | 7.408523 |
module BRAM (
clk,
add,
data_in,
data_out,
cs,
we,
oe
);
// parameters
parameter varWIDTH = 32; // number of bits in a word
parameter ADD_WIDTH = 10; // number of bits in the address
parameter PIPE_WIDTH = 16; // number of words in the output
// inputs
input clk, cs, we;
i... | 7.098866 |
module ram (
clk,
add,
data_in,
data_out,
cs,
we,
oe
);
parameter varWIDTH = 32; // number of bits in the output
parameter ADD_WIDTH = 10; // number of bits in the address
parameter FILENAME = "";
localparam [63:0] RAM_SIZE = 1 << ADD_WIDTH; // ram size
//input declaration
in... | 7.56569 |
module ram_tb ();
parameter DATA_WIDTH = 32; // number of bits in the output
parameter ADD_WIDTH = 4; // number of bits in the address
parameter RAM_SIZE = 1 << ADD_WIDTH; // ram size
parameter PIPE_SIZE = 4;
reg clk, cs, we, oe;
reg [ADD_WIDTH-1:0] add;
reg [DATA_WIDTH-1:0] data_in;
wire [DATA_WID... | 7.127235 |
module distcalc_euclid (
clk,
EN_Pipe,
EN_Acc,
EN_Sqrt,
RST_Acc,
RST_Sqrt,
PRE_Acc,
invec0,
invec1,
RDY_Pipe,
RDY_Acc,
RDY_Sqrt,
outval
);
//Parameters
parameter VARWIDTH = 32;
parameter PIPEWIDTH = 16;
//Inputs
input clk;
input EN_Pipe;
input EN_Acc;
... | 7.057303 |
module distance_test;
localparam varWIDTH = 32;
localparam pipeWIDTH = 16;
localparam HEADER_LENGTH = 2;
parameter ADD_WIDTH = 12; // what should the maximum value be?
/* Pulse input */
reg clk, START;
wire en_a, en_s;
wire rdy_p, rdy_a, rdy_s;
wire rst_a, rst_s, pre_a;
wire [ADD_WIDTH-1:0] bram_a... | 7.013026 |
module pipes_diffsquare (
EN,
vals0,
vals1,
pipeout
);
parameter WIDTH = 16; //size of each vals vector
//local parameters
localparam VARWIDTH = 32;
//input declaration
input EN;
input [VARWIDTH*WIDTH-1:0] vals0, vals1;
wire [VARWIDTH-1:0] in_vals0[0:WIDTH-1];
wire [VARWIDTH-1:0] in_val... | 7.791017 |
module diffsquared32 (
a,
b,
out
);
localparam VARWIDTH = 32;
//input declarations
input [VARWIDTH-1:0] a, b;
//output declarations
output [VARWIDTH-1:0] out;
wire [VARWIDTH-1:0] out;
//internal wires declaration
wire [VARWIDTH-1:0] sum;
wire [VARWIDTH-1:0] float;
wire [VARWIDTH-1:0] squ... | 7.985967 |
module squareroot (
EN,
clk,
rst,
a,
rdy,
sqrt
);
parameter WIDTH = 32;
//input declaration
input EN, clk, rst;
input [WIDTH - 1:0] a;
//output declaration
output rdy;
wire rdy;
output [WIDTH - 1:0] sqrt;
reg [WIDTH - 1:0] sqrt;
//internal data types
reg rst_internal;
wir... | 8.070748 |
module sub2 (
input [4:0] a_e,
output [4:0] sub_a_e
);
assign sub_a_e = 15 - a_e;
endmodule
| 6.873213 |
module is same with IP c_addsub_v12 in function and utilization
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
(* use_dsp48 = "yes" *) module sub28(A, B, CLK, CE, SCLR, S);
input s... | 6.593332 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1... | 6.821676 |
module main (
input [3:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
Sub2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module is same with IP c_addsub_v12 in function and utilization
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
(* use_dsp48 = "yes" *) module sub_48b(A, B, CLK, CE, SCLR, S);
input... | 6.593332 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(ins... | 7.507677 |
module main (
input [7:0] J1,
output [3:0] J3
);
wire [3:0] inst0_O;
Sub4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module main (
input [7:0] SWITCH,
output [3:0] LED
);
wire [3:0] inst0_O;
Sub4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module sub8 (
output wire [7:0] out,
input wire [7:0] A,
input wire [7:0] B
);
assign out = A - B;
endmodule
| 7.904405 |
module subbytes_block #(
// PARAMETERS.
parameter NB_BYTE = 8,
parameter N_BYTES = 16,
parameter CREATE_OUTPUT_REG = 0,
parameter USE_LUT = 1
) (
// OUTPUTS.
output wire [N_BYTES * NB_BYTE - 1 : 0] o_state,
// INPUTS.
input wire [N_BYTES * NB_BYTE - 1 :... | 6.840381 |
module subBytes_mem (
clk,
rst,
W_En,
R_En,
addr_in,
addr_out,
in,
out
);
input wire clk, rst, W_En, R_En;
input wire [3:0] addr_in, addr_out;
input wire [7:0] in;
output reg [7:0] out;
reg [7:0] ram[0:15];
integer i;
always @(posedge clk or negedge rst) begin
if (!rs... | 6.720435 |
module subBytes (
input [31:0] input_col,
output [31:0] output_col
);
//A song of Wires and Regs
reg [31:0] working_reg;
assign output_col = working_reg;
wire [7:0] output_col_byte1, output_col_byte2, output_col_byte3, output_col_byte4;
sbox SBOX (
.input_byte (input_col[7:0]),
.output... | 7.325733 |
module subByte_rowShift (
input clk,
input rst_n,
input [127 : 0] iBlockIn,
output reg [127 : 0] oBlockout
);
wire [127 : 0] wSubOut, wRotShift;
//字节替换逻辑，用8个双口rom实现
rom_2p rom_2p_inst0 (
.address_a(iBlockIn[127 : 120]),
.address_b(iBlockIn[119 : 112]),
.clock(clk),
.q_a(w... | 7.970927 |
module subchannel_sw (
input clk,
input reset,
input clear,
//Data and code inputs.
input ca_bit,
input [ (INPUT_WIDTH-1):0] data_i,
input [ (INPUT_WIDTH-1):0] data_q,
... | 6.653672 |
module subc_ctl ( /*AUTOARG*/
// Outputs
nack,
rt_rst,
// Inputs
ai2cb,
ack,
eof,
rt_ra,
rt_err,
rst_n
);
input ai2cb; // the ack from output ports
input ack; // the ack from the last stage of the input buffer
input eof; // the eof bit from the last stage of the input ... | 7.498287 |
module Suber (
input [31:0] data1,
input [31:0] data2,
output reg [31:0] result,
output reg zero,
output reg neg
);
/* Inputs declaration */
wire signed [31:0] data1;
wire signed [31:0] data2;
/* Main function */
always @(*) begin
result = data1 - data2;
z... | 7.580376 |
module subErrCtrlSplitter (
err_en,
err_ctrl,
sub_err_en,
sub_err_ctrl
);
parameter INW = 1; // Input bitwidth
parameter OUTW = 1; // Output bitwidth
parameter LOW = 0; // Lower limit for the submodule's error control
parameter HIGH = 1; // Upper limit for the submodule's error control
in... | 8.571143 |
module subkeys (
select,
key,
k1,
k2,
k3,
k4,
k5,
k6,
k7,
k8,
k9,
k10,
k11,
k12,
k13,
k14,
k15,
k16
);
input [64:1] key;
input select;
output [48:1] k1;
output [48:1] k2;
output [48:1] k3;
output [48:1] k4;
output [48:1] k5;
output ... | 7.044768 |
module z_add (
input x,
input y,
output [1:0] z
);
assign z = x + y;
endmodule
| 8.007447 |
module subordinate_verification #(
parameter C_AXI_ADDR_WIDTH = 4,
localparam C_AXI_DATA_WIDTH = 32
) (
// {{{
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
//
input wire S_AXI_AWVALID,
output wire ... | 6.738562 |
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