code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_tx;
reg clk;
reg rst_n;
reg we;
reg stb;
reg cyc;
reg [2:0] addr;
reg [7:0] data_o;
wire [7:0] data_i;
wire ack;
wire irq;
wire uart_pin;
reg [7:0] rx_data;
reg [7:0] irq_data;
nexi_uart_16550a_wb uart1 (
.clk_i (clk),
.rst_ni(rst_n),
.we_i (we),
.stb_i ... | 6.681822 |
module tb_picosoc;
reg clk;
wire [7:0] test_led;
reg [7:0] test_button = 0;
reg [7:0] test_switch = 0;
wire ser_tx;
reg ser_rx = 1'b1;
localparam ser_half_period = 217;
event ser_sample;
reg [7:0] buffer = {(8) {1'bz}};
reg [7:0] rx_buffer = {(8) {1'bz}};
tri1 test_scl, test_sda;
reg i2c_sl... | 6.809553 |
module tb_uC_8Bit ();
//define inputs
reg _clk, _reset;
//define outputs
wire [5:0] _cycle;
wire [7:0] _romAddress;
wire [7:0] _instructionReg, _programCounter;
wire [7:0] _R0, _R1, _R2, _R3;
wire [7:0] _Rhi, _Rlo, _Rquotient, _Rremainder;
wire _ramWrite;
wire [7:0] _ramAddress;
wire [7:0] _romO... | 6.632825 |
module tb_umi_data_aggregator #(
parameter TARGET = "DEFAULT", // pass through variable for hard macro
parameter TIMEOUT = 5000, // timeout value (cycles)
parameter PERIOD_CLK = 10 // clock period
) ();
// Local parameters
localparam STIMDEPTH = 1024;
localparam TCW = 8;
loca... | 6.502342 |
module tb_unsigned_divide_multicycle ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_unsigned_divide_multicycle.vcd");
$dumpvars(0, tb_unsigned_divide_multicycle);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE ... | 7.569862 |
module tb_unsigned_multiply_multicycle ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_unsigned_multiply_multicycle.vcd");
$dumpvars(0, tb_unsigned_multiply_multicycle);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #... | 6.56698 |
module tb_unsigned_sqrt_multicycle ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_unsigned_sqrt_multicycle.vcd");
$dumpvars(0, tb_unsigned_sqrt_multicycle);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100.... | 7.192979 |
module tb_upcntr;
// Inputs
reg clk, reset;
// Outputs
wire [3:0] cnt;
// Instantiate the Unit Under Test (UUT)
upcntr uut (
.clk (clk),
.reset(reset),
.cnt (cnt)
);
initial begin
$dumpfile("tb_upcntr.vcd");
$dumpvars(0, tb_upcntr);
// Initialize Inputs
clk = 0;
... | 7.679218 |
module tb_updown ();
reg [3:0] IN;
reg Up, Down, Load;
reg CLK = 0;
wire [3:0] OUT;
updown DUT (
OUT,
Up,
Down,
Load,
IN,
CLK
);
always #10 CLK = ~CLK;
initial begin
IN = 4'b1111;
Load = 1'b1;
Up = 1'b0;
Down = 1'b0;
#15 Load = 1'b0;
... | 6.734584 |
module tb_up_dn_cntr;
// Inputs
reg clk, reset, up_dnb;
// Outputs
wire [3:0] cnt;
// Instantiate the Unit Under Test (UUT)
up_dn_cntr uut (
.clk(clk),
.reset(reset),
.up_dnb(up_dnb),
.cnt(cnt)
);
initial begin
$dumpfile("tb_up_dn_cntr.vcd");
$dumpvars(0, tb_up_dn_cntr)... | 7.483354 |
module tb_up_dn_cntr_with_load;
// Inputs
reg clk, reset, load_en, up_dnb;
reg [3:0] load_data;
reg load_en_1, load_en_2;
// Outputs
wire [3:0] cnt;
// Instantiate the Unit Under Test (UUT)
up_dn_cntr_with_load uut (
.clk(clk),
.reset(reset),
.load_en(load_en),
.load_data(load_d... | 7.483354 |
module tb_up_dn_cntr_with_load_with_start_stop;
// Inputs
reg clk, reset, load_en, up_dnb, start_stop_b;
reg [3:0] load_data;
reg load_en_1, load_en_2;
// Outputs
wire [3:0] cnt;
// Instantiate the Unit Under Test (UUT)
up_dn_cntr_with_load_with_start_stop uut (
.clk(clk),
.reset(reset),
... | 7.483354 |
module XORSHIFT #(
parameter WIDTH = 32,
parameter SEED = 1
) (
input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL
);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t... | 6.534691 |
module tb_util ();
task assert_equals;
input [31:0] expected;
input [31:0] actual;
begin
if (actual === expected) $display("OK!");
else begin
$display("ERRO! @ %t , Esperado: %d, Obteve %d", $time, expected, actual);
$stop;
end
end
endtask
// Gera numeros aleat... | 7.867543 |
module testbench;
reg clk_tb, reset_tb;
reg [31:0] data_tb; // asynchronous
reg [31:0] s_data_fill; // asynchronous
parameter halfperiod = 5;
parameter reset_delay = 100;
wire [31:0] data; // synchronous
wire valid, ready; // valid asynchronous && ready asynchronous
wire valid_var;
master m0 (
... | 7.015571 |
module at each clock negative edge assuming the DFF is posedge triggered
*/
// TB clock generator
module CLK_GEN #(
parameter CLK_PERIOD = 10
)
(
output reg clk
);
initial begin
clk<=0;
forever #(CLK_PERIOD/2) clk<=~clk;
end
endmodule
| 6.819689 |
module TB;
// TB settings and local args
localparam CLK_PERIOD = 10;
integer idx = 0;
// signals driven by us
reg reset; // sequence detector reset signal
reg seq; // sequence detector 1-bit seq. input
// signals driven by duts and bus drivers/generators
wire out, clk;
// student ID
re... | 7.89986 |
module testbench;
reg clk_tb, reset_tb;
reg [31:0] data_tb; // asynchronous
parameter halfperiod = 5;
parameter reset_delay = 100;
wire [31:0] data; // synchronous
wire valid, ready; // synchronous
wire valid_var; // asynchronous
master m0 (
.clk(clk_tb),
.reset(reset_tb),
.tran... | 7.015571 |
module tb_vct ();
parameter H_Active = 1920;
parameter H_FrontPorch = 88;
parameter H_SyncWidth = 44;
parameter H_BackPorch = 148;
parameter V_Active = 1080;
parameter V_FrontPorch = 4;
parameter V_SyncWidth = 5;
parameter V_BackPorch = 36;
reg vtc_rst_n;
reg vtc_pix_clk;
wire vtc_vs_o;
wir... | 6.96521 |
module: vector_mac
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_vector_mac;
parameter VECTOR_LEN = 5, // number of elements in the vectors
A_CELL_WID... | 6.80325 |
module tb_vedic3bit;
reg [2:0]A,B; //ports declared
wire [5:0]mul;
vedic3bit M(A,B,mul);// module instantiation
initial //various test inputs
begin
A=3'b001;
B=3'b010;
#1 A=3'b010;
B=3'b100;
#1A=3'b100;
B=3'b101;
#1 A=3'b101;
B=3'b110;
#1A=3'b110;
B=3'b111;
end
e... | 7.285089 |
module tb_VGATest ();
reg clk;
wire [7:0] red;
wire [7:0] green;
wire [7:0] blue;
wire hsync;
wire vsync;
wire blankN;
wire vgaClk;
wrapper_VGATest uut (
.clk(clk),
.red(red),
.green(green),
.blue(blue),
.hsync(hsync),
.vsync(vsync),
.blankN(blankN),
.v... | 6.826965 |
module tb_vga_char ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire [15:0] rgb;
wire ... | 8.141251 |
module tb_vga_colorbar ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire [15:0] rgb;
wire ... | 8.73909 |
module tb_vga_ctrl ();
reg clk;
reg rst_n;
reg [15:0] in_rgb;
vga_ctrl component (
.clk(clk),
.rst_n(rst_n),
.in_rgb(in_rgb)
);
initial begin
clk = 1'b1;
rst_n = 1'b0;
in_rgb = 15'b0;
#10 rst_n = 1'b1;
#5000000 $finish;
end
always #1 clk = ~clk;
always #16 in... | 6.69603 |
module tb_vga_main ();
reg clk;
wire hsync, vsync;
wire [3:0] red;
wire [3:0] blue;
wire [3:0] green;
vga_main vga0 (
.clk(clk),
.io ({red, green, blue, vsync, hsync})
);
// 50 Mhz clock (20 ns period, so 10 ns between state changes)
// NOTE: adjust as required based on your dev board's... | 7.12936 |
module tb_vga_rom_pic ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire [15:0] rgb;
wire ... | 8.690512 |
module tb_vga_rom_pic_jump ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire [15:0] rgb;
wire... | 8.690512 |
module tb_vga_uart_pic ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire vsync;
wire [7:0... | 7.201704 |
module tb_video_gate ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_video_gate.vcd");
$dumpvars(0, tb_video_gate);
#10000000 $finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
parameter TUSER_WIDTH = 1;
param... | 7.511809 |
module tb_vmicro16_core;
// Inputs
reg clk;
reg reset;
// Instantiate the Unit Under Test (UUT)
vmicro16_core uut (
.clk (clk),
.reset(reset)
);
always #10 clk = ~clk;
// Nanosecond time format
initial $timeformat(-9, 0, " ns", 10);
initial begin
// Initialize Inputs
clk ... | 7.204079 |
module tb_vmicro16_soc;
// Inputs
reg clk;
reg reset;
// Create clock signal
always #10 clk = ~clk;
// Instantiate the Unit Under Test (UUT)
vmicro16_soc uut (
.clk (clk),
.reset(reset)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
// Assert reset for n ... | 7.365637 |
module tb_vmicro16_soc_prog;
// Inputs
reg clk;
reg reset;
reg uart_rx;
// Create clock signal
always #10 clk = ~clk;
///////////////////////////////////////////////
// task from https://www.edaplayground.com/x/4Lyz
//////////////////////////////////////////////
// Testbench uses a 25 MHz clock ... | 7.365637 |
module tb_vmicro16_soc;
// Inputs
reg clk;
reg reset;
wire halt;
wire [`APB_GPIO1_PINS-1:0] gpio1;
// Create clock signal
always #10 clk = ~clk;
// Instantiate the Unit Under Test (UUT)
vmicro16_soc uut (
.clk (clk),
.halt (halt),
.gpio1(gpio1),
.reset(reset)
);
initi... | 7.365637 |
module tb_voting_machine ();
reg t_clk;
reg t_rst;
reg t_candidate_1;
reg t_candidate_2;
reg t_candidate_3;
reg t_vote_over;
wire [5:0] t_result_1;
wire [5:0] t_result_2;
wire [5:0] t_result_3;
//instansiate component unit under test
voting_machine uut (
.clk(t_clk),
.rst(t_rst),
... | 7.006023 |
module simulates the generation of the video timing signals. It
// generates the hsync and vsync and blank timing signals.
//
module timing_gen #(
parameter DLY = 1,
parameter INTERLACE = 0
)
(
input wire clk,
input wire rst,
input wire ce,
input wire [13:0] active_li... | 6.687085 |
module simulates the AXI-4 streaming interface to the video bridge
// it generates handshaking, and regenerates the x,y pixel location based on eol and
// sof. From the pixel location, it creates an expected data value and compares
// this to the incoming video data.
//
module axis_emulation #(
parameter DLY = 1
... | 6.687085 |
module tb ();
reg [31:0] A;
reg [31:0] B;
wire [63:0] out;
initial begin
A = 32'hffffffff;
B = 32'hffffffff;
#10 A = 32'd4;
B = 32'd9;
#10 A = 32'h666;
B = 32'h44321;
#10 A = 32'h90012345;
B = 32'h54321;
#10 A = 32'h88888888;
B = 32'h55735;
#10 A = 32'hff431234;
... | 7.195167 |
module tb_warmup2_mpadder();
// Define internal regs and wires
reg clk;
reg reset;
reg instart;
reg [127:0] inA;
reg [127:0] inB;
wire [128:0] outC;
wire outdone;
warmup2_mpadder dut(
clk,
reset,
instart,
inA,
... | 7.099165 |
module tb_warpv ();
reg clock;
reg rst;
wire led;
cpu warpv (
.clk (clock),
.reset(rst),
.led (led)
);
initial begin
$dumpfile("./../Simulation/out.vcd");
$dumpvars(0, tb_warpv);
rst = 1;
clock = 0;
#200 rst = 0;
end
// generate clock
always #(5) clock = ... | 7.226376 |
module tb_water_led ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire [3:0] led_out;
//reg define
reg ... | 7.609034 |
module tb_waveform_from_pipe_bram ();
reg reset;
reg pipe_clk;
reg pipe_in_write;
reg [15:0] pipe_in_data;
reg pop_clk;
wire [31:0] wave;
wire [10:0] pipe_addr;
wire [10:1] pop_addr;
initial begin
reset = 0;
pipe_clk = 0;
pipe_in_write = 0;
pipe_in_data = 16'd0;
pop_clk = 0;
... | 6.512514 |
module: weight_controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_weight_controller;
parameter NEURON_NUM = 4, // number of cells in the vectors a and delta... | 7.420654 |
module: weight_updater
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_weight_updater;
parameter NEURON_NUM = 5, // size of the vectors a and delta
ACTI... | 6.92769 |
module: weight_updater
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_weight_updater_error;
parameter NEURON_NUM = 5, // size of the vectors a and delta
... | 6.92769 |
module: mem_test_with_soc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_whole_system_mem_and_soc;
// Inputs
reg clk;
reg reset;
reg rx;
reg interrupt;
reg bit8;
reg pari... | 7.727194 |
module tb_window ();
reg clk;
reg [11:0] in1, in2;
wire [11:0] out1, out2;
wire next;
wire [2:0] state;
integer i;
initial clk = 0;
always #400 clk = ~clk;
windowing windowing_inst (
.clk (clk),
.in1 (in1),
.in2 (in2),
.out1 (out1),
.out2 (out2),
.next (next),
... | 6.756002 |
module: window_on_background
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_window_on_background;
// Inputs
reg clk;
reg mode;
// Outputs
wire [2:0] r;
wire [2:0] g;
wir... | 7.550897 |
module tb_wire_assign;
reg in;
wire out;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
wire_assign UUT (
.in (in),
.out(out)
);
initial // initial block executes only once
begin
// values for inputs
in = 0;
#period; // wait for p... | 6.855927 |
module tb_wm8978_cfg ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire i2c_scl;
wire i2c_sda;
//reg define
... | 7.503996 |
module tb_writeback ();
localparam STEP = 10;
parameter OP_LOAD = 7'b0000011;
parameter OP_STORE = 7'b0100011;
parameter OP_BRANCH = 7'b1100011;
parameter OP_IMM = 7'b0010011;
parameter OP_OP = 7'b0110011;
parameter OP_JUMP = 7'b1101111;
reg [6 : 0] opcode;
reg [31 : 0] alu_out;
reg wb_reg;
r... | 6.713494 |
module : tb_writeback_unit
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in t... | 7.713825 |
module : tb_writeback_unit_CSR
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* ... | 7.713825 |
module tb_writer (
clk,
resetn,
data_in,
// data_valid_in, // Edit here
done,
image_class,
fifo_rdreq, // Edit here
// fifo_data,
fifo_empty // Edit here
);
parameter DWIDTH = 32;
parameter output_file = "";
//
parameter WIDTH = 56;
parameter HEIGHT = 56;
parameter... | 7.571256 |
module tb_write_axi_buffer ();
reg clk;
reg rst;
localparam LINE_SIZE = 8;
reg en;
reg addr;
reg [32*LINE_SIZE-1:0] data;
wire empty;
initial begin
repeat (300) begin
#5 clk = 1'b1;
#5 clk = 1'b0;
end
end
wire [3 : 0... | 7.029376 |
module tb_write_full ();
reg w_en;
reg w_clk;
reg w_rst;
reg [4:0] read_addr_gray_sync, temp, write_addr_gray;
wire [3:0] write_addr;
wire flag_full;
integer i;
initial begin
w_clk = 0;
w_rst = 0;
#20 w_rst = 1;
#40 w_rst = 0;
end
initial begin
for (i = 0; ... | 6.884622 |
module TB_x64_adc()
/* Inputs from ADC */
output adc_clk_n,
output adc_clk_p,
output [7:0] in_0_n,
output [7:0] in_0_p,
output fc_0_n,
output fc_0_p,
output [7:0] in_1_n,
output [7:0] in_1_p,
output ... | 6.963298 |
module tb_xdom_pulse_sender;
reg grst_i;
reg odom_clk_i;
reg odom_pulse_i;
reg xdom_clk_i;
wire xdom_pulse_o;
wire busy_o;
wire err_o;
xdom_pulse_sender uut (
.grst_i(grst_i),
.odom_clk_i(odom_clk_i),
.odom_pulse_i(odom_pulse_i),
.xdom_clk_i(xdom_clk_i),
.xdom_pulse_o... | 7.311821 |
module xnor_gate_top;
reg I0, I1;
wire Out;
xnor_gate gate0 (
I0,
I1,
Out
);
initial begin
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 0;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 1;
#1;
$display("I0 : %... | 6.65772 |
module.
`timescale 1ns/1ns
`include "my_xor.v"
module tb_xor;
reg [1:0]bus;
wire out;
my_xor test_xor(bus, out);
initial begin
$dumpfile("tb_xor.vcd");
$dumpvars(0, tb_xor);
bus = 2'b11;
#10;
bus = 2'b00;
#10;
bus = 2'b10;
#10;
bus = 2'b01;
... | 6.603418 |
module tb_xpsr_reg ();
reg [31:0] inst;
reg clk;
reg rst;
reg en_apsr;
reg en_ipsr;
reg en_epsr;
reg en_carry;
reg inst_valid;
wire [4:0] apsr;
wire [8:0] ipsr;
wire [9:0] epsr;
integer fd;
xpsr_reg u0 (
inst,
clk,
rst,
en_apsr,
en_ipsr,
en_epsr,
en... | 6.56803 |
module: tv80n_wrapper
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_z80_y_spi;
// Inputs
reg reset_n;
reg sysclk;
reg [7:0] cpudin;
// Outputs
wire m1_n;
wire mreq_n;
... | 6.539653 |
module tb_ZF;
// Input testcase spec:
parameter BID_WIDTH = 32;
parameter TEST_NUM = 1000;
//////////////////////////////////////////////////////////////////////
parameter H_width = BID_WIDTH * 16;
parameter y_width = BID_WIDTH * 8;
parameter link_to_H_binary = "C:/Users/ROG STRIX/Desktop/projecy/me... | 8.455647 |
module tb_zigzag ();
reg clk_i;
reg rstn_i;
reg [ `RUN_BIT-1:0] hd_run_i;
reg [ `CAT_BIT-1:0] hd_cat_i;
reg hd_gecerli_i;
wire hd_hazir_o;
wire [`PIXEL_BIT-1:0] ct_veri_o;
wire [`BLOCK_BIT-1:0] ct_row_o;
wire [`BLOCK_BIT-1:0] ... | 7.533416 |
module: zxuno
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_zxuno;
// Inputs
reg clk;
reg wssclk;
reg ramclk;
reg power_on_reset_n;
reg clkps2;
reg dataps2;
reg ear... | 7.354907 |
module ram512kb (
input wire [18:0] a,
inout wire [7:0] d,
input wire we_n
);
reg [7:0] ram[0:524287];
integer i;
initial begin
for (i = 0; i < 524288; i = i + 1) ram[i] = 0;
end
reg [7:0] dout;
assign d = (we_n == 1'b0) ? 8'hZZ : dout;
always @* begin
if (we_n == 1'b0) ram[a] = d;
... | 7.071599 |
module tb__ghash_core_vs_ghash_core_koa ();
// PARAMETERS.
localparam NB_BLOCK = 128;
localparam N_BLOCKS = 2;
localparam NB_DATA = NB_BLOCK * N_BLOCKS;
// OUTPUTS.
wire [ NB_BLOCK-1:0] tb_o_data_y_KOA;
wire [ NB_BLOCK-1:0] tb_o_data_y_N_BLK;
// INPUTS.
reg [ NB_DATA-1:0] tb_i_data_x_bus;... | 6.994495 |
module tc16a (
input [15:0] D,
input CMP,
output [15:0] Y
);
// internal signals
assign Y = (CMP ? ~D : D) + CMP;
endmodule
| 7.954677 |
module tc18a (
input [17:0] D,
input CMP,
output [17:0] Y
);
// internal signals
assign Y = (CMP ? ~D : D) + CMP;
endmodule
| 6.677291 |
module: TC1_traffic_light_controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TC1_traffic_light_controller_test;
// Inputs
reg clk;
reg sync_reset;
// Outputs
//wire st... | 7.203423 |
module: TC1_traffic_timer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TC1_traffic_timer_test;
// Inputs
reg start;
reg clk;
// Outputs
wire tMG;
wire tMY;
wire tSG;
wir... | 7.203423 |
module tc8s (
input [7:0] D,
input CMP,
output [7:0] Q,
input CE,
input CLK,
input SCLR
);
// internal signals
reg [7:0] s;
always @(posedge CLK) begin
if (SCLR) s <= 0;
else if (CE) s <= (CMP ? ~D : D) + CMP;
end
assign Q = s;
endmodule
| 6.77376 |
module TCAM_Adapter (
// inputs
clk,
rst,
i_Key,
i_Set_String,
i_Set_ID,
i_Set_Enable,
// outputs
o_RuleID,
o_Valid,
o_SetDone
);
// ==========================================================================
// == Parameters
// ======================================... | 8.038288 |
module tcam_bl (
clk,
cmp_data_mask,
cmp_din,
data_mask,
din,
we,
wr_addr,
busy,
match,
match_addr
);
input clk;
input [31 : 0] cmp_data_mask;
input [31 : 0] cmp_din;
input [31 : 0] data_mask;
input [31 : 0] din;
input we;
input [10 : 0] wr_addr;
output busy;
... | 6.538496 |
module upb_tcam_entry #(
parameter SRL_SIZE = 32, // use 32 here to generate SRLC32E instances
parameter TCAM_WIDTH = 49, // number of SRLs in parallel, so total width is log2(SRL_SIZE) * TCAM_WIDTH
parameter INPUT_WIDTH = 32, // input width for feeding data in
parameter FORCE_MUXCY = 0 // force usa... | 8.944739 |
module tcam_entry_tb;
logic CLK;
logic RST;
logic [9:0] content;
logic wdata;
logic waddr;
logic wen;
wire match;
// UUT
upb_tcam_entry #(
.SRL_SIZE(32), // use 32 here to generate SRLC32E instances
.TCAM_WIDTH(2), // number of SRLs in parallel, so total width is log2(SRL_SIZE) * TCA... | 7.322655 |
module tcam_line_array #(
parameter ADDR_WIDTH = 8,
parameter KEY_WIDTH = 8,
parameter MASK_DISABLE = 0
) (
input wire clk,
input wire rst,
input wire [ADDR_WIDTH-1:0] set_addr,
input wire [KEY_WIDTH-1:0] set_key,
input wire [KEY_WIDTH-1:0] set_xmask,
input wire set_clr,
input wi... | 8.524502 |
module tcam_line_encoder #(
parameter ADDR_WIDTH = 8
) (
input wire clk,
input wire rst,
input wire [2**ADDR_WIDTH-1:0] line_match,
input wire line_valid,
output wire [ADDR_WIDTH-1:0] addr,
output wire addr_valid,
output wire addr_null
);
reg encode;
reg [2**ADDR_WIDTH-1:0] line;
... | 7.198534 |
module tcam_lpm_bhv #(
parameter CDEP = 512, // CAM depth
parameter PWID = 32, // CAM/pattern width
parameter INOM = 1
) // binary / Initial CAM with no match (has priority over IFILE)
(
input clk, // clock
input rst, // global registers reset
... | 6.669445 |
module tcam_rtl
#(
parameter ADDR_WIDTH = 4,
parameter DATA_WIDTH = 32
)
(
input CLK,
input WR,
input [ADDR_WIDTH-1:0] ADDR_WR,
input [DATA_WIDTH-1:0] DIN,
input [DATA_WIDTH-1:0] DIN_MASK,
... | 7.302543 |
module tcam_sdpram #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 8,
parameter RAM_STYLE = "block"
) (
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] dina,
input wire [ADDR_WIDTH-1:0] addra,
input wire [ADDR_WIDTH-1:0] addrb,
input wire wea,
output wire [DATA_W... | 7.168283 |
module tcam_unit_test_logic #(
parameter TCAM_UNIT_ADDR = 0,
DPL_MATCH_FIELD_WIDTH = 16,
TCAM_ADDR_WIDTH = 10
) (
clk,
reset,
tcam_program_data,
tcam_program_mask,
tcam_program_addr,
tcam_program_enable,
of_match_field_data,
of_matched_addr_out,
of_matched_out
);
in... | 7.216543 |
module tcam_wrapper #(
parameter C_TCAM_ADDR_WIDTH = 4,
parameter C_TCAM_DATA_WIDTH = 16,
parameter C_TCAM_ADDR_TYPE = 0,
parameter C_TCAM_MATCH_ADDR_WIDTH = 4
) (
input CLK,
input WE,
input [C_TCAM_ADDR_WIDTH-1:0] WR_ADDR,
input [C_TCA... | 7.224859 |
module GAN2MCOD2BWP12T30P140 (
A1,
A2,
Z
);
input A1, A2;
output Z;
and (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.522351 |
module GOR2MCOD1BWP12T30P140 (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.517419 |
module GOR2MCOD2BWP12T30P140 (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.54915 |
module MAOI222D4BWP12T30P140 (
A,
B,
C,
ZN
);
input A, B, C;
output ZN;
and (I0_out, A, B);
and (I1_out, B, C);
and (I2_out, A, C);
or (I3_out, I0_out, I1_out, I2_out);
not (ZN, I3_out);
specify
if (B == 1'b1 && C == 1'b0) (A => ZN) = (0, 0);
if (B == 1'b0 && C == 1'b1) (A => ZN... | 6.533397 |
module BUFFD20BWPHVT (
I,
Z
);
input I;
output Z;
buf (Z, I);
specify
(I => Z) = (0, 0);
endspecify
endmodule
| 6.587266 |
module GBUFFD2BWPHVT (
I,
Z
);
input I;
output Z;
buf (Z, I);
specify
(I => Z) = (0, 0);
endspecify
endmodule
| 6.539864 |
module INVD20BWPHVT (
I,
ZN
);
input I;
output ZN;
not (ZN, I);
specify
(I => ZN) = (0, 0);
endspecify
endmodule
| 6.534856 |
module LVLLHD2BWPHVT (
I,
Z
);
input I;
output Z;
buf (Z, I);
specify
(I => Z) = (0, 0);
endspecify
endmodule
| 6.542499 |
module OR2XD1BWPHVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.717048 |
module HCOSCIND1BWP (
A,
CIN,
CS,
S,
CO
);
input A, CIN, CS;
output S, CO;
xor (I0_out, A, CIN);
not (I1_out, I0_out);
tsmc_mux(
S, A, I1_out, CS
);
not (I2_out, CIN);
and (CO, I2_out, A);
specify
if (CIN == 1'b0 && CS == 1'b1) (A => CO) = (0, 0);
if (CIN == 1'b0 && ... | 6.678211 |
module HCOSCOND1BWP (
A,
CI,
CS,
S,
CON
);
input A, CI, CS;
output S, CON;
xor (I0_out, A, CI);
tsmc_mux(
S, A, I0_out, CS
);
and (I1_out, A, CI);
not (CON, I1_out);
specify
if (CI == 1'b1 && CS == 1'b1) (A => CON) = (0, 0);
if (CI == 1'b1 && CS == 1'b0) (A => CON) = (... | 6.583092 |
module OR4D4BWP (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 6.608187 |
module AN2D1GHVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
and (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.512103 |
module AN2D2GHVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
and (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.780109 |
module AN2D4GHVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
and (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.670093 |
module AN2D8GHVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
and (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.501076 |
module AN2XD1GHVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
and (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.58762 |
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