code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_swpwm ();
initial $dumpvars(1, tb_swpwm);
initial $dumpvars(1, u_svpwm);
reg rstn = 1'b0;
reg clk = 1'b1;
always #(13563) clk = ~clk; // 36.864MHz
initial begin
repeat (4) @(posedge clk);
rstn <= 1'b1;
end
reg [11:0] theta = 0;
wire signed [15:0] x, y;
wire [11:0] rho;
w... | 7.369538 |
module tb_swin_wrap ();
// Parameters for Simulation
parameter clk_period = 10; // ns, 100MHz
parameter start_delay = 30; // clk cycle
parameter rst_delay = 20;
parameter rst_period = 5;
// Simulation Input Config
parameter WORD_WIDTH = 16 * 8;
parameter STREAM_LEN = 512;
// configuration RAM Rel... | 8.174588 |
module: SwitchEncoder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module tb_SwitchEncoder;
// Inputs
reg [4:0] sw;
// Outputs
wire [6:0] seg7;
// Instantiate t... | 7.791457 |
module tb_sync ();
//===========================================================================//
// Inputs to UUT
//===========================================================================//
reg clk;
reg rst_n;
reg async_sig;
//=======================================================================... | 7.06281 |
module: Synchro
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_synchro;
// Inputs
reg dato;
reg clk;
// Outputs
wire ds;
// Instantiate the Unit Under Test (UUT)
Synchr... | 6.947666 |
module: pal_sync_generator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_syncs;
// Inputs
reg clk;
// Outputs
wire raster_int_in_progress;
wire [8:0] hcnt;
wire [8:0] vc... | 7.642223 |
module tb_sync_counter ();
reg clk, rst;
wire [3:0] out0, out1, out2, out3;
sync_counter tb_sync (
out0,
out1,
out2,
out3,
clk,
rst
);
initial begin
clk = 0;
rst = 0;
end
initial #27 rst = 1;
initial begin
repeat (1000) #5 clk = ~clk;
end
endmodule
... | 6.529403 |
module tb_sync_fifo();
parameter DATA_WIDTH = 8;
parameter FIFO_DEPTH = 8;
parameter AFULL_DEPTH = FIFO_DEPTH - 1; //阈值
parameter AEMPTY_DEPTH = 1;
parameter RDATA_MODE = 0;
reg clk ;
reg rst_n ;
reg wr_en ;
reg [DATA_WIDTH-1:0] wr_d... | 6.800565 |
module tb_sync_merge;
/*AUTOREG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire a1; // From U_SYNC_MERGE of sync_merge.v
wire a2; // From U_SYNC_MERGE of sync_merge.v
wire r0; // From U_SYNC_MERGE of sync_merge.v
// End of automatics
reg r1, r2;
... | 7.162017 |
module tv_syntex ();
//reg [3:0] opcode;
reg [ 7:0] eightBit;
reg [15:0] sixteenBit;
initial begin
// opcode = 4'b1000;
// case(opcode)
// `ADD:
// $display("passed");
// default:
// $display("failed");
// endcase
eightBit = 16'b11111111;
#10 sixteenBit = eightBit;
... | 7.445106 |
module tb_syn_fifo ();
parameter DATA_WIDTH = 8;
parameter FIFO_DEPTH = 16;
parameter ADDR_WIDTH = 4;
/* ports defination */
reg clk, rst_n;
// read signal
reg r_en;
wire [DATA_WIDTH - 1 : 0] r_data;
wire [ ADDR_WIDTH : 0] data_avail;
wire is_empty;
... | 7.811771 |
module syn_fifo_v1_Nb_top;
parameter W = 8, D = 8;
reg RSTn;
reg CLK;
reg [W-1:0] DATA_IN;
reg WR_EN;
reg RD_EN;
wire FULL;
wire EMPTY;
wire [W-1:0] DATA_OUT;
syn_fifo_v1_Nb #(
.BUS_WIDTH (W),
.FIFO_DEPTH(D)
) fifo (
.RSTn(RSTn),
.CLK(CLK),
.DATA_IN(DATA_IN),
... | 7.046492 |
module tb_sysArr ();
parameter width_height = 4;
localparam weight_width = 8 * width_height;
localparam sum_width = 16 * width_height;
localparam data_width = 8 * width_height;
// inputs to DUT
reg clk;
reg active;
reg [data_width-1:0] datain;
reg [weight_width-1:0] win;
reg [sum_width-1:0] sumin;
... | 6.677419 |
module tb_sysArr2x2 ();
reg clk, active;
reg [15:0] datain, win;
reg [31:0] sumin;
reg [ 1:0] wwrite;
wire [15:0] maccout1, maccout2;
wire [7:0] wout1, wout2, dataout1, dataout2;
wire wwriteout1, wwriteout2, activeout1, activeout2;
always begin
#5;
clk = ~clk;
end // always
sysArr2x2 DU... | 7.372966 |
module tb_sysArrRow ();
localparam row_width = 4;
localparam weight_width = 8 * row_width;
localparam sum_width = 16 * row_width;
// Inputs to DUT
reg clk;
reg active;
reg [7:0] datain;
reg [weight_width-1:0] win;
reg [sum_width-1:0] sumin;
reg [row_width-1:0] wwrite;
// Outputs from DUT
wire... | 6.95534 |
module tb_softusb ();
reg sys_clk;
reg sys_rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
/* 100MHz system clock */
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
sysctl dut (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a (csr_a),
.csr_we... | 6.540109 |
module tb_system;
reg clk24;
reg reset;
reg RX;
wire TX;
wire spi0_mosi, spi0_miso, spi0_sclk, spi0_cs0, spi0_cs1;
wire spi1_mosi, spi1_miso, spi1_sclk, spi1_cs0, spi1_cs1;
wire i2c0_sda, i2c0_scl;
wire [31:0] gp_out;
// 24MHz clock source
always #21 clk24 = ~clk24;
// reset
initial begin
`... | 6.988862 |
module: system_toplevel
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_systemToplevel_with_processor;
// Inputs
reg clk;
reg reset;
reg bit8;
reg parity_en;
reg odd_n_even... | 8.638014 |
module tb_m6502_system ();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam DEBUG = 0;
localparam DISPLAY_CYCLE_CTR = 0;
localparam CLK_HALF_PERIOD = 1;
localpa... | 7.920387 |
module tb;
reg TCLK, TMS, TRST;
wire [3:0] STATE;
parameter TCLK_CYCLE = 2; //clock cycle: 2ns(500MHz)
parameter NUM_OF_TEST = 64; //number of test
// Instantiation of DUT:
tap_controller tap_controller_dut (
.TCK (TCLK),
.TMS (TMS),
.TRST (TRST),
.STATE(STATE)
);
// Gener... | 7.51795 |
module tb_tb ();
// START USER CODE (Do not remove this line)
// User: Put your signals here. Code in this
// section will not be overwritten.
// END USER CODE (Do not remove this line)
real CLK_P_PERIOD = 10000.000000;
real CLK_N_PERIOD = 10000.000000;
real RESET_LENGTH = 160000;
// Internal... | 6.710348 |
module top_module (
output reg A,
output reg B
); //
// generate input patterns here
initial begin
A = 0;
B = 0;
#10 A = 1;
#5 B = 1;
#5 A = 0;
#20 B = 0;
end
endmodule
| 7.203305 |
module top_module ();
reg clk, in;
reg [2:0] s;
wire out;
q7 dut (
.clk(clk),
.in (in),
.s (s),
.out(out)
);
initial begin
clk = 0;
in = 0;
s = 3'd2;
#10 s = 3'd6;
#10 in = 1;
s = 3'd2;
#10 in = 0;
s = 3'd7;
#10 in = 1;
s = 3'd0;
#30 ... | 6.627149 |
module tb_test_impl_micron_controller ();
reg clk50MHz;
reg sw_0;
reg sw_1;
reg sw_6;
reg sw_7;
wire mwe_L;
wire moe_L;
wire madv_L;
wire mclk;
wire mub_L;
wire mlb_L;
wire mce_L;
wire mcre;
wire [23:0] maddr;
assign maddr[23] = 1'b0;
wire [7:0] debug_out;
wire [15:0] mdata;
wire re... | 6.541423 |
module tb_tdm_input;
reg mclk;
wire [7:0] cnt256_n;
wire [15:0] ch1_out;
wire [15:0] ch2_out;
wire bclk;
wire wclk;
wire tdm_in;
// Instantiate the Unit Under Test (UUT)
tdm_input uut (
.mclk(mclk),
.cnt256_n(cnt256_n),
.tdm_in(tdm_in),
.ch1_out(ch1_out),
.ch2_out(ch2_... | 7.31184 |
module tb_teclado_conta;
//Inputs
reg [3:0] lin, col;
reg bot_press;
//Output
wire [11:0] s;
//Instancia a unidade a ser testada
teclado_conta uut (
.lin(lin),
.col(col),
.bot_press(bot_press),
.s(s)
);
always begin
bot_press = 1'b1;
#10;
bot_press = 1'b0;
#... | 6.901708 |
module temp_tb ();
// Signal Declarations
reg [3:0] in; // Inputs
wire [6:0] out; // Outputs
// Unit Under Test Instantiation
seg7 UUT (
.in (in),
.out(out)
);
initial begin
in = 4'b0000;
#10
// Print Current
$display(
"in0 = %4b | out = %7b", in, out
);
... | 7.59098 |
module: TemperatureCalculator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_TemperatureCalculator;
// Inputs
reg [31:0] tc_base;
reg [7:0] tc_ref;
reg [15:0] adc_data;
//... | 8.396779 |
module: tensor_product
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_tensor_product;
parameter A_VECTOR_LEN = 5, // length of vector a
B_VECTOR_LEN ... | 6.562861 |
module: tensor_product
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_tensor_product_error;
parameter A_VECTOR_LEN = 5, // length of vector a
B_VECTOR_LEN... | 6.562861 |
module tb_ternary_operator_mux;
// Inputs
reg i0, i1, sel;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
ternary_operator_mux uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.y (y)
);
initial begin
$dumpfile("tb_ternary_operator_mux.vcd");
$dumpvars(0, tb_ternary_op... | 8.378489 |
module of t_buffer.v
// AUTHOR : cjh
// TIME : 2016-04-11 09:53:02
//-------------------------------------------------------------
/******** Time scale ********/
`timescale 1ns/1ps
/******** 测试模块 ********/
module tb_testbench();
reg clk;
reg reset;
reg [31:0] pc;
reg is_hit;
reg [31:0] tar_addr;
wire[3... | 7.91304 |
module: lb_clockCounter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_testClockCounter;
// Inputs
reg clk;
reg reset;
reg [19:0] value;
// Outputs
wire done;
// Instan... | 6.890798 |
module tb_test_ALU_reg ();
reg [15:0] data_in;
reg [1:0] mux_sel;
reg [3:0] seg_reg;
reg [3:0] adr_reg_a;
reg [3:0] adr_reg_b;
reg [7:0] op_in;
reg we;
reg clk;
reg a_reset_l;
wire valid_o;
wire [15:0] data_o;
test_ALU_reg test_ALU_reg_i (
.data_in(data_in),
.mux_sel(mux_sel),
... | 7.504545 |
module tb_test_dma ();
(* DONT_TOUCH = "TRUE" *)reg aclk;
(* DONT_TOUCH = "TRUE" *)reg rst_n;
// axi_vip_0_mem_stimulus slv();
initial begin
aclk <= 1;
rst_n <= 0;
forever #5 aclk <= ~aclk;
end
design_test_dma_wrapper block_design (
aclk,
rst_n
);
integer fid;
integer ... | 6.615993 |
module tb_test_master #(
parameter BUS_WIDTH = 32,
parameter CTRL_WIDTH = 8,
parameter WRITE_TRANSFER = 1
) (
input [BUS_WIDTH-1:0] bus_in,
input ack,
input clk,
output reg req,
output reg [BUS_WIDTH-1:0] bus_out,
input [CTRL_WIDTH-1:0] ctrl_in,
output [CTRL_WIDTH-1:0] ctrl_out
)... | 8.827078 |
module tb_test_mux;
reg clk;
reg [1:0] sel;
reg [31:0] i;
test_mux text_mux (
.clk(clk),
.i0 (0),
.i1 (0),
.i2 (0),
.i3 (0),
.i4 (0),
.b (b)
);
always #1 clk = ~clk;
initial begin
clk = 'b0;
for (i = 0; i < 10; i = i + 1) begin
@(posedge clk);
... | 7.137476 |
module tb_test_source;
reg clk = 1'b0;
reg [ 8:0] ch1;
reg [ 8:0] ch2;
reg [ 8:0] ch3;
reg [ 8:0] ch4;
wire [ 2:0] stream_channel_count;
wire [72:0] data;
wire ready;
initial begin
forever begin
#4 clk = 1'b0; // generate a clock
ch1 <= data[8:0];
ch2 <= d... | 7.537447 |
module tb_test_source_800_600_RGB_444_ch1;
reg clk = 1'b0;
initial begin
forever #10 clk = ~clk; // generate a clock
end
wire ready = 1'b1;
wire [ 2:0] stream_channel_count = 3'b1;
wire [23:0] M_value;
wire [23:0] N_value;
wire [11:0] H_visible;
wire [11:0] V_visible;
wire [11:0] H_t... | 7.537447 |
module tb_texture_border_unit ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_texture_border_unit.vcd");
$dumpvars(0, tb_texture_border_unit);
#30000000;
$display("!!!!TIME OUT!!!!");
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
... | 7.300149 |
module tb_tft_char ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire [15:0] rgb_tft;
wire ... | 8.536565 |
module tb_tft_colorbar ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire [15:0] rgb_tft;
wire ... | 9.368047 |
module tb_tft_ctrl ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire locked;
wire rst_n;
wire ... | 7.902519 |
module : tb_timer
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Softwa... | 8.991571 |
module tb_Timer_Counter;
parameter s_IDLE = 2'b00;
parameter s_EXPOSURE = 2'b01;
parameter s_READOUT = 2'b10;
parameter s_INIT = 3'b000;
parameter s_NRE_1 = 3'b001;
parameter s_ADC_1 = 3'b010;
parameter s_NOTHING = 3'b011;
parameter s_NRE_2 = 3'b100;
parameter s_ADC_2 = 3'b101;
parameter s_END = 3'... | 7.163981 |
module tb_timing ();
//
// System Clock 125MHz
//
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
//
// Test Bench
//
reg sys_rst;
reg hsync, vsync;
wire video_en;
wire [10:0] video_hcnt, video_vcnt;
tmds_timing timing (
.rx0_pclk (sys_clk),
.rstbtn_n (... | 8.772504 |
module tb_tlp_demux ();
parameter PORTS = 2;
parameter DOUBLE_WORD = 32;
parameter HEADER_SIZE = 4 * DOUBLE_WORD;
parameter TLP_DATA_WIDTH = 8 * DOUBLE_WORD;
//
reg clk;
reg rst_n;
// input TLP
wire [TLP_DATA_WIDTH-1:0] in_data;
wire [ HEADER_SIZE-1:0] i... | 7.345245 |
module tb_Tomasulo ();
reg Clk;
reg Rst;
//Clock signal generation
initial begin
Clk = 1'b0;
forever #5 Clk <= ~Clk;
end
//Reset signal generation
initial begin
Rst = 1'b1;
#3;
Rst = 1'b0;
end
Tomasulo Tomasulo_inst (
.Clk(Clk),
.Rst(Rst)
);
endmodule
| 6.993863 |
module: SingleCycleProc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`define STRLEN 32
`define HalfClockPeriod 60
`define ClockPeriod `HalfClockPeriod * 2
module SingleCycleProcTest_v;
... | 6.596 |
module tb_top ();
`include "dut_params.v"
localparam CLK_FREQ = (FAMILY == "iCE40UP") ? 40 : 10;
localparam RESET_CNT = (FAMILY == "iCE40UP") ? 140 : 100;
reg rd_clk_i;
reg rst_i;
reg rd_clk_en_i;
reg rd_out_clk_en_... | 6.53356 |
module tb_top16;
reg nvdla_core_clk;
reg nvdla_wg_clk;
reg nvdla_core_rstn;
reg cfg_is_wg;
reg cfg_reg_en;
reg [8*16 -1:0] dat_actv_data;
reg [8 -1:0] dat_actv_nz;
reg [8 -1:0] dat_actv_pvld;
reg [8*16 -1:0] wt_actv_data;
reg [8 -1:0] wt_actv_nz;
reg [8 -1:0] wt_actv_pvld;
wire [34:0] mac_out_da... | 6.580442 |
module top2_tb ();
// Signal Declarations
reg clock; // Inputs
reg [1:0] KEY;
reg [9:0] SW;
// Outputs
wire [9:0] LEDR;
wire [7:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
//wire [5:0] count;
wire [3:0] HEX0_d, HEX1_d, HEX2_d, HEX3_d, HEX4_d, HEX5_d;
// Unit Under Test Instantiation
top UUT (
... | 8.03902 |
module tb_topmicro #(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D
) ();
wire [GPIO_D-1:0] gpio_i_d... | 7.681513 |
module tb_topseg;
reg rst, inclk;
wire [6:0] seg1, seg10;
top_secseg test_topseg (
rst,
inclk,
seg1,
seg10
);
initial begin
inclk = 0;
rst = 0;
end
initial #27 rst = 1;
initial begin
repeat (1000) #5 inclk = ~inclk;
end
endmodule
| 6.903797 |
module vidc_model (
input wire vclk,
input wire [31:0] vidc_d,
input wire vidc_nvidw,
output wire vidc_nvcs,
output wire vidc_nhs,
output reg vidc_nsndrq,
output reg vidc_nvidrq,
output reg vidc_flybk,
input wire vidc_nsndak,
... | 6.777963 |
module tb_top_clock;
reg rst, inclk;
wire [6:0] sec_seg1, sec_seg10;
wire [6:0] min_seg1, min_seg10;
wire [6:0] hour_seg1, hour_seg10;
top_clock test_top (
rst,
inclk,
sec_seg1,
sec_seg10,
min_seg1,
min_seg10,
hour_seg1,
hour_seg10
);
initial begin
in... | 7.27097 |
module tb_top_cpu ();
reg rst, clk;
wire [6:0] seg1, seg2, seg3, seg4, seg5, seg6;
top_cpu tcpu0 (
rst,
clk,
seg1,
seg2,
seg3,
seg4,
seg5,
seg6
);
initial begin
rst = 0;
#33;
rst = 1;
end
initial begin
clk = 0;
forever #5 clk = ~clk;
... | 6.935542 |
module tb_top_dds ();
//**************************************************************//
//*************** Parameter and Internal Signal ****************//
//**************************************************************//
parameter CNT_1MS = 20'd19000 ,
CNT_11MS = 21'd69000 ,
CN... | 8.369161 |
module tb_Top_GLB;
parameter FIFO_DATA_WIDTH = 8;
parameter FIFO_DEPTH = 16;
parameter PE_SIZE = 14;
parameter integer MEM0_DEPTH = 4116;
parameter integer MEM1_DEPTH = 1470;
parameter integer MEM0_ADDR_WIDTH = 13;
parameter integer MEM1_ADDR_WIDTH = 11;
parameter integer MEM0_DATA_WIDTH = 112;
parame... | 6.563521 |
module tb_i2c_drive ();
parameter T = 20; // a FPGA clock period
parameter SLAVE_ADDRESS = 7'b1010_000; // the address of slave
parameter SYSTEM_CLK = 26'd50_000_000; // system clock
parameter IIC_CLK = 26'd250_000; // IIC clock
parameter DIV_FREQ_FACTOR = SYSTEM_CLK / IIC_CLK; // the factor of dividing... | 7.768403 |
module tb_top_jacobi ();
reg clk;
reg rst_n;
wire [23:0] out;
always #10 clk = ~clk;
initial begin
clk = 'd0;
rst_n = 'd0;
#50 @(posedge clk) rst_n = 'd1;
#500000 $stop;
end
top_jacobi j1 (
.clk(clk),
.rst_n(rst_n),
.quotient_out(out)
);
endmodule
| 7.1751 |
module: top_level
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_top_level;
// Inputs
reg reset;
//reg btn_press;
reg clk;
// Outputs
wire UART_TX;
// Instantiate the U... | 7.56918 |
module tb_top_level_frameGenerator;
localparam LEN_TX_DATA = 64;
localparam LEN_TX_CTRL = 8;
reg tb_clock;
reg tb_reset;
wire [LEN_TX_DATA-1 : 0] tb_o_tx_data;
wire [LEN_TX_CTRL-1 : 0] tb_o_tx_ctrl;
initial begin
tb_clock = 1'b0;
tb_reset = 1'b0;
#1... | 6.544487 |
module tb_top_level_ukf ();
reg wr_enable;
reg [127:0] write_data;
reg aclr, fast_clock, slow_clock;
reg [5:0] a, i;
localparam dly = 100;
top_level_ukf testando_top (
.wr_rst(aclr),
.wr_enable(wr_enable),
.write_data(write_data),
.reset(aclr),
.fast_clock(fast_clock),
... | 6.544487 |
module tb_top_nto1_ddr ();
reg reset;
reg reset2;
reg match;
reg matcha;
reg clk;
wire refclk_n;
reg refclk_p;
wire clkout_p;
wire clkout_n;
wire clkout;
wire [7:0] dataout_p;
wire [7:0] dataout_n;
wire [7:0] dataout;
wire [63:0] dummy_out;
reg [63:0] old;
wire [63:0] dummy_outa;
reg ... | 6.623058 |
module tb_top_pcs;
reg clock, reset, enable;
wire [63 : 0] output_data;
wire [ 7 : 0] output_ctrl;
initial begin
clock = 0;
reset = 1;
enable = 0;
#5 reset = 0;
enable = 1;
end
always #1 clock = ~clock;
PCS_modules u_top (
.i_clock(clock),
.i_reset(reset),
.... | 7.305514 |
module: Top_RISC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_Top_RISC;
// Inputs
reg clk;
reg rst;
reg [31:0] InsR;
reg [31:0] io_IR;
always begin
clk = ... | 6.610172 |
module tb_top_RTC ();
reg r_clk, r_modify;
reg [7:0] r_min = 0, r_hour = 0;
wire [7:0] w_msec, w_sec, w_min, w_hour;
top_RTC DUT (
.i_clk(r_clk),
.i_modify(r_modify),
.i_im_min(r_min),
.i_im_hour(r_hour),
.o_msec(w_msec),
.o_sec(w_sec),
.o_min(w_min),
.o_hour(w_... | 6.793991 |
module tb_top_seg_595 ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire stcp; //输出数据存储寄时钟
wire shcp; //移位寄存器的时钟输... | 8.399944 |
module tb_top_spi_function;
reg clk;
reg rst_n;
wire [7:0] om_data_master;
wire [7:0] om_data_slave;
top_spi_function tb_U1 (
.clk (clk),
.rst_n(rst_n),
.om_data_master(om_data_master),
.om_data_slave (om_data_slave)
);
initial begin
clk = 0;
rst_n = 0;
end
always... | 7.822507 |
module tb_top_uart;
// Inputs
reg sys_clk;
reg sys_rst_n;
reg rx_data;
// Outputs
wire tx_data;
// Instantiate the Unit Under Test (UUT)
top_uart top_uart0 (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.rx_data (rx_data),
.tx_data (tx_data)
);
always #10 sys_clk = ~sys... | 7.530804 |
module tb_top_unit ();
reg i_clk;
integer i;
top_unit DUT (i_clk);
initial begin
i_clk = 1'b0;
forever #5 i_clk = ~i_clk;
end
initial begin
$dumpfile("tb_top_unit.vcd");
$dumpvars;
#1000 $finish;
end
/* initial
$monitor("$time=%t Rs1_exe=%b Rs2_Exe=%b Rd_mem=%b ",
... | 6.602995 |
module tb_touch_ctrl_led ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire led;
//reg define
reg sys_clk;
... | 8.977172 |
module: Traductor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_traductr;
// Inputs
reg [3:0] in;
reg clk;
reg rst;
// Outputs
wire [15:0] out;
// Instantiate the Unit... | 6.737957 |
module tb_traffic_syn;
reg CLK, reset, ERR, PA, PB;
wire [2:0] L_A, L_B, state;
wire RA, RB;
wire pa_r, pb_r;
parameter CLK_CYCLE = 10; // clock cycle = 5ns
// state code
localparam STATE0 = 3'b000,
STATE1 = 3'b001,
STATE2 = 3'b010,
STATE3 = 3'b011,
... | 7.336189 |
module tb_traffic_signal_controller;
// Inputs
reg clk;
reg x;
reg reset;
// Outputs
wire [1:0] hwy;
wire [1:0] cntry;
// Instantiate the Unit Under Test (UUT)
traffic_signal_controller uut (
.clk(clk),
.x(x),
.reset(reset),
.hwy(hwy),
.cntry(cntry)
);
always #5 c... | 6.723729 |
module tb_transmit_cgrundey ();
reg clk_en, ctr_clr, ctr_en, conv_en_n;
wire clk_out;
wire [11:0] reg_out;
clk #(100) C1 (
clk_en,
clk_out
);
transmit_cgrundey U1 (
clk_out,
ctr_clr,
ctr_en,
conv_en_n,
reg_out
);
initial begin
clk_en = 1'b1; // enable cl... | 6.596208 |
module: transpose
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_transpose;
// Inputs
reg [95:0] input_matrix;
// Outputs
wire [95:0] output_matrix;
// Memory
wire... | 6.563602 |
module tb_trigger_block ();
reg clk;
reg reset_n;
reg data_valid;
reg trig_in;
reg force_trig;
wire [31:0] pre_trig_counter;
wire [31:0] post_trig_counter;
wire [31:0] pre_trig_counter_value;
reg en_trig;
wire delayed_trig;
// Uncomment to t... | 7.022895 |
module tb_truthtable;
reg x3, x2, x1;
wire f;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
integer i;
truthtable UUT (
.x3(x3),
.x2(x2),
.x1(x1),
.f (f)
);
initial // initial block executes only once
begin
x3 = 0;
x2 = 0;... | 6.771978 |
module: AM_Transmission
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_TSC;
// Inputs
reg [127:0] key;
reg clk;
reg rst;
reg Tj_Trig;
// Instantiate the Unit Under Test ... | 7.490454 |
module tb_tssqrt ();
reg clk;
reg rst_n;
reg touch;
always #50 clk = ~clk;
initial begin
clk = 1'b0;
rst_n = 1'b0;
touch = 1'b0;
#500;
rst_n = 1'b1;
#5000;
touch = 1'b1;
#500000;
$finish;
end
initial begin
$fsdbDumpfile("test.fsdb");
$fsdbDumpvars(0, tb_ts... | 6.695365 |
module tb_tst_6502;
reg clk;
reg clk_2x;
reg reset;
wire [3:0] vdac;
wire [7:0] gpio_o;
reg [7:0] gpio_i;
reg RX;
wire TX;
wire snd_l, snd_r, snd_nmute;
wire spi0_mosi, spi0_miso, spi0_sclk, spi0_cs0;
wire ps2_clk, ps2_dat;
wire rgb0, rgb1, rgb2;
wire [3:0] tst;
// clock sources
always #3... | 9.110403 |
module tb_two_port_mem;
parameter addresses = 32;
parameter width = 8;
parameter muxFactor = 0;
//Auto-calculated, user dont touch
localparam addressWidth = $clog2(addresses);
reg [addressWidth-1:0] writeAddress;
reg writeEnable;
reg [ width-1:0] writeData;
reg [addre... | 8.086942 |
module tb_two_wide_bufs #(
parameter DATA_WIDTH = 8, // pixel bit depth
parameter ADDR_WIDTH = 6 // address width
) ();
// input signals
reg clk, data_vld, resetn;
reg [DATA_WIDTH-1 : 0] wdata0, wdata1;
// output signals
wire sync;
wire [DATA_WIDTH-1 : 0] rdata0, rdata1;
// test signals
reg... | 7.468497 |
module tb_tx_fifo;
reg clock, clear_b, psel, pwrite, next_word;
reg [7:0] pw_data;
wire validword, isempty, ssptxintr;
wire [7:0] tx_data;
tx_fifo DUT (
.PCLK(clock),
.CLEAR_B(clear_b),
.PSEL(psel),
.PWRITE(pwrite),
.PWDATA(pw_data),
.NextWord(next_word),
.ValidWor... | 6.654966 |
module tb_tx_fsm ();
reg clk_rd;
reg clk_wr;
reg rst_n;
initial begin
rst_n = 1'b0;
#25 rst_n = 1'b1;
end
// 50 MHz clk_rd:
initial begin
clk_rd = 1'b1;
forever begin
#10 clk_rd = ~clk_rd;
end
end
// 100 MHz clk_wr:
initial begin
clk_wr = 1'b1;
#2
forever be... | 6.696753 |
module tb_tx_gate;
// Inputs
reg sel, in;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
tx_gate uut (
.out(out),
.sel(sel),
.in (in)
);
initial begin
$dumpfile("tb_tx_gate.vcd");
$dumpvars(0, tb_tx_gate);
// Initialize Inputs
in = 1;
sel = 0;
#... | 8.488876 |
module tb_tx_memory_control;
reg clk, ena, rst;
wire data_user;
wire [7:0] txid, redundancy;
wire [15:0] segment_num;
wire [23:0] bramaddr24b, vramaddr;
wire [1:0] vramaddr_c;
wire [11:0] byte_data_counter;
wire hdmimode;
wire [23:0] startaddr;
wire [7:0] doutb;
wire [7:0] aux;
wire start_fram... | 6.724322 |
module tb_tx_rx_top;
parameter FRAME_WIDTH = 10;
parameter BAUD_RATE = 19200;
parameter SYS_CLK_FREQ = 200_000_000;
parameter SYS_CYCLE_TIME = 1_000_000_000 / SYS_CLK_FREQ;
parameter BIT_CYCLE_TIME = 1_000_000_000 / BAUD_RATE;
reg sys_clk;
reg reset;
reg ... | 6.579539 |
module testbench;
reg clk, rst, T;
wire Q;
T_FF inst_1 (
T,
clk,
rst,
Q
);
initial begin
clk = 1'b1; // 1
rst = 1'b0; // 0
T = 1'b0; // 0
#20 rst = 1'b1; // 1
#40 rst = 1'b0; // 0
T = 1'b1;
#90 T = 1'b0;
end
always begin
#10 clk = ~clk;
e... | 7.015571 |
module tb_uart_baud;
reg tb_data_clk = 0;
reg tb_rst = 0;
wire tb_baud_ena;
//1ns
localparam CLK_PERIOD = 100;
localparam RST_PERIOD = 1000;
localparam CLK_SPEED_HZ = 1000000000 / CLK_PERIOD;
//device under test
util_uart_baud_gen #(
.baud_clock_speed(CLK_SPEED_HZ),
.baud_rate(912600... | 7.174039 |
module for the SSP
// UART.
//
// Verilog Test Fixture created by ISE for module: UART_BRG
//
// Dependencies:
//
// Revision History:
//
// 0.01 08E10 MAM File Created
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_UAR... | 7.154123 |
module generates serial data. It is essentially
// a behavioral implementation of a UART transmitter, sending one character
// at a time (when invoked through one of its tasks), at a specified bit
// period. The character is sent using the RS232 protocol; START, 8 data
// bits (LSbit first), STOP.
//
// Pa... | 8.426276 |
module tb_uart_fifo ();
parameter DATA_WIDTH = 8;
parameter FIFO_DEPTH = 16;
parameter ADDR_WIDTH = 4;
/* ports defination */
// read signal
reg r_pt_reset;
reg r_clk;
reg r_rst_n;
reg r_en;
wire [DATA_WIDTH -... | 7.55081 |
module converts RS232 serial data to parallel data.
// It is essentially a behavioral implementation of a UART receiver,
// receiving the RS232 protocol; START, 8 data bits (LSbit first), STOP,
// and signaling that it has a complete character.
//
// Parameters:
// BAUD_RATE : Baud rate for the re... | 7.142293 |
module tb_uart_rx_clk_gen;
parameter SYS_CLK_FREQ = 200_000_000;
parameter BAUD_RATE = 19200;
parameter CYCLE_TIME = 1_000_000_000 / SYS_CLK_FREQ;
reg sys_clk;
reg reset;
wire sample_clk;
always #(0.5 * CYCLE_TIME) sys_clk = ~sys_clk;
// dut
uart_rx_clk_gen #(
.SYS_CLK_FREQ(SYS_CLK_FREQ)... | 7.616964 |
module tb_uart_sdram ();
//********************************************************************//
//****************** Internal Signal and Defparam ********************//
//********************************************************************//
//wire define
wire tx;
wire sdram_clk;
wire ... | 6.916271 |
module tb_uart_tx_clk_gen;
parameter SYS_CLK_FREQ = 200_000_000;
parameter BAUD_RATE = 19200;
parameter CYCLE_TIME = 1_000_000_000 / SYS_CLK_FREQ;
reg sys_clk;
reg reset;
wire bit_clk;
always #(0.5 * CYCLE_TIME) sys_clk = ~sys_clk;
// dut
uart_tx_clk_gen #(
.SYS_CLK_FREQ(SYS_CLK_FREQ),
... | 7.342384 |
module tb_uart_tx_send_logic;
parameter DATA_FRAME_WIDTH = 4;
parameter CYCLE_TIME = 5;
parameter NUM_TEST = 5;
reg bit_clk;
reg reset;
reg uart_tx_en;
reg [0:DATA_FRAME_WIDTH - 1] uart_tx_din;
wire ... | 6.682464 |
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