code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_swpwm ();
initial $dumpvars(1, tb_swpwm);
initial $dumpvars(1, u_svpwm);
reg rstn = 1'b0;
reg clk = 1'b1;
always #(13563) clk = ~clk; // 36.864MHz
initial begin
repeat (4) @(posedge clk);
rstn <= 1'b1;
end
reg [11:0] theta = 0;
wire signed [15:0] x, y;
wire [11:0] rho;
wire [11:0] phi;
wire pwm_en, pwm_a, pwm_b, pwm_c;
// 这里只是刚好借助了 sincos 模块来生成正弦波给 cartesian2polar ，只是为了仿真。在 FOC 设计中 sincos 模块并不是用来给 cartesian2polar 提供输入数据的，而是被 park_tr 调用。
sincos u_sincos (
.rstn (rstn),
.clk (clk),
.i_en (1'b1),
.i_theta(theta), // input : θ, 一个递增的角度值
.o_en (),
.o_sin (y), // output : y, 振幅为 ±16384 的正弦波
.o_cos (x) // output : x, 振幅为 ±16384 的余弦波
);
cartesian2polar u_cartesian2polar (
.rstn (rstn),
.clk (clk),
.i_en (1'b1),
.i_x (x / 16'sd5), // input : 振幅为 ±3277 的余弦波
.i_y (y / 16'sd5), // input : 振幅为 ±3277 的正弦波
.o_en (),
.o_rho (rho), // output: ρ, 应该是一直等于或近似 3277
.o_theta(phi) // output: φ, 应该是一个接近 θ 的角度值
);
svpwm u_svpwm (
.rstn (rstn),
.clk (clk),
.v_amp (9'd384),
.v_rho (rho), // input : ρ
.v_theta(phi), // input : φ
.pwm_en (pwm_en), // output
.pwm_a (pwm_a), // output
.pwm_b (pwm_b), // output
.pwm_c (pwm_c) // output
);
integer i;
initial begin
while (~rstn) @(posedge clk);
for (i = 0; i < 200; i = i + 1) begin
theta <= 25 * i; // 让 θ 递增
repeat (2048) @(posedge clk);
$display("%d/200", i);
end
$finish;
end
endmodule
| 7.369538 |
module tb_swin_wrap ();
// Parameters for Simulation
parameter clk_period = 10; // ns, 100MHz
parameter start_delay = 30; // clk cycle
parameter rst_delay = 20;
parameter rst_period = 5;
// Simulation Input Config
parameter WORD_WIDTH = 16 * 8;
parameter STREAM_LEN = 512;
// configuration RAM Related
parameter CONF_DATA_WIDTH = 19;
parameter CONF_ADDR_WIDTH = 9;
parameter CONF_MIF_FILE = "../../testdata/conf_file.mif";
//
reg clk;
reg rst_n;
reg [16*8-1:0] pix_data_in;
reg data_in_vld;
wire [8*16-1:0] data_out_line_0;
wire [8*16-1:0] data_out_line_1;
wire [8*16-1:0] data_out_line_2;
wire data_out_vld;
// Variables for Simulation
integer in_file;
integer line0_out_file;
integer line1_out_file;
integer line2_out_file;
integer ii, jj;
integer temp;
// clk generate
initial begin
#(clk_period) clk = 0;
forever begin
#(clk_period / 2) clk = ~clk;
end
end
// rst generate
initial begin
#(clk_period) rst_n = 1;
#(clk_period * rst_delay) rst_n = 0;
#(clk_period * rst_period) rst_n = 1;
end
// Sim data generate
initial begin
$vcdpluson;
end
reg [WORD_WIDTH-1:0] input_data[STREAM_LEN-1:0];
// Open file
initial begin
in_file = $fopen("../../testdata/input_swin.txt", "r");
line0_out_file = $fopen("../../testdata/output_line0.txt", "w");
line1_out_file = $fopen("../../testdata/output_line1.txt", "w");
line2_out_file = $fopen("../../testdata/output_line2.txt", "w");
end
initial begin
for (ii = 0; ii < STREAM_LEN; ii = ii + 1) begin
temp = $fscanf(in_file, "%x", input_data[ii]);
end
end
initial begin
// initialize the Config RAM with MIF file
$readmemh(CONF_MIF_FILE, u_swin_wrap.u_conf_ram.ram);
#(clk_period * start_delay);
// Send the data and enable signal
for (jj = 0; jj < STREAM_LEN; jj = jj + 1) begin
@(posedge clk);
data_in_vld <= 1;
pix_data_in <= input_data[jj];
end
@(posedge clk);
data_in_vld <= 0;
#(clk_period * 10);
/* -----\/----- EXCLUDED -----\/-----
// Begin read from BRAM
for (jj=0;jj<STREAM_LEN;jj=jj+1) begin
@(posedge clk);
rd_addr <= rd_addr + 1;
if(jj>1) begin
$fdisplay(out_file, "%x", rd_data_out);
end
end
@(posedge clk);
$fdisplay(out_file, "%x", rd_data_out);
@(posedge clk);
$fdisplay(out_file, "%x", rd_data_out);
-----/\----- EXCLUDED -----/\----- */
#(clk_period * 10);
$finish;
$fclose(line0_out_file);
$fclose(line1_out_file);
$fclose(line2_out_file);
end // initial begin
// Dump file
always @(posedge clk) begin
if (data_out_vld) begin
$fdisplay(line0_out_file, "%x", data_out_line_0);
$fdisplay(line1_out_file, "%x", data_out_line_1);
$fdisplay(line2_out_file, "%x", data_out_line_2);
end
end
// DUT instantition
swin_wrap u_swin_wrap (
.clk(clk),
.rst_n(rst_n),
.pix_data_in(pix_data_in),
.data_in_vld(data_in_vld),
.data_out_line_0(data_out_line_0),
.data_out_line_1(data_out_line_1),
.data_out_line_2(data_out_line_2),
.data_out_vld(data_out_vld)
);
endmodule
| 8.174588 |
module: SwitchEncoder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module tb_SwitchEncoder;
// Inputs
reg [4:0] sw;
// Outputs
wire [6:0] seg7;
// Instantiate the Unit Under Test (UUT)
SwitchEncoder uut (
.sw(sw),
.seg7(seg7)
);
initial begin
// Initialize Inputs
sw = 0; #10
sw = 1; #10
sw = 2; #10
sw = 3; #10
sw = 4; #10
sw = 5; #10
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.791457 |
module tb_sync ();
//===========================================================================//
// Inputs to UUT
//===========================================================================//
reg clk;
reg rst_n;
reg async_sig;
//===========================================================================//
// Outputs from UUT
//===========================================================================//
wire sync_sig;
//===========================================================================//
// A lcv for counting clocks
//===========================================================================//
integer i;
//===========================================================================//
// Create the clock @ 50 MHz (20 ns)
//===========================================================================//
always #20 clk = ~clk;
//===========================================================================//
// Create the vpd file
//===========================================================================//
initial begin
$vcdpluson(tb_sync);
end
//===========================================================================//
// Initialize signals and perform test
//===========================================================================//
initial begin
$display("======================================");
$display("Starting tb_sync with NUM_FFS = %0d", `NUM_FFS);
// Initialize signals
clk = 1'b0;
rst_n = 1'b0;
async_sig = 1'b0;
// Take UUT out of reset
@(negedge clk) rst_n = 1'b1;
// Set async_sig to 1'b1
@(negedge clk) async_sig = 1'b1;
// Verify that after NUM_FFS clocks, the async_sig appears at sync_sig
for (i = 32'd0; i < `NUM_FFS; i = i + 32'd1) begin
@(posedge clk);
end
// Check sync_sig
@(negedge clk)
if (sync_sig !== 1'b1) begin
$display("ERROR - expected 1'b1 on sync_sig, received %b @ %0t", sync_sig, $time);
end
// Set async_sig to 1'b0
@(negedge clk) async_sig = 1'b0;
// Verify that after NUM_FFS clock, the async_sig appears at sync_sig
for (i = 32'd0; i < `NUM_FFS; i = i + 32'd1) begin
@(posedge clk);
end
// Check sync_sig
@(negedge clk)
if (sync_sig !== 1'b0) begin
$display("ERROR - expected 1'b0 on sync_sig, received %b @ %0t", sync_sig, $time);
end
$display("======================================");
$finish();
end
//===========================================================================//
// UUT (sync.v)
//===========================================================================//
sync #(
.NUM_FFS(`NUM_FFS)
) sync_0 (
.clk(clk),
.rst_n(rst_n),
.async_sig(async_sig),
.sync_sig(sync_sig)
);
endmodule
| 7.06281 |
module: Synchro
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_synchro;
// Inputs
reg dato;
reg clk;
// Outputs
wire ds;
// Instantiate the Unit Under Test (UUT)
Synchro uut (
.dato(dato),
.clk(clk),
.ds(ds)
);
initial begin
// Initialize Inputs
dato = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#30;
dato = 1;
#50;
dato = 0;
// Add stimulus here
end
always #10 clk = ~clk;
endmodule
| 6.947666 |
module: pal_sync_generator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_syncs;
// Inputs
reg clk;
// Outputs
wire raster_int_in_progress;
wire [8:0] hcnt;
wire [8:0] vcnt;
wire [2:0] ro;
wire [2:0] go;
wire [2:0] bo;
wire hsync;
wire vsync;
wire csync;
wire int_n;
// Instantiate the Unit Under Test (UUT)
pal_sync_generator uut (
.clk(clk),
.mode(2'b00),
.rasterint_enable(1'b0),
.vretraceint_disable(1'b0),
.raster_line(9'd0),
.raster_int_in_progress(),
.ri(3'b111),
.gi(3'b111),
.bi(3'b111),
.hcnt(hcnt),
.vcnt(vcnt),
.ro(ro),
.go(go),
.bo(bo),
.hsync(hsync),
.vsync(vsync),
.csync(csync),
.int_n(int_n)
);
initial begin
// Initialize Inputs
clk = 0;
// Add stimulus here
end
always begin
clk = #(1000/14) ~clk;
end
endmodule
| 7.642223 |
module tb_sync_counter ();
reg clk, rst;
wire [3:0] out0, out1, out2, out3;
sync_counter tb_sync (
out0,
out1,
out2,
out3,
clk,
rst
);
initial begin
clk = 0;
rst = 0;
end
initial #27 rst = 1;
initial begin
repeat (1000) #5 clk = ~clk;
end
endmodule
| 6.529403 |
module tb_sync_fifo();
parameter DATA_WIDTH = 8;
parameter FIFO_DEPTH = 8;
parameter AFULL_DEPTH = FIFO_DEPTH - 1; //阈值
parameter AEMPTY_DEPTH = 1;
parameter RDATA_MODE = 0;
reg clk ;
reg rst_n ;
reg wr_en ;
reg [DATA_WIDTH-1:0] wr_data;
reg rd_en ;
wire [DATA_WIDTH-1:0] rd_data;
wire full ;
wire almost_full;
wire empty ;
wire almost_empty;
wire overflow; //上溢
wire underflow; //下溢
integer I;
sync_fifo #(
.DATA_WIDTH (DATA_WIDTH),
.FIFO_DEPTH (FIFO_DEPTH),
.RDATA_MODE (RDATA_MODE)
)inst_sync_fifo(
.clk (clk ),
.rst_n (rst_n ),
.wr_en (wr_en ),
.wr_data (wr_data ),
.rd_en (rd_en ),
.rd_data (rd_data ),
.full (full ),
.almost_full (almost_full ),
.empty (empty ),
.almost_empty(almost_empty),
.overflow (overflow ), //上溢
.underflow (underflow ) //下溢
);
initial begin
clk = 0; rst_n = 0; wr_en = 0; wr_data = 0; rd_en = 0;
#50 rst_n = 1；
end
always #5 clk = ~clk;
initial begin
#100；
send_wr;
end
task send_wr;
begin
for(I = 0;I < 8;I = I+1)begin
@(posedge clk)begin
wr_en <= 1'b1;
wr_data <= I+1;
end
end
@(posedge clk)begin
wr_en <= 1'b0;
wr_data <= 8'h0;
end
repeat(10) @(posedge clk);
$finish;
end
endtask
endmodule
| 6.800565 |
module tb_sync_merge;
/*AUTOREG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire a1; // From U_SYNC_MERGE of sync_merge.v
wire a2; // From U_SYNC_MERGE of sync_merge.v
wire r0; // From U_SYNC_MERGE of sync_merge.v
// End of automatics
reg r1, r2;
reg reset_n;
/* sync_merge AUTO_TEMPLATE(
); */
sync_merge U_SYNC_MERGE (
/*AUTOINST*/
// Outputs
.a1 (a1),
.a2 (a2),
.r0 (r0),
// Inputs
.r1 (r1),
.r2 (r2),
.a0 (a0),
.reset_n(reset_n)
);
assign #120 a0 = r0;
initial begin
$dumpfile("tb.vcd");
$dumpvars(0, tb_sync_merge);
end
initial begin
reset_n <= 'b0;
r1 <= 'b0;
r2 <= 'b0;
#100;
reset_n <= 'b1;
#1000;
r1 <= 'b1;
#1000;
r1 <= 'b0;
#1000;
r2 <= 'b1;
#1000;
r2 <= 'b0;
#1000;
$display("-I- Done !");
$finish;
end
endmodule
| 7.162017 |
module tv_syntex ();
//reg [3:0] opcode;
reg [ 7:0] eightBit;
reg [15:0] sixteenBit;
initial begin
// opcode = 4'b1000;
// case(opcode)
// `ADD:
// $display("passed");
// default:
// $display("failed");
// endcase
eightBit = 16'b11111111;
#10 sixteenBit = eightBit;
if (sixteenBit == 16'b0000_0000_1111_1111) begin
$display("passed. %b", sixteenBit);
end
#10 sixteenBit = $signed(eightBit);
if (sixteenBit == 16'b1111_1111_1111_1111) begin
$display("passed. %b", sixteenBit);
end
end
endmodule
| 7.445106 |
module tb_syn_fifo ();
parameter DATA_WIDTH = 8;
parameter FIFO_DEPTH = 16;
parameter ADDR_WIDTH = 4;
/* ports defination */
reg clk, rst_n;
// read signal
reg r_en;
wire [DATA_WIDTH - 1 : 0] r_data;
wire [ ADDR_WIDTH : 0] data_avail;
wire is_empty;
// write signal
reg w_en;
reg [DATA_WIDTH - 1 : 0] w_data;
wire [ ADDR_WIDTH : 0] room_avail;
wire is_full;
/* initial blocks */
// generate clock and reset signal
initial begin
clk = 0;
forever begin
#1 clk = ~clk;
end
end
initial begin
rst_n = 1;
#10 rst_n = 0;
#20 rst_n = 1;
end
// generate motivation
initial begin
w_en = 0;
r_en = 0;
w_data = 0;
end
initial begin
forever begin
repeat (2) @(posedge clk);
w_en = !is_full;
@(posedge clk);
w_en = 0;
end
end
initial begin
forever begin
repeat (2) @(posedge clk);
r_en = !is_empty;
@(posedge clk);
r_en = 0;
end
end
initial begin
forever begin
@(posedge w_en);
w_data = ($random) % 256;
end
end
syn_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.FIFO_DEPTH(FIFO_DEPTH),
.ADDR_WIDTH(ADDR_WIDTH)
) syn_fifo_ins (
.clk(clk),
.rst_n(rst_n),
.w_en(w_en),
.w_data(w_data),
.r_en(r_en),
.r_data(r_data),
.is_empty(is_empty),
.is_full(is_full),
.room_avail(room_avail),
.data_avail(data_avail)
);
endmodule
| 7.811771 |
module syn_fifo_v1_Nb_top;
parameter W = 8, D = 8;
reg RSTn;
reg CLK;
reg [W-1:0] DATA_IN;
reg WR_EN;
reg RD_EN;
wire FULL;
wire EMPTY;
wire [W-1:0] DATA_OUT;
syn_fifo_v1_Nb #(
.BUS_WIDTH (W),
.FIFO_DEPTH(D)
) fifo (
.RSTn(RSTn),
.CLK(CLK),
.DATA_IN(DATA_IN),
.WR_EN(WR_EN),
.RD_EN(RD_EN),
.FULL(FULL),
.EMPTY(EMPTY),
.DATA_OUT(DATA_OUT)
);
initial begin
fork
begin
CLK = 1;
forever begin
#5 CLK = ~CLK;
end
end
begin
RSTn = 0;
WR_EN = 0;
RD_EN = 0;
DATA_IN = 0;
#100 RSTn = 1;
begin
repeat (32) begin
@(posedge CLK);
#1;
$display(
$time,
" WR_EN ; %0d, RD_EN : %0d, DATA_IN : %0d :: FULL : %0d, EMPTY : %0d, DATA_OUT : %0d",
WR_EN, RD_EN, DATA_IN, FULL, EMPTY, DATA_OUT);
@(negedge CLK);
WR_EN = 1;
DATA_IN = $urandom % 100;
end
WR_EN = 0;
repeat (32) begin
@(posedge CLK);
#1;
$display(
$time,
" WR_EN ; %0d, RD_EN : %0d, DATA_IN : %0d :: FULL : %0d, EMPTY : %0d, DATA_OUT : %0d",
WR_EN, RD_EN, DATA_IN, FULL, EMPTY, DATA_OUT);
@(negedge CLK);
RD_EN = 1;
end
end
$finish;
end
join
end
endmodule
| 7.046492 |
module tb_sysArr ();
parameter width_height = 4;
localparam weight_width = 8 * width_height;
localparam sum_width = 16 * width_height;
localparam data_width = 8 * width_height;
// inputs to DUT
reg clk;
reg active;
reg [data_width-1:0] datain;
reg [weight_width-1:0] win;
reg [sum_width-1:0] sumin;
reg [width_height-1:0] wwrite;
// outputs from DUT
wire [sum_width-1:0] maccout;
wire [weight_width-1:0] wout;
wire [width_height-1:0] wwriteout;
wire [width_height-1:0] activeout;
wire [data_width-1:0] dataout;
// instantiation of DUT
sysArr DUT (
.clk (clk),
.active (active),
.datain (datain),
.win (win),
.sumin (sumin),
.wwrite (wwrite),
.maccout (maccout),
.wout (wout),
.wwriteout(wwriteout),
.activeout(activeout),
.dataout (dataout)
);
defparam DUT.width_height = width_height;
always begin
#5;
clk = ~clk;
end // always
initial begin
clk = 1'b0;
active = 1'b0;
datain = 32'h0000_0000;
win = 32'h0000_0000;
sumin = 64'h0000_0000_0000_0000;
wwrite = 4'b0000;
#10;
//win = 32'h0404_0404;
win = 32'h0403_0201;
wwrite = 4'b1111;
#10;
//win = 32'h0303_0303;
win = 32'h0403_0201;
#10;
//win = 32'h0202_0202;
win = 32'h0403_0201;
#10;
//win = 32'h0101_0101;
win = 32'h0403_0201;
wwrite = 4'b0000;
#10 datain = 32'h0000_0000;
active = 1'b1;
#10;
datain = 32'h0000_0401;
#10;
datain = 32'h0008_0502;
#10;
datain = 32'h0C09_0603;
#10;
datain = 32'h0D0A_0700;
#10;
datain = 32'h0E0B_0000;
#10;
datain = 32'h0F00_0000;
active = 1'b0;
#10;
datain = 32'h0000_0000;
#30;
wwrite = 4'b1111;
win = 32'h0F0B_0703;
#10;
win = 32'h0E0A_0602;
#10;
win = 32'h0D09_0501;
#10;
win = 32'h0C08_0400;
wwrite = 4'b0000;
#10;
datain = 32'h0000_0001;
active = 1'b1;
#10;
datain = 32'h0000_0502;
#10;
datain = 32'h0009_0603;
#10;
datain = 32'h0D0A_0704;
#10;
datain = 32'h0E0B_0800;
#10;
datain = 32'h0F0C_0000;
#10;
datain = 32'h1000_0000;
#10;
datain = 32'h0000_0015;
#10;
datain = 32'h0000_1D00;
#10;
datain = 32'h0021_0000;
#10;
datain = 32'h0400_0000;
#10;
datain = 32'h0000_0000;
active = 1'b0;
#30;
wwrite = 4'b1111;
win = 32'h000C_030A;
#10;
win = 32'h00AA_0B02;
#10;
win = 32'h000C_010A;
#10;
win = 32'h0000_0000;
wwrite = 4'b0000;
#10;
datain = 32'h0000_0000;
active = 1'b1;
#10;
datain = 32'h0000_AA00;
#10;
datain = 32'h00DD_BB00;
#10;
datain = 32'h01EE_CC00;
#10;
datain = 32'h01FF_0000;
#10;
datain = 32'h0900_0000;
active = 1'b0;
#10;
datain = 32'h0000_0000;
#30;
$stop;
end // initial
endmodule
| 6.677419 |
module tb_sysArr2x2 ();
reg clk, active;
reg [15:0] datain, win;
reg [31:0] sumin;
reg [ 1:0] wwrite;
wire [15:0] maccout1, maccout2;
wire [7:0] wout1, wout2, dataout1, dataout2;
wire wwriteout1, wwriteout2, activeout1, activeout2;
always begin
#5;
clk = ~clk;
end // always
sysArr2x2 DUT (
.clk (clk),
.active (active),
.datain (datain),
.win (win),
.sumin (sumin),
.wwrite (wwrite),
.maccout1 (maccout1),
.maccout2 (maccout2),
.wout1 (wout1),
.wout2 (wout2),
.wwriteout1(wwriteout1),
.wwriteout2(wwriteout2),
.activeout1(activeout1),
.activeout2(activeout2),
.dataout1 (dataout1),
.dataout2 (dataout2)
);
initial begin
clk = 1'b0;
active = 1'b0;
datain = 16'h0000;
win = 16'h0000;
sumin = 32'h0000_0000;
wwrite = 2'b00;
#10;
win = 16'h0101;
wwrite = 2'b11;
#20;
wwrite = 2'b00;
active = 1'b1;
datain = 16'h0001;
#10;
datain = 16'h0101;
#10;
datain = 16'h0101;
active = 1'b0;
#10;
active = 1'b1;
#10;
datain = 16'h0302;
#10;
datain = 16'h0400;
active = 1'b0;
end // initial
endmodule
| 7.372966 |
module tb_sysArrRow ();
localparam row_width = 4;
localparam weight_width = 8 * row_width;
localparam sum_width = 16 * row_width;
// Inputs to DUT
reg clk;
reg active;
reg [7:0] datain;
reg [weight_width-1:0] win;
reg [sum_width-1:0] sumin;
reg [row_width-1:0] wwrite;
// Outputs from DUT
wire [sum_width-1:0] maccout;
wire [weight_width-1:0] wout;
wire [row_width-1:0] wwriteout;
wire [row_width-1:0] activeout;
wire [7:0] dataout;
// Instantiation of DUT
sysArrRow DUT (
.clk (clk),
.active (active),
.datain (datain),
.win (win),
.sumin (sumin),
.wwrite (wwrite),
.maccout (maccout),
.wout (wout),
.wwriteout(wwriteout),
.activeout(activeout),
.dataout (dataout)
);
defparam DUT.row_width = row_width;
always begin
#5;
clk = ~clk;
end // always
initial begin
clk = 1'b0;
active = 1'b0;
datain = 8'h00;
win = 32'h0000_0000;
sumin = 64'h0000_0000_0000_0000;
wwrite = 4'b0000;
#10;
win = 32'h4433_2211;
wwrite = 4'b1111;
#10;
win = 32'hFFFF_FFFF;
wwrite = 4'b0000;
#10;
active = 1'b1;
#10;
datain = 8'h01;
#10;
datain = 8'h02;
#10;
datain = 8'h03;
#10;
datain = 8'h04;
#10;
active = 1'b0;
#50;
$stop;
end // initial
endmodule
| 6.95534 |
module tb_softusb ();
reg sys_clk;
reg sys_rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
/* 100MHz system clock */
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
sysctl dut (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a (csr_a),
.csr_we(csr_we),
.csr_do(csr_do),
.csr_di(csr_di)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("CSR write: %x=%x", address, data);
csr_we = 1'b0;
waitclock;
waitclock;
waitclock;
waitclock;
waitclock;
waitclock;
waitclock;
waitclock;
waitclock;
waitclock;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("CSR read : %x=%x", address, csr_do);
end
endtask
always begin
$dumpfile("softusb.vcd");
$dumpvars(0, dut);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
waitclock;
sys_rst = 1'b0;
#2000;
csrwrite(32'h34, 32'h03ffff);
csrwrite(32'h34, 32'h03ffff);
csrwrite(32'h34, 32'h03ffff);
csrwrite(32'h34, 32'h03ffff);
csrwrite(32'h34, 32'h00aa99);
csrwrite(32'h34, 32'h005566);
csrwrite(32'h34, 32'h0030a1);
csrwrite(32'h34, 32'h000000);
csrwrite(32'h34, 32'h0030a1);
csrwrite(32'h34, 32'h00000e);
csrwrite(32'h34, 32'h002000);
csrwrite(32'h34, 32'h002000);
csrwrite(32'h34, 32'h002000);
csrwrite(32'h34, 32'h002000);
csrwrite(32'h34, 32'h031111);
csrwrite(32'h34, 32'h03ffff);
#700;
$finish;
end
endmodule
| 6.540109 |
module tb_system;
reg clk24;
reg reset;
reg RX;
wire TX;
wire spi0_mosi, spi0_miso, spi0_sclk, spi0_cs0, spi0_cs1;
wire spi1_mosi, spi1_miso, spi1_sclk, spi1_cs0, spi1_cs1;
wire i2c0_sda, i2c0_scl;
wire [31:0] gp_out;
// 24MHz clock source
always #21 clk24 = ~clk24;
// reset
initial begin
`ifdef icarus
$dumpfile("tb_system.vcd");
$dumpvars;
`endif
// init regs
clk24 = 1'b0;
reset = 1'b1;
RX = 1'b1;
// release reset
#100 reset = 1'b0;
`ifdef icarus
// stop after 1 sec
#2000000 $finish;
`endif
end
// Unit under test
system uut (
.clk24(clk24), // 24MHz system clock
.reset(reset), // high-true reset
.RX(RX), // serial input
.TX(TX), // serial output
.spi0_mosi(spi0_mosi), // SPI core 0
.spi0_miso(spi0_miso),
.spi0_sclk(spi0_sclk),
.spi0_cs0 (spi0_cs0),
.spi0_cs1 (spi0_cs1),
.spi1_mosi(spi1_mosi), // SPI core 1
.spi1_miso(spi1_miso),
.spi1_sclk(spi1_sclk),
.spi1_cs0 (spi1_cs0),
.spi1_cs1 (spi1_cs1),
.i2c0_sda(i2c0_sda), // I2C core 0
.i2c0_scl(i2c0_scl),
.gp_out(gp_out) // general purpose output
);
endmodule
| 6.988862 |
module: system_toplevel
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_systemToplevel_with_processor;
// Inputs
reg clk;
reg reset;
reg bit8;
reg parity_en;
reg odd_n_even;
reg [3:0] baud_val;
reg rx;
// Outputs
wire tx;
reg [10:0] shifter;
reg [4:0] j;
reg [7:0] i;
// Instantiate the Unit Under Test (UUT)
system_toplevel uut (
.clk(clk),
.reset(reset),
.bit8(bit8),
.parity_en(parity_en),
.odd_n_even(odd_n_even),
.baud_val(baud_val),
.rx(rx),
.tx(tx)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
bit8 = 1;
parity_en = 0;
odd_n_even = 0;
baud_val = 4'b0100; //9600 BAUD
rx = 1;
#30;
reset = 0;
for(i=65; i<96; i=i+1) begin
#100;
shifter = {2'b11,i,1'b0};
for(j=0; j<10; j=j+1) begin
rx=shifter[j];
#104170;
end
#5145870;
end
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 8.638014 |
module tb_m6502_system ();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam DEBUG = 0;
localparam DISPLAY_CYCLE_CTR = 0;
localparam CLK_HALF_PERIOD = 1;
localparam CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg tb_clk;
reg tb_reset_n;
wire [ 7 : 0] tb_leds;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
system_m6502 dut (
.clk(tb_clk),
.reset_n(tb_reset_n),
.leds(tb_leds)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
//
// Monitor displaying information every cycle.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @(posedge tb_clk) begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (DISPLAY_CYCLE_CTR) $display("cycle = %016x:", cycle_ctr);
end // dut_monitor
//----------------------------------------------------------------
// reset_dut
//----------------------------------------------------------------
task reset_dut;
begin
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Set the input to the DUT to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
tb_clk = 0;
tb_reset_n = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// m6502_system_test
// The main test functionality.
//----------------------------------------------------------------
initial begin : m6502_system_test
$display(" -- Testbench for m6502 system started --");
init_sim();
reset_dut();
#(100 * CLK_PERIOD);
$display(" -- Testbench for m6502 system done --");
$finish;
end // m6502_system_test
endmodule
| 7.920387 |
module tb;
reg TCLK, TMS, TRST;
wire [3:0] STATE;
parameter TCLK_CYCLE = 2; //clock cycle: 2ns(500MHz)
parameter NUM_OF_TEST = 64; //number of test
// Instantiation of DUT:
tap_controller tap_controller_dut (
.TCK (TCLK),
.TMS (TMS),
.TRST (TRST),
.STATE(STATE)
);
// Generates the test clock:
always #(TCLK_CYCLE / 2) TCLK = ~TCLK;
// Initial value of signal:
initial begin
TCLK = 1;
TMS = 0;
TRST = 1;
end
// //Tests the design using fixed test patterns:
// initial fork
// #3 TRST = 0;//STATE 0
// #2.1 TMS = 0;//STATE 1
// #4.1 TMS = 1;//STATE 2
// #6.1 TMS = 0;//STATE 3
// #8.1 TMS = 0;//STATE 4
// #10.1 TMS = 1;//STATE 5
// #12.1 TMS = 0;//STATE 6
// #14.1 TMS = 1;//STATE 7
// #16.1 TMS = 1;//STATE 8
// #18.1 TMS = 1;//STATE 2
// #20.1 TMS = 1;//SATTE 9
// #22.1 TMS = 0;//STATE A
// #24.1 TMS = 0;//STATE B
// #26.1 TMS = 1;//STATE C
// #28.1 TMS = 0;//STATE D
// #30.1 TMS = 1;//STATE E
// #32.1 TMS = 1;//STATE F
// #34.1 TMS = 1;//STATE 2
// #36.1 TMS = 1;//STATE 9
// #38.1 TMS = 1;
// #40.1 TMS = 1;//STATE 0
// #42.1 TMS = 1;//STATE 0
// #44.1 TMS = 0;//STATE 1
// #46.1 TMS = 0;//STATE 1
// #48.1 TMS = 1;//STATE 2
// #50.1 TMS = 0;//STATE 3
// #52.1 TMS = 1;//STATE 5
// #54.1 TMS = 0;//STATE 6
// #56.1 TMS = 0;//STATE 6
// #58.1 TMS = 1; //STATE 7
// #60.1 TMS = 0; //STATE 4
// #62.1 TMS = 0;//STATE 4
// #64.1 TMS = 1;//STATE 5
// #66.1 TMS = 1;//STATE 8
// #68.1 TMS = 1;//STATE 2
// #70.1 TMS = 1;//STATE 9
// #72.1 TMS = 0;//STATE A
// #74.1 TMS = 1;//STATE C
// #76.1 TMS = 0;//STATE D
// #78.1 TMS = 0;//STATE D
// #80.1 TMS = 1;//STATE E
// #82.1 TMS = 0;//STATE B
// #84.1 TMS = 0;//STATE B
// #86.1 TMS = 1;//STATE C
// #88.1 TMS = 0;//STATE D
// #90.1 TMS = 1;//STATE E
// #92.1 TMS = 1;//STATE F
// #94.1 TMS = 0;//STATE 1
// #95 TRST = 1;
// #96 ;//STATE 0
// #100 $fclose();
// #100 $finish;
// join
//Tests the desigh using random test patterns:
integer count;
initial begin
#(4 * TCLK_CYCLE + 0.1) TRST = 0; // reset for 4 clocks
// Gives TMS with random value in each clock cycle
for (count = 0; count < NUM_OF_TEST; count = count + 1) #(TCLK_CYCLE) TMS = ({$random} % 2);
$fclose(the_file);
$finish;
end
// Monitors relavant signals and outputs to files:
reg [31:0] the_file;
initial begin
the_file = $fopen("tap_controller.out", "w");
//the unit of time returned by $time is ps, so we need to divide it by 1000:
$fmonitor(the_file, "At time %d ns, TMS = %b, STATE(hex) = %H", $time, TMS, STATE);
end
endmodule
| 7.51795 |
module tb_tb ();
// START USER CODE (Do not remove this line)
// User: Put your signals here. Code in this
// section will not be overwritten.
// END USER CODE (Do not remove this line)
real CLK_P_PERIOD = 10000.000000;
real CLK_N_PERIOD = 10000.000000;
real RESET_LENGTH = 160000;
// Internal signals
reg CLK_N;
reg CLK_P;
reg RESET;
wire [7:0] sync_ch_ctl_bl16_0_ERASE_END_O_pin;
wire [7:0] sync_ch_ctl_bl16_0_ERASE_START_O_pin;
wire [7:0] sync_ch_ctl_bl16_0_OP_FAIL_O_pin;
wire [7:0] sync_ch_ctl_bl16_0_PROG_END_O_pin;
wire [7:0] sync_ch_ctl_bl16_0_PROG_START_O_pin;
wire [7:0] sync_ch_ctl_bl16_0_READ_END_O_pin;
wire [7:0] sync_ch_ctl_bl16_0_READ_START_O_pin;
wire sync_ch_ctl_bl16_0_SSD_ALE_pin;
wire [7:0] sync_ch_ctl_bl16_0_SSD_CEN_pin;
wire sync_ch_ctl_bl16_0_SSD_CLE_pin;
wire sync_ch_ctl_bl16_0_SSD_CLK_pin;
wire sync_ch_ctl_bl16_0_SSD_DQS_pin;
wire [7:0] sync_ch_ctl_bl16_0_SSD_DQ_pin;
reg [7:0] sync_ch_ctl_bl16_0_SSD_RB_pin;
wire sync_ch_ctl_bl16_0_SSD_WPN_pin;
wire sync_ch_ctl_bl16_0_SSD_WRN_pin;
tb dut (
.RESET(RESET),
.CLK_P(CLK_P),
.CLK_N(CLK_N),
.sync_ch_ctl_bl16_0_SSD_DQ_pin(sync_ch_ctl_bl16_0_SSD_DQ_pin),
.sync_ch_ctl_bl16_0_SSD_CLE_pin(sync_ch_ctl_bl16_0_SSD_CLE_pin),
.sync_ch_ctl_bl16_0_SSD_ALE_pin(sync_ch_ctl_bl16_0_SSD_ALE_pin),
.sync_ch_ctl_bl16_0_SSD_CEN_pin(sync_ch_ctl_bl16_0_SSD_CEN_pin),
.sync_ch_ctl_bl16_0_SSD_CLK_pin(sync_ch_ctl_bl16_0_SSD_CLK_pin),
.sync_ch_ctl_bl16_0_SSD_WRN_pin(sync_ch_ctl_bl16_0_SSD_WRN_pin),
.sync_ch_ctl_bl16_0_SSD_WPN_pin(sync_ch_ctl_bl16_0_SSD_WPN_pin),
.sync_ch_ctl_bl16_0_SSD_RB_pin(sync_ch_ctl_bl16_0_SSD_RB_pin),
.sync_ch_ctl_bl16_0_SSD_DQS_pin(sync_ch_ctl_bl16_0_SSD_DQS_pin),
.sync_ch_ctl_bl16_0_PROG_START_O_pin(sync_ch_ctl_bl16_0_PROG_START_O_pin),
.sync_ch_ctl_bl16_0_PROG_END_O_pin(sync_ch_ctl_bl16_0_PROG_END_O_pin),
.sync_ch_ctl_bl16_0_READ_START_O_pin(sync_ch_ctl_bl16_0_READ_START_O_pin),
.sync_ch_ctl_bl16_0_READ_END_O_pin(sync_ch_ctl_bl16_0_READ_END_O_pin),
.sync_ch_ctl_bl16_0_ERASE_START_O_pin(sync_ch_ctl_bl16_0_ERASE_START_O_pin),
.sync_ch_ctl_bl16_0_ERASE_END_O_pin(sync_ch_ctl_bl16_0_ERASE_END_O_pin),
.sync_ch_ctl_bl16_0_OP_FAIL_O_pin(sync_ch_ctl_bl16_0_OP_FAIL_O_pin)
);
// Clock generator for CLK_P
initial begin
CLK_P = 1'b0;
forever #(CLK_P_PERIOD / 2.00) CLK_P = ~CLK_P;
end
// Clock generator for CLK_N
initial begin
CLK_N = 1'b1;
forever #(CLK_N_PERIOD / 2.00) CLK_N = ~CLK_N;
end
// Reset Generator for RESET
initial begin
RESET = 1'b1;
#(RESET_LENGTH) RESET = ~RESET;
end
// START USER CODE (Do not remove this line)
// User: Put your stimulus here. Code in this
// section will not be overwritten.
wire [7:0] RB;
wire DQS;
wire [7:0] DQ;
wire CLE;
wire ALE;
wire [7:0] CEN;
wire CLK;
wire WRN;
wire WPN;
nand_ssd nand_ssd (
.DQ (sync_ch_ctl_bl16_0_SSD_DQ_pin),
/*AUTOINST*/
// Outputs
.RB (RB[7:0]),
.DQS(DQS),
// Inputs
.CLE(CLE),
.ALE(ALE),
.CEN(CEN[7:0]),
.CLK(CLK),
.WPN(WPN),
.WRN(WRN)
);
always @(*) begin
sync_ch_ctl_bl16_0_SSD_RB_pin = RB;
end
assign sync_ch_ctl_bl16_0_SSD_DQS_pin = DQS;
assign CLE = sync_ch_ctl_bl16_0_SSD_CLE_pin;
assign ALE = sync_ch_ctl_bl16_0_SSD_ALE_pin;
assign CEN = sync_ch_ctl_bl16_0_SSD_CEN_pin;
assign WPN = sync_ch_ctl_bl16_0_SSD_WPN_pin;
assign WRN = sync_ch_ctl_bl16_0_SSD_WRN_pin;
assign CLK = sync_ch_ctl_bl16_0_SSD_CLK_pin;
// END USER CODE (Do not remove this line)
endmodule
| 6.710348 |
module top_module (
output reg A,
output reg B
); //
// generate input patterns here
initial begin
A = 0;
B = 0;
#10 A = 1;
#5 B = 1;
#5 A = 0;
#20 B = 0;
end
endmodule
| 7.203305 |
module top_module ();
reg clk, in;
reg [2:0] s;
wire out;
q7 dut (
.clk(clk),
.in (in),
.s (s),
.out(out)
);
initial begin
clk = 0;
in = 0;
s = 3'd2;
#10 s = 3'd6;
#10 in = 1;
s = 3'd2;
#10 in = 0;
s = 3'd7;
#10 in = 1;
s = 3'd0;
#30 in = 0;
end
always #5 clk = ~clk;
endmodule
| 6.627149 |
module tb_test_impl_micron_controller ();
reg clk50MHz;
reg sw_0;
reg sw_1;
reg sw_6;
reg sw_7;
wire mwe_L;
wire moe_L;
wire madv_L;
wire mclk;
wire mub_L;
wire mlb_L;
wire mce_L;
wire mcre;
wire [23:0] maddr;
assign maddr[23] = 1'b0;
wire [7:0] debug_out;
wire [15:0] mdata;
wire ready;
wire [15:0] BCR_CONFIG;
assign BCR_CONFIG = {
1'b0, // [15:15] Operating mode (Synchronous)
1'b1, // [14:14] Initial latency (Fixed)
3'b011, // [13:11] Latency counter (Code 3)
1'b1, // [10:10] WAIT polarity (Active high)
1'b0, // [9:9] Reserved, must be set to 0
1'b1, // [8:8] Wait config (Asserted one cycle before delay)
2'b00, // [7:6] Reserved, must be set to 0
2'b01, // [5:4] Drive strength (1/2 strength, this is default)
1'b1, // [3:3] Burst wrap (No wrap)
3'b001 // [2:0] Burst length (4 words)
};
assign mdata = (moe_L == 0) ? BCR_CONFIG : 'bz;
test_impl_micron_controller ctrl (
.clk50MHz(clk50MHz),
.sw_0(sw_0), //LSb addr
.sw_1(sw_1), //MSb addr
.sw_6(sw_6), //we
.sw_7(sw_7), //en
.mwe_L(mwe_L),
.moe_L(moe_L),
.madv_L(madv_L),
.mclk(mclk),
.ready(ready),
.mub_L(mub_L),
.mlb_L(mlb_L),
.mce_L(mce_L),
.mcre(mcre),
.maddr(maddr),
.debug_out(debug_out),
.mem_data(mdata)
);
initial begin
clk50MHz <= 0;
sw_0 <= 0;
sw_1 <= 0;
sw_6 <= 0;
sw_7 <= 1;
#20 sw_7 <= 0;
sw_6 <= 1;
#300 sw_6 <= 0;
#400 sw_0 <= 1;
sw_1 <= 0;
#20 sw_0 <= 0;
sw_1 <= 1;
#20 sw_0 <= 1;
sw_1 <= 1;
end
always begin
#10 clk50MHz = ~clk50MHz;
end
micron_sram #(
.NUM_ELEMENTS(8)
) ram (
.clk(mclk),
.addr(maddr),
.adv_L(madv_L),
.ce_L(mce_L),
.oe_L(moe_L),
.we_L(mwe_L),
.mem_wait(mem_wait),
.data(mdata),
.ub_L(mub_L),
.lb_L(mlb_L)
);
endmodule
| 6.541423 |
module tb_tdm_input;
reg mclk;
wire [7:0] cnt256_n;
wire [15:0] ch1_out;
wire [15:0] ch2_out;
wire bclk;
wire wclk;
wire tdm_in;
// Instantiate the Unit Under Test (UUT)
tdm_input uut (
.mclk(mclk),
.cnt256_n(cnt256_n),
.tdm_in(tdm_in),
.ch1_out(ch1_out),
.ch2_out(ch2_out)
);
audio_clkgen gen0 (
.mclk(mclk),
.bclk(bclk),
.wclk(wclk),
.cnt256_n(cnt256_n)
);
tdm_gen sig_gen (
.bclk(bclk),
.wclk(wclk),
.tdm_out(tdm_in)
);
//Master Clock
initial begin
mclk = 1;
forever begin
#40;
mclk = ~mclk;
end
end
initial begin
#100;
// Add stimulus here
end
endmodule
| 7.31184 |
module tb_teclado_conta;
//Inputs
reg [3:0] lin, col;
reg bot_press;
//Output
wire [11:0] s;
//Instancia a unidade a ser testada
teclado_conta uut (
.lin(lin),
.col(col),
.bot_press(bot_press),
.s(s)
);
always begin
bot_press = 1'b1;
#10;
bot_press = 1'b0;
#10;
end
//Valores quaisquer para teste
initial begin
lin = 8;
col = 4;
#20; //2
lin = 4;
col = 2;
#20; //6
lin = 2;
col = 8;
#20; //7
lin = 1;
col = 2; //"Enter"
$monitor("Saida s (BCD) e seu respectivo valor decimal: %12b %x", s, s);
#20 lin = 2;
col = 4;
#20; //8
lin = 1;
col = 2; //"Enter"
$monitor("Saida s (BCD) e seu respectivo valor decimal: %12b %x", s, s);
#20 lin = 4;
col = 8;
#20; //4
lin = 2;
col = 2;
#20; //9
lin = 8;
col = 2;
#20; //3
lin = 1;
col = 2; //"Enter"
$monitor("Saida s (BCD) e seu respectivo valor decimal: %12b %x", s, s);
#20 lin = 1;
col = 4;
#20; //0
lin = 4;
col = 4;
#20; //5
lin = 1;
col = 2; //"Enter"
$monitor("Saida s (BCD) e seu respectivo valor decimal: %12b %x", s, s);
$finish;
end
endmodule
| 6.901708 |
module temp_tb ();
// Signal Declarations
reg [3:0] in; // Inputs
wire [6:0] out; // Outputs
// Unit Under Test Instantiation
seg7 UUT (
.in (in),
.out(out)
);
initial begin
in = 4'b0000;
#10
// Print Current
$display(
"in0 = %4b | out = %7b", in, out
);
// Automatically stop testbench execution
$stop;
end
endmodule
| 7.59098 |
module: TemperatureCalculator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_TemperatureCalculator;
// Inputs
reg [31:0] tc_base;
reg [7:0] tc_ref;
reg [15:0] adc_data;
// Outputs
wire [31:0] tempc;
// Instantiate the Unit Under Test (UUT)
TemperatureCalculator uut (
.tc_base(tc_base),
.tc_ref(tc_ref),
.adc_data(adc_data),
.tempc(tempc)
);
initial begin
// Initialize Inputs
tc_base = 32'b00000000000000000000000010101011;
tc_ref = 8'b00001111;
adc_data = 16'b0000000000010111;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 8.396779 |
module: tensor_product
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_tensor_product;
parameter A_VECTOR_LEN = 5, // length of vector a
B_VECTOR_LEN = 5, // length of vector b
A_CELL_WIDTH = 8, // width of the integer part of fixed point vector values of a
B_CELL_WIDTH = 8, // width of the integer part of fixed point vector values of b
RESULT_CELL_WIDTH = 12, // width of the integer part of the result vector values
FRACTION_WIDTH = 0, // width of the fraction of both a and b values
TILING_H = 2, // the number of cells from vector b processed each turn
TILING_V = 2; // the number of rows being processed each turn.
// Inputs
reg clk;
reg rst;
// a
reg [A_VECTOR_LEN*A_CELL_WIDTH-1:0] a;
reg a_valid;
wire a_ready;
// b
reg [B_VECTOR_LEN*B_CELL_WIDTH-1:0] b;
reg b_valid;
wire b_ready;
// result
wire [A_VECTOR_LEN*B_VECTOR_LEN*RESULT_CELL_WIDTH-1:0] result;
wire result_valid;
reg result_ready;
// overflow
wire error;
// memory
wire [RESULT_CELL_WIDTH-1:0] result_mem [0:B_VECTOR_LEN-1][0:A_VECTOR_LEN-1];
genvar i, j;
generate
for (i=0; i<B_VECTOR_LEN; i=i+1) begin
for (j=0; j<A_VECTOR_LEN; j=j+1) begin
assign result_mem[i][j] = result[i*B_VECTOR_LEN*RESULT_CELL_WIDTH+j*RESULT_CELL_WIDTH+:RESULT_CELL_WIDTH];
end
end
endgenerate
// Instantiate the Unit Under Test (UUT)
tensor_product
#(
.A_VECTOR_LEN (A_VECTOR_LEN ),
.B_VECTOR_LEN (B_VECTOR_LEN ),
.A_CELL_WIDTH (A_CELL_WIDTH ),
.B_CELL_WIDTH (B_CELL_WIDTH ),
.FRACTION_WIDTH (FRACTION_WIDTH ),
.RESULT_CELL_WIDTH(RESULT_CELL_WIDTH),
.TILING_H (TILING_H ),
.TILING_V (TILING_V ))
uut (
.clk(clk),
.rst(rst),
.a(a),
.a_valid(a_valid),
.a_ready(a_ready),
.b(b),
.b_valid(b_valid),
.b_ready(b_ready),
.result(result),
.result_valid(result_valid),
.result_ready(result_ready),
.error(error)
);
always
#1 clk <= ~clk;
initial begin
// Initialize Inputs
clk <= 0;
rst <= 1;
a <= {-8'd50 , 8'd40 , 8'd30 , 8'd20 , 8'd10}; // 10 , 20 , 30 , 40 , 50
a_valid <= 0;
b <= {8'd1 , 8'd2 , -8'd3 , 8'd4 , 8'd5}; // 5 , 4 , 3 , 2 , 1
b_valid <= 0;
result_ready <= 0;
#20 rst <= 0;
#20 a_valid <= 1;
#20 b_valid <= 1;
#24 result_ready <= 1;
#50 result_ready <= 0;
end
endmodule
| 6.562861 |
module: tensor_product
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_tensor_product_error;
parameter A_VECTOR_LEN = 5, // length of vector a
B_VECTOR_LEN = 5, // length of vector b
A_CELL_WIDTH = 8, // width of the integer part of fixed point vector values of a
B_CELL_WIDTH = 8, // width of the integer part of fixed point vector values of b
RESULT_CELL_WIDTH = 8, // width of the integer part of the result vector values
FRACTION_WIDTH = 1, // width of the fraction of both a and b values
TILING_H = 2, // the number of cells from vector b processed each turn
TILING_V = 2; // the number of rows being processed each turn.
// Inputs
reg clk;
reg rst;
reg start;
reg [A_VECTOR_LEN*A_CELL_WIDTH-1:0] a;
reg [B_VECTOR_LEN*B_CELL_WIDTH-1:0] b;
// wires to memory
wire [RESULT_CELL_WIDTH-1:0] result_mem [0:B_VECTOR_LEN-1][0:A_VECTOR_LEN-1];
//wire [2*RESULT_CELL_WIDTH-1:0] result_vec [B_VECTOR_LEN*A_VECTOR_SIZE-1:0];
genvar i, j;
generate
for (i=0; i<B_VECTOR_LEN; i=i+1) begin
for (j=0; j<A_VECTOR_LEN; j=j+1) begin
assign result_mem[i][j] = result[i*B_VECTOR_LEN*RESULT_CELL_WIDTH+j*RESULT_CELL_WIDTH+:RESULT_CELL_WIDTH];
end
end
endgenerate
// Outputs
wire [A_VECTOR_LEN*B_VECTOR_LEN*RESULT_CELL_WIDTH-1:0] result;
wire valid;
wire error;
// Instantiate the Unit Under Test (UUT)
tensor_product
#(
.A_VECTOR_LEN (A_VECTOR_LEN ),
.B_VECTOR_LEN (B_VECTOR_LEN ),
.A_CELL_WIDTH (A_CELL_WIDTH ),
.B_CELL_WIDTH (B_CELL_WIDTH ),
.FRACTION_WIDTH (FRACTION_WIDTH ),
.RESULT_CELL_WIDTH(RESULT_CELL_WIDTH),
.TILING_H (TILING_H ),
.TILING_V (TILING_V ))
uut (
.clk(clk),
.rst(rst),
.start(start),
.a(a),
.b(b),
.result(result),
.valid(valid),
.error(error)
);
always
#1 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
start = 0;
a = {-8'd50 , 8'd40 , 8'd30 , 8'd20 , 8'd10}; // 10 , 20 , 30 , 40 , 50
b = {8'd5 , 8'd10 , -8'd15, 8'd20 , 8'd25}; // 5 , 4 , 3 , 2 , 1
#20 rst = 1;
#20 rst = 0;
#20 start = 1;
#2 start = 0;
end
endmodule
| 6.562861 |
module tb_ternary_operator_mux;
// Inputs
reg i0, i1, sel;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
ternary_operator_mux uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.y (y)
);
initial begin
$dumpfile("tb_ternary_operator_mux.vcd");
$dumpvars(0, tb_ternary_operator_mux);
// Initialize Inputs
sel = 0;
i0 = 0;
i1 = 0;
#300 $finish;
end
always #75 sel = ~sel;
always #10 i0 = ~i0;
always #55 i1 = ~i1;
endmodule
| 8.378489 |
module of t_buffer.v
// AUTHOR : cjh
// TIME : 2016-04-11 09:53:02
//-------------------------------------------------------------
/******** Time scale ********/
`timescale 1ns/1ps
/******** 测试模块 ********/
module tb_testbench();
reg clk;
reg reset;
reg [31:0] pc;
reg is_hit;
reg [31:0] tar_addr;
wire[31:0] tar_data;
wire tar_en;
reg [31:0] exp_tar_data;
reg exp_tar_en;
/******** 测试参数 ********/
reg [31:0] vector_num; // text times
reg [31:0] errors; // error times
reg [97:0] test_vectors[13:0]; // text vectors
/******** 被测试模块的实例化 ********/
t_buffer #(54,9,512) dut(.clk (clk), // clock
.pc (pc),
.is_hit (is_hit),
.tar_addr (tar_addr),
.tar_data (tar_data),
.tar_en (tar_en)
);
/******** 定义时钟信号 ********/
always
begin
clk = 1;
#10;
clk = 0;
#10;
end
/******** 读取测试用例，定义复位信号 ********/
initial
begin
$readmemb("tb_example.tv",test_vectors);
vector_num = 0;
errors = 0;
reset = 1; #27;
reset = 0;
end
/******** 在时钟上升沿，把测试用例输入实例化模块 ******/
always @ (posedge clk)
begin
#1; {pc,is_hit,tar_addr,exp_tar_data,exp_tar_en} = test_vectors[vector_num];
end
/********** output wave **********/
initial
begin
$dumpfile("tb_testbench.vcd");
$dumpvars(0,tb_testbench);
end
/******** 结果检测 ********/
always @ (negedge clk)
begin
if(~reset)
begin
if(~({tar_data,tar_en} == {exp_tar_data,exp_tar_en}))
begin
$display("error: vector_num = %d",vector_num);
$display("output = %h(%h expected),output = %h(%h expected)",tar_data,exp_tar_data,tar_en,exp_tar_en);
errors = errors + 1;
end
vector_num = vector_num + 1;
if(test_vectors[vector_num] === 98'bx)
begin
$display("%d test completed with %d errors",vector_num,errors);
$finish;
end
end
end
endmodule
| 7.91304 |
module: lb_clockCounter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_testClockCounter;
// Inputs
reg clk;
reg reset;
reg [19:0] value;
// Outputs
wire done;
// Instantiate the Unit Under Test (UUT)
lb_clockCounter uut (
.clk(clk),
.reset(reset),
.value(value),
.done(done)
);
always
#10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
value = 10;
#10;
reset = 1;
// Wait 100 ns for global reset to finish
#4100;
#10;
reset = 0;
#10;
reset = 1;
// Wait 100 ns for global reset to finish
#4100;
// Add stimulus here
end
endmodule
| 6.890798 |
module tb_test_ALU_reg ();
reg [15:0] data_in;
reg [1:0] mux_sel;
reg [3:0] seg_reg;
reg [3:0] adr_reg_a;
reg [3:0] adr_reg_b;
reg [7:0] op_in;
reg we;
reg clk;
reg a_reset_l;
wire valid_o;
wire [15:0] data_o;
test_ALU_reg test_ALU_reg_i (
.data_in(data_in),
.mux_sel(mux_sel),
.seg_reg(seg_reg),
.adr_reg_a(adr_reg_a),
.adr_reg_b(adr_reg_b),
.op_in(op_in),
.we(we),
.clk(clk),
.a_reset_l(a_reset_l),
.valid_o(valid_o),
.data_o(data_o)
);
///////////////////////////////////////////////
//// Template for clk and reset generation ////
//// uncomment it when needed ////
///////////////////////////////////////////////
parameter CLKPERIODE = 100;
initial clk = 1'b1;
always #(CLKPERIODE / 2) clk = !clk;
initial begin
a_reset_l = 1'b0;
#33 a_reset_l = 1'b1;
end
///////////////////////////////////////////////
// Template for testcase specific pattern generation
// File has to be situated in simulation/<simulator_name>/[testcase] directory
`include "testcase.v"
endmodule
| 7.504545 |
module tb_test_dma ();
(* DONT_TOUCH = "TRUE" *)reg aclk;
(* DONT_TOUCH = "TRUE" *)reg rst_n;
// axi_vip_0_mem_stimulus slv();
initial begin
aclk <= 1;
rst_n <= 0;
forever #5 aclk <= ~aclk;
end
design_test_dma_wrapper block_design (
aclk,
rst_n
);
integer fid;
integer i;
initial begin
fid = $fopen("dma_test.txt", "w");
#30_000;
$display(
"-------------------------------start output--------------------------------------------");
for (i = 0; i < 4800; i = i + 1) begin
$fwrite(
fid, "%x\n",
block_design.design_test_dma_i.blk_mem_gen_1.inst.native_mem_mapped_module.blk_mem_gen_v8_4_1_inst.memory[32768+i]);
// if(i%4!=3)
// $fwrite(fid, " ");
// else
// $fwrite(fid, "\n");
end
$display(
"-------------------------------finish output--------------------------------------------");
$fclose(fid);
end
endmodule
| 6.615993 |
module tb_test_master #(
parameter BUS_WIDTH = 32,
parameter CTRL_WIDTH = 8,
parameter WRITE_TRANSFER = 1
) (
input [BUS_WIDTH-1:0] bus_in,
input ack,
input clk,
output reg req,
output reg [BUS_WIDTH-1:0] bus_out,
input [CTRL_WIDTH-1:0] ctrl_in,
output [CTRL_WIDTH-1:0] ctrl_out
);
parameter STATE_REQ = 0;
parameter STATE_PRESENT_ADDR = 1;
parameter STATE_SLAVE_WAIT = 2;
parameter STATE_WRITE_DATA = 3;
parameter STATE_READ_DATA = 4;
parameter STATE_IDLE = 5;
parameter BURST_LENGTH = 4;
reg [3:0] nextState;
reg [3:0] currentState;
reg [3:0] counter;
reg we;
assign ctrl_out = {
3'b000, //not used
3'b010, //burst = 4
we,
1'b0
}; //wait
wire wait_in;
assign wait_in = ctrl_in[0];
initial begin
nextState <= 0;
currentState <= 0;
counter <= 0;
we <= 0;
end
always @(posedge clk) begin
currentState <= nextState;
end
//counter
reg counter_en;
always @(posedge clk) begin
if (counter_en) begin
counter = counter + 1;
end
end
//Outputs
always @(*) begin
case (currentState)
STATE_REQ: begin
req <= 1;
counter_en <= 0;
end
STATE_PRESENT_ADDR: begin
bus_out <= 2;
we <= WRITE_TRANSFER;
counter_en <= 0;
end
STATE_SLAVE_WAIT: begin
bus_out <= 0;
end
STATE_WRITE_DATA: begin
bus_out <= counter;
counter_en <= 1;
end
STATE_READ_DATA: begin
counter_en <= 1;
end
STATE_IDLE: begin
req <= 0;
counter_en <= 0;
end
endcase
end
//Next State Logic
always @(*) begin
case (currentState)
STATE_REQ: begin
if (ack) begin
nextState <= STATE_PRESENT_ADDR;
end else begin
nextState <= STATE_REQ;
end
end
STATE_PRESENT_ADDR: begin
nextState <= STATE_SLAVE_WAIT;
end
STATE_SLAVE_WAIT: begin //Wait for slave to lower WAIT
if (wait_in == 0) begin
if (WRITE_TRANSFER) begin
nextState <= STATE_WRITE_DATA;
end else begin
nextState <= STATE_READ_DATA;
end
end else begin
nextState <= STATE_SLAVE_WAIT;
end
end
STATE_WRITE_DATA: begin
if (counter == BURST_LENGTH - 1) begin
nextState <= STATE_IDLE;
end else begin
nextState <= STATE_WRITE_DATA;
end
end
STATE_READ_DATA: begin
if (counter == BURST_LENGTH - 1) begin
nextState <= STATE_IDLE;
end else begin
nextState <= STATE_READ_DATA;
end
end
STATE_IDLE: begin
nextState <= STATE_IDLE;
end
endcase
end
endmodule
| 8.827078 |
module tb_test_mux;
reg clk;
reg [1:0] sel;
reg [31:0] i;
test_mux text_mux (
.clk(clk),
.i0 (0),
.i1 (0),
.i2 (0),
.i3 (0),
.i4 (0),
.b (b)
);
always #1 clk = ~clk;
initial begin
clk = 'b0;
for (i = 0; i < 10; i = i + 1) begin
@(posedge clk);
$display("Value of b=0x%x", b);
end
$finish;
end
endmodule
| 7.137476 |
module tb_test_source;
reg clk = 1'b0;
reg [ 8:0] ch1;
reg [ 8:0] ch2;
reg [ 8:0] ch3;
reg [ 8:0] ch4;
wire [ 2:0] stream_channel_count;
wire [72:0] data;
wire ready;
initial begin
forever begin
#4 clk = 1'b0; // generate a clock
ch1 <= data[8:0];
ch2 <= data[26:18];
ch3 <= data[44:36];
ch4 <= data[62:54];
#4 clk = 1'b1; // generate a clock
ch1 <= data[17:9];
ch2 <= data[35:27];
ch3 <= data[53:45];
ch4 <= data[71:63];
end
end
test_source i_test_source (
.clk (clk),
.stream_channel_count(stream_channel_count),
.ready (ready),
.data (data)
);
endmodule
| 7.537447 |
module tb_test_source_800_600_RGB_444_ch1;
reg clk = 1'b0;
initial begin
forever #10 clk = ~clk; // generate a clock
end
wire ready = 1'b1;
wire [ 2:0] stream_channel_count = 3'b1;
wire [23:0] M_value;
wire [23:0] N_value;
wire [11:0] H_visible;
wire [11:0] V_visible;
wire [11:0] H_total;
wire [11:0] V_total;
wire [11:0] H_sync_width;
wire [11:0] V_sync_width;
wire [11:0] H_start;
wire [11:0] V_start;
wire H_vsync_active_high;
wire V_vsync_active_high;
wire flag_sync_clock;
wire flag_YCCnRGB;
wire flag_422n444;
wire flag_YCC_colour_709;
wire flag_range_reduced;
wire flag_interlaced_even;
wire [ 1:0] flags_3d_Indicators;
wire [ 4:0] bits_per_colour;
wire [72:0] raw_data;
test_source_800_600_RGB_444_ch1 i_test_source (
.M_value(M_value),
.N_value(N_value),
.H_visible (H_visible),
.H_total (H_total),
.H_sync_width(H_sync_width),
.H_start (H_start),
.V_visible (V_visible),
.V_total (V_total),
.V_sync_width (V_sync_width),
.V_start (V_start),
.H_vsync_active_high (H_vsync_active_high),
.V_vsync_active_high (V_vsync_active_high),
.flag_sync_clock (flag_sync_clock),
.flag_YCCnRGB (flag_YCCnRGB),
.flag_422n444 (flag_422n444),
.flag_range_reduced (flag_range_reduced),
.flag_interlaced_even(flag_interlaced_even),
.flag_YCC_colour_709 (flag_YCC_colour_709),
.flags_3d_Indicators (flags_3d_Indicators),
.bits_per_colour (bits_per_colour),
.stream_channel_count(stream_channel_count),
.clk (clk),
.ready(ready),
.data (raw_data)
);
endmodule
| 7.537447 |
module tb_texture_border_unit ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_texture_border_unit.vcd");
$dumpvars(0, tb_texture_border_unit);
#30000000;
$display("!!!!TIME OUT!!!!");
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100.5) reset = 1'b0;
parameter USER_WIDTH = 0;
parameter ADDR_X_WIDTH = 10;
parameter ADDR_Y_WIDTH = 10;
parameter X_WIDTH = 10 + 1;
parameter Y_WIDTH = 9 + 1;
parameter M_REGS = 0;
reg [ADDR_X_WIDTH-1:0] param_width = 64;
reg [ADDR_Y_WIDTH-1:0] param_height = 48;
reg [ 2:0] param_x_op = 3'b000;
reg [ 2:0] param_y_op = 3'b000;
// reg [USER_BITS-1:0] s_user;
reg signed [ X_WIDTH-1:0] s_x;
reg signed [ Y_WIDTH-1:0] s_y;
reg s_valid;
wire s_ready;
// wire [USER_BITS-1:0] m_user;
wire signed [ X_WIDTH-1:0] m_x;
wire signed [ Y_WIDTH-1:0] m_y;
wire m_border;
wire [ADDR_X_WIDTH-1:0] m_addrx;
wire [ADDR_Y_WIDTH-1:0] m_addry;
wire m_valid;
reg m_ready = 1;
always @(posedge clk) begin
if (reset) begin
s_x <= -10;
s_y <= -10;
s_valid <= 0;
end else begin
if (s_valid && s_ready) begin
s_x <= s_x + 1;
if (s_x == param_width + 9) begin
s_x <= -10;
s_y <= s_y + 1;
end
end
s_valid <= 1;
end
end
jelly_texture_border_unit #(
.USER_WIDTH (X_WIDTH + Y_WIDTH),
.ADDR_X_WIDTH(ADDR_X_WIDTH),
.ADDR_Y_WIDTH(ADDR_Y_WIDTH),
.X_WIDTH (X_WIDTH),
.Y_WIDTH (Y_WIDTH),
.M_REGS (M_REGS)
) i_texture_border_unit (
.reset(reset),
.clk (clk),
.cke (1),
.param_width (param_width),
.param_height(param_height),
.param_x_op (param_x_op),
.param_y_op (param_y_op),
.s_user ({s_x, s_y}),
.s_x (s_x),
.s_y (s_y),
.s_valid(s_valid),
.s_ready(s_ready),
.m_user ({m_x, m_y}),
.m_border(m_border),
.m_addrx (m_addrx),
.m_addry (m_addry),
.m_valid (m_valid),
.m_ready (m_ready)
);
endmodule
| 7.300149 |
module tb_tft_char ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire [15:0] rgb_tft;
wire vsync;
wire tft_clk;
wire tft_de;
wire tft_bl;
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//**************************** Clk And Rst ***************************//
//********************************************************************//
//sys_clk,sys_rst_n初始赋值
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
//sys_clk:产生时钟
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- tft_char_inst -------------
tft_char tft_char_inst (
.sys_clk (sys_clk), //输入工作时钟,频率50MHz,1bit
.sys_rst_n(sys_rst_n), //输入复位信号,低电平有效,1bit
.rgb_tft(rgb_tft), //输出像素信息,16bit
.hsync (hsync), //输出行同步信号,1bit
.vsync (vsync), //输出场同步信号,1bit
.tft_clk(tft_clk), //输出TFT时钟信号,1bit
.tft_de (tft_de), //输出TFT使能信号,1bit
.tft_bl (tft_bl) //输出背光信号,1bit
);
endmodule
| 8.536565 |
module tb_tft_colorbar ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire hsync;
wire [15:0] rgb_tft;
wire vsync;
wire tft_clk;
wire tft_de;
wire tft_bl;
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//**************************** Clk And Rst ***************************//
//********************************************************************//
//sys_clk,rst_n初始赋值
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
//clk：产生时钟
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- tft_colorbar_inst -------------
tft_colorbar tft_colorbar_inst (
.sys_clk (sys_clk), //输入工作时钟,频率50MHz
.sys_rst_n(sys_rst_n), //输入复位信号,低电平有效
.rgb_tft(rgb_tft), //输出像素信息
.hsync (hsync), //输出行同步信号
.vsync (vsync), //输出场同步信号
.tft_clk(tft_clk), //输出TFT时钟信号
.tft_de (tft_de), //输出TFT使能信号
.tft_bl (tft_bl) //输出背光信号
);
endmodule
| 9.368047 |
module tb_tft_ctrl ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire locked;
wire rst_n;
wire tft_clk_9m;
//reg define
reg sys_clk;
reg sys_rst_n;
reg [15:0] pix_data;
//********************************************************************//
//**************************** Clk And Rst ***************************//
//********************************************************************//
//sys_clk,sys_rst_n初始赋值
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
//sys_clk：产生时钟
always #10 sys_clk = ~sys_clk;
//rst_n:VGA模块复位信号
assign rst_n = (sys_rst_n & locked);
//pix_data:输入像素点色彩信息
always @(posedge tft_clk_9m or negedge rst_n)
if (rst_n == 1'b0) pix_data <= 16'h0;
else pix_data <= 16'hffff;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- clk_gen_inst -------------
clk_gen clk_gen_inst (
.areset(~sys_rst_n), //输入复位信号,高电平有效,1bit
.inclk0(sys_clk), //输入50MHz晶振时钟,1bit
.c0 (tft_clk_9m), //输出TFT工作时钟,频率9Mhz,1bit
.locked(locked) //输出pll locked信号,1bit
);
//------------- tft_ctrl_inst -------------
tft_ctrl tft_ctrl_inst (
.tft_clk_9m(tft_clk_9m), //输入时钟,频率9MHz
.sys_rst_n (rst_n), //系统复位,低电平有效
.pix_data (pix_data), //待显示数据
.pix_x (pix_x), //输出TFT有效显示区域像素点X轴坐标
.pix_y (pix_y), //输出TFT有效显示区域像素点Y轴坐标
.rgb_tft(rgb_tft), //TFT显示数据
.hsync (hsync), //TFT行同步信号
.vsync (vsync), //TFT场同步信号
.tft_clk(tft_clk), //TFT像素时钟
.tft_de (tft_de), //TFT数据使能
.tft_bl (tft_bl) //TFT背光信号
);
endmodule
| 7.902519 |
module : tb_timer
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_timer();
parameter DATA_WIDTH = 32;
parameter ADDRESS_BITS = 32;
parameter MTIME_ADDR = 32'h0020bff8;
parameter MTIME_ADDR_H = 32'h0020bffC;
parameter MTIMECMP_ADDR = 32'h00204000;
parameter MTIMECMP_ADDR_H = 32'h00204004;
reg clock;
reg reset;
reg readEnable;
reg writeEnable;
reg [DATA_WIDTH/8-1:0] writeByteEnable;
reg [ADDRESS_BITS-1:0] address;
reg [DATA_WIDTH-1:0] writeData;
wire [DATA_WIDTH-1:0] readData;
wire timer_interrupt;
timer #(
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_BITS(ADDRESS_BITS),
.MTIME_ADDR(MTIME_ADDR),
.MTIME_ADDR_H(MTIME_ADDR_H),
.MTIMECMP_ADDR(MTIMECMP_ADDR),
.MTIMECMP_ADDR_H(MTIMECMP_ADDR_H)
) DUT (
.clock(clock),
.reset(reset),
.readEnable(readEnable),
.writeEnable(writeEnable),
.writeByteEnable(writeByteEnable),
.address(address),
.writeData(writeData),
.readData(readData),
.timer_interrupt(timer_interrupt)
);
always #5 clock = ~clock;
initial begin
clock = 1'b1;
reset = 1'b1;
readEnable = 1'b0;
writeEnable = 1'b0;
address = 32'd0;
writeData = 32'd0;
writeByteEnable = 4'b1111;
repeat (3) @ (posedge clock);
reset = 1'b0;
repeat (10) @ (posedge clock);
repeat (1) @ (posedge clock);
readEnable = 1'b1;
writeEnable = 1'b0;
address = MTIME_ADDR;
writeData = 32'd0;
repeat (1) @ (posedge clock);
#1
if( readData !== 32'd11 ) begin
$display("\nError: Unexpected mtime_l value!");
$display("\ntb_timer --> Test Failed!\n\n");
$stop();
end
repeat (1) @ (posedge clock);
$display("\ntb_timer --> Test Passed!\n\n");
$stop;
end
endmodule
| 8.991571 |
module tb_Timer_Counter;
parameter s_IDLE = 2'b00;
parameter s_EXPOSURE = 2'b01;
parameter s_READOUT = 2'b10;
parameter s_INIT = 3'b000;
parameter s_NRE_1 = 3'b001;
parameter s_ADC_1 = 3'b010;
parameter s_NOTHING = 3'b011;
parameter s_NRE_2 = 3'b100;
parameter s_ADC_2 = 3'b101;
parameter s_END = 3'b110;
reg r_Clock = 1'b0;
reg r_Reset = 1'b0;
reg [1:0] r_Main_FSM = s_IDLE;
wire [2:0] w_RD_FSM;
wire [1:0] w_RD_timer;
//Instantiation of Timer_Counter, called UUT (Unit Under Test)
Timer_Counter UUT (
.i_Clock(r_Clock),
.i_Reset(r_Reset),
.i_Main_FSM(r_Main_FSM),
.o_RD_FSM(w_RD_FSM),
.o_RD_timer(w_RD_timer)
);
always #2 r_Clock <= !r_Clock;
initial begin //Function calls to create a *.vcd file
$dumpfile("dump.vcd"); //NECESSARY JUST TO SIMULATE IN edaplayground.com
$dumpvars(1); //WITH EITHER VERILOG OR SYSTEMVERILOG
end
initial begin //Initial block
r_Reset <= 1'b1;
#6 //6us seconds
r_Reset <= 1'b0;
#6 r_Main_FSM <= s_READOUT;
$display("Test Complete");
end
endmodule
| 7.163981 |
module tb_timing ();
//
// System Clock 125MHz
//
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
//
// Test Bench
//
reg sys_rst;
reg hsync, vsync;
wire video_en;
wire [10:0] video_hcnt, video_vcnt;
tmds_timing timing (
.rx0_pclk (sys_clk),
.rstbtn_n (sys_rst),
.rx0_hsync (hsync),
.rx0_vsync (vsync),
.video_en (video_en),
.video_hcnt(video_hcnt),
.video_vcnt(video_vcnt)
);
//
// a clock
//
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
//
// Scinario
//
reg [1:0] rom[0:8360];
reg [15:0] counter = 16'd0;
always @(posedge sys_clk) begin
{vsync, hsync} <= rom[counter];
counter <= counter + 12'd1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_timing);
$readmemb("request.mem", rom);
sys_rst = 1'b1;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#1000000;
$finish;
end
endmodule
| 8.772504 |
module tb_tlp_demux ();
parameter PORTS = 2;
parameter DOUBLE_WORD = 32;
parameter HEADER_SIZE = 4 * DOUBLE_WORD;
parameter TLP_DATA_WIDTH = 8 * DOUBLE_WORD;
//
reg clk;
reg rst_n;
// input TLP
wire [TLP_DATA_WIDTH-1:0] in_data;
wire [ HEADER_SIZE-1:0] in_hdr;
wire in_sop;
wire in_eop;
wire in_valid;
wire in_ready;
// read TLP out
wire [TLP_DATA_WIDTH-1:0] r_out_data;
wire [ HEADER_SIZE-1:0] r_out_hdr;
wire r_out_sop;
wire r_out_eop;
wire r_out_valid;
reg r_out_ready, r_out_ready_nxt;
// write TLP out
wire [TLP_DATA_WIDTH-1:0] w_out_data;
wire [ HEADER_SIZE-1:0] w_out_hdr;
wire w_out_sop;
wire w_out_eop;
wire w_out_valid;
reg w_out_ready, w_out_ready_nxt;
// control
reg enable;
// generate clock
initial begin
clk = 0;
forever #1 clk = ~clk;
end
// reset
initial begin
enable = 1;
rst_n = 1'b1;
#10 rst_n = 0;
#10 rst_n = 1'b1;
end
always @* begin
w_out_ready_nxt = w_out_ready;
r_out_ready_nxt = r_out_ready;
if (w_out_ready == 0) begin
w_out_ready_nxt = 1;
end
if (w_out_ready & w_out_valid) begin
w_out_ready_nxt = 0;
end
if (r_out_ready == 0) begin
r_out_ready_nxt = 1;
end
if (r_out_ready & r_out_valid) begin
r_out_ready_nxt = 0;
end
end
always @(posedge clk) begin
if (!rst_n) begin
w_out_ready <= 0;
r_out_ready <= 0;
end else begin
w_out_ready <= w_out_ready_nxt;
r_out_ready <= r_out_ready_nxt;
end
end
// tlp包发送模块，用于产生随机的tlp包，包括读存储器包、写存储器包以及非法包。每当in_ready信号为1时，包持续1拍再变换。
tlp_tx #(
.DOUBLE_WORD(DOUBLE_WORD),
.HEADER_SIZE(HEADER_SIZE),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH)
) tlp_tx (
.clk(clk),
.rst_n(rst_n),
.in_ready(in_ready),
.in_data(in_data),
.in_hdr(in_hdr),
.in_sop(in_sop),
.in_eop(in_eop),
.in_valid(in_valid)
);
tlp_demux #(
.PORTS(PORTS),
.DOUBLE_WORD(DOUBLE_WORD),
.HEADER_SIZE(HEADER_SIZE),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH)
) tlp_demux_ins (
.clk(clk),
.rst_n(rst_n),
.in_data(in_data),
.in_hdr(in_hdr),
.in_sop(in_sop),
.in_eop(in_eop),
.in_valid(in_valid),
.in_ready(in_ready),
.r_out_data(r_out_data),
.r_out_hdr(r_out_hdr),
.r_out_sop(r_out_sop),
.r_out_eop(r_out_eop),
.r_out_valid(r_out_valid),
.r_out_ready(r_out_ready),
.w_out_data(w_out_data),
.w_out_hdr(w_out_hdr),
.w_out_sop(w_out_sop),
.w_out_eop(w_out_eop),
.w_out_valid(w_out_valid),
.w_out_ready(w_out_ready),
.enable(enable)
);
endmodule
| 7.345245 |
module tb_Tomasulo ();
reg Clk;
reg Rst;
//Clock signal generation
initial begin
Clk = 1'b0;
forever #5 Clk <= ~Clk;
end
//Reset signal generation
initial begin
Rst = 1'b1;
#3;
Rst = 1'b0;
end
Tomasulo Tomasulo_inst (
.Clk(Clk),
.Rst(Rst)
);
endmodule
| 6.993863 |
module: SingleCycleProc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`define STRLEN 32
`define HalfClockPeriod 60
`define ClockPeriod `HalfClockPeriod * 2
module SingleCycleProcTest_v;
task passTest;
input [31:0] actualOut, expectedOut;
input [`STRLEN*8:0] testType;
inout [7:0] passed;
if(actualOut == expectedOut) begin $display ("%s passed", testType); passed = passed + 1; end
else $display ("%s failed: 0x%x should be 0x%x", testType, actualOut, expectedOut);
endtask
task allPassed;
input [7:0] passed;
input [7:0] numTests;
if(passed == numTests) $display ("All tests passed");
else $display("Some tests failed: %d of %d passed", passed, numTests);
endtask
// Inputs
reg CLK;
reg Reset_L;
reg [31:0] startPC;
reg [7:0] passed;
// Outputs
wire [31:0] dMemOut;
// Instantiate the Unit Under Test (UUT)
SingleCycleProc uut (
.CLK(CLK),
.Reset_L(Reset_L),
.startPC(startPC),
.dMemOut(dMemOut)
);
initial begin
// Initialize Inputs
Reset_L = 1;
startPC = 0;
passed = 0;
// Wait for global reset
#(1 * `ClockPeriod);
// Program 1
#1
Reset_L = 0; startPC = 0;
#(1 * `ClockPeriod);
Reset_L = 1;
#(33 * `ClockPeriod);
passTest(dMemOut, 120, "Results of Program 1", passed);
// Program 2
#(1 * `ClockPeriod)
Reset_L = 0; startPC = 32'h60;
#(1 * `ClockPeriod);
Reset_L = 1;
#(11 * `ClockPeriod);
passTest(dMemOut, 2, "Results of Program 2", passed);
// Program 3
#(1 * `ClockPeriod)
Reset_L = 0; startPC = 32'hA0;
#(1 * `ClockPeriod);
Reset_L = 1;
#(26 * `ClockPeriod);
passTest(dMemOut, 32'hfeedbeef, "Result 1 of Program 3", passed);
#(1 * `ClockPeriod);
passTest(dMemOut, 32'hfeedb48f, "Result 2 of Program 3", passed);
#(1 * `ClockPeriod);
passTest(dMemOut, 32'hfeeeb48f, "Result 3 of Program 3", passed);
#(1 * `ClockPeriod);
passTest(dMemOut, 32'h0000b4a0, "Result 4 of Program 3", passed);
#(1 * `ClockPeriod);
passTest(dMemOut, 32'hddb7dde0, "Result 5 of Program 3", passed);
#(1 * `ClockPeriod);
passTest(dMemOut, 32'h07f76df7, "Result 6 of Program 3", passed);
#(1 * `ClockPeriod);
passTest(dMemOut, 32'hfff76df7, "Result 7 of Program 3", passed);
#(1 * `ClockPeriod);
passTest(dMemOut, 1, "Result 8 of Program 3", passed);
#(1 * `ClockPeriod);
passTest(dMemOut, 0, "Result 9 of Program 3", passed);
#(1 * `ClockPeriod);
passTest(dMemOut, 0, "Result 10 of Program 3", passed);
#(1 * `ClockPeriod);
passTest(dMemOut, 1, "Result 11 of Program 3", passed);
#(1 * `ClockPeriod);
passTest(dMemOut, 32'hfeed4b4f, "Result 12 of Program 3", passed);
// Done
allPassed(passed, 14);
$stop;
end
initial begin
CLK = 0;
end
// The following is correct if clock starts at LOW level at StartTime //
always begin
#`HalfClockPeriod CLK = ~CLK;
#`HalfClockPeriod CLK = ~CLK;
end
endmodule
| 6.596 |
module tb_top ();
`include "dut_params.v"
localparam CLK_FREQ = (FAMILY == "iCE40UP") ? 40 : 10;
localparam RESET_CNT = (FAMILY == "iCE40UP") ? 140 : 100;
reg rd_clk_i;
reg rst_i;
reg rd_clk_en_i;
reg rd_out_clk_en_i;
reg rd_en_i;
reg [RADDR_WIDTH-1:0] rd_addr_i;
wire [RDATA_WIDTH-1:0] rd_data_o;
integer i1;
reg chk = 1'b1;
// ----------------------------
// GSR instance
// ----------------------------
`ifndef iCE40UP
GSR GSR_INST (
.GSR_N(1'b1),
.CLK (1'b0)
);
`endif
`include "dut_inst.v"
initial begin
rst_i = 1'b1;
#RESET_CNT;
rst_i = 1'b0;
end
initial begin
rd_clk_i = 1'b0;
forever #CLK_FREQ rd_clk_i = ~rd_clk_i;
end
localparam TARGET_READ = RADDR_DEPTH;
initial begin
rd_en_i <= 1'b0;
rd_clk_en_i <= 1'b0;
rd_out_clk_en_i <= 1'b0;
rd_addr_i <= {RADDR_WIDTH{1'b0}};
@(negedge rst_i);
@(posedge rd_clk_i);
rd_en_i <= 1'b1;
rd_clk_en_i <= 1'b1;
rd_out_clk_en_i <= 1'b1;
for (i1 = 0; i1 < TARGET_READ; i1 = i1 + 1) begin
@(posedge rd_clk_i);
rd_addr_i <= rd_addr_i + 1;
end
@(posedge rd_clk_i);
if (REGMODE == "reg") @(posedge rd_clk_i);
if (chk == 1'b1) begin
$display("-----------------------------------------------------");
$display("----------------- SIMULATION PASSED -----------------");
$display("-----------------------------------------------------");
end else begin
$display("-----------------------------------------------------");
$display("!!!!!!!!!!!!!!!!! SIMULATION FAILED !!!!!!!!!!!!!!!!!");
$display("-----------------------------------------------------");
end
$finish;
end
reg [RDATA_WIDTH-1:0] mem[2 ** RADDR_WIDTH-1:0];
initial begin
if (INIT_MODE == "mem_file" && INIT_FILE != "none") begin
if (INIT_FILE_FORMAT == "hex") begin
$readmemh(INIT_FILE, mem, 0, RADDR_DEPTH - 1);
end else begin
$readmemb(INIT_FILE, mem, 0, RADDR_DEPTH - 1);
end
end
end
wire rd_en_w = rd_en_i & rd_clk_en_i & rd_out_clk_en_i;
reg [RADDR_WIDTH-1:0] rd_addr_p_r = {RADDR_WIDTH{1'b0}};
always @(posedge rd_clk_i, posedge rst_i) begin
if (rst_i == 1'b1) begin
rd_addr_p_r <= {RADDR_WIDTH{1'b0}};
end else begin
rd_addr_p_r <= rd_addr_i;
end
end
if (REGMODE == "noreg") begin
reg rd_en_p_r;
always @(posedge rd_clk_i) begin
if (rst_i) begin
rd_en_p_r <= 1'b0;
end else begin
rd_en_p_r <= rd_en_w;
end
end
always @(posedge rd_clk_i) begin
if (rd_en_p_r & ~rst_i) begin
if (mem[rd_addr_p_r] !== rd_data_o) begin
chk <= 1'b0;
$display("Expected DATA = %h, Read DATA = %h, LOCATION: %h", mem[rd_addr_p_r], rd_data_o,
rd_addr_p_r);
end
end
end
end else begin
reg rd_en_p_r;
reg rst_p_i = 1'b1;
reg [RADDR_WIDTH-1:0] rd_addr_mem_r;
reg [ 1:0] allow_check;
wire [RDATA_WIDTH-1:0] target_mem = mem[rd_addr_mem_r];
always @(posedge rd_clk_i) begin
if (rst_i) begin
rd_en_p_r <= 1'b0;
rd_addr_mem_r <= {{RADDR_WIDTH{1'b0}}};
rst_p_i <= 1'b1;
allow_check <= 2'b00;
end else begin
rd_en_p_r <= rd_en_w;
rd_addr_mem_r <= rd_addr_p_r;
rst_p_i <= rst_i;
if (allow_check != 2'b11) allow_check <= allow_check + 1'b1;
end
end
always @(posedge rd_clk_i) begin
if (rd_en_p_r == 1'b1 & ~rst_p_i & (allow_check == 2'b11)) begin
if (mem[rd_addr_mem_r] !== rd_data_o) begin
chk <= 1'b0;
$display("Expected DATA = %h, Read DATA = %h, LOCATION: %h", mem[rd_addr_mem_r],
rd_data_o, rd_addr_mem_r);
end
end
end
end
endmodule
| 6.53356 |
module tb_top16;
reg nvdla_core_clk;
reg nvdla_wg_clk;
reg nvdla_core_rstn;
reg cfg_is_wg;
reg cfg_reg_en;
reg [8*16 -1:0] dat_actv_data;
reg [8 -1:0] dat_actv_nz;
reg [8 -1:0] dat_actv_pvld;
reg [8*16 -1:0] wt_actv_data;
reg [8 -1:0] wt_actv_nz;
reg [8 -1:0] wt_actv_pvld;
wire [34:0] mac_out_data;
wire mac_out_pvld;
mac_unit UUT (
.nvdla_core_clk(nvdla_core_clk)
, .nvdla_wg_clk(nvdla_wg_clk)
, .nvdla_core_rstn(nvdla_core_rstn)
, .cfg_is_wg(cfg_is_wg)
, .cfg_reg_en(cfg_reg_en)
, .dat_actv_data(dat_actv_data)
, .dat_actv_nz(dat_actv_nz)
, .dat_actv_pvld(dat_actv_pvld)
, .wt_actv_data(wt_actv_data)
, .wt_actv_nz(wt_actv_nz)
, .wt_actv_pvld(wt_actv_pvld)
, .mac_out_data(mac_out_data)
, .mac_out_pvld(mac_out_pvld)
);
//Clock
always begin
#1 nvdla_core_clk = !nvdla_core_clk;
end
integer outfile0;
integer outfile1;
reg [128:0] A;
reg [128:0] B;
initial begin
nvdla_core_clk = 1;
nvdla_core_rstn = 0;
#200 nvdla_core_rstn = 1;
wt_actv_nz = 8'hff;
dat_actv_nz = 8'hff;
wt_actv_pvld = 8'hff;
dat_actv_pvld = 8'hff;
#200 outfile0 = $fopen("./input_data/data_file.dat", "r");
outfile1 = $fopen("./input_data/weight_file.dat", "r");
while (!$feof(
outfile0
)) begin
$fscanf(outfile0, "%h\n", A);
$fscanf(outfile0, "%h\n", B);
dat_actv_data = A;
wt_actv_data = B;
#2;
end
//once reading and writing is finished, close the file.
$fclose(outfile0);
$fclose(outfile1);
end
always @(mac_out_data) begin
$display("data: %0h -- weight: %0h mac_out_data: %0h", dat_actv_data, wt_actv_data,
mac_out_data);
end
endmodule
| 6.580442 |
module top2_tb ();
// Signal Declarations
reg clock; // Inputs
reg [1:0] KEY;
reg [9:0] SW;
// Outputs
wire [9:0] LEDR;
wire [7:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
//wire [5:0] count;
wire [3:0] HEX0_d, HEX1_d, HEX2_d, HEX3_d, HEX4_d, HEX5_d;
// Unit Under Test Instantiation
top UUT (
.MAX10_CLK1_50(clock),
.KEY(KEY),
.SW(SW),
.LEDR(LEDR),
.HEX0(HEX0),
.HEX1(HEX1),
.HEX2(HEX2),
.HEX3(HEX3),
.HEX4(HEX4),
.HEX5(HEX5)
);
hex2dec h0 (
.in (HEX0),
.out(HEX0_d)
);
hex2dec h1 (
.in (HEX1),
.out(HEX1_d)
);
hex2dec h2 (
.in (HEX2),
.out(HEX2_d)
);
hex2dec h3 (
.in (HEX3),
.out(HEX3_d)
);
hex2dec h4 (
.in (HEX4),
.out(HEX4_d)
);
hex2dec h5 (
.in (HEX5),
.out(HEX5_d)
);
initial begin
clock = 1'b0;
end
always begin
#100 clock = ~clock;
end
initial begin
SW[9:0] = 10'b00000_00011;
KEY[1] = 1'b0;
$display("Testing all functions");
$display("| H5 | H4 | H3 | H2 | H1 | H0 | L9 | L8 | L0 |");
$display("-------------------------------------------------------------");
KEY[0] = 1'b1; //reset
#500 @(posedge clock);
#10;
KEY[0] = 1'b0; //reset
@(posedge clock);
#10;
KEY[0] = 1'b1; //reset
repeat (40) begin
@(posedge clock);
#10;
$display("| %1d | %1d | %1d | %1d | %1d | %1d | %1b | %1b | %1b |", HEX5_d,
HEX4_d, HEX3_d, HEX2_d, HEX1_d, HEX0_d, LEDR[9], LEDR[8], LEDR[0]);
$display("-------------------------------------------------------------");
end
// Automatically stop testbench execution
$stop;
end
endmodule
| 8.03902 |
module tb_topmicro #(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D
) ();
wire [GPIO_D-1:0] gpio_i_data_tri_i;
reg [GPIO_D-1:0] gpio_o_data_tri_o;
wire o_led;
reg CLK100MHZ;
initial begin
CLK100MHZ = 1'b0;
gpio_o_data_tri_o = 32'h9; // reste
#20 gpio_o_data_tri_o = 32'h1E;
#3210 gpio_o_data_tri_o = 32'h0;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#20 $finish;
end
always #2.5 CLK100MHZ = ~CLK100MHZ;
micro_sim u_micro_sim (
.gpio_i_data_tri_i(gpio_i_data_tri_i),
.o_led(o_led),
.CLK100MHZ(CLK100MHZ),
.gpio_o_data_tri_o(gpio_o_data_tri_o)
);
endmodule
| 7.681513 |
module tb_topseg;
reg rst, inclk;
wire [6:0] seg1, seg10;
top_secseg test_topseg (
rst,
inclk,
seg1,
seg10
);
initial begin
inclk = 0;
rst = 0;
end
initial #27 rst = 1;
initial begin
repeat (1000) #5 inclk = ~inclk;
end
endmodule
| 6.903797 |
module vidc_model (
input wire vclk,
input wire [31:0] vidc_d,
input wire vidc_nvidw,
output wire vidc_nvcs,
output wire vidc_nhs,
output reg vidc_nsndrq,
output reg vidc_nvidrq,
output reg vidc_flybk,
input wire vidc_nsndak,
input wire vidc_nvidak
);
/* Shoot for roughly 640x480 mode timings */
parameter hcyc = 800;
parameter hsw = 95;
parameter hstart = 132;
parameter hend = 772;
parameter vcyc = 525;
parameter vsw = 3;
parameter vstart = 33;
parameter vend = 513;
reg [31:0] x;
reg [31:0] y;
reg [ 7:0] dmac;
reg last_va;
initial begin
x <= 0;
y <= 0;
vidc_flybk <= 0;
vidc_nvidrq <= 1;
vidc_nsndrq <= 1;
dmac <= 0;
end
always @(posedge vclk) begin
if (x < hcyc) begin
x <= x + 1;
end else begin
x <= 0;
if (y < vcyc) begin
y <= y + 1;
end else begin
y <= 0;
end
end // else: !if(x < hcyc)
if (y == vend) begin
vidc_flybk <= 1;
end else if (y == vstart - 1) begin
vidc_flybk <= 0;
end
if (y >= vstart && y < vend && x[3:0] == 4'b1111 && x > hsw) begin
// Do some DMA requests
vidc_nvidrq <= 0;
dmac <= 0;
end
last_va <= vidc_nvidak;
if (last_va == 1 && vidc_nvidak == 0) begin
if (dmac < 3) dmac <= dmac + 1;
else vidc_nvidrq <= 1;
end
end // always @ (vclk)
assign vidc_nvcs = ~(y < vsw);
assign vidc_nhs = ~(x < hsw);
endmodule
| 6.777963 |
module tb_top_clock;
reg rst, inclk;
wire [6:0] sec_seg1, sec_seg10;
wire [6:0] min_seg1, min_seg10;
wire [6:0] hour_seg1, hour_seg10;
top_clock test_top (
rst,
inclk,
sec_seg1,
sec_seg10,
min_seg1,
min_seg10,
hour_seg1,
hour_seg10
);
initial begin
inclk = 0;
rst = 0;
end
initial #27 rst = 1;
initial begin
repeat (2000000) #5 inclk = ~inclk;
end
endmodule
| 7.27097 |
module tb_top_cpu ();
reg rst, clk;
wire [6:0] seg1, seg2, seg3, seg4, seg5, seg6;
top_cpu tcpu0 (
rst,
clk,
seg1,
seg2,
seg3,
seg4,
seg5,
seg6
);
initial begin
rst = 0;
#33;
rst = 1;
end
initial begin
clk = 0;
forever #5 clk = ~clk;
end
endmodule
| 6.935542 |
module tb_top_dds ();
//**************************************************************//
//*************** Parameter and Internal Signal ****************//
//**************************************************************//
parameter CNT_1MS = 20'd19000 ,
CNT_11MS = 21'd69000 ,
CNT_41MS = 22'd149000 ,
CNT_51MS = 22'd199000 ,
CNT_60MS = 22'd249000 ;
//wire define
wire dac_clk;
wire [ 7:0] dac_data;
//reg define
reg sys_clk;
reg sys_rst_n;
reg [21:0] tb_cnt;
reg key_in;
reg [ 1:0] cnt_key;
reg [ 3:0] key;
//defparam define
defparam top_dds_inst.key_control_inst.CNT_MAX = 24;
//**************************************************************//
//************************** Main Code *************************//
//**************************************************************//
//sys_rst_n,sys_clk,key
initial begin
sys_clk = 1'b0;
sys_rst_n <= 1'b0;
key <= 4'b0000;
#200;
sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
//tb_cnt:按键过程计数器，通过该计数器的计数时间来模拟按键的抖动过程
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) tb_cnt <= 22'b0;
else if (tb_cnt == CNT_60MS) tb_cnt <= 22'b0;
else tb_cnt <= tb_cnt + 1'b1;
//key_in:产生输入随机数，模拟按键的输入情况
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) key_in <= 1'b1;
else if((tb_cnt >= CNT_1MS && tb_cnt <= CNT_11MS)
|| (tb_cnt >= CNT_41MS && tb_cnt <= CNT_51MS))
key_in <= {$random} % 2;
else if (tb_cnt >= CNT_11MS && tb_cnt <= CNT_41MS) key_in <= 1'b0;
else key_in <= 1'b1;
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_key <= 2'd0;
else if (tb_cnt == CNT_60MS) cnt_key <= cnt_key + 1'b1;
else cnt_key <= cnt_key;
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) key <= 4'b1111;
else
case (cnt_key)
0: key <= {3'b111, key_in};
1: key <= {2'b11, key_in, 1'b1};
2: key <= {1'b1, key_in, 2'b11};
3: key <= {key_in, 3'b111};
default: key <= 4'b1111;
endcase
//**************************************************************//
//************************ Instantiation ***********************//
//**************************************************************//
//------------- top_dds_inst -------------
top_dds top_dds_inst (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.key (key),
.dac_clk (dac_clk),
.dac_data(dac_data)
);
endmodule
| 8.369161 |
module tb_Top_GLB;
parameter FIFO_DATA_WIDTH = 8;
parameter FIFO_DEPTH = 16;
parameter PE_SIZE = 14;
parameter integer MEM0_DEPTH = 4116;
parameter integer MEM1_DEPTH = 1470;
parameter integer MEM0_ADDR_WIDTH = 13;
parameter integer MEM1_ADDR_WIDTH = 11;
parameter integer MEM0_DATA_WIDTH = 112;
parameter integer MEM1_DATA_WIDTH = 112;
parameter integer WEIGHT_ROW_NUM = 70;
parameter integer WEIGHT_COL_NUM = 294;
reg clk;
reg rst_n;
reg en;
wire [MEM0_DATA_WIDTH-1:0] mem0_q0_o;
wire mem0_q0_vaild;
wire [MEM1_DATA_WIDTH-1:0] rdata_o;
wire [PE_SIZE-1:0] weight_en_col_o;
wire sa_data_mover_en;
Top_GLB #(
.FIFO_DATA_WIDTH(FIFO_DATA_WIDTH),
.FIFO_DEPTH(FIFO_DEPTH),
.PE_SIZE(PE_SIZE),
.MEM0_DEPTH(MEM0_DEPTH),
.MEM1_DEPTH(MEM1_DEPTH),
.MEM0_ADDR_WIDTH(MEM0_ADDR_WIDTH),
.MEM1_ADDR_WIDTH(MEM1_ADDR_WIDTH),
.MEM0_DATA_WIDTH(MEM0_DATA_WIDTH),
.MEM1_DATA_WIDTH(MEM1_DATA_WIDTH),
.WEIGHT_ROW_NUM(WEIGHT_ROW_NUM), // 64 + 6
.WEIGHT_COL_NUM(WEIGHT_COL_NUM) // 288 + 6
) DUT (
.clk(clk),
.rst_n(rst_n),
.en(en),
.mem0_q0_o(mem0_q0_o),
.mem0_q0_vaild(mem0_q0_vaild),
.rdata_o(rdata_o),
.weight_en_col_o(weight_en_col_o),
.sa_data_mover_en(sa_data_mover_en)
);
always #5 clk = ~clk;
initial begin
clk = 0;
rst_n = 0;
en = 0;
#50 rst_n = 1;
#20 en = 1;
end
endmodule
| 6.563521 |
module tb_i2c_drive ();
parameter T = 20; // a FPGA clock period
parameter SLAVE_ADDRESS = 7'b1010_000; // the address of slave
parameter SYSTEM_CLK = 26'd50_000_000; // system clock
parameter IIC_CLK = 26'd250_000; // IIC clock
parameter DIV_FREQ_FACTOR = SYSTEM_CLK / IIC_CLK; // the factor of dividing system clock
parameter ADDR_WIDTH = 1'b1; //1: 16bit address ; 0:8 bit address
reg sys_clk;
reg sys_rst_n;
//reg sda;
initial begin
for (integer i = 0; i <= 1500000; i = i + 1) #10 sys_clk = ~sys_clk;
end
initial begin
sys_clk = 1'b0;
sys_rst_n = 1'b1;
#(T * 5) sys_rst_n = 1'b0;
#(T * 5) sys_rst_n = 1'b1;
end
top_iic #(
.SLAVE_ADDRESS (SLAVE_ADDRESS),
.SYSTEM_CLK (SYSTEM_CLK),
.IIC_CLK (IIC_CLK),
.DIV_FREQ_FACTOR(DIV_FREQ_FACTOR),
.ADDR_WIDTH (ADDR_WIDTH)
) inst_top_iic (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.scl (scl),
.sda (sda)
);
EEPROM_AT24C64 inst_EEPROM_AT24C64 (
.scl(scl),
.sda(sda)
);
pullup (sda);
pulldown (sda);
initial $vcdpluson();
initial begin
$fsdbDumpfile("top_iic.fsdb");
$fsdbDumpvars(0);
end
endmodule
| 7.768403 |
module tb_top_jacobi ();
reg clk;
reg rst_n;
wire [23:0] out;
always #10 clk = ~clk;
initial begin
clk = 'd0;
rst_n = 'd0;
#50 @(posedge clk) rst_n = 'd1;
#500000 $stop;
end
top_jacobi j1 (
.clk(clk),
.rst_n(rst_n),
.quotient_out(out)
);
endmodule
| 7.1751 |
module: top_level
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_top_level;
// Inputs
reg reset;
//reg btn_press;
reg clk;
// Outputs
wire UART_TX;
// Instantiate the Unit Under Test (UUT)
top_level uut (
.reset(reset),
//.btn_press(btn_press),
.clk(clk),
.UART_TX(UART_TX)
);
initial begin
// Initialize Inputs
reset = 1;
//btn_press = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
#100;
// Add stimulus here
end
always #5 clk = ~clk;
endmodule
| 7.56918 |
module tb_top_level_frameGenerator;
localparam LEN_TX_DATA = 64;
localparam LEN_TX_CTRL = 8;
reg tb_clock;
reg tb_reset;
wire [LEN_TX_DATA-1 : 0] tb_o_tx_data;
wire [LEN_TX_CTRL-1 : 0] tb_o_tx_ctrl;
initial begin
tb_clock = 1'b0;
tb_reset = 1'b0;
#1 tb_reset = 1'b1;
#1 tb_reset = 1'b0;
#1000000 $finish;
end
always #1 tb_clock = ~tb_clock;
top_level_frameGenerator #() test_top_level_frameGenerator (
.i_clock (tb_clock),
.i_reset (tb_reset),
.o_tx_data(tb_o_tx_data),
.o_tx_ctrl(tb_o_tx_ctrl)
);
endmodule
| 6.544487 |
module tb_top_level_ukf ();
reg wr_enable;
reg [127:0] write_data;
reg aclr, fast_clock, slow_clock;
reg [5:0] a, i;
localparam dly = 100;
top_level_ukf testando_top (
.wr_rst(aclr),
.wr_enable(wr_enable),
.write_data(write_data),
.reset(aclr),
.fast_clock(fast_clock),
.slow_clock(slow_clock)
);
initial begin
slow_clock = 0;
forever begin
#50 slow_clock = ~slow_clock;
end
end
initial begin
fast_clock = 0;
forever begin
#25 fast_clock = ~fast_clock;
end
end
initial begin
$display("reset high");
aclr <= 1'b1;
#1000;
wr_enable <= 1'b0;
write_data <= {32'h00000000, 32'h00000000, 32'h00000000, 32'h00000000};
$display("reset low");
#100 aclr <= 1'b0;
#200;
write_data_diag(32'h0000000C);
//for(i=0; i<12; i=i+1) begin
write_data_diag(32'h40000000);
//end
#1100
//for(a=0; a<4; a=a+1) begin
write_data_lower(
32'h3f800000, 32'h3f800000, 32'h3f800000, 32'h3f800000);
//end
#6600 wr_enable <= 1'b0;
write_data <= {32'h00000000, 32'h00000000, 32'h00000000, 32'h00000000};
#1000;
$display("Successful completion. All transfers passed");
//$finish;
$stop;
end
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
task write_data_diag;
input [31:0] diag1;
begin
#dly wr_enable <= 1'b1;
write_data <= {32'h00000000, 32'h00000000, 32'h00000000, diag1};
end
endtask
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
task write_data_lower;
input [31:0] data1, data2, data3, data4;
begin
#dly wr_enable <= 1'b1;
write_data <= {data4, data3, data2, data1};
end
endtask
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//localparam CLK_SPEED = 2; // IF clk = 122.88Mhz = 8.14nS, For half of clock, CLK_SPEED = 8.14nS/2 = 4.07nS
/*
always
#5 clk= ~clk; */
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
endmodule
| 6.544487 |
module tb_top_nto1_ddr ();
reg reset;
reg reset2;
reg match;
reg matcha;
reg clk;
wire refclk_n;
reg refclk_p;
wire clkout_p;
wire clkout_n;
wire clkout;
wire [7:0] dataout_p;
wire [7:0] dataout_n;
wire [7:0] dataout;
wire [63:0] dummy_out;
reg [63:0] old;
wire [63:0] dummy_outa;
reg [63:0] olda;
initial refclk_p = 0;
initial clk = 0;
always #(1000) refclk_p = ~refclk_p;
always #(4000) clk = ~clk;
assign refclk_n = ~refclk_p;
initial begin
reset = 1'b1;
reset2 = 1'b0;
#150000 reset = 1'b0;
#300000 reset2 = 1'b1;
end
always @ (posedge clk) // Check data
begin
old <= dummy_out;
if (dummy_out[63:60] == 4'h3 && dummy_out[59:0] == {old[58:0], old[59]}) begin
match <= 1'b1;
end else begin
match <= 1'b0;
end
end
top_nto1_ddr_diff_tx diff_tx (
.refclkin_p (refclk_p),
.refclkin_n (refclk_n),
.dataout_p (dataout_p),
.dataout_n (dataout_n),
.clkout_p (clkout_p),
.clkout_n (clkout_n),
.reset (reset)
);
top_nto1_ddr_diff_rx diff_rx (
.clkin_p (clkout_p),
.clkin_n (clkout_n),
.datain_p (dataout_p),
.datain_n (dataout_n),
.reset (reset),
.dummy_out (dummy_out)
);
always @ (posedge clk) // Check data
begin
olda <= dummy_outa;
if (dummy_outa[63:60] == 4'h3 && dummy_outa[59:0] == {olda[58:0], olda[59]}) begin
matcha <= 1'b1;
end else begin
matcha <= 1'b0;
end
end
top_nto1_ddr_se_tx se_tx (
.refclkin_p (refclk_p),
.refclkin_n (refclk_n),
.dataout (dataout),
.clkout (clkout),
.reset (reset)
);
top_nto1_ddr_se_rx se_rx (
.clkin1 (clkout),
.clkin2 (clkout),
.datain (dataout),
.reset (reset),
.dummy_out (dummy_outa)
);
endmodule
| 6.623058 |
module tb_top_pcs;
reg clock, reset, enable;
wire [63 : 0] output_data;
wire [ 7 : 0] output_ctrl;
initial begin
clock = 0;
reset = 1;
enable = 0;
#5 reset = 0;
enable = 1;
end
always #1 clock = ~clock;
PCS_modules u_top (
.i_clock(clock),
.i_reset(reset),
.i_enable_encoder(enable),
.i_enable_scrambler(enable),
.i_bypass(0),
.i_enable_descrambler(enable),
.i_enable_decoder(enable)
);
endmodule
| 7.305514 |
module: Top_RISC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_Top_RISC;
// Inputs
reg clk;
reg rst;
reg [31:0] InsR;
reg [31:0] io_IR;
always begin
clk = ~clk;
#50;
end
always@(posedge clk) begin
//#99;
InsR <= io_IR;
end
// Instantiate the Unit Under Test (UUT)
Top_RISC uut (
.clk(clk),
.rst(rst),
.InsR(InsR)
);
initial begin
// Initialize Inputs
clk = 1;
rst = 1;
InsR = 0;
io_IR = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
#100;
// Add stimulus here
io_IR = 32'hfe010113; #100; //addi sp,sp,-3
io_IR = 32'h00812e23; #100; //sw s0,28(sp)
io_IR = 32'h02010413; #100; //addi s0,sp,32
io_IR = 32'h00500793; #100; //li a5,5
io_IR = 32'hfef42623; #100; //sw a5,-20(s0)
io_IR = 32'h00a00793; #100; //li a5,10
io_IR = 32'hfef42423; #100; //sw a5,-24(s0)
io_IR = 32'hfec42703; #100; //lw a4,-20(s0)
io_IR = 32'hfe842783; #100; //lw a5,-24(s0)
io_IR = 32'h00f707b3; #100; //add a5,a4,a5
io_IR = 32'hfef42223; #100; //sw a5,-28(s0)
end
endmodule
| 6.610172 |
module tb_top_RTC ();
reg r_clk, r_modify;
reg [7:0] r_min = 0, r_hour = 0;
wire [7:0] w_msec, w_sec, w_min, w_hour;
top_RTC DUT (
.i_clk(r_clk),
.i_modify(r_modify),
.i_im_min(r_min),
.i_im_hour(r_hour),
.o_msec(w_msec),
.o_sec(w_sec),
.o_min(w_min),
.o_hour(w_hour)
);
always #5 r_clk = ~r_clk;
initial begin
#00 r_clk = 0;
r_modify = 0;
#500 r_min = 30;
r_hour = 2;
#10 r_modify = 1;
#10 r_modify = 0;
end
endmodule
| 6.793991 |
module tb_top_seg_595 ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire stcp; //输出数据存储寄时钟
wire shcp; //移位寄存器的时钟输入
wire ds; //串行数据输入
wire oe; //输出使能信号
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//对sys_clk,sys_rst_n赋初始值
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#100 sys_rst_n <= 1'b1;
end
//clk:产生时钟
always #10 sys_clk <= ~sys_clk;
//重新定义参数值，缩短仿真时间
defparam top_seg_595_inst.seg_595_dynamic_inst.seg_dynamic_inst.CNT_MAX=19;
defparam top_seg_595_inst.data_gen_inst.CNT_MAX = 49;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- seg_595_static_inst -------------
top_seg_595 top_seg_595_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号，低电平有效
.stcp(stcp), //输出数据存储寄时钟
.shcp(shcp), //移位寄存器的时钟输入
.ds (ds), //串行数据输入
.oe (oe) //输出使能信号
);
endmodule
| 8.399944 |
module tb_top_spi_function;
reg clk;
reg rst_n;
wire [7:0] om_data_master;
wire [7:0] om_data_slave;
top_spi_function tb_U1 (
.clk (clk),
.rst_n(rst_n),
.om_data_master(om_data_master),
.om_data_slave (om_data_slave)
);
initial begin
clk = 0;
rst_n = 0;
end
always #2 clk = ~clk;
initial begin
#100 rst_n <= 1'b1;
#100000 rst_n <= 1'b0;
#10 $stop();
end
endmodule
| 7.822507 |
module tb_top_uart;
// Inputs
reg sys_clk;
reg sys_rst_n;
reg rx_data;
// Outputs
wire tx_data;
// Instantiate the Unit Under Test (UUT)
top_uart top_uart0 (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.rx_data (rx_data),
.tx_data (tx_data)
);
always #10 sys_clk = ~sys_clk;
initial begin
// Initialize Inputs
sys_clk = 0;
sys_rst_n = 0;
rx_data = 1;
// Wait 100 ns for global reset to finish
#100;
sys_rst_n = 1'b1;
#8680;
rx_data = 1;
#8680;
rx_data = 1;
#8680;
rx_data = 0; //start
#8680;
rx_data = 0; //1
#8680;
rx_data = 1; //2
#8680;
rx_data = 0; //3
#8680;
rx_data = 1; //4
#8680;
rx_data = 0; //5
#8680;
rx_data = 1; //6
#8680;
rx_data = 0; //7
#8680;
rx_data = 1; //8
#(8680 * 20);
;
rx_data = 1;
#8680;
rx_data = 0;
#8680;
rx_data = 1; //1
#8680;
rx_data = 0;
#8680;
rx_data = 1;
#8680;
rx_data = 0; //4
#8680;
rx_data = 1;
#8680;
rx_data = 0;
#8680;
rx_data = 1;
#8680;
rx_data = 0; //8
#8680;
rx_data = 1;
#8680;
rx_data = 1;
#8680;
rx_data = 1;
#100000;
$finish;
end
initial begin
$monitor("%dns rx_data is %b tx_data is %b\n", $time, rx_data, tx_data);
end // initial
initial begin
$fsdbDumpfile("tb_top_uart.fsdb");
$fsdbDumpvars(0, tb_top_uart);
$fsdbDumpMDA();
end
endmodule
| 7.530804 |
module tb_top_unit ();
reg i_clk;
integer i;
top_unit DUT (i_clk);
initial begin
i_clk = 1'b0;
forever #5 i_clk = ~i_clk;
end
initial begin
$dumpfile("tb_top_unit.vcd");
$dumpvars;
#1000 $finish;
end
/* initial
$monitor("$time=%t Rs1_exe=%b Rs2_Exe=%b Rd_mem=%b ",
$time,DUT.Cpuu.Rs1_PIPELINE[1],DUT.Cpuu.Rs2_PIPELINE[1],
DUT.Cpuu.Rd_PIPELINE[2]); */
initial
$monitor(
"time:%t R10=%d R7=%d R8=%d R20=%d R9=%d R4=%d R3=%d R5=%d ",
$time,
DUT.Cpuu.regFile.xREG[10],
DUT.Cpuu.regFile.xREG[7],
DUT.Cpuu.regFile.xREG[8],
DUT.Cpuu.regFile.xREG[20],
DUT.Cpuu.regFile.xREG[9],
DUT.Cpuu.regFile.xREG[4],
DUT.Cpuu.regFile.xREG[3],
DUT.Cpuu.regFile.xREG[5]
);
endmodule
| 6.602995 |
module tb_touch_ctrl_led ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire led;
//reg define
reg sys_clk;
reg sys_rst_n;
reg touch_key;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//sys_clk,sys_rst_n初始赋值，模拟触摸按键信号值
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
touch_key <= 1'b0;
#200 sys_rst_n <= 1'b1;
#200 touch_key <= 1'b1;
#2000 touch_key <= 1'b0;
#1000 touch_key <= 1'b1;
#3000 touch_key <= 1'b0;
end
//clk：产生时钟
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- touch_ctrl_led_inst -------------
touch_ctrl_led touch_ctrl_led_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号，低电平有效
.touch_key(touch_key), //触摸按键信号
.led(led) //led输出信号
);
endmodule
| 8.977172 |
module: Traductor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_traductr;
// Inputs
reg [3:0] in;
reg clk;
reg rst;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
Traductor uut (
.in(in),
.out(out),
.clk(clk),
.rst(rst)
);
initial begin
// Initialize Inputs
in = 4'b0010;
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always #10 clk=~clk;
endmodule
| 6.737957 |
module tb_traffic_syn;
reg CLK, reset, ERR, PA, PB;
wire [2:0] L_A, L_B, state;
wire RA, RB;
wire pa_r, pb_r;
parameter CLK_CYCLE = 10; // clock cycle = 5ns
// state code
localparam STATE0 = 3'b000,
STATE1 = 3'b001,
STATE2 = 3'b010,
STATE3 = 3'b011,
STATE4 = 3'b100,
STATE5 = 3'b101,
STATE6 = 3'b110,
STATE7 = 3'b111;
//DUT
traffic_control_binary traffic_control_dut (
.CLK(CLK),
.reset(reset),
.ERR(ERR),
.PA(PA),
.PB(PB),
.L_A(L_A),
.L_B(L_B),
.RA(RA),
.RB(RB)
);
// Monitor the internal signal: pa_r, pb_r, state
assign {pa_r, pb_r} = {traffic_control_dut.pa_r, traffic_control_dut.pb_r};
assign state = traffic_control_dut.state;
// Generates system clock
always #(0.5 * CLK_CYCLE) CLK = ~CLK;
reg [31:0] out_file;
initial begin
out_file = $fopen("traffic_control_binary_syn.out", "w");
$timeformat(-9, 0.1, "ns", 2);
$fmonitor(
out_file,
"At time %t, CLK=%b, reset=%b, ERR=%b, PA=%b, PB=%b, L_A=%b, L_B=%b, state=%b, RA=%b, RB=%b",
$time, CLK, reset, ERR, PA, PB, L_A, L_B, state, RA, RB);
end
initial begin
CLK = 1;
PA = 0;
PB = 0;
ERR = 0;
reset = 1;
#(3.1 * CLK_CYCLE) reset = 0;
// push button when controller steps into state 0
// pushing button in state 0 has no effects
wait (state == STATE0) PA = 1;
#(1.5 * CLK_CYCLE) PA = 0;
// wait for a round and push button in state 1
wait (state == STATE2);
wait (state == STATE1) PB = 1;
#(1.5 * CLK_CYCLE) PB = 0;
// wait for a round and push button in state 2
wait (state == STATE0);
wait (state == STATE2) PA = 1;
#(1.5 * CLK_CYCLE) PA = 0;
// wait for a round and push button in state 3
wait (state == STATE0);
wait (state == STATE3);
PB = 1;
#(1.5 * CLK_CYCLE) PB = 0;
// wait for a round and push button in state 4
wait (state == STATE0);
wait (state == STATE4) PA = 1;
#(1.5 * CLK_CYCLE) PA = 0;
// wait for a round and push button in state 5
wait (state == STATE0);
wait (state == STATE5) PB = 1;
#(1.5 * CLK_CYCLE) PB = 0;
// wait for a round and push button in state 6
wait (state == STATE0);
wait (state == STATE6);
PA = 1;
#(1.5 * CLK_CYCLE) PA = 0;
// Test the priority among reset, ERR and PA(PB)
wait (state == STATE0);
wait (state == STATE1) #(0.1 * CLK_CYCLE) reset = 1;
ERR = 1;
PB = 1;
#(4 * CLK_CYCLE) reset = 0;
ERR = 0;
PB = 0;
wait (state == STATE3) $fclose(out_file);
$finish;
end
initial begin
$sdf_annotate("./netlist/traffic_control_binary.sdf", traffic_control_dut,, "sdf.log",
"MAXIMUM", "1.0:1.0:1.0", "FROM_MAXIMUM");
$enable_warnings;
$log("ncsim.log"); //outputs the log in console to file
end
endmodule
| 7.336189 |
module tb_traffic_signal_controller;
// Inputs
reg clk;
reg x;
reg reset;
// Outputs
wire [1:0] hwy;
wire [1:0] cntry;
// Instantiate the Unit Under Test (UUT)
traffic_signal_controller uut (
.clk(clk),
.x(x),
.reset(reset),
.hwy(hwy),
.cntry(cntry)
);
always #5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
x = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#10;
x = 0;
#10;
x = 0;
#10;
x = 1;
#10;
x = 0;
#10;
x = 0;
#10;
x = 1;
#10;
x = 1;
#10;
reset = 1;
end
endmodule
| 6.723729 |
module tb_transmit_cgrundey ();
reg clk_en, ctr_clr, ctr_en, conv_en_n;
wire clk_out;
wire [11:0] reg_out;
clk #(100) C1 (
clk_en,
clk_out
);
transmit_cgrundey U1 (
clk_out,
ctr_clr,
ctr_en,
conv_en_n,
reg_out
);
initial begin
clk_en = 1'b1; // enable clock
conv_en_n = 1'b1; // disable converters
ctr_en = 1'b0; // disable counter
ctr_clr = 1'b0;
#10 ctr_clr = 1'b1; // clear counter
#40 ctr_clr = 1'b0;
#50 ctr_en = 1'b1; // enable counter
#50 conv_en_n = 1'b0; // enable converters
end
endmodule
| 6.596208 |
module: transpose
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_transpose;
// Inputs
reg [95:0] input_matrix;
// Outputs
wire [95:0] output_matrix;
// Memory
wire [7:0] output_matrix_mem [0:11];
genvar i;
generate
for (i=0; i<12; i=i+1) begin: MEM
assign output_matrix_mem[i] = output_matrix[i*8+:8];
end
endgenerate
// Instantiate the Unit Under Test (UUT)
transpose uut (
.input_matrix(input_matrix),
.output_matrix(output_matrix)
);
initial begin
// Initialize Inputs
input_matrix = {8'd11, 8'd10, 8'd9, 8'd8, 8'd7, 8'd6, 8'd5, 8'd4, 8'd3, 8'd2, 8'd1, 8'd0};
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.563602 |
module tb_trigger_block ();
reg clk;
reg reset_n;
reg data_valid;
reg trig_in;
reg force_trig;
wire [31:0] pre_trig_counter;
wire [31:0] post_trig_counter;
wire [31:0] pre_trig_counter_value;
reg en_trig;
wire delayed_trig;
// Uncomment to to implament the force trirgger signal
//`define FORCE_TRIG_TEST = 1
parameter CLK_HALF_PERIOD = 5; // 100Mhz
parameter RST_DEASSERT_DELAY = 100;
parameter TRIG_ASSERT_DELAY = 1000;
parameter DATA_VALID_DELAY_IN_CLK_CYCLES = 5;
parameter PRE_TRIG_COUNT = 32'd5;
parameter POST_TRIG_COUNT = 32'd10;
parameter GO_DELAY = 110;
parameter END_SIM_DELAY = 10000;
// Generate the clock
initial begin
clk = 1'b0;
end
always begin
#CLK_HALF_PERIOD clk = ~clk;
end
// Generate the reset_n
initial begin
reset_n = 1'b0;
#RST_DEASSERT_DELAY reset_n = 1'b1;
end
// Generate data valid signal
initial begin
data_valid = 1'b0;
end
always begin
repeat (DATA_VALID_DELAY_IN_CLK_CYCLES * 2) #CLK_HALF_PERIOD;
data_valid = 1'b1;
repeat (2) #CLK_HALF_PERIOD;
data_valid = 1'b0;
end
`ifdef FORCE_TRIG_TEST
// Generate trigger signal
initial begin
trig_in = 1'b0;
end
initial begin
force_trig = 1'b0;
#TRIG_ASSERT_DELAY force_trig = 1'b1;
end
`else
initial begin
trig_in = 1'b0;
#TRIG_ASSERT_DELAY trig_in = 1'b1;
end
initial begin
force_trig = 1'b0;
end
`endif
// Generate en_trig signal
initial begin
en_trig = 1'b0;
#GO_DELAY en_trig = 1'b1;
end
initial begin
#END_SIM_DELAY;
$stop;
$finish; // close the simulation
end
// Display a warning message when
initial begin
if (GO_DELAY < RST_DEASSERT_DELAY) begin
$display("***********************************************");
$display("* Warning!!! *");
$display("* Warning!!! Warning!!! *");
$display("* Warning!!! *");
$display("* *");
$display("* *");
$display("* Go signal is asserted while in active reset *");
$display("* *");
$display("***********************************************");
$stop;
end
end
assign pre_trig_counter = PRE_TRIG_COUNT;
assign post_trig_counter = POST_TRIG_COUNT;
trigger_block dut (
.clk (clk),
.reset_n (reset_n),
.data_valid (data_valid),
.trig_in (trig_in),
.force_trig (force_trig),
.pre_trig_counter (pre_trig_counter),
.pre_trig_counter_value(pre_trig_counter_value),
.post_trig_counter (post_trig_counter),
.en_trig (en_trig),
.delayed_trig (delayed_trig)
);
endmodule
| 7.022895 |
module tb_truthtable;
reg x3, x2, x1;
wire f;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
integer i;
truthtable UUT (
.x3(x3),
.x2(x2),
.x1(x1),
.f (f)
);
initial // initial block executes only once
begin
x3 = 0;
x2 = 0;
x1 = 0;
#period; // wait for period
if (f !== 1) begin
$display("test 1 failed");
$finish;
end else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3, x2, x1, f);
x3 = 0;
x2 = 0;
x1 = 1;
#period; // wait for period
if (f !== 1) begin
$display("test 2 failed");
$finish;
end else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3, x2, x1, f);
x3 = 0;
x2 = 1;
x1 = 0;
#period; // wait for period
if (f !== 0) begin
$display("test 3 failed");
$finish;
end else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3, x2, x1, f);
x3 = 0;
x2 = 1;
x1 = 1;
#period; // wait for period
if (f !== 1) begin
$display("test 4 failed");
$finish;
end else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3, x2, x1, f);
x3 = 1;
x2 = 0;
x1 = 0;
#period; // wait for period
if (f !== 0) begin
$display("test 5 failed");
$finish;
end else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3, x2, x1, f);
x3 = 1;
x2 = 0;
x1 = 1;
#period; // wait for period
if (f !== 0) begin
$display("test 6 failed");
$finish;
end else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3, x2, x1, f);
x3 = 1;
x2 = 1;
x1 = 0;
#period; // wait for period
if (f !== 1) begin
$display("test 7 failed");
$finish;
end else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3, x2, x1, f);
x3 = 1;
x2 = 1;
x1 = 1;
#period; // wait for period
if (f !== 0) begin
$display("test 8 failed");
$finish;
end else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3, x2, x1, f);
$display("all tests passed");
$finish;
end
endmodule
| 6.771978 |
module: AM_Transmission
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_TSC;
// Inputs
reg [127:0] key;
reg clk;
reg rst;
reg Tj_Trig;
// Instantiate the Unit Under Test (UUT)
TSC uut (
.clk(clk),
.rst(rst),
.key(key),
.Tj_Trig(Tj_Trig)
);
initial begin
// Initialize Inputs
key = 0;
clk = 0;
rst = 0;
Tj_Trig = 0;
// Wait 100 ns for global reset to finish
#5;
rst = 1;
Tj_Trig = 1;
key = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
// Add stimulus here
#25
Tj_Trig = 0;
rst = 0;
#300 $finish;
end
always #5 clk = ~clk;
endmodule
| 7.490454 |
module tb_tssqrt ();
reg clk;
reg rst_n;
reg touch;
always #50 clk = ~clk;
initial begin
clk = 1'b0;
rst_n = 1'b0;
touch = 1'b0;
#500;
rst_n = 1'b1;
#5000;
touch = 1'b1;
#500000;
$finish;
end
initial begin
$fsdbDumpfile("test.fsdb");
$fsdbDumpvars(0, tb_tssqrt, "+all");
end
ts_sqrt u_ts_sqrt (
.clk (clk),
.rst_n(rst_n),
.touch(touch)
);
endmodule
| 6.695365 |
module tb_tst_6502;
reg clk;
reg clk_2x;
reg reset;
wire [3:0] vdac;
wire [7:0] gpio_o;
reg [7:0] gpio_i;
reg RX;
wire TX;
wire snd_l, snd_r, snd_nmute;
wire spi0_mosi, spi0_miso, spi0_sclk, spi0_cs0;
wire ps2_clk, ps2_dat;
wire rgb0, rgb1, rgb2;
wire [3:0] tst;
// clock sources
always #31.25 clk = ~clk;
always #15.625 clk_2x = ~clk_2x;
// reset
initial begin
`ifdef icarus
$dumpfile("tb_tst_6502.vcd");
$dumpvars;
`endif
// init regs
clk = 1'b0;
clk_2x = 1'b0;
reset = 1'b1;
RX = 1'b1;
// release reset
#1000 reset = 1'b0;
`ifdef icarus
// stop after 1 sec
#10000000 $finish;
`endif
end
// Unit under test
tst_6502 uut (
.clk (clk), // 16MHz CPU clock
.clk_2x (clk_2x), // 32MHz Video clock
.reset (reset), // Low-true reset
.vdac (vdac), // video DAC
.gpio_o (gpio_o), // gpio
.gpio_i (gpio_i),
.RX (RX), // serial
.TX (TX),
.snd_l (snd_l), // audio
.snd_r (snd_r),
.snd_nmute(snd_nmute),
.spi0_mosi(spi0_mosi), // SPI core 0
.spi0_miso(spi0_miso),
.spi0_sclk(spi0_sclk),
.spi0_cs0 (spi0_cs0),
.ps2_clk (ps2_clk), // PS/2 Keyboard port
.ps2_dat (ps2_dat),
.rgb0 (rgb0), // LED drivers
.rgb1 (rgb1),
.rgb2 (rgb2),
.tst (tst) // diagnostic port
);
endmodule
| 9.110403 |
module tb_two_port_mem;
parameter addresses = 32;
parameter width = 8;
parameter muxFactor = 0;
//Auto-calculated, user dont touch
localparam addressWidth = $clog2(addresses);
reg [addressWidth-1:0] writeAddress;
reg writeEnable;
reg [ width-1:0] writeData;
reg [addressWidth-1:0] readAddress;
reg readEnable;
wire [ width-1:0] readData;
reg clk;
initial begin
writeAddress = 0;
writeEnable = 0;
writeData = 0;
readAddress = 0;
readEnable = 0;
clk = 0;
end
always begin
#5 clk = ~clk;
end
integer i, k;
initial begin
repeat (10) @(posedge clk);
for (i = 0; i < addresses; i = i + 1) begin
writeAddress = i;
writeEnable = 1;
writeData = 0;
writeData = i[width-1:0];
@(posedge clk);
end
writeAddress = 0;
writeEnable = 0;
writeData = 0;
end
initial begin
repeat (12) @(posedge clk);
for (k = 0; k < addresses; k = k + 1) begin
readAddress = k;
readEnable = 1;
@(posedge clk);
#1;
if (readData[width-1:0] != k[width-1:0]) begin
$display("ERROR");
$finish;
end
end // for (k=0;k<addresses;k=k+1)
readAddress = 0;
readEnable = 0;
$display("Tested %d addresses", addresses);
$display("PASS");
$finish;
end
twoPortMem #(
.addresses(addresses),
.width (width),
.muxFactor(muxFactor)
) mem (
.writeAddress(writeAddress),
.writeClk(clk),
.writeEnable(writeEnable),
.writeData(writeData),
.readAddress(readAddress),
.readClk(clk),
.readEnable(readEnable),
.readData(readData)
);
endmodule
| 8.086942 |
module tb_two_wide_bufs #(
parameter DATA_WIDTH = 8, // pixel bit depth
parameter ADDR_WIDTH = 6 // address width
) ();
// input signals
reg clk, data_vld, resetn;
reg [DATA_WIDTH-1 : 0] wdata0, wdata1;
// output signals
wire sync;
wire [DATA_WIDTH-1 : 0] rdata0, rdata1;
// test signals
reg [7:0] tstcase;
reg test_failed, failed;
two_wide_transpose_buf #(DATA_WIDTH, ADDR_WIDTH) DUT (
.wdata0(wdata0),
.wdata1(wdata1),
.i_clk(clk),
.wen(data_vld),
.i_resetn(resetn),
.rdata0(rdata0),
.rdata1(rdata1),
.rsync(sync)
);
initial begin
clk = 0;
data_vld = 0;
resetn = 0;
wdata0 = 0;
wdata1 = 0;
tstcase = 0;
failed = 0;
test_failed = 0;
end
// generate
always clk = #5 ~clk;
always @(negedge clk) begin
if (tstcase < 128 + 2) begin
if (tstcase == 0) begin
resetn <= 0;
end else if (tstcase == 2) begin
resetn <= 1;
data_vld <= 1;
end else if (tstcase == 66) begin
data_vld <= 0;
end
wdata0 <= tstcase - 2;
wdata1 <= tstcase - 2 + 1;
if (sync) begin
$display("Got back %0d, %0d: ", rdata0, rdata1);
end
end
// handle printing errors
#1
if (failed) begin
// would have been the previous testc case
$display("ERORR: test case %0d failed", tstcase - 1);
failed <= 0;
test_failed <= 1;
end
// increment the test case number
#1 tstcase = tstcase + 2;
end
endmodule
| 7.468497 |
module tb_tx_fifo;
reg clock, clear_b, psel, pwrite, next_word;
reg [7:0] pw_data;
wire validword, isempty, ssptxintr;
wire [7:0] tx_data;
tx_fifo DUT (
.PCLK(clock),
.CLEAR_B(clear_b),
.PSEL(psel),
.PWRITE(pwrite),
.PWDATA(pw_data),
.NextWord(next_word),
.ValidWord(validword),
.IsEmpty(isempty),
.TxData(tx_data),
.SSPTXINTR(ssptxintr)
);
initial begin
clock = 1'b0;
clear_b = 1'b0;
psel = 1'b0;
pwrite = 1'b0;
next_word = 1'b0;
@(posedge clock);
#1;
@(posedge clock);
// Stop clearing
clear_b = 1'b1;
#80;
// Input some data
psel = 1'b1;
pwrite = 1'b1;
pw_data = 8'hAE;
#40;
pw_data = 8'h39;
#40;
pw_data = 8'hC7;
#40;
psel = 1'b0;
#80;
// Now reading out some of the data
next_word = 1'b1;
#40;
next_word = 1'b0;
#800;
next_word = 1'b1;
#40;
next_word = 1'b0;
#800;
next_word = 1'b1;
#40;
next_word = 1'b0;
#800;
$stop;
end
always #20 clock = ~clock;
endmodule
| 6.654966 |
module tb_tx_fsm ();
reg clk_rd;
reg clk_wr;
reg rst_n;
initial begin
rst_n = 1'b0;
#25 rst_n = 1'b1;
end
// 50 MHz clk_rd:
initial begin
clk_rd = 1'b1;
forever begin
#10 clk_rd = ~clk_rd;
end
end
// 100 MHz clk_wr:
initial begin
clk_wr = 1'b1;
#2
forever begin
#5 clk_wr = ~clk_wr;
end
end
reg wr_req;
reg [31:0] wr_data;
wire rd_empty;
wire out_tx_data;
wire out_tx_en;
tx_fsm #(
.BAUD(5_000_000) // 波特率是时钟频率的1/10
) component (
.clk_wr(clk_wr),
.clk_rd(clk_rd),
.wr_rst_n(rst_n),
.rd_rst_n(rst_n),
.wr_req(wr_req),
.wr_data(wr_data),
.rd_empty(rd_empty),
.out_tx_data(out_tx_data),
.out_tx_en(out_tx_en)
);
initial begin
tx_send(32'ha1b2c3d4);
tx_send(32'h9f7e5d3c);
$stop;
end
task tx_send;
input reg [31:0] tx_task_data;
begin
wr_req = 1'b0;
wr_data = tx_task_data;
#55;
wr_req <= 1'b1;
#10;
wr_req <= 1'b0;
#10000;
end
endtask
initial begin
$dumpfile("tb_tx_fsm.vcd");
$dumpvars(0, component);
end
endmodule
| 6.696753 |
module tb_tx_gate;
// Inputs
reg sel, in;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
tx_gate uut (
.out(out),
.sel(sel),
.in (in)
);
initial begin
$dumpfile("tb_tx_gate.vcd");
$dumpvars(0, tb_tx_gate);
// Initialize Inputs
in = 1;
sel = 0;
#20 $finish;
end
always #2 sel = ~sel;
always #1 in = $random;
endmodule
| 8.488876 |
module tb_tx_memory_control;
reg clk, ena, rst;
wire data_user;
wire [7:0] txid, redundancy;
wire [15:0] segment_num;
wire [23:0] bramaddr24b, vramaddr;
wire [1:0] vramaddr_c;
wire [11:0] byte_data_counter;
wire hdmimode;
wire [23:0] startaddr;
wire [7:0] doutb;
wire [7:0] aux;
wire start_frame, oneframe_done;
wire framemode;
wire maxdetect;
send_control send_control_i (
.clk125MHz(clk),
.RST(rst),
.switches(8'b11011111),
.busy(busy),
.start_frame(start_frame),
.oneframe_done(oneframe_done),
.maxdetect(maxdetect),
.segment_num_inter(segment_num),
.txid_inter(txid),
.aux_inter(aux),
.start_sending(start_sending),
.hdmimode(hdmimode),
.framemode(framemode),
.redundancy(redundancy)
);
byte_data byte_data_i (
.clk(clk),
.start(start_sending),
.advance(1'b1),
.aux(aux),
.segment_num(segment_num),
.index_clone(txid),
.vramdata(doutb),
.startaddr(startaddr),
// output
.busy(busy),
.data(),
.counter(byte_data_counter),
.data_user(data_user),
.data_valid(),
.data_enable()
);
reg pclk;
VGA_Sync_Pulses vga (
.i_Clk(pclk),
.o_HSync(HSync),
.o_VSync(VSync),
.o_Col_Count(),
.o_Row_Count()
);
tx_memory_control #(
.SEGMENT_NUMBER_MAX(5)
) uut (
.pclk(),
.rst(rst),
.clk125MHz(clk),
.txid(txid),
.hdmimode(hdmimode),
// .framemode(framemode),
.segment_num(segment_num),
.redundancy(redundancy),
.ena(ena),
.rgb_r(8'haa),
.rgb_b(8'hbb),
.rgb_g(8'hcc),
.byte_data_counter(byte_data_counter),
.bramaddr24b(bramaddr24b),
.data_user(data_user),
.startaddr(startaddr),
.oneframe_done(oneframe_done),
.maxdetect(maxdetect),
.doutb(doutb)
);
localparam cycle = 16;
initial begin
$dumpfile("tb_tx_memory_control.vcd");
$dumpvars(0, tb_tx_memory_control);
clk = 0;
ena = 0;
rst = 1;
#cycle;
rst = 0;
#(cycle * 700000);
$finish;
end
always begin
#12 pclk = !pclk;
end
always begin
#8 clk = !clk;
end
endmodule
| 6.724322 |
module tb_tx_rx_top;
parameter FRAME_WIDTH = 10;
parameter BAUD_RATE = 19200;
parameter SYS_CLK_FREQ = 200_000_000;
parameter SYS_CYCLE_TIME = 1_000_000_000 / SYS_CLK_FREQ;
parameter BIT_CYCLE_TIME = 1_000_000_000 / BAUD_RATE;
reg sys_clk;
reg reset;
reg uart_tx_en;
reg [0:FRAME_WIDTH - 1] uart_tx_din;
wire uart_tx_dout;
wire uart_tx_done;
uart_tx_top #(
.SYS_CLK_FREQ(SYS_CLK_FREQ),
.BAUD_RATE (BAUD_RATE),
.FRAME_WIDTH (FRAME_WIDTH)
) uart_tx_top_dut (
.sys_clk(sys_clk),
.reset(reset),
.uart_tx_en(uart_tx_en),
.uart_tx_din(uart_tx_din),
.uart_tx_dout(uart_tx_dout),
.uart_tx_done(uart_tx_done),
.uart_tx_bit_clk()
);
wire [0:FRAME_WIDTH - 1] uart_rx_dout;
wire uart_rx_done;
wire uart_rx_data_error;
wire uart_rx_frame_error;
uart_rx_top #(
.SYS_CLK_FREQ(SYS_CLK_FREQ),
.BAUD_RATE(BAUD_RATE),
.FRAME_WIDTH(FRAME_WIDTH)
) uart_rx_top_inst (
.sys_clk(sys_clk),
.reset(reset),
.uart_rx_din(uart_tx_dout),
.uart_rx_dout(uart_rx_dout),
.uart_rx_done(uart_rx_done),
.uart_rx_data_error(uart_rx_data_error),
.uart_rx_frame_error(uart_rx_frame_error),
.uart_rx_sample_clk()
);
always #(0.5 * SYS_CYCLE_TIME) sys_clk = ~sys_clk;
integer file;
initial begin : test
integer i;
sys_clk = 1;
reset = 1;
uart_tx_en = 0;
#(3.5 * BIT_CYCLE_TIME) reset = 0;
for (i = 1; i <= 2 ** FRAME_WIDTH; i = i + 1) begin
if (uart_tx_done) begin
uart_tx_en = 1;
uart_tx_din = i;
end else begin
uart_tx_en = 0;
i = i - 1;
end
#(BIT_CYCLE_TIME);
end
#(50 * BIT_CYCLE_TIME) $fclose(file);
$finish;
end
initial begin
file = $fopen("./output.log", "w");
end
wire sample_clk = uart_rx_top_inst.sample_clk_i;
always @(posedge sample_clk) begin
if (uart_rx_done)
$fdisplay(
file,
"data(decimal): %1d, data(binary): %b, data_error: %b, frame_error: %b",
uart_rx_dout,
uart_rx_dout,
uart_rx_data_error,
uart_rx_frame_error
);
end
endmodule
| 6.579539 |
module testbench;
reg clk, rst, T;
wire Q;
T_FF inst_1 (
T,
clk,
rst,
Q
);
initial begin
clk = 1'b1; // 1
rst = 1'b0; // 0
T = 1'b0; // 0
#20 rst = 1'b1; // 1
#40 rst = 1'b0; // 0
T = 1'b1;
#90 T = 1'b0;
end
always begin
#10 clk = ~clk;
end
endmodule
| 7.015571 |
module tb_uart_baud;
reg tb_data_clk = 0;
reg tb_rst = 0;
wire tb_baud_ena;
//1ns
localparam CLK_PERIOD = 100;
localparam RST_PERIOD = 1000;
localparam CLK_SPEED_HZ = 1000000000 / CLK_PERIOD;
//device under test
util_uart_baud_gen #(
.baud_clock_speed(CLK_SPEED_HZ),
.baud_rate(912600)
) dut (
//clock and reset
.uart_clk(tb_data_clk),
.uart_rst(~tb_rst),
.baud_ena(tb_baud_ena)
);
//reset
initial begin
tb_rst <= 1'b1;
#RST_PERIOD;
tb_rst <= 1'b0;
end
//copy pasta, vcd generation
initial begin
$dumpfile("sim/icarus/tb_uart_baud.vcd");
$dumpvars(0, tb_uart_baud);
end
//clock
always begin
tb_data_clk <= ~tb_data_clk;
#(CLK_PERIOD / 2);
end
//copy pasta, no way to set runtime... this works in vivado as well.
initial begin
#1_000_000; // Wait a long time in simulation units (adjust as needed).
$display("END SIMULATION");
$finish;
end
endmodule
| 7.174039 |
module for the SSP
// UART.
//
// Verilog Test Fixture created by ISE for module: UART_BRG
//
// Dependencies:
//
// Revision History:
//
// 0.01 08E10 MAM File Created
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_UART_BRG_v;
// Inputs
reg Rst;
reg Clk;
reg [3:0] PS;
reg [7:0] Div;
reg [3:0] Baud;
// Outputs
wire CE_16x;
// Instantiate the Unit Under Test (UUT)
UART_BRG uut (
.Rst(Rst),
.Clk(Clk),
.PS(PS),
.Div(Div),
.CE_16x(CE_16x)
);
initial begin
// Initialize Inputs
Rst = 1;
Clk = 0;
Baud = 0;
// Wait 100 ns for global reset to finish
#101;
Rst = 0;
// Add stimulus here
@(posedge Clk);
@(posedge Clk);
@(posedge Clk);
@(posedge Clk);
@(posedge Clk);
@(posedge Clk);
@(posedge Clk);
@(posedge Clk);
@(posedge Clk) #1 Baud = 1;
@(negedge CE_16x) #1 Baud = 2;
@(negedge CE_16x) #1 Baud = 3;
@(negedge CE_16x);
@(negedge CE_16x) #1 Baud = 4;
@(negedge CE_16x) #1 Baud = 5;
@(negedge CE_16x) #1 Baud = 6;
@(negedge CE_16x) #1 Baud = 7;
@(negedge CE_16x) #1 Baud = 8;
@(negedge CE_16x) #1 Baud = 9;
@(negedge CE_16x) #1 Baud = 10;
@(negedge CE_16x) #1 Baud = 11;
@(negedge CE_16x) #1 Baud = 12;
@(negedge CE_16x) #1 Baud = 13;
@(negedge CE_16x) #1 Baud = 14;
@(negedge CE_16x) #1 Baud = 15;
@(negedge CE_16x)
@(negedge CE_16x) Baud = 0;
end
///////////////////////////////////////////////////////////////////////////////
//
// Clocks
//
always #10.416 Clk = ~Clk;
///////////////////////////////////////////////////////////////////////////////
//
// Simulation Drivers/Models
//
// Baud Rate Generator's PS and Div for defined Baud Rates (48 MHz Oscillator)
always @(Baud)
begin
case(Baud)
4'b0000 : {Div, PS} <= 12'b0000_0000_0000; // Div = 1; PS = 1
4'b0001 : {Div, PS} <= 12'b0000_0001_0000; // Div = 2; PS = 1
4'b0010 : {Div, PS} <= 12'b0000_0101_0000; // Div = 6; PS = 1
4'b0011 : {Div, PS} <= 12'b0000_1111_0000; // Div = 16; PS = 1
4'b0100 : {Div, PS} <= 12'b0000_0000_1100; // Div = 1; PS = 13
4'b0101 : {Div, PS} <= 12'b0000_0001_1100; // Div = 2; PS = 13
4'b0110 : {Div, PS} <= 12'b0000_0010_1100; // Div = 3; PS = 13
4'b0111 : {Div, PS} <= 12'b0000_0011_1100; // Div = 4; PS = 13
4'b1000 : {Div, PS} <= 12'b0000_0101_1100; // Div = 6; PS = 13
4'b1001 : {Div, PS} <= 12'b0000_1011_1100; // Div = 12; PS = 13
4'b1010 : {Div, PS} <= 12'b0001_0111_1100; // Div = 24; PS = 13
4'b1011 : {Div, PS} <= 12'b0010_1111_1100; // Div = 48; PS = 13
4'b1100 : {Div, PS} <= 12'b0101_1111_1100; // Div = 96; PS = 13
4'b1101 : {Div, PS} <= 12'b1011_1111_1100; // Div = 192; PS = 13
4'b1110 : {Div, PS} <= 12'b0111_1111_1100; // Div = 128; PS = 13
4'b1111 : {Div, PS} <= 12'b1111_1111_1100; // Div = 256; PS = 13
endcase
end
endmodule
| 7.154123 |
module generates serial data. It is essentially
// a behavioral implementation of a UART transmitter, sending one character
// at a time (when invoked through one of its tasks), at a specified bit
// period. The character is sent using the RS232 protocol; START, 8 data
// bits (LSbit first), STOP.
//
// Parameters:
//
// Tasks:
// send_char_bitper : Sends a character at the specified bit period
// (in NANOSECONDS)
// set_bitper : Sets the default bit period in NANOSECONDS
// send_char : Sends a character at the default bit period
// send_char_push : Sends a character at the default bit period, and
// pushes the character into the data FIFO
//
// Functions:
//
// Internal variables:
// reg [63:0] bit_period
//
//
// Notes :
//
//
// Multicycle and False Paths
// None - this is a testbench file only, and is not intended for synthesis
//
// All times in this testbench are expressed in units of nanoseconds, with a
// precision of 1ps increments
`timescale 1ns/1ps
module tb_uart_driver (
output data_out // Transmitted serial data
);
//***************************************************************************
// Parameter definitions
//***************************************************************************
parameter BAUD_RATE = 57_600; // This is the default bit rate - can be
// overridden by "set_bitper"
//***************************************************************************
// Register declarations
//***************************************************************************
// bit_period is 1/BAUD_RATE, but needs to be in ns (not seconds), so
// we multiply by 1e9. We need to round
reg [63:0] bit_period = (1_000_000_000 + BAUD_RATE/2) /BAUD_RATE;
reg data_out_reg = 1'b1;
//***************************************************************************
// Tasks
//***************************************************************************
// The bit period is in nanoseconds since you can't pass a real to a task
task set_bitper;
input [63:0] new_bit_per;
begin
bit_period = new_bit_per;
end
endtask
task send_char_bitper (
input [7:0] char,
input [63:0] bit_per
);
integer i;
begin
$display ("%t Sending character %x (%c)",$realtime, char,char);
data_out_reg = 1'b0; // send start bit
#(bit_per);
for (i=0; i<=7; i=i+1)
begin
data_out_reg = char[i];
#(bit_per);
end
data_out_reg = 1'b1; // send stop bit
#(bit_per);
end
endtask
task send_char (
input [7:0] char
);
begin
send_char_bitper(char,bit_period);
end
endtask
task send_char_push (
input [7:0] char
);
begin
tb_char_fifo_i0.push(char);
send_char(char);
end
endtask
//***************************************************************************
// Code
//***************************************************************************
assign data_out = data_out_reg;
endmodule
| 8.426276 |
module tb_uart_fifo ();
parameter DATA_WIDTH = 8;
parameter FIFO_DEPTH = 16;
parameter ADDR_WIDTH = 4;
/* ports defination */
// read signal
reg r_pt_reset;
reg r_clk;
reg r_rst_n;
reg r_en;
wire [DATA_WIDTH - 1 : 0] r_data;
// wire [ADDR_WIDTH : 0] data_avail;
wire is_empty;
// write signal
reg w_pt_reset;
reg w_clk;
reg w_rst_n;
reg w_en;
reg [DATA_WIDTH - 1 : 0] w_data;
// wire [ADDR_WIDTH : 0] room_avail;
wire is_full;
/* initial blocks */
// generate clock and reset signal
initial begin
w_clk = 0;
forever begin
#3 w_clk = ~w_clk;
end
end
initial begin
r_clk = 0;
forever begin
#2 r_clk = ~r_clk;
end
end
initial begin
w_pt_reset = 1;
r_pt_reset = 1;
w_rst_n = 1;
r_rst_n = 1;
#10 w_rst_n = 0;
r_rst_n = 0;
#10 w_rst_n = 1;
r_rst_n = 1;
end
// generate motivation
initial begin
w_en = 0;
r_en = 0;
w_data = 0;
end
initial begin
forever begin
repeat (2) @(posedge w_clk);
w_en = !is_full;
@(posedge w_clk);
w_en = 0;
end
end
initial begin
forever begin
repeat (2) @(posedge r_clk);
r_en = !is_empty;
@(posedge r_clk);
r_en = 0;
end
end
initial begin
forever begin
@(posedge w_en);
w_data = ($random) % 256;
end
end
UartFiFo #(
.FIFO_WIDTH(DATA_WIDTH),
.FIFO_DEPTH(FIFO_DEPTH),
.ADDR_WIDTH(ADDR_WIDTH)
) UartFiFo_ins (
.w_clk(w_clk),
.w_rst_n(w_rst_n),
.w_pt_reset(w_pt_reset),
.w_en(w_en),
.w_data(w_data),
.r_clk(r_clk),
.r_rst_n(r_rst_n),
.r_pt_reset(r_pt_reset),
.r_en(r_en),
.r_data(r_data),
.is_empty(is_empty),
.is_full(is_full)
);
endmodule
| 7.55081 |
module converts RS232 serial data to parallel data.
// It is essentially a behavioral implementation of a UART receiver,
// receiving the RS232 protocol; START, 8 data bits (LSbit first), STOP,
// and signaling that it has a complete character.
//
// Parameters:
// BAUD_RATE : Baud rate for the receiver
//
// Tasks:
// start : Enables the checker
//
// Functions:
// None
//
// Notes :
//
//
// Multicycle and False Paths
// None - this is a testbench file only, and is not intended for synthesis
//
// All times in this testbench are expressed in units of nanoseconds, with a
// precision of 1ps increments
`timescale 1ns/1ps
module tb_uart_monitor (
input data_in, // Incoming serial data
output reg [7:0] char, // Received character
output reg char_val // Pulsed when char is valid
);
//***************************************************************************
// Parameter definitions
//***************************************************************************
parameter BAUD_RATE = 57_600;
localparam BIT_PER = (1_000_000_000.0)/BAUD_RATE;
//***************************************************************************
// Register declarations
//***************************************************************************
reg enabled = 1'b0;
integer i;
//***************************************************************************
// Tasks
//***************************************************************************
task start;
begin
enabled = 1'b1;
end
endtask
//***************************************************************************
// Code
//***************************************************************************
initial
char_val = 1'b0;
always @(negedge data_in)
begin
if (enabled)
begin
// This should be the leading edge of the start bit
#(BIT_PER * 1.5); // Wait until the middle of the first bit
for (i = 0; i<=7; i=i+1)
begin
// Capture the bit
char[i] = data_in;
// Wait to the middle of the next
#(BIT_PER);
end
// We should be in the middle of the stop
if (data_in !== 1'b1)
begin
$display("%t ERROR Framing error detected in %m",$realtime());
end
// Pulse char_val for 1ns
char_val = 1'b1;
char_val <= #1 1'b0;
end // if enabled
end // always
endmodule
| 7.142293 |
module tb_uart_rx_clk_gen;
parameter SYS_CLK_FREQ = 200_000_000;
parameter BAUD_RATE = 19200;
parameter CYCLE_TIME = 1_000_000_000 / SYS_CLK_FREQ;
reg sys_clk;
reg reset;
wire sample_clk;
always #(0.5 * CYCLE_TIME) sys_clk = ~sys_clk;
// dut
uart_rx_clk_gen #(
.SYS_CLK_FREQ(SYS_CLK_FREQ),
.BAUD_RATE (BAUD_RATE)
) uart_rx_clk_gen_dut (
.sys_clk (sys_clk),
.reset (reset),
.sample_clk(sample_clk)
);
initial begin
sys_clk = 1;
reset = 1;
#(3.5 * CYCLE_TIME) reset = 0;
#5000000 // 5ms
$finish;
end
endmodule
| 7.616964 |
module tb_uart_sdram ();
//********************************************************************//
//****************** Internal Signal and Defparam ********************//
//********************************************************************//
//wire define
wire tx;
wire sdram_clk;
wire sdram_cke;
wire sdram_cs_n;
wire sdram_cas_n;
wire sdram_ras_n;
wire sdram_we_n;
wire [ 1:0] sdram_ba;
wire [12:0] sdram_addr;
wire [ 1:0] sdram_dqm;
wire [15:0] sdram_dq;
//reg define
reg sys_clk;
reg sys_rst_n;
reg rx;
reg [ 7:0] data_mem [9:0]; //data_mem是一个存储器，相当于一个ram
//********************************************************************//
//**************************** Clk And Rst ***************************//
//********************************************************************//
//读取sim文件夹下面的data.txt文件，并把读出的数据定义为data_mem
initial $readmemh("E:/sources/sdram_test/uart_sdram/sim/test_data.txt", data_mem);
//时钟、复位信号
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
initial begin
rx <= 1'b1;
#200 rx_byte();
end
task rx_byte();
integer j;
for (j = 0; j < 10; j = j + 1) rx_bit(data_mem[j]);
endtask
task rx_bit(input [7:0] data); //data是data_mem[j]的值。
integer i;
for (i = 0; i < 10; i = i + 1) begin
case (i)
0: rx <= 1'b0; //起始位
1: rx <= data[0];
2: rx <= data[1];
3: rx <= data[2];
4: rx <= data[3];
5: rx <= data[4];
6: rx <= data[5];
7: rx <= data[6];
8: rx <= data[7]; //上面8个发送的是数据位
9: rx <= 1'b1; //停止位
endcase
#1040; //一个波特时间=ssys_clk周期*波特计数器
end
endtask
//重定义defparam,用于修改参数,缩短仿真时间
defparam uart_sdram_inst.uart_rx_inst.BAUD_CNT_END = 52;
defparam uart_sdram_inst.uart_rx_inst.BAUD_CNT_END_HALF = 26;
defparam uart_sdram_inst.uart_tx_inst.BAUD_CNT_END = 52;
defparam uart_sdram_inst.fifo_read_inst.BAUD_CNT_END_HALF = 26;
defparam uart_sdram_inst.fifo_read_inst.BAUD_CNT_END = 52;
defparam sdram_model_plus_inst.addr_bits = 13;
defparam sdram_model_plus_inst.data_bits = 16;
defparam sdram_model_plus_inst.col_bits = 9;
defparam sdram_model_plus_inst.mem_sizes = 2*1024*1024;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//-------------uart_sdram_inst-------------
uart_sdram uart_sdram_inst (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.rx (rx),
.tx(tx),
.sdram_clk (sdram_clk),
.sdram_cke (sdram_cke),
.sdram_cs_n (sdram_cs_n),
.sdram_cas_n(sdram_cas_n),
.sdram_ras_n(sdram_ras_n),
.sdram_we_n (sdram_we_n),
.sdram_ba (sdram_ba),
.sdram_addr (sdram_addr),
.sdram_dqm (sdram_dqm),
.sdram_dq (sdram_dq)
);
//-------------sdram_model_plus_inst-------------
sdram_model_plus sdram_model_plus_inst (
.Dq (sdram_dq),
.Addr (sdram_addr),
.Ba (sdram_ba),
.Clk (sdram_clk),
.Cke (sdram_cke),
.Cs_n (sdram_cs_n),
.Ras_n(sdram_ras_n),
.Cas_n(sdram_cas_n),
.We_n (sdram_we_n),
.Dqm (sdram_dqm),
.Debug(1'b1)
);
endmodule
| 6.916271 |
module tb_uart_tx_clk_gen;
parameter SYS_CLK_FREQ = 200_000_000;
parameter BAUD_RATE = 19200;
parameter CYCLE_TIME = 1_000_000_000 / SYS_CLK_FREQ;
reg sys_clk;
reg reset;
wire bit_clk;
always #(0.5 * CYCLE_TIME) sys_clk = ~sys_clk;
// dut
uart_tx_clk_gen #(
.SYS_CLK_FREQ(SYS_CLK_FREQ),
.BAUD_RATE (BAUD_RATE)
) uart_tx_clk_gen_dut (
.sys_clk(sys_clk),
.reset (reset),
.bit_clk(bit_clk)
);
initial begin
sys_clk = 1;
reset = 1;
#(3.5 * CYCLE_TIME) reset = 0;
#5000000 // 5ms
$finish;
end
endmodule
| 7.342384 |
module tb_uart_tx_send_logic;
parameter DATA_FRAME_WIDTH = 4;
parameter CYCLE_TIME = 5;
parameter NUM_TEST = 5;
reg bit_clk;
reg reset;
reg uart_tx_en;
reg [0:DATA_FRAME_WIDTH - 1] uart_tx_din;
wire uart_tx_dout;
wire uart_tx_done;
always #(0.5 * CYCLE_TIME) bit_clk = ~bit_clk;
// dut
uart_tx_send_logic #(
.DATA_FRAME_WIDTH(DATA_FRAME_WIDTH),
.PARITY (0)
) uart_tx_send_logic_dut (
.bit_clk (bit_clk),
.reset (reset),
.uart_tx_en (uart_tx_en),
.uart_tx_din (uart_tx_din),
.uart_tx_dout(uart_tx_dout),
.uart_tx_done(uart_tx_done)
);
initial begin : test
integer i;
bit_clk = 1;
reset = 1;
uart_tx_en = 0;
#(3.5 * CYCLE_TIME) reset = 0;
for (i = 1; i < NUM_TEST + 1; i = i + 1) begin
if (uart_tx_done) begin
uart_tx_en = 1;
uart_tx_din = i;
end else begin
uart_tx_en = 0;
i = i - 1;
end
#(CYCLE_TIME);
end
#(5 * CYCLE_TIME) $finish;
end
endmodule
| 6.682464 |
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