code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_Seven_Seg_Display ();
wire [6:0] Display;
reg [6:0] BCD;
Seven_Seg_Display DUT (
Display,
BCD
);
initial begin
#5 BCD = 4'b0000;
#5 BCD = 4'b0001;
#5 BCD = 4'b0010;
#5 BCD = 4'b0011;
#5 BCD = 4'b0100;
#5 BCD = 4'b0101;
#5 BCD = 4'b0110;
#5 BCD = 4'b0111;... | 6.686807 |
module : tb_seven_stage_cache_top_factorial
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"),... | 7.317527 |
module : tb_seven_stage_cache_top_fibonacci
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"),... | 7.317527 |
module : tb_seven_stage_cache_top_gcd
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to de... | 7.317527 |
module : tb_seven_stage_cache_top_hanoi
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to ... | 7.317527 |
module : tb_seven_stage_cache_top_mandelbrot
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software")... | 7.317527 |
module : tb_seven_stage_cache_top_primes
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to... | 7.317527 |
module tb_left_rotate;
reg clk, load;
reg [2:0] amount;
reg [7:0] data;
wire [7:0] out;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
left_rotate UUT (
.clk(clk),
.load(load),
.amount(amount),
.data(data),
.out(out)
);
initial ... | 6.692446 |
module tb_shifter8;
reg tb_clk, tb_reset_n; // 2 regs
reg [2:0] tb_op; // 3bits reg tb_op
reg [1:0] tb_shamt; // 2bits reg tb_shamt
reg [7:0] tb_d_in; // 8bits reg tb_d_in
wire [7:0] tb_d_out; // 8bits wire tb_d_out
shifter8 U0_shifter8 (
.clk(tb_clk),
.reset_n(tb_reset_n),
.op(tb... | 6.748092 |
module tb_shiftreg;
parameter n = 4;
wire [n-1:0] Q;
reg EN, in, CLK;
shiftreg shifte (
Q,
EN,
in,
CLK
);
initial begin
CLK = 0;
end
always #2 CLK = ~CLK;
initial $monitor($time, " EN=%b in=%b Q=%b\n", EN, in, Q);
initial begin
in = 0;
EN = 0;
#4 in = 1;
... | 6.935148 |
module tb_shift_counter;
wire [7:0] count;
reg clk, reset;
shift_counter counter (
count,
clk,
reset
);
initial begin
clk <= 0;
#0 reset <= 1;
#20 reset <= 0;
#95 reset <= 1;
#105 reset <= 0;
end
initial begin
repeat (100) begin
#10 clk = ~clk;
end
... | 6.90184 |
module tb_shift_custom;
// Parameters
parameter SYS_PERIOD = 20; // 系统时钟
parameter VGA_PERIOD = 20; // VGA时钟
// sobel_img_gen Outputs
reg VGA_HS;
reg VGA_VS;
reg VGA_DE;
reg [11:0] VGA_X;
reg [11:0] VGA_Y;
wire o_sobel_data;
// shift_custom Inputs
reg ... | 8.138566 |
module tb_shift_line_buffer;
reg sclk;
reg s_rst_n;
reg in_line_vaild;
reg [7:0] din;
wire [7:0] taps0x;
wire [7:0] taps1x;
wire [7:0] taps2x;
//------------- generate system signals ------------------------------------
initial begin
sclk = 1;
s_rst_n <= 0;
din <= 'd0;
in_line_vail... | 6.653422 |
module tb_shift_reg ();
parameter WIDTH = 8;
reg clk;
reg d;
reg en;
reg reset;
wire [WIDTH-1:0] q;
ShiftReg #(WIDTH) sreg (
.clk(clk),
.d(d),
.en(en),
.reset(reset),
.q(q)
);
initial begin
clk = 0;
d = 0;
en = 0;
reset = 1;
#5 en = 1;
d = 1;
... | 6.846966 |
module tb_shift_register;
parameter DEPTH = 4;
parameter WIDTH = 4;
reg clk;
reg rst_n;
reg en;
reg [WIDTH-1:0] d;
wire [WIDTH-1:0] q;
shift_register #(
.DEPTH(DEPTH),
.WIDTH(WIDTH)
) _shift_register (
.clk (clk),
.rst_n(rst_n),
.en (en),
.d (d),
.q ... | 7.38506 |
module tb_Shif_reg4 ();
reg Data_In, reset;
reg clock = 0;
wire Data_out;
Shif_reg4 DUT (
Data_out,
Data_In,
clock,
reset
);
always #5 clock = ~clock; // clock declaration
initial begin
Data_In = 1'b0;
reset = 0; // apply serial input
#10 reset = 1'b1;
#10 Dat... | 6.608219 |
module tb_sie ();
reg usb_clk;
initial usb_clk = 1'b0;
always #10 usb_clk = ~usb_clk;
reg usb_clk_rx;
initial usb_clk_rx = 1'b0;
always #10 usb_clk_rx = ~usb_clk_rx;
reg usb_rst;
task waitclock;
begin
@(posedge usb_clk);
#1;
end
endtask
reg [7:0] tx_data;
reg tx_valid;
wi... | 6.501981 |
module: signExtend
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_sigExtend;
// Inputs
reg [15:0] i_data;
// Outputs
wire [31:0] o_data;
// Instantiate the Unit Under Tes... | 6.52184 |
module tb_sigmoid_seq ();
localparam DATA_WIDTH = 8;
localparam NUM_INPUT_DATA = 1;
localparam WIDTH_INPUT_DATA = NUM_INPUT_DATA * DATA_WIDTH;
localparam NUM_OUTPUT_DATA = 1;
localparam WIDTH_OUTPUT_DATA = WIDTH_INPUT_DATA;
localparam signed [DATA_WIDTH-1:0] ZERO_POINT = {DATA_WIDTH{1'b0}};
localparam N... | 7.060484 |
module tb_signal_gen;
// Praramers
parameter INPUT_PORTS = 3;
// Inputs
reg clk;
reg rst;
reg req;
// Outputs
wire [INPUT_PORTS-1:0] stm_value;
wire gnt;
// Instantiate the Unit Under Test (UUT)
signal_gen #(
.INPUT_PORTS(INPUT_PORTS)
) uut (
.clk(clk),
.rst(rst),
.req... | 7.430905 |
module tb_signal_transfer ();
localparam S_RATE = 1000.0 / 200.0;
localparam M_RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_signal_transfer.vcd");
$dumpvars(0, tb_signal_transfer);
#1000000 $finish;
end
reg s_clk = 1'b1;
always #(S_RATE / 2.0) s_clk = ~s_clk;
reg s_reset = 1'b1;
... | 8.62057 |
module tb_signedextender;
reg [ 4:0] in = 5'b11001;
wire [15:0] out;
SignedExtender5to16 uut (
.in (in),
.out(out)
);
initial begin
#20 in = 5'b00111;
end
endmodule
| 6.683495 |
module tb_signed_divide_multicycle ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_signed_divide_multicycle.vcd");
$dumpvars(0, tb_signed_divide_multicycle);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100.... | 7.351884 |
module tb_ext_sign ();
parameter NB_IN = 16;
parameter NB_OUT = 32;
reg [ NB_IN-1:0] i_data;
wire [NB_OUT-1:0] o_data;
initial begin
i_data = 16'd7;
#40 i_data = 16'd57;
#40 i_data = 16'd273;
#40 i_data = 16'hff01;
#200 $finish;
end
ext_sign ext_sign (
.i_data(i_data)... | 7.514208 |
module tb_sign_extender ();
reg signed [7:0] in;
reg s;
wire [15:0] out;
integer i, j;
sign_extender uut (
.In (in),
.S (s),
.Out(out)
);
initial begin
$display("Starting Testbench");
//testing signed things
in = 8'b11111111;
s = 1;
#5;
in = 8'b00001111;... | 7.307135 |
module tb_sim;
`include "bch_params.vh"
parameter T = 4;
parameter OPTION = "SERIAL";
parameter DATA_BITS = 64;
parameter BITS = 8;
parameter REG_RATIO = 1;
parameter SEED = 0;
localparam BCH_PARAMS = bch_params(DATA_BITS, T);
reg [31:0] seed = SEED;
integer samples = 0;
initial begin
$d... | 6.638818 |
module tb_simple_fsm;
reg clk, reset, in;
wire out;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
simple_fsm UUT (
.clk(clk),
.reset(reset),
.in(in),
.out(out)
);
initial // Clock generation
begin
clk = 0;
forever begin
... | 8.263991 |
module tb_Simple_AXI_RAM;
parameter NUM_SLOTS = 5;
parameter ADDR_WIDTH_BITS = $clog2(NUM_SLOTS);
parameter DATA_WIDTH_BYTES = 4;
parameter DATA_WIDTH_BITS = DATA_WIDTH_BYTES * 8;
// Interface Signals
reg clk;
reg rst; // reset on high
// AXI4-Lite I... | 6.577202 |
module tb_reg_mem;
parameter DATA_WIDTH = 8; //8 bit wide data
parameter ADDR_BITS = 5; //32 Addresses
reg [ ADDR_BITS-1:0] addr;
reg [DATA_WIDTH-1:0] data_in;
wire [DATA_WIDTH-1:0] data_out;
reg wen, clk;
//Note passing of parameters syntax
reg_mem #(DATA_WIDTH, ADDR_BITS) RM (
addr,
... | 7.502985 |
module tb_simple_CPU;
parameter DATA_WIDTH = 8; //8 bit wide data
parameter ADDR_BITS = 5; //32 Addresses
parameter INSTR_WIDTH = 20; //20b instruction
reg clk, rst;
reg [INSTR_WIDTH-1:0] instruction;
reg [ DATA_WIDTH-1:0] output_reg;
simple_cpu #(DATA_WIDTH, ADDR_BITS, INSTR_WIDTH) SCPU_DUT (
... | 7.02698 |
module tb_simple_fsm ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//reg define
reg sys_clk;
reg sys_rst_n;
reg pi_money;
... | 8.263991 |
module tb_simple_hash;
// Inputs
reg [ `HASH_WORD_WIDTH-1:0] data_in;
// Outputs
wire [`HASH_RESULT_WIDTH-1:0] data_out;
// Instantiate the Unit Under Test (UUT)
simple_hash uut (
.data_in (data_in),
.data_out(data_out)
);
initial begin
data_in = 0;
#20;
data_in = 1;
#2... | 6.534743 |
module tb_Simple_RAM;
parameter DATA_WIDTH_BYTES = 4;
parameter DATA_WIDTH_BITS = DATA_WIDTH_BYTES * 8;
parameter NUM_SLOTS = 5;
parameter ADDR_WIDTH_BITS = $clog2(NUM_SLOTS);
// Interface signals
reg clk;
reg rst;
reg r_en;
... | 6.980752 |
module TestBench ();
reg clk;
reg reset;
reg [31:0] addr;
reg [3:0] mask;
reg enable;
reg cmd;
reg [31:0] write_data;
wire [31:0] load_data;
wire valid;
mem memory (
clk,
reset,
addr,
mask,
enable,
cmd,
write_data,
load_data,
valid
);
a... | 7.747207 |
module tb_SingleCycle ();
reg clk, rst;
// 產生時脈，週期：10ns
initial begin
clk = 1;
forever #5 clk = ~clk;
end
initial begin
rst = 1'b1;
/*
指令資料記憶體，檔名"instr_mem.txt, data_mem.txt"可自行修改
每一行為1 Byte資料，以兩個十六進位數字表示
且為Little Endian編碼
*/
$readmemh("instr_mem.txt", CPU.InstrMem.mem_array);... | 7.196278 |
module TB_SingleDP ();
//2- Delcaracion de señales.
//Registers
reg CLK;
//3- Module Structure
//Instances
SingleDP Finish (CLK);
always #100 CLK = ~CLK; //Always
initial begin
//Evalue
$dumpfile("Phase 1");
$dumpvars(0, TB_SingleDP);
CLK <= 0;
#1200 $stop;
end
endmodu... | 6.687279 |
module : tb_single_cycle_cache_top_factorial
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software")... | 7.223153 |
module : tb_single_cycle_cache_top_fibonacci
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software")... | 7.223153 |
module : tb_single_cycle_cache_top_gcd
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to d... | 7.223153 |
module : tb_single_cycle_cache_top_hanoi
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to... | 7.223153 |
module : tb_single_cycle_cache_top_mandelbrot
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"... | 7.223153 |
module : tb_single_cycle_cache_top_primes
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), t... | 7.223153 |
module tb_single_MIPS;
reg clk;
reg reset;
mips_single MIPS (
clk,
reset
);
initial begin
forever #2 clk <= ~clk;
end
initial begin
clk <= 1'b0;
reset <= 1'b0;
#2 reset <= 1'b1;
#2 reset <= 1'b0;
#222 $stop;
end
endmodule
| 6.694941 |
module tb_single_port_ram;
reg clk;
reg we;
reg [15:0] addr;
reg [15:0] din;
wire [15:0] dout;
initial begin
$from_myhdl(clk, we, addr, din);
$to_myhdl(dout);
end
single_port_ram dut (
clk,
we,
addr,
din,
dout
);
endmodule
| 6.842034 |
module tb_sin_3phase_tbl ();
localparam RATE = 1000.0 / 125.0;
initial begin
$dumpfile("tb_sin_3phase_tbl.vcd");
$dumpvars(0, tb_sin_3phase_tbl);
#100000 $finish;
end
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
wire cke =... | 7.032748 |
module siso_left_Nb_top;
parameter W = 4, SW = 4;
reg RST;
reg CLK;
reg LSHIFT;
reg [W-1:0] IN;
wire [W-1:0] OUT;
siso_left_Nb #(
.BUS_WIDTH (W),
.SISO_WIDTH(SW)
) siso_l (
.RST(RST),
.CLK(CLK),
.LSHIFT(LSHIFT),
.IN(IN),
.OUT(OUT)
);
initial begin
RS... | 7.062855 |
module siso_left_right_Nb_top;
parameter W = 4, SW = 4;
reg RST;
reg CLK;
reg [1:0] SHIFT;
reg [W-1:0] IN;
wire [W-1:0] OUT;
siso_left_right_Nb #(
.BUS_WIDTH (W),
.SISO_WIDTH(SW)
) siso_l (
.RST(RST),
.CLK(CLK),
.SHIFT(SHIFT),
.IN(IN),
.OUT(OUT)
);
initi... | 7.027217 |
module siso_right_Nb_top;
parameter W = 4, SW = 4;
reg RST;
reg CLK;
reg RSHIFT;
reg [W-1:0] IN;
wire [W-1:0] OUT;
siso_right_Nb #(
.BUS_WIDTH (W),
.SISO_WIDTH(SW)
) siso_l (
.RST(RST),
.CLK(CLK),
.RSHIFT(RSHIFT),
.IN(IN),
.OUT(OUT)
);
initial begin
... | 6.96141 |
module tb_site (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,... | 7.655482 |
module tb_sm ();
reg n;
reg d;
reg clk;
reg rst;
wire op;
wire [1:0] state;
wire [1:0] nstate;
sm UUT (
.n ( n ),
.d ( d ),
.clk ( clk ),
.rst ( rst ),
.op ( op ),
.state ( state ),
.nstate ( nstate )
);
initial begin
clk = 0;
rst = 1;
... | 6.602217 |
module tb_sm4_core ();
reg r_clk;
reg r_rst;
reg r_flag;
reg r_key_en;
reg [127:0] r_key;
reg r_din_en;
reg [127:0] r_din;
reg [ 31:0] r_err;
reg [ 2:0] r_count;
reg r_test;
wire s_dout_en;
wire [127:0] s_dout;
wire s_... | 6.516363 |
module tb_CountEvenOneZero;
// Inputs
reg data_in, clk, reset;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
CountEvenOneZero uut (
.data_in(data_in),
.clk(clk),
.reset(reset),
.out(out)
);
initial begin
$dumpfile("tb_CountEvenOneZero.vcd");
$dumpvars(0,... | 6.869616 |
module tb_snif #(
parameter ADR_WIDTH = 6
) ();
reg clk;
reg rst;
reg [ADR_WIDTH-1:0] adr_i;
reg we_i;
wire detect_o;
integer j;
snif #(
.ADR_WIDTH(ADR_WIDTH)
) i_snif (
.clk_i(clk),
.rst_i(rst),
.adr_i(adr_i),
.we_i (we_i),
.detect_o(detect_o)
);
in... | 7.47311 |
module tb_snurisc;
reg reset, clk;
initial clk = 0;
always #50 clk = !clk;
initial begin
$vcdplusfile;
$vcdpluson;
end
initial begin
reset = 1;
#200 reset = 0;
#2000 $finish;
end
snurisc dut (
.reset(reset),
.clk (clk)
);
endmodule
| 6.609914 |
module tb_sobel;
reg clock;
reg reset_n;
reg readdatavalid;
reg [15:0] readdata;
reg waitrequest;
reg ready;
reg cont = 1;
reg [9:0] counter = 0;
reg [15:0] memory[0:131072];
wire [31:0] address;
reg [31:0] rdadr;
reg isread = 0;
initial begin
isread <= 0;
clock <= 0;
ready <= 0;
... | 7.497741 |
module tb_sobel ();
//wire define
wire tx;
wire hsync;
wire vsync;
wire [7:0] rgb;
//reg define
reg clk;
reg rst_n;
reg rx;
reg [7:0] data_mem[9999:0]; //data_mem是一个存储器，相当于一个ram
//读取sim文件夹下面的data.txt文件，并把读出的数据定义为data_mem
initial $readmemh("E:/GitLib/Alt... | 8.05892 |
module tb_soc ();
reg cpu_en;
reg clk;
reg rst_n;
reg io_rtcToggle;
wire rd_insn_en;
wire [ `PC_WIDTH - 1 : 0] pc;
reg [`WORD_WIDTH - 1 : 0] insn;
soc_top u_soc_top (
.cpu_en ... | 6.85777 |
module: soc_block
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_soc_block;
// Inputs
reg clk;
reg reset;
reg rx;
reg interrupt;
reg bit8;
reg parity_en;
reg odd_n_even;... | 6.636792 |
module tb_soc_bram_ctl ();
parameter PERIOD = 2;
reg clk = 0; // Posedge = 0
wire [31:0] dread;
wire done;
reg [31:0] dwrite;
reg [7:0] addr;
reg rw, valid;
`ifdef SIM
always #(PERIOD / 2) clk = ~clk;
`endif
initial begin
`ifdef SIM
$dumpfile("tb_bram_ctl.vcd");
$dumpvars(0, bram_ctl, f_st... | 6.681025 |
module tb_soc_j68 (
input UART0_RX, // RX load port
output UART0_TX, // TX load port
input UART1_RX, // RX terminal
output UART1_TX // TX terminal
);
// ========================================================================
// Reset and clock generation
// ================================... | 7.002042 |
module tb_softusb ();
reg sys_clk;
reg sys_rst;
reg usb_clk;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
wire irq;
/* 100MHz system clock... | 6.540109 |
module tb_sort;
reg clk, rst_n;
reg vaild_i;
reg [ 15:0] v_in;
reg [127:0] x_in;
wire [ 15:0] v_out;
wire [127:0] x_out;
wire datavaild_o;
top top_sort_u0 (
.clk(clk),
.rst_n(rst_n),
.vaild_i(vaild_i),
.v_in(v_in),
.x_in(x_in),
.v_out(v_out),
... | 6.600177 |
module sort2_tb ();
// Signal Declarations
reg [3:0] in0, in1; // Inputs
wire [3:0] out0, out1; // Outputs
// Unit Under Test Instantiation
sort2 UUT (
.in0 (in0),
.in1 (in1),
.out0(out0),
.out1(out1)
);
initial begin
in1 = 4'b0000;
in0 = 4'b1111;
#10
// Print ... | 6.65339 |
module tb_sort2values;
/*test the three cases A=B, A<B, A>B and verify the control signal start and
and the push signal*/
reg clock;
reg reset;
reg start;
reg [7:0] A, B;
wire [7:0] data_out;
wire push;
initial //following block executed only once
begin
clock = 0;
reset = 0;
... | 6.666778 |
module sort4_tb ();
// Signal Declarations
reg [3:0] in0, in1, in2, in3; // Inputs
wire [3:0] out0, out1, out2, out3; // Outputs
// Unit Under Test Instantiation
sort4 UUT (
.in0 (in0),
.in1 (in1),
.in2 (in2),
.in3 (in3),
.out0(out0),
.out1(out1),
.out2(out2),
... | 6.672724 |
module TB_Sorter #(
parameter N = 16,
W = 16
);
// Inputs
reg clk;
reg [W-1:0] DATA_IN[N-1:0];
reg start;
// Outputs
wire [N*W-1:0] keyIn, keyOut;
//wire [N*W:0] keyIn_tmp [0:1];
wire [W-1:0] DATA_OUT[N-1:0];
wire ready;
integer f, i;
SorterMain #(4, W) sorter (
//INPUT
.c... | 6.837896 |
module tb_sort_4sequence ();
// note this only runs for 50 cycles with the below settings
// alter TB_TIMEOUT to run longer
localparam TB_TIMEOUT = 96000;
localparam TB_CLK_PERIOD = 2000;
localparam TB_RST_PERIOD = 4000;
reg ini;
reg writeoutput;
reg [1:0] count;
reg [1:0] countout;
integer outfi... | 7.411279 |
module: FIR1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or... | 7.743492 |
module tb_SpecialPcUnit;
localparam ADDRESS_BITS = 20;
localparam DATA_WIDTH = 32;
reg clk;
reg rst;
reg en;
reg [ADDRESS_BITS-1:0] curr_pc;
wire done;
wire valid;
wire [ADDRESS_BITS-1:0] out_pc;
S... | 6.905456 |
module: spi
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_spi;
// Inputs
reg clk;
reg enviar_dato;
reg recibir_dato;
reg [7:0] din;
reg spi_do;
// Outputs
wire [7:0] d... | 6.909089 |
module testbench;
reg clk = 0;
reg cs;
reg sr_in;
reg [7:0] data;
wire sr_out;
wire [7:0] gpioout;
integer i;
spigpio testbe (
.clk(clk),
.cs(cs),
.sr_in(sr_in),
.gpioout(gpioout),
.sr_out(sr_out)
);
initial begin
... | 7.015571 |
module tb_spi_flash_be ();
//wire define
wire cs_n;
wire sck;
wire mosi;
//reg define
reg clk;
reg rst_n;
reg key;
//时钟、复位信号、模拟按键信号
initial begin
clk = 0;
rst_n <= 0;
key <= 0;
#100 rst_n <= 1;
#1000 key <= 1;
#20 key <= 0;
end
always #10 clk <= ~clk;
defpa... | 6.979364 |
module tb_spi_flash_pp ();
//wire define
wire cs_n;
wire sck;
wire mosi;
wire [7:0] cmd_data;
//reg define
reg clk;
reg rst_n;
reg key;
//时钟、复位信号、模拟按键信号
initial begin
clk = 0;
rst_n <= 0;
key <= 0;
#100 rst_n <= 1;
#1000 key <= 1;
... | 6.979364 |
module tb_spi_flash_read ();
//wire define
wire cs_n;
wire sck;
wire mosi;
wire miso;
wire tx;
//reg define
reg clk;
reg rst_n;
reg key;
//时钟、复位信号、模拟按键信号
initial begin
clk = 0;
rst_n <= 0;
key <= 0;
#100 rst_n <= 1;
#1000 key <= 1;
#20 key <= 0;
end
always... | 6.979364 |
module tb_spi_flash_se ();
//wire define
wire cs_n;
wire sck;
wire mosi;
//reg define
reg clk;
reg rst_n;
reg key;
//时钟、复位信号、模拟按键信号
initial begin
clk = 0;
rst_n <= 0;
key <= 0;
#100 rst_n <= 1;
#1000 key <= 1;
#20 key <= 0;
end
always #10 clk <= ~clk;
defpa... | 6.979364 |
module tb_spi_flash_seq_wr ();
//wire define
wire tx;
wire cs_n;
wire sck;
wire mosi;
wire miso;
//reg define
reg clk;
reg rst_n;
reg rx;
reg [7:0] data_mem[299:0]; //data_mem是一个存储器，相当于一个ram
//读取sim文件夹下面的data.txt文件，并把读出的数据定义为data_mem
init... | 6.979364 |
module TB_SPI_MasSlv;
reg rstb;
reg clk = 1'b0;
reg mlb = 1'b0;
reg start = 1'b0;
reg [7:0] m_tdat = 8'b00000000;
reg [1:0] cdiv = 0;
wire din;
wire ss;
wire sck;
wire dout;
wire Mdone;
wire [7:0] Mrdata;
reg ten = 1'b0;
reg [7:0] s_tdata = 8'b00000000;
wire SLVdone;
wire [7:0] SLVrdata;... | 7.040552 |
module tb_SPI_Master ();
reg clk;
reg rst;
wire SPI_MOSI;
wire SPI_SCLK;
wire SPI_CS;
wire SPI_MISO;
reg [31:0] sendData;
wire [31:0] recvData;
reg sendStart;
SPI_Master spimaster (
.clk(clk),
.rst(rst),
.sendStart(sendStart),
.SPI_MOSI(SPI_MOSI),
.SPI_SCLK(SPI_SCLK),... | 6.949372 |
module prescaler (
Q,
CLK
);
output [0:0] Q;
input CLK;
wire CLK;
wire [0:0] Q;
wire [4:0] plusOp;
wire \w_counter_reg_n_0_[0] ;
wire \w_counter_reg_n_0_[1] ;
wire \w_counter_reg_n_0_[2] ;
wire \w_counter_reg_n_0_[3] ;
LUT1 #(
.INIT(2'h1)
) \w_counter[0]_i_1 (
.I0(\w_counter_... | 7.858126 |
module tb_SPI_Transmitter ();
reg clk;
reg rst;
wire sendComplete;
wire MOSI;
wire SCLK;
wire CS;
wire MISO;
reg [31:0] sendData;
wire [31:0] recvData;
SPI_Transmitter transmitter (
.clk(clk),
.rst(rst),
.sendComplete(sendComplete),
.MOSI(MOSI),
.SCLK(SCLK),
.CS... | 7.051019 |
module tb_SpongentHash;
wire [87:0] hash;
reg [87:0] reference_hash;
reg clk;
reg rst;
reg en;
wire rdy;
SpongentHash uut (
.clk(clk),
.rst(rst),
.en(en),
.rdy(rdy),
.hash_out(hash)
);
initial begin
clk = 0;
rst = 1;
en = 0;
// Set refe... | 6.627228 |
module: SPSLmnCE
//
// Dependencies:
//
// Revision:
//
// 0.01 13G20 MAM File Created
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_SPSLmnCE;
parameter pDataWidth = 8;
parameter pAddrWidth = 4;
parameter pDepth = (2**pAddrWidth);... | 7.139502 |
module tb_sp_mash111;
// mash111 Parameters
parameter PERIOD = 10;
parameter WIDTH = 9;
parameter OUT_REG = 1;
// mash111 Inputs
reg clk = 0;
reg rst_n = 0;
reg [WIDTH-1:0] x_i = 0;
// mash111 Outputs
wire [ 3:0] y_o;
wire [WIDTH-1:0] e_o;
initial begin
f... | 6.650396 |
module tb_squareroot ();
reg [15:0] num = 'b0;
wire [7:0] sqr;
wire sqr_flag;
reg CLK = 0;
reg RST = 1;
square_root dut (
.num(num),
.CLK(CLK),
.RST(RST),
.sqr(sqr),
.sqr_flag(sqr_flag)
);
always #2.5 CLK = ~CLK;
initial begin
#2 RST = 0;
#5 num = 16'd4;
... | 6.599975 |
module TB_SRAM_Controller ();
reg clk = 1'b0, rst = 1'b0;
// Input from Memory Stage
reg write_enable = 1'b0, read_enable = 1'b0;
reg [ `ADDRESS_LEN - 1 : 0] address;
reg [ `REGISTER_LEN - 1 : 0] write_data;
// To WB Stage
wire [ `REGISTER_LEN - 1 : 0] read_data;
// To Freeze other Stage... | 6.606895 |
module emulates the external SRAM device during simulation
module tb_SRAM_Emulator (
input logic Clock_50,
input logic Resetn,
inout wire [15:0] SRAM_data_io,
input logic [17:0] SRAM_address,
input logic SRAM_UB_N,
input logic SRAM_LB_N,
input logic SRAM_WE_N,
input logic SRAM_CE_N,
input logic SRAM_OE_N
);
... | 7.334367 |
module tb_src_a_mux ();
localparam STEP = 10;
reg [31 : 0] pc;
reg [31 : 0] rs1_data;
reg [31 : 0] imm;
reg [`SEL_SRC_A_WIDTH - 1 : 0] select;
wire [31 : 0] alu_src_a;
src_a_mux src_a_mux (
.pc(pc),
.rs1_data(rs1_data),
.imm(imm),
.select(select),
.alu_src_a(alu_src_a)
)... | 6.886737 |
module tb_src_b_mux ();
localparam STEP = 10;
reg [31 : 0] rs2_data;
reg [31 : 0] imm;
reg [`SEL_SRC_B_WIDTH - 1 : 0] select;
wire [31 : 0] alu_src_b;
src_b_mux src_b_mux (
.rs2_data(rs2_data),
.imm(imm),
.select(select),
.alu_src_b(alu_src_b)
);
initial begin
rs2_data = ... | 7.118669 |
module tb_srlatch; //testbench of SR-Latch
reg tb_r, tb_s; // 2 inputs
wire tb_q, tb_q_bar; // use 2wires
_srlatch U0_srlatch (
.r(tb_r),
.s(tb_s),
.q(tb_q),
.q_bar(tb_q_bar)
); // instance by using _srlatch
initial begin
tb_r = 1'b0;
tb_s = 1'b0; //input (tb_r,tb_s)=(0,... | 6.552543 |
module: SSP_UART
//
// Dependencies: SSP_UART
//
// Revision History:
//
// 0.01 08F13 MAM File Created
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_SSP_UART_v;
// UUT Interface
reg Rst;
reg Clk;
reg SSP_SSEL;
reg... | 7.30643 |
module tb_stage #(
parameter STAGE = 0, //valid: 0-4
parameter PHV_LEN = 48 * 8 + 32 * 8 + 16 * 8 + 5 * 20 + 256,
parameter KEY_LEN = 48 * 2 + 32 * 2 + 16 * 2 + 5,
parameter ACT_LEN = 25,
parameter KEY_OFF = 3 * 6
) ();
reg clk;
reg rst_n;
reg [PHV_LEN-1:0] ph... | 7.268105 |
module tb_state ();
reg sclk;
reg s_rst_n;
reg catcher;
reg jockey_r;
reg jockey_l;
reg key;
wire direct;
wire stepenable;
initial begin
sclk = 1'b1;
s_rst_n <= 1'b0;
catcher <= 1'b1;
jockey_l <= 1'b1;
jockey_r <= 1'b1;
key <= 1'b0;
#100 s_rst_n <= 1'b1;
... | 7.588164 |
module tb_state_cola_1 ();
reg sys_clk;
reg sys_rst_n;
reg pi_money;
wire po_cola;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
pi_money <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
//pi_money 随机数模拟投币情况
always @(posedge sys_clk or negedge sys_rst_n)
... | 6.556409 |
module tb_state_cola_2 ();
reg sys_clk;
reg sys_rst_n;
reg pi_money_one;
reg pi_money_half;
wire po_cola;
wire po_money;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
pi_money_half <= 1'b0;
pi_money_one <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
... | 6.556409 |
module tb_stimulus_gen;
parameter PERIOD = 10; // 100MHz clock
parameter INPUT_PORTS = 3;
parameter RESET_PORT = 1; // 0: no reset, 1: has reset
parameter RESET_SENS = 0; // 0: Active Low, 1: Active High
// Inputs
// Internal Signals
reg clk;
wire [INPUT_PORTS-1:0] stm_value;
wire rsb;
wire gn... | 7.691737 |
module tb_stream_joint ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_stream_joint.vcd");
$dumpvars(0, tb_stream_joint);
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
parameter NUM = 4;
parameter ID_WIDTH = 4;
paramete... | 7.268285 |
module tb_subbyte ();
reg clk;
reg rst_n;
reg [127:0] data_in;
reg start_in;
reg en_de;
// internal wires
wire [127:0] data_out;
wire ready_out;
// dump variable
parameter DUMP_FILE = "tb.vcd";
initial begin
$display("Dump variables..");
$dumpvars("AC");
$dumpfile(D... | 6.642068 |
module simulates the top-level module for the Sudoku Master
// game.
`timescale 1ns/1ns
module tb_sudokuMasterTop ();
reg CLK, RST;
reg [3:0] userNum;
reg upButton, downButton, leftButton, rightButton;
reg writeSwitch;
wire [6:0] userNumDisp;
wire wpInd;
wire [27:0] rowDisp;
wire winInd;
wire [6:0] t... | 6.687085 |
module: Sumador4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_Sumador4;
// Inputs
reg [63:0] inputPC;
// Outputs
wire [63:0] Nextinst;
// Instantiate the Unit Under Tes... | 6.729994 |
module tb_super ();
localparam BITS = 8;
localparam T = 4;
localparam DATA_BITS = 64;
localparam PIPELINE_STAGES = 0;
localparam N = 127;
reg [BITS-1:0] data_in;
reg clk;
reg pre_start;
wire start;
reg ce;
wire ready;
wire [BITS-1:0] data_out;
wire first;
wire last;
wire data_bits;
wir... | 6.67692 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.