code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module td_fused_top_fifo_w10_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd10;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w5_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w5_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w7_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w7_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w7_d2_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w7_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_Block_entry_proc_proc408 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37738_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd8;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37738_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 3;
parameter MEM_SIZE = 8;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
inpu... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37738_products_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd144;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [Address... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37738_products_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 8;
parameter MEM_SIZE = 144;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37738_weight_vecs_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd288;
parameter AddressWidth = 32'd9;
input reset;
input c... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37738_weight_vecs_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 9;
parameter MEM_SIZE = 288;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0]... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37738_ifmap_vec_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd144;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input ... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37738_ifmap_vec_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 8;
parameter MEM_SIZE = 144;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input... | 6.827284 |
module td_fused_top_start_for_tdf4_readFilters36_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
... | 6.827284 |
module td_fused_top_start_for_tdf4_readFilters36_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [D... | 6.827284 |
module td_fused_top_fifo_w16_d2_S_x1 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
... | 6.827284 |
module td_fused_top_fifo_w16_d2_S_x1_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0]... | 6.827284 |
module td_fused_top_fifo_w11_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd11;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w11_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd11;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w12_d8_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
... | 6.827284 |
module td_fused_top_fifo_w12_d8_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] ... | 6.827284 |
module td_fused_top_fifo_w6_d8_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w6_d8_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w1_d9_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w1_d9_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w11_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd11;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w11_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd11;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w7_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w7_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_tdf4_l2_writeOutputs_133_running_sums_1 (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] addres... | 6.827284 |
module td_fused_top_tdf4_l2_writeOutputs_133_running_sums_1_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] ... | 6.827284 |
module td_fused_top_Block_entry_proc_proc403 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37832_l2_products #(
parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 4,
BufferCount = 2,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37832_l2_products_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37832_l2_products_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37832_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd8;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37832_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 3;
parameter MEM_SIZE = 8;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
inpu... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37832_products_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd144;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [Address... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37832_products_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 8;
parameter MEM_SIZE = 144;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37832_weight_vecs_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd288;
parameter AddressWidth = 32'd9;
input reset;
input c... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37832_weight_vecs_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 9;
parameter MEM_SIZE = 288;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0]... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37832_ifmap_vec_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd144;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input ... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37832_ifmap_vec_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 8;
parameter MEM_SIZE = 144;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input... | 6.827284 |
module td_fused_top_start_for_tdf3_readFilters30_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
... | 6.827284 |
module td_fused_top_start_for_tdf3_readFilters30_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [D... | 6.827284 |
module td_fused_top_fifo_w16_d2_S_x0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
... | 6.827284 |
module td_fused_top_fifo_w16_d2_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0]... | 6.827284 |
module td_fused_top_fifo_w12_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w12_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w6_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w6_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w4_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w4_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w4_d2_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w4_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_Block_entry_proc_proc397 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37928_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd8;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37928_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 3;
parameter MEM_SIZE = 8;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
inpu... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37928_products_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressW... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37928_products_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
o... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37928_weight_vecs_0_0_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
inpu... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37928_weight_vecs_0_0_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37928_ifmap_vec_0_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
inp... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP37928_ifmap_vec_0_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
in... | 6.827284 |
module td_fused_top_start_for_tdf2_readFilters24_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
... | 6.827284 |
module td_fused_top_start_for_tdf2_readFilters24_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [D... | 6.827284 |
module td_fused_top_fifo_w16_d2_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
... | 6.827284 |
module td_fused_top_fifo_w16_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] ... | 6.827284 |
module td_fused_top_fifo_w1_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w1_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w12_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w12_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w6_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w6_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w5_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w5_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w5_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w5_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_Block_entry_proc_proc392 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd8;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 3;
parameter MEM_SIZE = 8;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
inpu... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd144;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [Address... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 8;
parameter MEM_SIZE = 144;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_weight_vecs_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd288;
parameter AddressWidth = 32'd9;
input reset;
input c... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_weight_vecs_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 9;
parameter MEM_SIZE = 288;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0]... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd144;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input ... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 8;
parameter MEM_SIZE = 144;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input... | 6.827284 |
module td_fused_top_start_for_tdf1_readFilters18_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
... | 6.827284 |
module td_fused_top_start_for_tdf1_readFilters18_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [D... | 6.827284 |
module td_fused_top_fifo_w16_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w16_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w1_d9_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w1_d9_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w14_d9_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd14;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w14_d9_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd14;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w7_d9_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w7_d9_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
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