code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TemperatureMonitor_tb ();
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam time PER1 = 20 * ONE_NS;
// Declare the input clock signals
reg DCLK_TB = 1;
wire [ 6:0] DADDR_TB;
wire DEN_TB;
wire DWE_TB;
wire [15:0] DI_TB;
wire [15:0] DO_TB;
wire DRD... | 8.35573 |
module RW_DATA_MODULE (
input CLK,
input RW,
input [79:0] DATA_TO_SEND,
input [7:0] COUNTER,
input ENABLE,
input INIT,
inout ONE_WIRE_LINE,
output reg [79:0] DATA_RECEIVED,
output READY,
output reg test_pin
);
wire ONE_WIRE_ENABLE;
reg DATA_TO_DRIVER = 0;
reg ONE_WIRE_ENA... | 7.169553 |
module CLK_DIVIDER_3P3MHz (
input CLK_3P3MHz,
output UPDATE_COUNTER,
output BTN_SAMPLE,
output ONE_WIRE_CLK,
output READ_OUT_TIMER
);
reg [19:0] COUNTER = 20'b0;
always @(posedge CLK_3P3MHz) COUNTER <= COUNTER + 1;
assign UPDATE_COUNTER = COUNTER[19];
assign READ_OUT_TIMER = COUNTER[13];
... | 8.139274 |
module Digilent_IOX (
// -- Connections to Digilent Parallel Port (DPP) interface
// -- Controlled by Digilent ADEPT 2 software and USB controller
input ASTB, // Address strobe
input DSTB, // Data strobe
input WRITE, // Read/Write control
inout ... | 7.604002 |
module CLK_DIVIDER_3P3MHz (
input CLK_3P3MHz,
output UPDATE_COUNTER,
output BTN_SAMPLE,
output ONE_WIRE_CLK,
output READ_OUT_TIMER
);
reg [19:0] COUNTER = 20'b0;
always @(posedge CLK_3P3MHz) COUNTER <= COUNTER + 1;
assign UPDATE_COUNTER = COUNTER[19];
assign READ_OUT_TIMER = COUNTER[13];
... | 8.139274 |
module Digilent_IOX (
// -- Connections to Digilent Parallel Port (DPP) interface
// -- Controlled by Digilent ADEPT 2 software and USB controller
input ASTB, // Address strobe
input DSTB, // Data strobe
input WRITE, // Read/Write control
inout ... | 7.604002 |
module RW_DATA_MODULE (
input CLK,
input RW,
inout [71:0] DATA,
inout [7:0] COUNTER,
input ENABLE,
input INIT,
inout ONE_WIRE_LINE,
output READY,
output OK
);
wire ONE_WIRE_DATA;
wire ONE_WIRE_ENABLE;
reg ONE_WIRE_DATA_reg = 0;
reg ONE_WIRE_ENABLE_reg = 0;
wire ONE_WIRE_R... | 7.169553 |
module CLK_DIVIDER_3P3MHz (
input CLK_3P3MHz,
output BTN_SAMPLE,
output ONE_WIRE_CLK
);
reg [19:0] COUNTER = 20'b0;
always @(posedge CLK_3P3MHz) COUNTER <= COUNTER + 1;
assign BTN_SAMPLE = COUNTER[17];
assign ONE_WIRE_CLK = COUNTER[1];
endmodule
| 8.139274 |
module Digilent_IOX (
// -- Connections to Digilent Parallel Port (DPP) interface
// -- Controlled by Digilent ADEPT 2 software and USB controller
input ASTB, // Address strobe
input DSTB, // Data strobe
input WRITE, // Read/Write control
inout ... | 7.604002 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Descri... | 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Descri... | 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Descri... | 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Descri... | 7.09244 |
module func_hdl_top
#(
parameter DATAW = <dataw>
,parameter STREAMW = <streamw>
)
(
input clock
,input resetn
,input ivalid
,input iready
,output ovalid
,output oready
<ports>
);
//statically synchronized, no handshaking
assign ovalid = 1'b1;
assign oready = 1'b1;
// ival... | 7.616956 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Descri... | 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Descri... | 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Descri... | 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Descri... | 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Descri... | 7.09244 |
module: GasDetectorSensor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TemplateTB;
// Inputs
reg arst;
reg clk;
reg din;
// Outputs
wire [2:0] dout;
// Instantiate the U... | 7.168269 |
module conv3d_kernel_{{n_channel}}_channel_size_3 #(
parameter DATA_WIDTH = 32,
parameter IMG_WIDTH = 56,
parameter IMG_HEIGHT = 56,
parameter CHANNEL = {{n_channel}},
// Cx_Wy = CHANNELx_WEIGHTy
{{param_weight_bias}}
)
(
{{port}}
);
localparam NUM_OPERANDs = CHANNEL;
lo... | 7.186689 |
module conv3d_{{n_kernel}}_kernel_{{n_channel}}_channel_size_3 #(
parameter DATA_WIDTH = 32,
parameter IMG_WIDTH = 56,
parameter IMG_HEIGHT = 56,
parameter CHANNEL = {{n_channel}},
parameter NUM_KERNEL = {{n_kernel}},
// Kx_Cy_Wz = KERNELx_CHANNELy_WEIGHTz
{{param_weight_bias}}
)
(
... | 6.915441 |
module {{module_name}} #(
parameter DATA_WIDTH = 32,
parameter WIDTH = 56,
parameter HEIGHT = 56,
parameter CHANNEL_OUT = {{n_kernel}}
)
(
{{port}}
);
// testbench cho mach conv3d_8kernel_3channel
wire [DATA_WIDTH-1:0] conv_out [0: CHANNEL_OUT -1];
wire conv_valid_out;
... | 7.532924 |
module TempLoader
/*
*/
(
//input clock
input wire MCLK,
//time(sec)
output reg [13:0] TEMPDATA,
//control
input wire nLOAD,
output reg nCOMPLETE,
output reg nCS = 1'b1,
inout wire SIO,
output reg CLK = 1'b0
);
/*
TC77 DATA LOADER
*/
//TC77 fmax = 7MHz, 48MH... | 6.54294 |
module tempo #(
parameter BPM = 60,
parameter GENERATE_CLOCK = 1,
)(
input wire clock_in,
output reg clock_out,
output reg whole,
output reg half,
output reg quarter,
output reg eighth,
output reg sixteenth,
output reg thirtysecond,
output reg sixtyfourth,
);
localparam COUNTER_BPM = ... | 6.778752 |
module TemporaryWord(
input clk,
input start,
input [31:0] e,
input [31:0] f,
input [31:0] g,
input [31:0] h,
input [31:0] const,
input [31:0] word,
input [31:0] a,
input [31:0] b,
input [31:0] c,
output [31:0] outputFirst,
outpu... | 6.551848 |
module TemporaryWordOne(
input clk,
input rst,
input [31:0]e,
input [31:0]f,
input [31:0]g,
input [31:0]h,
input [31:0] const,
input [31:0]word,
output [31:0] outputData
);
wire [31:0] func5Out;
wire [31:0] func4Out;
Function4 rotrE(clk,rst,e,func4Out);
Function5... | 6.551848 |
module TemporaryWordTwo (
input clk,
input rst,
input [31:0] a,
input [31:0] b,
input [31:0] c,
output [31:0] outputData
);
wire [31:0] func6Output;
wire [31:0] func4Output;
Function3 func3 (
clk,
rst,
a,
func4Output
);
Function6 maj (
rst,
a,
... | 6.551848 |
module: temporizador
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module temporizadorSim;
// Inputs
reg clk_100MHz;
reg [1:0] value;
reg start_timer;
// Outputs
wire t_expired;
... | 7.383646 |
module TemporizadorTest (
input clk,
input btnl,
input btnd,
input btnr,
input btnp,
input [3:0] speed,
output [7:3] led,
output [6:0] seg,
output [3:0] an
);
wire out;
wire on;
Debouncer started (
.clk(clk),
.signal(btnp),
.signal_state(out)
);
temporiza... | 7.722977 |
module: temporizador
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module temporizador_test;
// Inputs
reg clk_100MHz;
reg value;
reg start_timer;
// Outputs
wire t_expired;
// ... | 7.383646 |
module tempo_selector (
input [ 2:0] val,
output [31:0] beat_cycles
);
reg [31:0] cycles;
always @* //NOTE: You are describing combo logic, since there is no clock signal
case (val)
3'b000: cycles = 32'd100000000;
3'b001: cycles = 32'd80000000;
3'b010: cycles = 32'd66666666;
3'... | 7.626886 |
module TempReg (
input CLK,
input [31:0] IData,
output reg [31:0] OData
);
initial begin
OData = 0;
end
always @(posedge CLK) begin
OData <= IData;
end
endmodule
| 8.830372 |
module Tempreture (
clk,
rst,
ds,
led,
cs,
key1,
key2,
key3,
key_p,
key_i,
key_d,
static_p1,
static_p2,
work_status,
show_flag_wire,
heater_status,
fan_status,
heater_control,
loopfin
);
input key1, key2, key3, key_p, key_i, key_d;
input rs... | 7.907516 |
module: TemperatureCalculator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tempretureCalculatorTest;
// Inputs
reg [7:0] factoryBaseTemp;
reg [3:0] factoryTempCoef;
reg [3:0]... | 8.396779 |
module tempsense #(
parameter DAC_RESOLUTION = 6,
parameter COUNTER_BITWIDTH = 12
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input wire clk,
input wire rst_n,
input wire start_conv_in,
output wire [DAC_RESOLUTI... | 8.085909 |
module tempsense_vdac #(
parameter BITWIDTH = 6
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input wire [BITWIDTH-1:0] data,
input wire enable,
output wir... | 7.359722 |
module tempsense_vdac_cell #(
parameter PARALLEL_CELLS = 4
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input wire sign,
input wire data,
input wire enable,
output wire vout_analog
);
wire en_vref, en_pupd, npu_pd;
... | 7.359722 |
module temperature_top (
output [7:0] led_output_o, //iesire pentru aprinderea fiecarui led
output alert_o, //semnalul de alerta(este 1 daca iesirea este aprox in exteriorul 19:26)
input [39:0] sensors_data_i, // val de temperatura
input [4:0] sensors_en_i
); //bit de enable, daca este 1 atunci est... | 7.039424 |
module temp_decoder_encoder (
clock,
clock_4x,
reset,
rxtx,
rx_byte,
rx_valid,
tx_bytes,
tx_num_bytes,
tx_valid,
tx_switch
);
parameter MAX_BYTES = 5;
input clock;
input clock_4x;
input reset;
inout rxtx;
input [MAX_BYTES*8-1:0] tx_bytes;
input [3:0] tx_num_bytes;... | 6.67617 |
module temp_demo (
input wire clk_in,
input wire rst_n,
inout wire dq,
output wire [4:0] temp
);
wire clk;
//clk_div
clk_div clk_div_inst (
.clk_in (clk_in),
.rst_n (rst_n),
.clk_out(clk)
);
//temp_rd
temp_rd temp_rd_inst (
.clk_in(clk), //1.024M
.rst_n(rst... | 7.076962 |
module HPR_HEAPMANGER_T0 (
input clk,
input reset,
output reg [63:0] RESULT,
input [63:0] SIZE_IN_BYTES,
input REQ,
output reg ACK,
output reg FAIL
);
reg [32:0] base;
always @(posedge clk)
if (reset) begin
ACK <= 0;
FAIL <= 0;
base <= 4096; // Do n... | 6.619502 |
module temp_read_driver (
input clk, // 100 MHz clock
input rst, // Asynchronous reset, tied to dip switch 0
output reg iocs, // chip select
output reg read,
input rda, // received data available
input [ 7:0] data_in,
... | 7.688327 |
module temp_register (
input clk,
reset_n,
load,
increment,
decrement,
input [7:0] data,
output negative,
positive,
zero
);
endmodule
| 7.226009 |
module Temp_Reg_A (
input clk,
input [31:0] data_in,
output reg [31:0] data_out
);
always @(posedge clk) begin
data_out <= data_in;
end
endmodule
| 7.133229 |
module Temp_Reg_ALU (
input clk,
input [31:0] data_in,
output reg [31:0] data_out
);
always @(posedge clk) begin
data_out <= data_in;
end
endmodule
| 7.525206 |
module Temp_Reg_B (
input clk,
input [31:0] data_in,
output reg [31:0] data_out
);
always @(posedge clk) begin
data_out <= data_in;
end
endmodule
| 7.162564 |
module Temp_Reg_DM (
input clk,
input lb_sign,
input [31:0] data_in,
output reg [31:0] data_out
);
reg lb_pos;
always @(posedge clk) begin
if (!lb_sign) data_out <= data_in;
else data_out <= {{24{data_in[7]}}, data_in[7:0]};
end
endmodule
| 7.577336 |
module temp_result_calc (
clk,
rst,
ldresult,
one_bit_mult_x,
powercnt,
init_result,
temp_result
);
input clk, rst, init_result, ldresult;
input [11:0] one_bit_mult_x;
input [5:0] powercnt;
output reg [11:0] temp_result;
always @(posedge clk, posedge rst) begin
if (rst) temp_re... | 6.545635 |
module temp_sense (
input clk,
arst, // < 80 MHz
output reg [7:0] degrees_c,
output reg [7:0] degrees_f,
output reg [11:0] degrees_f_bcd,
output reg fresh_sample,
failed_sample
);
parameter OFFSET_DEGREES = 8'd133;
/////////////////////////////////////
// slow down the clock by 2 fo... | 8.244752 |
module temp_sense_s5 (
input clk, // ~50-100 MHz
output reg [7:0] degrees_c,
output reg [7:0] degrees_f
);
//////////////////////////////////////////////
wire [7:0] tsd_out;
wire tsd_done;
reg tsd_clr = 1'b0;
reg tsd_clr_inv = 1'b0 /* synthesis preserve */;
wire tsd_clk;
reg tsd_ce = 1'b0 ... | 7.32193 |
module temp_test (
input wire [31:0] test,
output reg [31:0] boop
);
always @(*) begin
boop = test;
end
endmodule
| 6.623247 |
module JK (
clk,
j,
k,
q,
qn
);
input clk, j, k;
output q, qn;
reg q;
wire qn;
always @(posedge clk) begin
case ({
j, k
})
2'b00: q <= q;
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= ~q;
default: q <= q;
endcase
end
assign qn ... | 6.897092 |
module TENBASET_TxD (
clk20,
SendingPacket,
pkt_data,
rdaddress,
ShiftData,
ShiftCount,
CRCflush,
CRC,
readram,
Ethernet_TDp,
Ethernet_TDm
);
input clk20; // a 20MHz clock (this code won't work with a different frequency)
input [7:0] pkt_data;
output [10:0] rdaddress;... | 7.086672 |
module TensorReg ( // tensor register , read data from it on negedge, send data to it on posedge
input iClk,
input ena, // high volt active , enable signal
input wEna, // high volt active, write enable signal
input [4:0] addrIn,
input [255:0] dataIn,
output reg [255:0] dataOut
);
reg [255... | 6.663223 |
module FPAddSub_single_32 (
clk,
rst,
a,
b,
operation,
result,
flags
);
// Clock and reset
input clk; // Clock signal
input rst; // Reset (active high, resets pipeline registers)
// Input ports
input [31:0] a; // Input A, a 32-bit floating point number
input [31:0] b; // In... | 6.626859 |
module FpAddSub_b_32 (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
SumS_5,
Shift,
PSgn,
Opr
);
input [22:0] Mmax; // The larger mantissa
input [23:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; //... | 6.675503 |
module FPAddSub_c_32 (
SumS_5,
Shift,
CExp,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [32:0] SumS_5; // Smaller mantissa after 16|12|8|4 shift
input [4:0] Shift; // Shift amount
// Input ports
input [7:0] CExp;
// Output ports
output [22:... | 6.891648 |
module FPAddSub_d_32 (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
NegE,
InputExc,
P,
Flags
);
// Input ports
input ZeroSum; // Sum is zero
input [8:0] NormE; // Normalized exponent
input [22:0] NormM; // Normalized mantissa
input R; // Rou... | 7.959097 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [16-1:0] a; // Input A, a 32-bit floating point number
input [16-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; ... | 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [23-1:0] NormM; // Normalized 7
input [8:0] NormE; // Normalized exponent
// Output Ports
output [8:0] RoundE;
output [8:0] RoundEP;
output [23:0] RoundM;
output [23:0] Roun... | 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [23:0] RoundM; // Normalized 7
input [23:0] RoundMP; // Normalized exponent
input [8:0] RoundE; // Normalized 7 + 1
input [8:0] RoundEP; // Normalized 8+ 1... | 7.570448 |
module tensor_weight_y1_bkb_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 144;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" ... | 7.058897 |
module tensor_weight_y1_bkb (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd144;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - ... | 7.058897 |
module tensor_weight_y2_bkb_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 144;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" ... | 7.058897 |
module tensor_weight_y2_bkb (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd144;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - ... | 7.058897 |
module TensTimer (
input wire clk, //250Hz
input wire rst_n,
input wire [1:0] state,
output reg slake
);
parameter ZERO = 2'b01;
reg [11:0] cnt = 0;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
slake <= 0;
cnt <= 0;
end else if (state... | 6.827799 |
module tens_comp (
x,
y
);
input [3:0] x;
output reg [3:0] y;
//case statement used to find 10's complement of input
always @(x) begin
case (x)
4'b0000: y = 4'b1010;
4'b0001: y = 4'b1001;
4'b0010: y = 4'b1000;
4'b0011: y = 4'b0111;
4'b0100: y = 4'b0110;
4'b0101: y... | 6.655538 |
module tenth_sec_clk (
input wire clk, // 100MHz
output clock_divide_tenth_sec // 101Hz
);
localparam div_val = 9999999;
integer counter = 0;
reg hold = 0;
assign clock_divide_tenth_sec = hold;
always @(posedge clk) begin
if (counter == div_val) begin
counter = 0; //resets counter
... | 7.185516 |
module ten_gige_phy_clk_gen (
input areset,
input refclk_p,
input refclk_n,
output refclk,
output clk156,
output dclk
);
wire clk156_buf;
wire dclk_buf;
wire clkfbout;
IBUFDS_GTE2 ibufds_inst (
.O (refclk),
.ODIV2(),
.CEB (1'b0),
.I (refclk_p),
.IB... | 6.893508 |
module ten_gig_eth_mac (
input reset,
//Transmit user I/F
input tx_clk0,
input tx_dcm_lock,
input tx_underrun,
input [63:0] tx_data,
input [ 7:0] tx_data_valid,
input tx_start,
output tx_ack,
input [ 7:0] tx_ifg_delay,
output ... | 6.594556 |
module ten_gig_eth_mac_0 (
// Port declarations
input tx_clk0,
input reset,
input wire tx_axis_aresetn,
input wire [63 : 0] tx_axis_tdata,
input wire [ 7:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
input wire tx_axis_tlast,... | 6.594556 |
module ten_gig_eth_mac_0_sync_resetn (
input clk, // clock to be sync'ed to
input resetn_in, // Reset to be 'synced'
output resetn_out // synced reset
);
// Internal Signals
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_async0 = 1'b0;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO... | 6.594556 |
module ten_gig_eth_mac_0_xgmii_if (
// Port declarations
input reset,
input rx_axis_rstn,
input tx_clk0,
input tx_clk90,
input [63:0] xgmii_txd_core,
input [ 7:0] xgmii_txc_core,
output [31:0] xgmii_txd,
output ... | 6.594556 |
module ten_gig_eth_mac_UCB (
input reset,
input tx_clk0,
input tx_dcm_lock,
input rx_clk0,
input rx_dcm_lock,
// transmit interface
output tx_underrun,
input [63:0] tx_data,
input [7:0] tx_data_valid,
input tx_start,
output tx_ack,
output tx_ifg_delay,
output tx_stati... | 6.594556 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
//---------------------------------------------------------------------------
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// ... | 9.028271 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
// An active high reset is included with a parameterized reset
// value
//-----------------------------------------------... | 9.028271 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
//---------------------------------------------------------------------------
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// ... | 9.028271 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
// An active high reset is included with a parameterized reset
// value
//-----------------------------------------------... | 9.028271 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
// An active high reset is included with a parameterized reset
// value
//-----------------------------------------------... | 9.028271 |
module holds the top level component declaration for the
// 10Gb/E PCS/PMA core.
//---------------------------------------------------------------------------
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. ... | 7.541523 |
module ten_mhz_clock (
clock_in,
reset,
clock_out
);
input clock_in, reset;
output reg clock_out;
reg [11:0] counter;
always @(posedge clock_in or negedge reset) begin
if (!reset) begin
counter <= 0;
clock_out <= 0;
end else begin
if (counter == 12'h004) begin
c... | 6.734305 |
module fibonacci_lfsr2(
input clk, [5:0]seedz,
input rst_n,
output [3:0] data
);
wire feedback = data[3] ^ data[1] ;
reg [3:0] out1 = 0 , out2 = 0;
always @(posedge clk)
if (~rst_n)
out1 <= 3'hf;
else
out1 <= {out1[2:0], feedback} ;
always @(negedge c... | 6.969171 |
module ten_sec_clk (
input wire clk, // 100MHz
output clock_divide_ten_sec // 1Hz
);
localparam div_val = 499999999;
integer counter = 0;
reg hold = 0;
assign clock_divide_ten_sec = hold;
always @(posedge clk) begin
if (counter == div_val) begin
counter = 0; //resets counter
hold =... | 7.157244 |
module TERAISC_AB_DECODER (
DI_SYSCLK,
DI_PHASE_A,
DI_PHASE_B,
DO_PULSE,
DO_DIRECT
);
// input
//
input DI_SYSCLK;
input DI_PHASE_A;
input DI_PHASE_B;
// output
//
output DO_PULSE;
output DO_DIRECT;
// register
//
reg DO_PULSE;
reg PULSE_DOUBLE;
reg PULSE_DOUB... | 6.860234 |
module TERAISC_PWM_EX (
clk,
reset_n,
//
s_cs,
s_address,
s_write,
s_writedata,
s_read,
s_readdata,
//
PWM
);
`define REG_TOTAL_DUR 0
`define REG_HIGH_DUR 1
`define REG_ADJ_SPEED 2
`define REG_ABORT 3
`define REG_STATUS 2
input clk;
input reset_n;
input s_... | 7.608025 |
module TERASIC_ADC_READ (
clk,
reset_n,
// avalon slave
s_chipselect,
s_read,
s_readdata,
s_write,
s_writedata,
// export interface
SPI_CLK,
SPI_CS_n,
SPI_IN,
SPI_OUT
);
input clk;
input reset_n;
input s_chipselect;
input s_read;
output reg [15:0] s_readd... | 8.29736 |
module TERASIC_CAMERA (
clk,
reset_n,
// streaming source interface
st_data,
st_valid,
st_sop,
st_eop,
st_ready,
// export
CAMERA_D,
CAMERA_FVAL,
CAMERA_LVAL,
CAMERA_PIXCLK
);
input clk;
input reset_n;
output [23:0] st_data;
output st_valid;
output... | 7.909958 |
module TERASIC_CLOCK_COUNT (
// avalon bus
s_clk_in,
s_reset_in,
s_address_in,
s_read_in,
s_readdata_out,
s_write_in,
s_writedata_in,
// clock bus
CLK_1,
CLK_2
);
`define REG_START 2'b00
`define REG_READ_CLK1 2'b01
`define REG_READ_CLK2 2'b10
input s_clk_in;
inpu... | 7.507823 |
module TERASIC_DC_MOTOR_PWM (
input clk,
input reset_n,
//
input s_cs,
input [ 1:0] s_address,
input s_write,
input [31:0] s_writedata,
input s_read,
output reg [31:0] s_readdata,
//
output reg PWM,
ou... | 6.59791 |
module Terasic_IrDA_0 (
input wire s_read, // avalon_slave.read
input wire s_cs_n, // .chipselect_n
output wire [31:0] s_readdata, // .readdata
input wire s_write, // .write
input wire [31:0] s_writedata,... | 7.328238 |
module TERASIC_IRM (
clk, // must be 50 MHZ
reset_n,
// interrrupt
irq,
// avalon slave
s_cs_n,
s_read,
s_readdata,
s_write,
s_writedata,
// export
ir
);
input clk;
input reset_n;
output reg irq;
input s_cs_n;
input s_read;
output [31:0] s_readdata;
i... | 7.674776 |
module TERASIC_IR_RX_FIFO (
clk, // must be 50 MHZ
reset_n,
// interrrupt
irq,
// avalon slave
s_address,
s_cs_n,
s_read,
s_readdata,
s_write,
s_writedata,
// export
ir
);
`define IR_RX_DATA_REG 0
`define IR_RX_CS_REG 1
input s_address;
input clk;
inp... | 8.14762 |
module TERASIC_LOOPBACK (
clk,
reset_n,
// avalon mm slave
s_cs,
s_read,
s_readdata,
s_write,
s_writedata,
//
lb_in,
lb_out
);
parameter PAIR_NUM = 32;
parameter PAIR_BIR = 1;
input clk;
input reset_n;
//
input s_cs;
input s_read;
input s_write;
output reg... | 8.584522 |
module TERASIC_PWM_EX (
clk,
reset_n,
//
s_cs,
s_address,
s_write,
s_writedata,
s_read,
s_readdata,
//
PWM
);
`define REG_TOTAL_DUR 0
`define REG_HIGH_DUR 1
`define REG_ADJ_SPEED 2
`define REG_ABORT 3
`define REG_STATUS 2
input clk;
input reset_n;
input s_... | 7.700539 |
module board_regs (
input wire clk,
input wire rst,
input wire cs,
input wire we,
input wire [ 7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter def... | 7.886152 |
module TERASIC_SPI_3WIRE (
clk,
reset_n,
//
s_chipselect,
s_address,
s_write,
s_writedata,
s_read,
s_readdata,
// condui
SPI_CS_n,
SPI_SCLK,
SPI_SDIO
);
input clk;
input reset_n;
// avalon slave
input s_chipselect;
input [3:0] s_address;
input s_write... | 8.216858 |
module TERASIC_SRAM (
// global clk/reset
clk,
reset_n,
// avalon slave
s_chipselect_n,
s_byteenable_n,
s_write_n,
s_read_n,
s_address,
s_writedata,
s_readdata,
// SRAM interface
SRAM_DQ,
SRAM_ADDR,
SRAM_UB_n,
SRAM_LB_n,
SRAM_WE_n,
SRAM_CE_n,
... | 7.627867 |
module TERASIC_STREAM_SOURCE (
// clock
clk,
reset_n,
// mm slave
s_cs,
s_read,
s_write,
s_readdata,
s_writedata,
// streaming source
src_ready,
src_valid,
src_data,
src_sop,
src_eop,
user_mode
);
parameter VIDEO_W = 800;
parameter VIDEO_H = 600... | 7.054555 |
module terminal (
`include "fifo_define.v"
input wire wr_en,
input wire rd_en,
input wire [`width-1:0] wr_data,
input wire terminal_valid,
input wire rstn,
input wire clk,
output reg [`width-1:0] rd_data, // APB ... | 8.692363 |
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