code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module td_fused_top_fifo_w4_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w4_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w4_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w4_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_Block_entry_proc_proc (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0 #(
parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 3,
BufferCount = 2,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd14;
parameter AddressWidth = 32'd4;
input reset;
input clk... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 4;
parameter MEM_SIZE = 14;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd14;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [Addres... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 4;
parameter MEM_SIZE = 14;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd27;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressW... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 27;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
o... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec #(
parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 5,
BufferCount = 2,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
in... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd54;
parameter AddressWidth = 32'd6;
input reset;
input clk;
... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 6;
parameter MEM_SIZE = 54;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
... | 6.827284 |
module td_fused_top_td_fused_axi_in_p (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4;
parameter AddressWidth = ... | 6.827284 |
module td_fused_top_td_fused_axi_in_p_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 2;
parameter MEM_SIZE = 4;
input [AWIDTH-1:0] addr0;
input ce0... | 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd49000;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
i... | 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 49000;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input... | 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd6272;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
inp... | 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 13;
parameter MEM_SIZE = 6272;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input c... | 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd3136;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3136;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd12544;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 14;
parameter MEM_SIZE = 12544;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd25088;
parameter AddressWidth = 32'd15;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 15;
parameter MEM_SIZE = 25088;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd50176;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 50176;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_axi_in_p (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4;
parameter AddressWidth = ... | 6.827284 |
module td_fused_top_td_fused_axi_in_p_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 2;
parameter MEM_SIZE = 4;
input [AWIDTH-1:0] addr0;
input ce0... | 6.827284 |
module td_fused_top_td_fused_axi_in_p (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4;
parameter AddressWidth = ... | 6.827284 |
module td_fused_top_td_fused_axi_in_p_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 2;
parameter MEM_SIZE = 4;
input [AWIDTH-1:0] addr0;
input ce0... | 6.827284 |
module td_fused_top_td_fused_axi_in_p_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 2;
parameter MEM_SIZE = 4;
input [AWIDTH-1:0] addr0;
input ce0... | 6.827284 |
module td_fused_top_mac_muladd_10s_9ns_8ns_16_4_1 (
clk,
reset,
ce,
din0,
din1,
din2,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
... | 6.827284 |
module td_fused_top_mac_muladd_10s_9ns_8ns_16_4_1_DSP48_0 (
input clk,
input rst,
input ce,
input [10 - 1:0] in0,
input [9 - 1:0] in1,
input [8 - 1:0] in2,
output [16 - 1:0] dout
);
wire [27 - 1:0] a;
wire [18 - 1:0] b;
wire [48 - 1:0] c;
wire [45 - 1:0] m;
wire [48 - 1:0] p;
re... | 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd49000;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
i... | 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 49000;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input... | 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd49000;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
i... | 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 49000;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input... | 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 49000;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input... | 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd3136;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3136;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd3136;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3136;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3136;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd50176;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 50176;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd50176;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 50176;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 50176;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd25088;
parameter AddressWidth = 32'd15;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 15;
parameter MEM_SIZE = 25088;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd25088;
parameter AddressWidth = 32'd15;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 15;
parameter MEM_SIZE = 25088;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 15;
parameter MEM_SIZE = 25088;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd12544;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 14;
parameter MEM_SIZE = 12544;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd12544;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 14;
parameter MEM_SIZE = 12544;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 14;
parameter MEM_SIZE = 12544;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd6272;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
inp... | 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 13;
parameter MEM_SIZE = 6272;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input c... | 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd6272;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
inp... | 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 13;
parameter MEM_SIZE = 6272;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input c... | 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 13;
parameter MEM_SIZE = 6272;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input c... | 6.827284 |
module teater ();
reg clock, nreset, d;
DFlipFlop D1 (
q,
clock,
nreset,
d
);
always #10 clock = ~clock;
initial begin
//$dumpfile("testDFlipFlop.dump");
//$dumpvars(1,D1);
#0 d = 0;
clock = 0;
nreset = 0;
#50 nreset = 1;
#1000 $finish;
end
always #8... | 7.39571 |
module tea_decryptor_core #(
parameter DELTA = 32'h9E3779B9
) (
input wire resetn
, input wire clk
, input wire [127:0] key
, input wire [ 63:0] textI
, input wire textI_vld
, output wire [ 63:0] textO
, output wire textO_vld
);
//----------------... | 6.93617 |
module tea_decryptor_stream
#(parameter STREAM_WIDTH_DATA=64
, STREAM_WIDTH_DS=(STREAM_WIDTH_DATA/8)
, STREAM_WIDTH_TID=8
, STREAM_WIDTH_TDEST=3
, STREAM_WIDTH_TUSER=1
, TEA_KEY=128'hABAB_ABAB_ABAB_ABAB_ABAB_ABAB_ABAB_ABAB
, ... | 6.93617 |
module tea_encryptor_core #(
parameter DELTA = 32'h9E3779B9
) (
input resetn
, input clk
, input wire [127:0] key
, input wire [ 63:0] textI
, input wire textI_vld
, output wire [ 63:0] textO
, output wire textO_vld
);
//----------------... | 6.740986 |
module tea_encryptor_stream
#(parameter STREAM_WIDTH_DATA=64
, STREAM_WIDTH_DS=(STREAM_WIDTH_DATA/8)
, STREAM_WIDTH_TID=8
, STREAM_WIDTH_TDEST=3
, STREAM_WIDTH_TUSER=1
, TEA_KEY=128'hABAB_ABAB_ABAB_ABAB_ABAB_ABAB_ABAB_ABAB
, ... | 6.740986 |
module _90_fa (
A,
B,
C,
X,
Y
);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B, C;
output [WIDTH-1:0] X, Y;
wire [WIDTH-1:0] t1, t2, t3;
assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
assign Y = t1 ^ C, X = t2 | t3;
endmodule
| 7.517837 |
module _90_lcu (
P,
G,
CI,
CO
);
parameter WIDTH = 2;
input [WIDTH-1:0] P, G;
input CI;
output [WIDTH-1:0] CO;
integer i, j;
reg [WIDTH-1:0] p, g;
wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
always @* begin
p = P;
g = G;
// in almost all cases CI will be constant ze... | 7.065403 |
module _90_alu (
A,
B,
CI,
BI,
X,
Y,
CO
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO... | 7.174058 |
module \$__div_mod_u (
A,
B,
Y,
R
);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
output [WIDTH-1:0] Y, R;
wire [WIDTH*WIDTH-1:0] chaindata;
assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
genvar i;
generate
begin
for (i = 0; i < WIDTH; i = i + 1) begin : stage
wi... | 7.101288 |
module \$__div_mod (
A,
B,
Y,
R
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH =
A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;... | 6.657259 |
module _90_pow (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = 1;
endmodule
| 6.825399 |
module _90_pmux (
A,
B,
S,
Y
);
parameter WIDTH = 1;
parameter S_WIDTH = 1;
input [WIDTH-1:0] A;
input [WIDTH*S_WIDTH-1:0] B;
input [S_WIDTH-1:0] S;
output [WIDTH-1:0] Y;
wire [WIDTH-1:0] Y_B;
genvar i, j;
generate
wire [WIDTH*S_WIDTH-1:0] B_AND_S;
for (i = 0; i < S_WIDTH; i... | 7.254615 |
module \$add (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if ((A_WIDTH == 32) && (B_WIDTH == 32)) begin
wire [16:... | 7.120414 |
module TecladoPS2_Interface (
input iCLK,
input iCLK_50,
input Reset,
inout PS2_KBCLK,
inout PS2_KBDAT,
// Barramento de IO
input wReadEnable,
wWriteEnable,
input [ 3:0] wByteEnable,
input [31:0] wAddress,
wWriteData,
output [31:0] wReadData,
// Para o Co... | 6.778261 |
module teclado_conta (
lin,
col,
bot_press,
s
);
/*Tratando o teclado como uma matriz 4x4, como abaixo
1 2 3 A
4 5 6 B
7 8 9 C
* 0 # D
Cada botao pode ser representado por duas "coordenadas",
no caso, linha e coluna da matriz*/
input [3:0] lin, col;
i... | 6.829625 |
module Teller (
teller,
tcount
);
input [2:0] teller;
output wire [1:0] tcount;
// Sum is tcount[0]
// S = A ^ B ^ C
assign tcount[0] = teller[0] ^ teller[1] ^ teller[2];
// Carry is the tcount[1]
// Carry = AB + ACin + BCin
assign tcount[1] = (teller[0] & teller[1]) + (teller[2] & teller[1])... | 7.39674 |
module holds the Verilog component declaration for temac1
* (the Tri-Mode MAC core).
* Copyright 2003 Xilinx Inc.
*/
/****************************************************************************
* Component Declaration for trimac (the Tri-Mode MAC core).
*********************************************************... | 7.998157 |
module iiitb_cps (
input clk,
reset_n,
input sensor_entrance,
sensor_exit,
input [1:0] password_1,
password_2,
output wire GREEN_LED,
RED_LED,
output reg [6:0] HEX_1,
HEX_2
);
parameter IDLE = 3'b000, WAIT_PASSWORD = 3'b001, WRONG_PASS = 3'b010, RIGHT_PASS = 3'b011,STOP = 3'b10... | 8.117646 |
module: TemperatureAnalyzer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tempAnalizerTest;
// Inputs
reg [7:0] temperature;
// Outputs
wire temperatureAbnormality;
// Inst... | 9.080435 |
module tempCont (
input clk_i, //@100 MHz
input rst_i,
input [7:0] temp_i,
input [2:0] tempCase_i, //40, 70, 100, 127, 150
output PWM_o //30-120 Hz.
);
reg [19:0] div = 20'b0;
reg [19:0] maxCount = 20'b0;
reg [1:0] statePulse = 2'b0;
reg rst = 1'b0;
always @(posedge clk_i) begin //De... | 8.711436 |
module NextStateAddressSelector (
output reg [1:0] M,
input [2:0] N,
input Sts
);
always @(N, Sts) begin
case (N)
3'b000: M = 2'b00; // Encoder
3'b001: if (Sts == 0) M = 2'b01; // 1
else M = 2'b10; // Control Register
3'b010: M = 2'b10; // Control Register
3'b011: M = 2'b1... | 7.265287 |
module Adder (
output reg [5:0] Out,
input [5:0] In
);
always @(In) begin
Out = In + 6'b000001;
end
endmodule
| 6.893856 |
module IncrementRegister (
output reg [5:0] Out,
input [5:0] In,
input Clk
);
always @(posedge Clk) begin
Out = In;
end
endmodule
| 6.680637 |
module Inverter (
output reg InvOut,
input In,
VarInv
);
always @(In, VarInv)
case (VarInv)
1'b0: if (In == 0) InvOut = 0;
else InvOut = 1;
1'b1: if (In == 1) InvOut = 0;
else InvOut = 1;
endcase
endmodule
| 7.198219 |
module InverterMux (
output reg InvIn,
input MOC,
Cond,
unsignee,
double,
load,
EntrySix,
Entryseven,
Entryeight,
input [2:0] S
);
always @(S, MOC, Cond) begin
case (S)
3'b000: InvIn = MOC;
3'b001: InvIn = Cond;
3'b010: InvIn = unsignee;
3'b011: InvI... | 7.278959 |
module ControlRegister (
output reg [5:0] state,
output reg FR,
RF,
IR,
MAR,
MDR,
ReadWrite,
MOV,
MD,
ME,
Inv,
output reg [1:0] MA,
output reg [1:0] MB,
output reg [1:0] MC,
output reg [4:0] OP,
output reg [5:0] CR,
output reg [2:0] N,
output reg [... | 6.822423 |
module temperature #(
parameter WIDTH = 32,
parameter S_WIDTH_A = 1
) (
input clk, // Must be less than 80 MHz, should be greater than 20 MHz
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH-1:0] slave_writedata,
input slave_read,
inp... | 8.072365 |
module tb_temperatureAbnormalityDetector ();
reg [4:0] factoryBaseTemp;
reg [3:0] factoryTempCoef;
reg [3:0] tempSensorValue;
wire hightemprature;
wire lowtemprature;
temperatureAbnormalityDetector tad (
factoryBaseTemp,
factoryTempCoef,
tempSensorValue,
lowtemprature,
hightemp... | 7.590233 |
module temperatureAbnormalityDetector (
factoryBaseTemp,
factoryTempCoef,
tempSensorValue,
lowTempAbnormality,
highTempAbnormality
);
input [4:0] factoryBaseTemp;
input [3:0] factoryTempCoef;
input [3:0] tempSensorValue;
output lowTempAbnormality;
output highTempAbnormality;
wire [7:0] t... | 7.663437 |
module tb_temperatureAnalyzer ();
reg [7:0] t;
wire ht;
wire lt;
temperatureAnalyzer a (
t,
ht,
lt
);
initial begin
t = 7'b0000000;
#10;
t = 7'b0000001;
#10;
t = 7'b0000010;
#10;
t = 7'b0000011;
#10;
t = 7'b0000100;
#10;
t = 7'b0000101;
#10;
... | 7.590233 |
module temperatureAnalyzer (
temperature,
highTempAbnormality,
lowTempAbnormality
);
input [7:0] temperature;
output lowTempAbnormality;
output highTempAbnormality;
assign lowTempAbnormality = (temperature < 35);
assign highTempAbnormality = (temperature > 39);
endmodule
| 6.911668 |
module tb_temperatureCalculator ();
reg [4:0] factoryBaseTemp;
reg [3:0] factoryTempCoef;
reg [3:0] tempSensorValue;
wire [7:0] temperature;
temperatureCalculator tc (
factoryBaseTemp,
factoryTempCoef,
tempSensorValue,
temperature
);
initial begin
factoryTempCoef <= 4'b0010;... | 7.590233 |
module temperatureCalculator (
factoryBaseTemp,
factoryTempCoef,
tempSensorValue,
temperature
);
input [4:0] factoryBaseTemp;
input [3:0] factoryTempCoef;
input [3:0] tempSensorValue;
output [7:0] temperature;
wire [7:0] mpo;
wire cout;
Multiplier4x4 m (
mpo,
factoryTempCoef,
... | 7.291612 |
module TemperatureMonitor_exdes (
DADDR_IN, // Address bus for the dynamic reconfiguration port
DCLK_IN, // Clock input for the dynamic reconfiguration port
DEN_IN, // Enable Signal for the dynamic reconfiguration port
DI_IN, // Input data bus for the dynamic reconfiguration port
DWE_IN, // Wri... | 8.35573 |
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